KR20200069573A - Printed circuit board with embedded bridge and semiconductor package comrpising the same - Google Patents

Abstract

The present invention provides a printed circuit board with an embedded bridge and a semiconductor package comprising the same. The printed circuit board with an embedded bridge includes: a first connection structure having a first wiring layer and a first connection via layer electrically connected to the first wiring layer; a second connection structure disposed on the first connection structure and including a second wiring layer and a second connection via layer electrically connected to the second wiring layer; a bridge embedded in the first connection structure and electrically connected to the first and second wiring layers through the first and second connection via layers, respectively; and a passive component embedded in the first connection structure and electrically connected to the first and second wiring layers through the first and second connection via layers, respectively. Each of the first and second connection via layers includes a connection via and the connection vias of the first and second connection via layers are tapered in opposite directions. The present invention can lower the process complexity and increase the integrity characteristics.

Description

Bridge embedded substrate and semiconductor package{PRINTED CIRCUIT BOARD WITH EMBEDDED BRIDGE AND SEMICONDUCTOR PACKAGE COMRPISING THE SAME}

The present disclosure relates to a bridge embedded substrate in which a bridge capable of electrically connecting electronic components disposed on a printed circuit board is embedded in a printed circuit board, and a semiconductor package in which electronic components are mounted on the bridge embedded substrate.

Recently, the interposer market for electrical connection of die-to-die is growing due to the high specification of sets and the adoption of HBM (High Bandwidth Memory), and silicon is currently the mainstream material for interposers. However, in the case of a silicon-based interposer, not only is the material cost of the interposer itself large, but also the TSV (Through Silicon Via) formation is complicated and the cost is high.

To solve this, a substrate including a silicon-based interconnect bridge capable of electrical connection of die-to-die has been developed. However, in the case of a silicon-based interconnect bridge, there is a reliability issue due to a mismatch of CTE (Coefficient of Thermal Expansion) between the silicon material of the bridge and the organic material of the substrate, and there is also a problem that power integrity characteristics are deteriorated.

One of the various objects of the present disclosure is that a bridge including a circuit capable of electrically connecting electronic components to each other is built-in, which can solve reliability issues, reduce process difficulty, and also improve power integrity characteristics. It is to provide a new type of bridge embedded substrate and a semiconductor package including the same.

One of the various solutions proposed through the present disclosure is to implement a substrate to include a plurality of connection structures, wherein a passive component and a bridge are embedded together in one connection structure to implement a bridge embedded substrate.

For example, the bridge embedded substrate according to an example may include a first connection structure including a first wiring layer and a first connection via layer electrically connected to the first wiring layer; A second connection structure disposed on the first connection structure and including a second wiring layer and a second connection via layer electrically connected to the second wiring layer; A bridge buried in the first connection structure and electrically connected to the first and second wiring layers through the first and second connection via layers, respectively; And a passive component embedded in the first connection structure, and electrically connected to the first and second wiring layers through the first and second connection via layers, respectively. The first and second connection via layers include connection vias, and the connection vias of the first and second connection via layers may be tapered in opposite directions.

In addition, the semiconductor package according to an example, the above-described bridge embedded substrate; And first and second electronic components disposed parallel to each other on the second connection structure and electrically connected to the second wiring layer, respectively. Including, The first and second electronic components are electrically connected to each other through the bridge, the passive component may be arranged to overlap at least a portion on the plane with at least one of the first and second electronic components have.

As one of several effects of the present disclosure, a reliability issue may be solved, a process difficulty may be reduced, and a new type of bridge embedded substrate capable of improving power integrity characteristics and a semiconductor package including the same may be provided. .

1 is a block diagram schematically showing an example of an electronic device system.
2 is a perspective view schematically showing an example of an electronic device.
3 is a cross-sectional view schematically illustrating a case in which a 3D BGA package is mounted on a main board of an electronic device.
4 is a cross-sectional view schematically illustrating a case in which a 2.5D silicon interposer package is mounted on a main board.
5 is a cross-sectional view schematically illustrating a case in which a 2.5D organic interposer package is mounted on a main board.
6 is a cross-sectional view schematically showing an example of a semiconductor package including a bridge embedded substrate.
7 to 10 are process diagrams schematically showing an example of manufacturing the bridge embedded substrate of FIG. 6.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shape and size of elements in the drawings may be exaggerated or reduced for a more clear description.

Electronics

1 is a block diagram schematically showing an example of an electronic device system.

Referring to the drawings, the electronic device 1000 accommodates the main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and/or electrically connected to the main board 1010. They are also combined with other components described below to form various signal lines 1090.

The chip-related components 1020 include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory; Application processor chips such as a central processor (eg, CPU), graphics processor (eg, GPU), digital signal processor, encryption processor, microprocessor, microcontroller; Logic chips such as analog-to-digital converters and application-specific ICs (ASICs) are included, but are not limited thereto, and other types of chip-related components may be included. It goes without saying that these parts 1020 may be combined with each other.

As network related parts 1030, Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM , GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and any other wireless and wired protocols specified thereafter, including, but not limited to, many other wireless or wired Any of the standards or protocols can be included. In addition, it is needless to say that the network-related parts 1030 may be combined with each other along with the chip-related parts 1020.

Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fire ceramics (LTCC), electromagnetic magnetic interference (EMI) filters, and multi-layer ceramic condenser (MLCC). , But is not limited thereto, and other passive components used for various other purposes may be included. In addition, of course, other components 1040 may be combined with each other along with the chip-related component 1020 and/or the network-related component 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and/or electrically connected to the main board 1010. Examples of other parts include a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), and a compass ( Not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage device (e.g., hard disk drive) (not shown), compact disk (CD) (not shown), and DVD (digital versatile disk) (not shown), and the like, but is not limited to this, in addition to other types of electronic devices 1000 may be used for various purposes, including, of course, may be included.

The electronic device 1000 includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer ( It may be a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, automotive, or the like. However, the present invention is not limited thereto, and of course, it may be any other electronic devices that process data.

2 is a perspective view schematically showing an example of an electronic device.

Referring to the drawings, a semiconductor package including an organic interposer is applied to various electronic devices as described above for various purposes. For example, the motherboard 1110 is accommodated inside the body 1101 of the smart phone 1100, and various components 1120 are physically and/or electrically connected to the motherboard 1110. In addition, other components that may or may not be physically and/or electrically connected to the motherboard 1110, such as the camera 1130, are housed in the body 1101. Some of the components 1120 may be chip-related components, and some of them may be a semiconductor package 1121 using an interposer. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, of course, may be other electronic devices.

Semiconductor package

In general, a semiconductor chip has a large number of fine electrical circuits integrated, but it cannot serve as a semiconductor finished product by itself, and there is a possibility of being damaged by an external physical or chemical impact. Therefore, rather than using the semiconductor chip itself, the semiconductor chip is packaged and used in electronic devices or the like in a package state.

The reason for the need for semiconductor packaging is that from the viewpoint of electrical connection, there is a difference in the circuit width of the semiconductor chip and the main board of the electronic device. Specifically, in the case of a semiconductor chip, the size of the connection pad and the spacing between the connection pads are very fine, whereas in the case of a main board used in electronic devices, the size of the component mounting pad and the spacing of the component mounting pad are much larger than the scale of the semiconductor chip . Therefore, it is difficult to mount the semiconductor chip directly on such a main board, and a packaging technology capable of buffering the circuit width difference between each other is required.

Hereinafter, with reference to the drawings it will be described in more detail with respect to using the interposer of the semiconductor package manufactured by such a packaging technology.

3 is a cross-sectional view schematically illustrating a case in which a 3D BGA package is mounted on a main board of an electronic device.

Among semiconductor chips, application specific integrated circuits (ASICs) such as graphics processing units (GPUs) are very expensive, so it is very important to perform packaging with high yield. For this purpose, a ball grid array (BGA) substrate 2210 or the like capable of redistributing thousands to millions of connection pads is first prepared before mounting a semiconductor chip, and an expensive GPU 2220 or the like is used. The same semiconductor chip is subsequently mounted and packaged on a BGA substrate 2210 using a surface mounting technology (SMT), and then finally mounted on the main board 2110.

On the other hand, in the case of the GPU 2220, it is necessary to minimize the signal path with a memory such as a high bandwidth memory (HBM: High Bandwidth Memory), and for this purpose, a semiconductor chip such as the HBM 2240 is interposer 2230. After mounting on the packaging, it is used to stack and use it in the form of a package on package (POP) on a package on which the GPU 2220 is mounted. However, in this case, there is a problem that the thickness of the device is too thick, and there is a limit to minimize the signal path.

4 is a cross-sectional view schematically illustrating a case in which a 2.5D silicon interposer package is mounted on a main board.

As a method for solving the above-described problem, a first semiconductor chip such as GPU 2220 and a second semiconductor chip such as HBM 2240 on a silicon interposer 2250 surface side-by-side. As a 2.5D interposer technology for packaging after mounting, it may be considered to manufacture a semiconductor package 2310 including a silicon interposer. In this case, the GPU 2220 and the HBM 2240 having thousands to millions of connection pads can be re-wired through the interposer 2250, and these can be electrically connected with a minimum path. In addition, when the semiconductor package 2310 including such a silicon interposer is mounted on the BGA substrate 2210 again and redistributed, it may be finally mounted on the main board 2110. However, in the case of the silicon interposer 2250, not only is formation of a through silicon via (TSV) very difficult, but also the manufacturing cost is considerable, which is disadvantageous for large area and low cost.

5 is a cross-sectional view schematically illustrating a case in which a 2.5D organic interposer package is mounted on a main board.

As a method for solving the above-described problem, it may be considered to use the organic interposer 2260 instead of the silicon interposer 2250. For example, the organic interposer is a 2.5D interposer technology that surface-mounts and packages a first semiconductor chip such as GPU 2220 and a second semiconductor chip such as HBM 2240 on the organic interposer 2260. It is conceivable to manufacture the containing semiconductor package 2320. In this case, the GPU 2220 and the HBM 2240 having thousands to millions of connection pads can be re-wired through the interposer 2260, and these can be electrically connected with a minimum path. In addition, when the semiconductor package 2310 including such an organic interposer is mounted on the BGA substrate 2210 again and redistributed, it may be finally mounted on the main board 2110. In addition, it is advantageous for large area and low cost. However, in the case of a semiconductor package 2320 including such an organic interposer, warpage occurs due to a mismatch in thermal expansion coefficient (CTE) between the molding material of the interposer 2260 and the chips 2220 and 2240 when a molding process is performed. Problems such as occurrence, deterioration of underfill fillability, cracks between the die and the molding material may occur. Also, in the case of an organic interposer, it may be disadvantageous for realizing a fine pattern.

As a method for solving the above-described problem, although not specifically shown in the drawings, it is possible to consider forming a silicon-based interconnection bridge having a fine pattern separately and inserting it into a cavity of a BGA substrate to embed it. However, in this case, it is difficult to form a cavity and implement a corresponding microcircuit in a BGA substrate, which may cause problems of process and yield drop. Therefore, there is a need for a new type of semiconductor package that can solve all of these problems.

Hereinafter, a new type of bridge embedded substrate capable of solving reliability issues, lowering process difficulty, and also improving power integrity characteristics, and a semiconductor package including the same will be described with reference to the drawings.

6 is a cross-sectional view schematically showing an example of a semiconductor package including a bridge embedded substrate.

Referring to the drawings, the semiconductor package 500 according to an example includes a bridge embedded substrate 100 and first and second electronic components 210 and 220 arranged side by side on the bridge embedded substrate 100. . First and second electrical connection metals 180 and 190 may be disposed on both sides of the bridge embedded substrate 100. The first and second electronic components 210 and 220 may be connected to the bridge embedded substrate 100 through the second electrical connection metal 190, respectively.

The bridge embedded substrate 100 according to an example includes one or more first wiring layers 142 and first insulating layers 141 disposed on the first insulating layer 141 and the first insulating layer 141, respectively. It is disposed on the first connection structure 140 and the first connection structure 140 including one or more first connection via layers 143 penetrating through the first wiring layer 142 and electrically connected to each other. One or more layers of the second wiring layer 152 and the second insulating layer 151 disposed on the layer 151 and the second insulating layer 151, respectively, and electrically connected to the second wiring layer 152, respectively. The second connection structure 150 including the second connection via layer 153 is buried in the first connection structure 140 and the first and second wiring layers through the first and second connection via layers 143 and 153 The first and second wiring layers 142 and 152 are buried in the bridge 110 and the first connection structure 140 electrically connected to the 142 and 152, respectively, and through the first and second connecting via layers 143 and 153. ) And passive parts 120 electrically connected to each other. At this time, the first and second connection via layers 143 and 153 each include connection vias, and the connection vias of the first and second connection via layers 143 and 153 have a tapered shape in opposite directions.

As described above, the bridge 110 in which the circuit layer 112 and the connection via layer 113 are formed on the organic insulating layer 111 of one or more layers is basically embedded in the first connection structure 140 in the bridge embedded substrate 100. In other words, unlike the conventional silicon-based bridge, even if it is embedded in the first connection structure 140, the reliability problem due to CTE mismatch can be solved. In addition, a passive component 120 is built into the first connection structure 140 at the same level as the bridge 110. The passive component 120 may be of various types such as capacitors and inductors. As described above, when various types of passive components 120 are embedded together with the bridge 110, when the first and second electronic components 210 and 220 are disposed on the bridge embedded substrate 100, the passive components ( Since 120) may be arranged such that at least one of the first and second electronic components 210 and 220 overlaps at least a portion on a plane, an electrical connection path may be simplified. For example, the passive component 120 may be connected very closely to the power stages of the first and second electronic components 210 and 220. Therefore, power integrity characteristics and the like can be stably improved.

In addition, the bridge embedded substrate 100 includes a first connection structure 140 having a bridge 110 and passive components 120 and a second connection structure 150 disposed on the first connection structure 140. As described above, both of the first and second connecting via layers 143 and 153 are components that are distinguished from each other having a tapered shape in opposite directions to each other. As described above, the bridge embedded substrate 100 includes the connection structures 140 and 150 which are the electrical connection paths, respectively, on the basis of the bridge 110 and the passive components 120, respectively. It is easy to improve the performance of the semiconductor package 500 including the same, or the electronic device including the semiconductor package 500.

In addition, the bridge-embedded substrate 100 of this type arranges the bridge 110 and the passive component 120 side by side with each other at the same level, and the bridge 110 on one side of the bridge 110 and the passive component 120. And forming the first connection structure 140 filling the passive component 120, and then forming the second connection structure 150 on the other side of the bridge 110 and the passive component 120. In this case, the bridge 110 and the passive component 120 are easily attached, and the bridge 110 and the passive component 120 are buried in the first connection structure 140, and then the second connection is provided on a flat surface provided. Since the structure 150 can be formed, process difficulty can be reduced. That is, the top side facing the second insulating layer 151 of the second connecting structure 150 of each of the bridge 110 and the passive component 120 is the first insulating layer 141 of the first connecting structure 140. Coplanar with the top side facing the second insulating layer 151 of the second connection structure 150 of the. That is, it can be roughly coplanar.

Meanwhile, the first and second connection via layers 143 and 153 of the first and second connection structures 140 and 150 may include first to third connection vias, respectively. The first connection vias 143a and 153a of the first and second connection via layers 143 and 153 bridge the first and second wiring layers 142 and 152 in opposite directions to each other based on the bridge 110. 110), and each of the first and second connecting via layers 143 and 153, and the second connecting vias 143b and 153b, respectively, are first and second in opposite directions based on the passive component 120. The wiring layers 142 and 152 may be connected to the passive component 120, respectively. The third connection vias 143c and 153c of the first and second connection via layers 143 and 153 may be connected to each other. That is, the first and second connecting via layers 143 and 153 can physically contact each other without a separate wiring layer between them.

Meanwhile, the third connection via 143c of the first connection via layer 143 may have a higher height than the first and second connection vias 143a and 143b. This, unlike the first and second connection vias 143a and 143b of the first connection via layer 143 are disposed on the bridge 110 and the passive component 120, respectively, the third connection via 143c is This is because it can be arranged in parallel with the bridge 110 and the passive component 120. At this time, each of the bridge 110 and the passive component 120 may be positioned at a level between the upper and lower surfaces of the third connecting via 143c of the first connecting via layer 143.

On the other hand, the bridge embedded substrate 100 may be formed through the adhesive layer 130, as will be described later, in this case, the bridge 110 and the passive component 120 are parallel to each other at the same level as each other on the adhesive layer 130. Can be deployed. In this case, in the case of the first connection via layer 143, the third connection via 143c may penetrate the adhesive layer 130, and in the case of the second connection via layer 153, the first and second connection vias ( 153a and 153b) may penetrate the adhesive layer 130, respectively. In this regard, the first and second connection vias 153a and 153b of the second connection via layer 153 may each have a height higher than that of the third connection via 153c. If necessary, the adhesive layer 130 may be removed in the process. In this case, the first to third connection vias 153a, 153b, and 153c of the second connection via layer 153 may have substantially the same height.

Hereinafter, each component of the semiconductor package according to an example will be described in more detail with reference to the drawings.

The bridge embedded substrate 100 includes a bridge 110, a passive component 120, a first connection structure 140, and a second connection structure 150. The bridge embedded substrate 100 may further include an adhesive layer 130 disposed between the first and second connection structures 140 and 150 as necessary. In addition, if necessary, the first and second passivation layers 160 and 170 and/or the first and second electrical connection metals 180 and 190 disposed on the first and second connection structures 140 and 150 may be used. It may further include. In addition, if necessary, a third connection structure 195 may be further disposed between the first connection structure 140 and the first passivation layer 160.

The bridge 110 may be an organic bridge 110. For example, the bridge 110 passes through each of the organic insulating layer 111, the circuit layer 112 disposed on the organic insulating layer 111, and the organic insulating layer 111, respectively, and the circuit layer 112 ), and connection via layers 113 connected to each other. The number of layers of the organic insulating layer 111, the circuit layer 112, and the connecting via layer 113 may be more or less than that shown in the drawing.

The organic insulating layer 111 may include an insulating material, and the insulating material may be, for example, PID (Photo Image-able Dielectric). Each of the layers of the organic insulating layer 111 may be separated from each other or may be uncertain. When PID is used as the material of the organic insulating layer 111, the thickness of the organic insulating layer 111 can be minimized and a photo via hole can be formed. As a result, the circuit layer 112 and the connecting via layer 113 can be formed. It can be easily designed with high density. For example, the circuit layer 112 and the connection via layer 113 may be designed with higher density than the first wiring layer 142 and the second connection via layer 153 of the first connection structure 140. Specifically, the thickness of each circuit layer 112 may be thinner than the thickness of each of the first wiring layers 142, and the upper/lower spacing may be narrower. In addition, the average diameter of each connection via layer 113 may be smaller than the average diameter of each connection via of the first connection via layer 143, and the height or thickness may also be smaller, and the finer pitch (Fine) Pitch) may make the pitch between vias narrower. Even if other materials are used as the insulating material of the organic insulating layer 111, the circuit layer 112 and the connecting via layer 113 are designed with higher density than the first wiring layer 142 and the first connecting via layer 143. Preferably.

The circuit layer 112 electrically connects the first and second electronic components 210 and 220 to each other. The circuit layer 112 may perform various functions according to the design of the corresponding layer, but at least includes a signal pattern and a signal pad. Circuit layer 112 is copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof Conductive materials, such as metal materials, can be used.

The connecting via layer 113 electrically connects the circuit layers 112 formed on different layers, and as a result, forms an electrical path in the bridge 110. Each of the connecting via layers 113 may include a plurality of connecting vias. Connection via layer 113 Each connection via is copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) Or, it may include a conductive material such as an alloy of these, specifically a metallic material. The connecting via layer 113 can perform various functions according to the design design of the corresponding layer, but at least includes a signal via. Each of the connection via layers 113 may be a field type filled with a conductive material, or a conformal type in which a conductive material is disposed along the wall surface of the via. Each connecting via of the connecting via layer 113 may have a tapered shape in the same direction as each connecting via of the first connecting via layer 143.

The passive component 120 may be one or a plurality. Each passive component 120 may be the same or different from each other. The passive component 120 may be a known passive component such as a capacitor or an inductor. The passive components 120 may each have external electrodes. That is, the passive components 120 may be independent chip-type components. At least one of the first and second electronic components 210 and 220 is preferably disposed directly above the at least one passive component 120. Through this arrangement, a minimum electrical path can be provided, and power supply stability and the like can be achieved.

The adhesive layer 130 may be a known adhesive tape. The adhesive layer 130 may be disposed between the first and second connection structures 140 and 150. The bridge 110 and the passive component 120 may be attached to the adhesive layer 130 side by side with each other at the same level. Therefore, each surface attached to the adhesive layer 130 of the bridge 110 and the passive component 120 may be coplanar. That is, it can be roughly coplanar. The material of the adhesive layer 130 is not particularly limited, and may include a known insulating resin having adhesive properties. The adhesive layer 130 may be removed in the middle of the process. Even in this case, each surface exposed from the first connection structure 140 of the bridge 110 and the passive component 120 may be coplanar.

The first connection structure 140 penetrates one or more first insulating layers 141, one or more first wiring layers 142 disposed on the first insulating layers 141, and the first insulating layer 141, respectively. And a first connection via layer 143 connected to one or more first wiring layers 142. The first connection structure 140 covers the bridge 110 and the passive component 120, and may have a considerable thickness. That is, the first connection structure 140 may be thicker than the second and third connection structures 150 and 195, respectively, and the scales of the first wiring layer 142 and the first connection via layer 143 are also second and second. The third wiring layers 152 and 192 and the second and third connection via layers 153 and 193 may be larger than the scale. The number of layers of the first insulating layer 141, the first wiring layer 142, and the first connection via layer 143 may be greater than or less than that shown in the drawing.

The first insulating layer 141 may include an insulating material, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a mixture of these resins with an inorganic filler or glass with an inorganic filler Resin impregnated with fibers (Glass Fiber, Glass Cloth, Glass Fabric), for example, prepreg, ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), etc. may be used.

The first wiring layer 142 performs various functions within the first connection structure 140 according to the design design of the corresponding layer. For example, it may include a ground pattern, a power pattern, a signal pattern, and the like. Here, the signal pattern includes various signals except for the ground pattern and the power pattern, for example, a data signal. In addition, various pads may be included. Materials for forming the first wiring layer 142 are copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti), respectively. ), or a conductive material such as an alloy thereof, specifically a metal material.

The first connection via layer 143 electrically connects the first wiring layer 142 formed on different layers to each other, and also connects the first wiring layer 142 to the second wiring layer 1521, the bridge 110, and passive components. It is also electrically connected to (120). As a result, an electrical path is formed in the first connection structure 140. Each of the first connection via layers 143 may include a plurality of connection vias. Each connection via is copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. It may include a conductive material, specifically a metal material. Each connection via may include a ground via, a power via, a signal via, and the like. Each connecting via may be of a filled type filled with a conductive material, or a conformal type in which a conductive material is disposed along the wall surface of the via. Each connection via may have a tapered shape opposite to each connection via of the second connection via layer 153.

The second connection structure 150 penetrates through at least one second insulating layer 151, at least one second wiring layer 152 disposed on the second insulating layer 151, and a second insulating layer 151, respectively. And a second connection via layer 153 connected to one or more second wiring layers 152. The second connection structure 150 may be implemented in a fine design thinner than the first connection structure 140. For example, the second wiring layer 152 and the second connection via layer 153 may be designed with higher density than the first wiring layer 142 and the first connection via layer 143. Specifically, the thickness of each of the second wiring layers 152 may be thinner than the thickness of each of the first wiring layers 142, and the upper/lower spacing may be narrower. In addition, the average diameter of each connection via of the second connection via layer 153 may be smaller than the average diameter of each connection via of the first connection via layer 143, and the height or thickness may also be smaller, and the finer pitch may be obtained. The pitch between vias may be narrower with (Fine Pitch).

The second insulating layer 151 may include an insulating material, for example, a photosensitive insulating material (PID), or alternatively, may include a non-photosensitive insulating material, such as ABF. The second wiring layer 152 also performs various functions within the second connection structure 150 according to the design design of the corresponding layer. For example, it may include a ground pattern, a power pattern, a signal pattern, and the like. Here, the signal pattern includes various signals except for the ground pattern and the power pattern, for example, a data signal. In addition, various pads may be included. The forming material of the second wiring layer 152 is copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), respectively. ), or a conductive material such as an alloy thereof, specifically a metal material.

The second connection via layer 153 electrically connects the second wiring layer 152 formed on different layers to each other, and also connects the second wiring layer 152 to the first wiring layer 142, the bridge 110, and passive components. It is also electrically connected to (120). As a result, an electrical path is formed in the second connection structure 150. Each of the second connection via layers 153 may include a plurality of connection vias. Each connection via is copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. It may include a conductive material, specifically a metal material. Each connection via may include a ground via, a power via, a signal via, and the like. Each connecting via may be of a filled type filled with a conductive material, or a conformal type in which a conductive material is disposed along the wall surface of the via. Each connection via may have a tapered shape opposite to each connection via of the first connection via layer 143.

The third connection structure 195 penetrates through at least one third insulating layer 191, at least one third wiring layer 192 disposed on the third insulating layer 191, and a third insulating layer 191, respectively. And a third connection via layer 193 connected to one or more third wiring layers 192. The third connection structure 195 may be implemented in a fine design thinner than the first connection structure 140 like the second connection structure 150. For example, the third wiring layer 192 and the third connection via layer 193 may be designed with higher density than the first wiring layer 142 and the first connection via layer 143. Specifically, the thickness of each of the third wiring layers 192 may be thinner than the thickness of each of the first wiring layers 142, and the upper/lower spacing may be narrower. In addition, the average diameter of each connection via of the third connection via layer 193 may be smaller than the average diameter of each connection via of the first connection via layer 143, and the height or thickness may also be smaller, and the pitch between the vias May be narrower.

The third insulating layer 191 may include an insulating material, for example, a photosensitive insulating material (PID), or alternatively, may include a non-photosensitive insulating material, such as ABF. The third wiring layer 192 performs various functions within the third connection structure 195 according to the design design of the corresponding layer. For example, it may include a ground pattern, a power pattern, a signal pattern, and the like. Here, the signal pattern includes various signals except for the ground pattern and the power pattern, for example, a data signal. In addition, various pads may be included. Materials for forming the third wiring layer 192 are copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti), respectively. ), or a conductive material such as an alloy thereof, specifically a metal material.

The third connection via layer 193 electrically connects the third wiring layer 192 formed on different layers to each other, and also connects the third wiring layer 192 to the first wiring layer 142, the bridge 110, and passive components. It is also electrically connected to (120). As a result, an electrical path is formed in the third connection structure 195. Each of the third connection via layers 193 may include a plurality of connection vias. Each connection via is copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. It may include a conductive material, specifically a metal material. Each connection via may include a ground via, a power via, a signal via, and the like. Each connecting via may be of a filled type filled with a conductive material, or a conformal type in which a conductive material is disposed along the wall surface of the via. Each connecting via may have a tapered shape in the same direction as each connecting via of the first connecting via layer 143.

The first and second passivation layers 160 and 170 are disposed on the first and second connection structures 140 and 150, respectively, to protect them. When the third connection structure 195 is further disposed, the first passivation layer 160 may be disposed on the third connection structure 195. The first and second passivation layers 160 and 170 may include an insulating material, for example, may include a photosensitive insulating material (PID), or alternatively, may include a non-photosensitive insulating material, such as ABF. It might be. When the first and second passivation layers 160 and 170 are further disposed with the first and second wiring layers 142 and 152 or the third connection structure 195, the third and second wiring layers 192 and 152 are respectively provided. It may have an opening exposing at least a portion of.

The first and second electrical connection metals 180 and 190 may be formed of a low melting point metal, for example, solder such as tin (Sn)-aluminum (Al)-copper (Cu), etc. This is only an example, and the material is not particularly limited thereto. The first and second electrical connection metals 180 and 190 may be lands, balls, pins, and the like. The first and second electrical connection metals 180 and 190 may be formed of multiple layers or single layers. When formed in a multi-layer, it may include copper pillars and solder, and when formed in a single layer, it may include tin-silver solder or copper, but this is only an example and is not limited thereto. .

The first and second electronic components 210 and 220 may be semiconductor chips, respectively. In this case, the semiconductor chip may include an integrated circuit (IC) in which hundreds to millions of devices are integrated in one chip. In this case, the integrated circuit includes, for example, a processor such as a central processor (eg, CPU), a graphics processor (eg, GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller. Chip, specifically, may be an application processor (AP), but is not limited thereto, volatile memory (eg, DRAM), non-volatile memory (eg, ROM), flash memory, high bandwidth memory (HBM) Of course, it may be a memory chip such as an analog-to-digital converter, a logic chip such as an application-specific IC (ASIC), or another type such as a power management IC (PMIC). As a non-limiting example, the first electronic component 210 may include a processor chip such as an AP, and the second electronic component 2200 may include a memory chip such as HBM, but is not limited thereto.

Each of the first and second electronic components 210 and 220 may be formed based on an active wafer, and in this case, as a base material forming each body, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. Can be used. Various circuits may be formed on the body. Connection pads (not shown) for electrically connecting the first and second electronic components 210 and 220 to other components may be formed on each body, and the connection pads (not shown) include aluminum (Al), And a conductive material such as copper (Cu). Each of the first and second electronic components 210 and 220 may be a bare die, in which case a bump (not shown) is disposed on a connection pad (not shown) to form the second electrical connection metal 190. It may be surface mounted on the bridge built-in substrate (100). However, the present invention is not limited thereto, and the first and second electronic components 210 and 220 may be packaged dies.

7 to 10 are process diagrams schematically showing an example of manufacturing the bridge embedded substrate of FIG. 6.

Referring to FIG. 7, first, the carrier 300 is prepared. The carrier 300 may be a copper clad laminate (CCL) type deteach film. Next, an adhesive layer 130 is formed on the carrier 300. Next, the bridge 110 and the passive component 120 prepared in advance on the adhesive layer 130 are attached to each other side by side.

Referring to FIG. 8, next, a first insulating layer 141 covering the bridge 110 and the passive component 120 is formed on the adhesive layer 130 using ABF or the like, and the first insulating layer 141 is formed. After the via hole is processed with a laser drill or the like, the first wiring layer 142 and the first connecting via layer 143 are formed by a plating process. Next, a series of processes are repeated as necessary to form the first connection structure 140. Next, the carrier 300 is removed, and a metal film (not shown) remaining on the adhesive layer 130 is removed by etching.

Referring to FIG. 9, next, a second insulating layer 151 is formed by using PID or ABF on the opposite side of the side where the first connection structure 140 of the adhesive layer 130 is formed. If necessary, the adhesive layer 130 may be removed before that. In this case, the second insulating layer 151 is formed on the side where the surfaces of the bridge 110 and the passive component 120 of the first connection structure 140 are exposed. Next, after processing the via hole by photolithography and/or laser drilling, a second wiring layer 152 and a second connection via layer 153 are formed by a plating process.

Referring to FIG. 10, next, a series of processes are repeated as necessary to form a second connection structure 150. At this time, if necessary, the third insulating structure 195 is formed by forming the third insulating layer 191, the third wiring layer 192, and the third connecting via layer 193 in the same manner on the opposite side. Next, if necessary, the first and second passivation layers 160 and 170 are formed on both sides using ABF or the like, and openings are formed on each side to manufacture the bridge embedded substrate 100 according to the above-described example. Can be.

In the present disclosure, the lower side, the lower side, the lower side, etc. are used as the direction toward the mounting surface of the semiconductor package including the organic interposer on the basis of the cross section of the drawing for convenience, and the upper side, upper side, upper side, etc. are used in opposite directions. Did. However, this defines the direction for convenience of explanation, and it goes without saying that the scope of the claims is not particularly limited by the description of the direction.

The term "connected" in the present disclosure is a concept that includes not only directly connected but also indirectly connected through an adhesive layer or the like. In addition, the meaning of being electrically connected is a concept including both physically connected and non-connected cases. In addition, expressions such as first and second are used to distinguish one component from another component, and do not limit the order and/or importance of the components. In some cases, the first component may be referred to as a second component, and similarly, the second component may be referred to as a first component without departing from the scope of rights.

The expression “an example” used in the present disclosure does not mean the same exemplary embodiments, but is provided to explain different unique features. However, the examples presented above are not excluded from being implemented in combination with other example features. For example, although the matter described in a particular example is not described in another example, it may be understood as a description related to another example, unless there is a description contrary to or contradicting the matter in another example.

The terms used in the present disclosure are only used to describe an example, and are not intended to limit the present disclosure. In this case, the singular expression includes a plural expression unless the context clearly indicates otherwise.

Claims (10)

A first connection structure including a first wiring layer and a first connection via layer electrically connected to the first wiring layer;
A second connection structure disposed on the first connection structure and including a second wiring layer and a second connection via layer electrically connected to the second wiring layer;
A bridge embedded in the first connection structure and electrically connected to the first and second wiring layers through the first and second connection via layers, respectively; And
A passive component embedded in the first connection structure and electrically connected to the first and second wiring layers through the first and second connection via layers, respectively; It includes,
The first and second connection via layers each include a connection via,
The connection vias of the first and second connection via layers are tapered in opposite directions,
Bridge built-in substrate.
According to claim 1,
The bridge and the passive component are respectively embedded in the first connection structure in parallel with each other at the same level.
Bridge built-in substrate.
According to claim 2,
The first and second connection structures include first and second insulating layers on which the first and second wiring layers and the first and second connecting via layers are disposed, respectively.
The top side facing the second insulating layer of each of the bridge and the passive component is coplanar with the top side facing the second insulating layer of the first insulating layer,
Bridge built-in substrate.
According to claim 2,
The first and second connection via layers each include first to third connection vias,
The first connection via of each of the first and second connection via layers connects the first and second wiring layers to the bridge, respectively, in opposite directions based on the bridge,
The second connecting vias of each of the first and second connecting via layers connect the first and second wiring layers to the passive components in opposite directions to each other based on the passive component,
The third connection vias of each of the first and second connection via layers are connected to each other,
Bridge built-in substrate.
The method of claim 4,
The third connection via of the first connection via layer is higher than the first and second connection vias of the first connection via layer,
The bridge and the passive component are located at levels between upper and lower surfaces of the third connecting via of the first connecting via layer, respectively.
Bridge built-in substrate.
The method of claim 4,
An adhesive layer disposed between the first and second connection structures; Further comprising,
The bridge and the passive component are respectively attached to the adhesive layer side by side at the same level with each other, respectively embedded in the first connection structure,
Bridge built-in board.
The method of claim 6,
The third connection via of the first connection via layer penetrates the adhesive layer,
The first and second connection vias of the second connection via layer respectively penetrate the adhesive layer,
Bridge built-in substrate.
According to claim 1,
The first connection structure is thicker than the second connection structure,
Bridge built-in substrate.
According to claim 1,
The bridge includes an organic insulating layer, a circuit layer disposed on the organic insulating layer, and a connection via layer penetrating the organic insulating layer and connected to the circuit layer.
Bridge built-in substrate.
The bridge embedded substrate of any one of claims 1 to 9; And
First and second electronic components disposed side by side on the second connection structure and electrically connected to the second wiring layer, respectively; It includes,
The first and second electronic components are electrically connected to each other through the bridge,
The passive component is disposed such that at least a portion of the first and second electronic components overlaps at least a portion on a plane.
Semiconductor package.

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