KR102632363B1 - Printed circuit board with embedded bridge and semiconductor package comrpising the same - Google Patents

Abstract

The present disclosure provides a first connection structure including a first wiring layer and a first connection via layer electrically connected to the first wiring layer, a second wiring layer and a first connection structure disposed on the first connection structure and electrically connected to the second wiring layer. A second connection structure including two connection via layers, a bridge embedded in the first connection structure and electrically connected to the first and second wiring layers through the first and second connection via layers, respectively, and the first connection. It includes passive components embedded in the structure and electrically connected to the first and second wiring layers through the first and second connection via layers, respectively, wherein the first and second connection via layers each include connection vias, The connection vias of the first and second connection via layers relate to a bridge embedded substrate tapered in opposite directions, and a semiconductor package including the same.

Description

Bridge embedded board and semiconductor package {PRINTED CIRCUIT BOARD WITH EMBEDDED BRIDGE AND SEMICONDUCTOR PACKAGE COMRPISING THE SAME}

The present disclosure relates to a bridge-embedded board in which a bridge capable of electrically connecting electronic components disposed on a printed circuit board is built into the printed circuit board, and a semiconductor package in which electronic components are mounted on the bridge-embedded board.

Recently, the interposer market for die-to-die electrical connection is growing due to the higher specifications of sets and the adoption of HBM (High Bandwidth Memory), and silicon is currently the mainstream material for interposers. However, in the case of silicon-based interposers, there is a problem that not only is the material cost of the interposer itself high, but also the formation of TSV (Through Silicon Via) is complicated and expensive.

To solve this problem, a substrate including a silicon-based interconnect bridge that enables die-to-die electrical connection is being developed. However, in the case of silicon-based interconnect bridges, there is a reliability issue due to CTE (Coefficient of Thermal Expansion) mismatch between the silicon material of the bridge and the organic material of the substrate, and there is also a problem of deterioration of power integrity characteristics.

One of the several purposes of the present disclosure is to build a bridge that includes a circuit that can electrically connect electronic components to each other, and that can still solve reliability issues, reduce process difficulty, and improve power integrity characteristics. The aim is to provide a new type of bridge-embedded board and a semiconductor package including the same.

One of several solutions proposed through this disclosure is to implement a board to include a plurality of connection structures, and at this time, implement a bridge-embedded board by embedding passive components and a bridge together in one connection structure.

For example, a bridge embedded substrate according to one example includes a first connection structure including a first wiring layer and a first connection via layer electrically connected to the first wiring layer; a second connection structure disposed on the first connection structure and including a second wiring layer and a second connection via layer electrically connected to the second wiring layer; a bridge embedded in the first connection structure and electrically connected to the first and second wiring layers through the first and second connection via layers, respectively; and a passive component embedded in the first connection structure and electrically connected to the first and second wiring layers through the first and second connection via layers, respectively. It includes, wherein the first and second connection via layers each include a connection via, and the connection vias of the first and second connection via layers may be tapered in opposite directions.

Additionally, a semiconductor package according to one example includes the bridge embedded substrate described above; and first and second electronic components arranged side by side on the second connection structure and each electrically connected to the second wiring layer; It includes, wherein the first and second electronic components are electrically connected to each other through the bridge, and the passive component may be arranged so that at least a portion of the passive component overlaps at least one of the first and second electronic components on a plane. there is.

One of the many effects of the present disclosure is to provide a new type of bridge embedded substrate that can solve reliability issues, reduce process difficulty, and improve power integrity characteristics, and a semiconductor package including the same. .

1 is a block diagram schematically showing an example of an electronic device system.
Figure 2 is a perspective view schematically showing an example of an electronic device.
Figure 3 is a cross-sectional view schematically showing a case where a 3D BGA package is mounted on the main board of an electronic device.
Figure 4 is a cross-sectional view schematically showing a case where a 2.5D silicon interposer package is mounted on a motherboard.
Figure 5 is a cross-sectional view schematically showing a case where a 2.5D organic interposer package is mounted on a motherboard.
Figure 6 is a cross-sectional view schematically showing an example of a semiconductor package including a bridge embedded substrate.
7 to 10 are process diagrams schematically showing an example of manufacturing the bridge embedded substrate of FIG. 6.

Hereinafter, the present disclosure will be described with reference to the attached drawings. The shapes and sizes of elements in the drawings may be exaggerated or reduced for clearer explanation.

Electronics

1 is a block diagram schematically showing an example of an electronic device system.

Referring to the drawing, the electronic device 1000 accommodates the main board 1010. The main board 1010 is physically and/or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040. These are combined with other components described later to form various signal lines 1090.

Chip-related components 1020 include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory; Application processor chips such as central processors (eg, CPU), graphics processors (eg, GPU), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; Logic chips such as analog-digital converters and ASICs (application-specific ICs) are included, but are not limited to these, and of course other types of chip-related components may also be included. Additionally, of course, these components 1020 can be combined with each other.

Network-related parts (1030) include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM. , GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and any other wireless and wired protocols designated as such, but are not limited to, and many other wireless or wired protocols. Any of the standards or protocols may be included. In addition, of course, the network-related components 1030 can be combined with the chip-related components 1020.

Other parts (1040) include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (Electro Magnetic Interference) filter, MLCC (Multi-Layer Ceramic Condenser), etc. , but is not limited to this, and may include passive parts used for various other purposes. In addition, of course, the other components 1040 can be combined with the chip-related components 1020 and/or the network-related components 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and/or electrically connected to the main board 1010. Examples of other components include a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), and a compass ( (not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage device (e.g., hard disk drive) (not shown), compact disk (CD) (not shown), and DVD (digital versatile disk) (not shown), etc. However, it is not limited thereto, and of course, other parts used for various purposes may be included depending on the type of electronic device 1000.

The electronic device 1000 includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer ( It may be a computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, etc. However, it is not limited to this, and of course, it can be any other electronic device that processes data.

Figure 2 is a perspective view schematically showing an example of an electronic device.

Referring to the drawings, a semiconductor package including an organic interposer is applied to various electronic devices as described above for various purposes. For example, a motherboard 1110 is accommodated inside the body 1101 of the smart phone 1100, and various components 1120 are physically and/or electrically connected to the motherboard 1110. Additionally, other components, such as the camera 1130, that may or may not be physically and/or electrically connected to the motherboard 1110 are accommodated within the body 1101. Some of the components 1120 may be chip-related components, and some of them may be a semiconductor package 1121 that uses an interposer. Meanwhile, the electronic device is not necessarily limited to the smart phone 1100, and of course may be other electronic devices.

semiconductor package

In general, a semiconductor chip integrates numerous microscopic electrical circuits, but it cannot function as a finished semiconductor product by itself, and there is a possibility that it may be damaged by external physical or chemical shock. Therefore, rather than using the semiconductor chip itself, the semiconductor chip is packaged and used in electronic devices as a package.

The reason why semiconductor packaging is necessary is because, from the perspective of electrical connection, there is a difference in circuit width between the semiconductor chip and the main board of electronic devices. Specifically, in the case of semiconductor chips, the size of the connection pads and the spacing between the connection pads are very small, whereas in the case of motherboards used in electronic devices, the size of the component mounting pads and the spacing between the component mounting pads are much larger than the scale of the semiconductor chip. . Therefore, it is difficult to directly mount a semiconductor chip on such a motherboard, and packaging technology that can buffer the difference in circuit width between them is required.

Below, with reference to the drawings, we will look at the use of an interposer among semiconductor packages manufactured using this packaging technology in more detail.

Figure 3 is a cross-sectional view schematically showing a case where a 3D BGA package is mounted on the main board of an electronic device.

Among semiconductor chips, application specific integrated circuits (ASICs), such as graphics processing units (GPUs), are very expensive for each chip, so it is very important to package them at a high yield. For this purpose, a ball grid array (BGA: Ball Grid Array) board (2210) capable of rewiring thousands to millions of connection pads is first prepared before mounting a semiconductor chip, and expensive devices such as GPU (2220) are prepared. The same semiconductor chip is subsequently mounted and packaged on the BGA board 2210 using surface mounting technology (SMT), and then finally mounted on the main board 2110.

Meanwhile, in the case of GPU (2220), it is necessary to minimize the signal path with memory such as high bandwidth memory (HBM), and for this purpose, a semiconductor chip such as HBM (2240) is used as an interposer (2230). It is used to package the GPU 2220 by mounting it on a package and stacking it in a package on package (POP) form on the package in which the GPU 2220 is mounted. However, in this case, there is a problem that the thickness of the device becomes too thick, and there are limits to minimizing the signal path.

Figure 4 is a cross-sectional view schematically showing a case where a 2.5D silicon interposer package is mounted on a motherboard.

As a way to solve the above-mentioned problem, a first semiconductor chip such as GPU 2220 and a second semiconductor chip such as HBM 2240 are placed side by side on the silicon interposer 2250. It can be considered to manufacture a semiconductor package 2310 including a silicon interposer using 2.5D interposer technology that packages after mounting. In this case, not only can the GPU 2220 and the HBM 2240, which have thousands to millions of connection pads, be rewired through the interposer 2250, but they can also be electrically connected through a minimal path. Additionally, the semiconductor package 2310 including the silicon interposer can be mounted again on the BGA board 2210 and rewired, and finally mounted on the main board 2110. However, in the case of the silicon interposer 2250, not only is the formation of a through silicon via (TSV) very difficult, but the manufacturing cost is also considerable, which is disadvantageous for enlarging the area and reducing the cost.

Figure 5 is a cross-sectional view schematically showing a case where a 2.5D organic interposer package is mounted on a motherboard.

As a way to solve the above-mentioned problem, it may be considered to use the organic interposer 2260 instead of the silicon interposer 2250. For example, the organic interposer is manufactured using 2.5D interposer technology, which involves surface mounting a first semiconductor chip such as GPU 2220 and a second semiconductor chip such as HBM 2240 side by side on the organic interposer 2260 and then packaging them. It may be considered to manufacture a semiconductor package 2320 that includes the semiconductor package 2320. In this case, not only can the GPU 2220 and the HBM 2240, which have thousands to millions of connection pads, be rewired through the interposer 2260, but they can also be electrically connected through a minimal path. Additionally, the semiconductor package 2310 including the organic interposer can be mounted again on the BGA board 2210 and rewired, and finally mounted on the main board 2110. In addition, it is advantageous for large area and low cost. However, in the case of the semiconductor package 2320 including such an organic interposer, when the molding process is performed, warpage may occur due to a mismatch in coefficient of thermal expansion (CTE) with the molding material of the interposer 2260 and the chips 2220 and 2240. Problems such as cracking, deterioration of underfill paper fillability, and cracks between die and molding materials may occur. Additionally, organic interposers may be disadvantageous in implementing fine patterns.

As a solution to the above-described problem, although not specifically shown in the drawings, it may be considered to separately form a silicon-based interconnection bridge with a fine pattern and insert it into the cavity of the BGA substrate. However, in this case, cavity formation and corresponding microcircuit implementation within the BGA substrate are difficult, which may lead to problems with process and yield decline. Accordingly, a new type of semiconductor package that can solve all of these problems is required.

Below, a new type of bridge embedded board that can solve reliability issues, reduce process difficulty, and improve power integrity characteristics, and a semiconductor package including the same will be described with reference to the drawings.

Figure 6 is a cross-sectional view schematically showing an example of a semiconductor package including a bridge embedded substrate.

Referring to the drawings, a semiconductor package 500 according to an example includes a bridge embedded substrate 100 and first and second electronic components 210 and 220 arranged side by side on the bridge embedded substrate 100. . First and second electrical connection metals 180 and 190 may be disposed on both sides of the bridge embedded substrate 100. The first and second electronic components 210 and 220 may be connected to the bridge embedded board 100 through a second electrical connection metal 190, respectively.

The bridge embedded substrate 100 according to one example includes one or more first insulating layers 141 and one or more first wiring layers 142 and one or more first insulating layers 141 respectively disposed on the first insulating layer 141. A first connection structure 140 including one or more first connection via layers 143 that penetrate through and are each electrically connected to the first wiring layer 142, and is disposed on the first connection structure 140 and includes one or more layers of second insulation. One or more second wiring layers 152 disposed on the layer 151 and the second insulating layer 151, respectively, and one or more layers penetrating the second insulating layer 151 and each being electrically connected to the second wiring layer 152. A second connection structure 150 including a second connection via layer 153, embedded in the first connection structure 140, and connected to the first and second wiring layers through the first and second connection via layers 143 and 153. The bridge 110 is electrically connected to (142, 152), respectively, and is embedded in the first connection structure 140, and is connected to the first and second wiring layers (142, 152) through the first and second connection via layers (143, 153). ) and passive components 120 each electrically connected. At this time, the first and second connection via layers 143 and 153 each include connection vias, and the connection vias of the first and second connection via layers 143 and 153 have a shape tapered in opposite directions.

In this way, the bridge 110, which is basically one or more organic insulating layers 111 with a circuit layer 112 and a connection via layer 113 formed on the bridge embedded substrate 100, is built into the first connection structure 140. As such, unlike conventional silicon-based bridges, the reliability problem caused by CTE mismatch can be solved even if it is embedded in the first connection structure 140. Additionally, in addition to the bridge 110, a passive component 120 is built into the first connection structure 140 at the same level. Passive components 120 may be of various types, such as capacitors and inductors. In this way, when various types of passive components 120 are embedded together with the bridge 110, when the first and second electronic components 210 and 220 are disposed on the bridge embedded substrate 100, the passive components ( 120) may be arranged so that at least a portion of the first and second electronic components 210 and 220 overlap on a plane, thereby simplifying the electrical connection path. For example, the passive component 120 may be connected very close to the power terminals of the first and second electronic components 210 and 220. Therefore, power integrity characteristics, etc. can be stably improved.

In addition, the bridge embedded substrate 100 includes a first connection structure 140 in which the bridge 110 and passive components 120 are embedded, and a second connection structure 150 disposed on the first connection structure 140. As described above, both are distinct components in that the connection vias of the first and second connection via layers 143 and 153 have a shape tapered in opposite directions. In this way, the bridge embedded board 100 includes connection structures 140 and 150, which are electrical connection paths substantially above and below the bridge 110 and the passive component 120, respectively, and provide upper and lower electrical connections. Because this is easy, the performance of the semiconductor package 500 including it or the electronic device including the semiconductor package 500 can be improved.

In addition, this type of bridge embedded board 100 arranges the bridge 110 and the passive component 120 side by side at the same level, and the bridge 110 is placed on one side of the bridge 110 and the passive component 120. It can be manufactured by forming a first connection structure 140 that buries the passive component 120 and then forming a second connection structure 150 on the other side of the bridge 110 and the passive component 120. In this case, it is easy to attach the bridge 110 and the passive component 120, and after the bridge 110 and the passive component 120 are embedded in the first connection structure 140, the second connection is made on the provided flat surface. Since the structure 150 can be formed, the process difficulty can be reduced. That is, the uppermost side of the bridge 110 and the passive component 120 facing the second insulating layer 151 of the second connection structure 150 is the first insulating layer 141 of the first connection structure 140. It can be coplanar with the uppermost side facing the second insulating layer 151 of the second connection structure 150. In other words, approximately coplanarity can be achieved.

Meanwhile, the first and second connection via layers 143 and 153 of the first and second connection structures 140 and 150 may include first to third connection vias, respectively. The first connection vias 143a and 153a of each of the first and second connection via layers 143 and 153 bridge the first and second wiring layers 142 and 152 in opposite directions with respect to the bridge 110. 110), and the second connection vias 143b and 153b of each of the first and second connection via layers 143 and 153 are connected to the first and second connection vias in opposite directions with respect to the passive component 120. The wiring layers 142 and 152 may be connected to the passive component 120, respectively. The third connection vias 143c and 153c of the first and second connection via layers 143 and 153 may be connected to each other. That is, the first and second connection via layers 143 and 153 can physically contact each other without a separate wiring layer between them.

Meanwhile, the third connection via 143c of the first connection via layer 143 may be taller than the first and second connection vias 143a and 143b. This is, unlike the first and second connection vias 143a and 143b of the first connection via layer 143, which are respectively disposed on the bridge 110 and the passive component 120, the third connection via 143c is This is because it can be placed side by side with the bridge 110 and the passive component 120. At this time, each of the bridge 110 and the passive component 120 may be located at a level between the upper and lower surfaces of the third connection via 143c of the first connection via layer 143.

Meanwhile, the bridge embedded substrate 100 may be formed through the adhesive layer 130, as will be described later. In this case, the bridge 110 and the passive component 120 are aligned with each other at the same level on the adhesive layer 130. can be placed. At this time, in the case of the first connection via layer 143, the third connection via (143c) may penetrate the adhesive layer 130, and in the case of the second connection via layer 153, the first and second connection vias ( 153a and 153b) may each penetrate the adhesive layer 130. From this perspective, the first and second connection vias 153a and 153b of the second connection via layer 153 may each be taller than the third connection via 153c. The adhesive layer 130 may be removed during the process if necessary. In this case, the first to third connection vias 153a, 153b, and 153c of the second connection via layer 153 may have substantially the same height.

Hereinafter, each component of the semiconductor package according to the example will be described in more detail with reference to the drawings.

The bridge embedded substrate 100 includes a bridge 110, a passive component 120, a first connection structure 140, and a second connection structure 150. The bridge embedded substrate 100 may further include an adhesive layer 130 disposed between the first and second connection structures 140 and 150, if necessary. In addition, if necessary, the first and second passivation layers (160, 170) and/or the first and second electrical connection metals (180, 190) disposed on the first and second connection structures (140, 150). More may be included. Additionally, if necessary, a third connection structure 195 may be further disposed between the first connection structure 140 and the first passivation layer 160.

Bridge 110 may be an organic bridge 110 . For example, the bridge 110 penetrates one or more organic insulating layers 111, a circuit layer 112 disposed on the organic insulating layer 111, and the organic insulating layer 111, respectively, and forms a circuit layer 112. ) and a connection via layer 113 connected to each other. The number of layers of the organic insulating layer 111, the circuit layer 112, and the connecting via layer 113 may be more or less than what is shown in the drawing.

The organic insulating layer 111 may include an insulating material, and in this case, the insulating material may be, for example, PID (Photo Image-able Dielectric). The boundaries of each layer of the organic insulating layer 111 may be distinct from each other or may be unclear. When PID is used as the material for the organic insulating layer 111, the thickness of the organic insulating layer 111 can be minimized and a photo via hole can be formed, so that the circuit layer 112 and the connecting via layer 113 can be formed. It can be easily designed at high density. For example, the circuit layer 112 and the connection via layer 113 can be designed to have higher density than the first wiring layer 142 and the second connection via layer 153 of the first connection structure 140. Specifically, the thickness of each circuit layer 112 may be thinner than the thickness of each first wiring layer 142, and the upper/bottom gap may be narrower. In addition, the average diameter of each connection via of the connection via layer 113 may be smaller than the average diameter of each connection via of the first connection via layer 143, the height or thickness may also be smaller, and the pitch may be finer (Fine pitch). Pitch), the pitch between vias may be narrower. Even when a different material is used as the insulating material of the organic insulating layer 111, the circuit layer 112 and the connection via layer 113 are designed to have a higher density than the first wiring layer 142 and the first connection via layer 143. It is desirable to do so.

The circuit layer 112 substantially electrically connects the first and second electronic components 210 and 220 to each other. The circuit layer 112 can perform various functions depending on the design of the corresponding layer, but includes at least a signal pattern and a signal pad. The circuit layer 112 is made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Conductive materials such as, specifically, metal materials can be used.

The connection via layer 113 electrically connects the circuit layers 112 formed in different layers, and as a result, forms an electrical path within the bridge 110. Each connection via layer 113 may include a plurality of connection vias. Each connection via of the connection via layer 113 is made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti). , or conductive materials such as alloys thereof, specifically metal materials. The connection via layer 113 may perform various functions depending on the design of the corresponding layer, but includes at least a signal via. Each connection via of the connection via layer 113 may be a field type filled with a conductive material, or a conformal type in which a conductive material is disposed along the wall of the via. Each connection via of the connection via layer 113 may have a tapered shape in the same direction as each connection via of the first connection via layer 143.

There may be one or more passive components 120. Each passive component 120 may be the same or different from each other. The passive component 120 may be a known passive component such as a capacitor or inductor. Each of the passive components 120 may have an external electrode. That is, the passive components 120 may each be independent chip-type components. At least one of the first and second electronic components 210 and 220 is preferably disposed directly above the at least one passive component 120. Through this arrangement, a minimum electrical path can be provided and power supply stability can be achieved.

The adhesive layer 130 may be a known adhesive tape. The adhesive layer 130 may be disposed between the first and second connection structures 140 and 150. The bridge 110 and the passive component 120 may be attached to the adhesive layer 130 at the same level and in parallel with each other. Accordingly, each surface attached to the adhesive layer 130 of the bridge 110 and the passive component 120 can be coplanared. In other words, approximately coplanarity can be achieved. The material of the adhesive layer 130 is not particularly limited, and may include a known insulating resin having adhesive properties. The adhesive layer 130 may be removed during the process. Even in this case, each surface exposed from the first connection structure 140 of the bridge 110 and the passive component 120 may be coplanar.

The first connection structure 140 penetrates one or more first insulating layers 141, one or more first wiring layers 142 respectively disposed on the first insulating layer 141, and the first insulating layer 141. and includes a first connection via layer 143 connected to one or more first wiring layers 142. The first connection structure 140 covers the bridge 110 and the passive component 120 and may have a considerable thickness. That is, the first connection structure 140 may be thicker than the second and third connection structures 150 and 195, respectively, and the scale of the first wiring layer 142 and the first connection via layer 143 is also similar to the second and third connection structures 150 and 195. It may be larger than the scale of the third wiring layer (152, 192) and the second and third connection via layers (153, 193). The number of layers of the first insulating layer 141, the first wiring layer 142, and the first connection via layer 143 may be more or less than what is shown in the drawing.

The first insulating layer 141 may include an insulating material, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or these resins are mixed with an inorganic filler, or glass together with an inorganic filler. Resins impregnated into fibers (glass fiber, glass cloth, glass fabric), for example, prepreg, Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), etc. may be used.

The first wiring layer 142 performs various functions within the first connection structure 140 according to the design of the corresponding layer. For example, it may include a ground pattern, power pattern, signal pattern, etc. Here, the signal pattern includes various signals excluding ground patterns, power patterns, etc., such as data signals. Additionally, it may include various pads. Materials forming the first wiring layer 142 include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti). ), or conductive materials such as alloys thereof, specifically metal materials, may be used.

The first connection via layer 143 electrically connects the first wiring layers 142 formed in different layers to each other, and also connects the first wiring layer 142 to the second wiring layer 1521, the bridge 110, and the passive components. It is also electrically connected to (120). As a result, an electrical path is formed within the first connection structure 140. Each of the first connection via layers 143 may include a plurality of connection vias. Each connection via is made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. It may contain a conductive material, specifically a metal material. Each connection via may include a ground via, a power via, a signal via, etc. Each connection via may be a fieldd type filled with a conductive material, or a conformal type in which a conductive material is disposed along the wall of the via. Each connection via may have a tapered shape in the opposite direction to each connection via of the second connection via layer 153.

The second connection structure 150 penetrates one or more second insulating layers 151, one or more second wiring layers 152 respectively disposed on the second insulating layer 151, and the second insulating layer 151. and includes a second connection via layer 153 connected to one or more second wiring layers 152. The second connection structure 150 may be implemented in a fine design to be thinner than the first connection structure 140. For example, the second wiring layer 152 and the second connection via layer 153 can be designed to have higher density than the first wiring layer 142 and the first connection via layer 143. Specifically, the thickness of each second wiring layer 152 may be thinner than the thickness of each first wiring layer 142, and the upper/bottom gap may be narrower. In addition, the average diameter of each connection via in the second connection via layer 153 may be smaller than the average diameter of each connection via in the first connection via layer 143, the height or thickness may also be smaller, and the pitch may be finer. (Fine Pitch), the pitch between vias can be narrower.

The second insulating layer 151 may include an insulating material, for example, a photosensitive insulating material (PID), or alternatively, it may include a non-photosensitive insulating material, such as ABF. The second wiring layer 152 also performs various functions within the second connection structure 150 depending on the design of the corresponding layer. For example, it may include a ground pattern, power pattern, signal pattern, etc. Here, the signal pattern includes various signals excluding ground patterns, power patterns, etc., such as data signals. Additionally, it may include various pads. Materials forming the second wiring layer 152 include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti). ), or conductive materials such as alloys thereof, specifically metal materials, may be used.

The second connection via layer 153 electrically connects the second wiring layers 152 formed in different layers to each other, and also connects the second wiring layer 152 to the first wiring layer 142, the bridge 110, and the passive components. It is also electrically connected to (120). As a result, an electrical path is formed within the second connection structure 150. Each second connection via layer 153 may include a plurality of connection vias. Each connection via is made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. It may contain a conductive material, specifically a metal material. Each connection via may include a ground via, a power via, a signal via, etc. Each connection via may be a fieldd type filled with a conductive material, or a conformal type in which a conductive material is disposed along the wall of the via. Each connection via may have a tapered shape in the opposite direction to each connection via of the first connection via layer 143.

The third connection structure 195 penetrates one or more third insulating layers 191, one or more third wiring layers 192 respectively disposed on the third insulating layer 191, and the third insulating layer 191. and includes a third connection via layer 193 connected to one or more third wiring layers 192. The third connection structure 195, like the second connection structure 150, may be implemented with a fine design to be thinner than the first connection structure 140. For example, the third wiring layer 192 and the third connection via layer 193 can be designed to have higher density than the first wiring layer 142 and the first connection via layer 143. Specifically, the thickness of each third wiring layer 192 may be thinner than the thickness of each first wiring layer 142, and the upper/bottom gap may be narrower. In addition, the average diameter of each connection via in the third connection via layer 193 may be smaller than the average diameter of each connection via in the first connection via layer 143, the height or thickness may also be smaller, and the pitch between vias may be smaller. may be narrower.

The third insulating layer 191 may include an insulating material, for example, a photosensitive insulating material (PID), or alternatively, it may include a non-photosensitive insulating material, such as ABF. The third wiring layer 192 performs various functions within the third connection structure 195 according to the design of the corresponding layer. For example, it may include a ground pattern, power pattern, signal pattern, etc. Here, the signal pattern includes various signals excluding ground patterns, power patterns, etc., such as data signals. Additionally, it may include various pads. The materials forming the third wiring layer 192 include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti). ), or conductive materials such as alloys thereof, specifically metal materials, may be used.

The third connection via layer 193 electrically connects the third wiring layers 192 formed in different layers to each other, and also connects the third wiring layer 192 to the first wiring layer 142, bridge 110, and passive components. It is also electrically connected to (120). As a result, an electrical path is formed within the third connection structure 195. Each of the third connection via layers 193 may include a plurality of connection vias. Each connection via is made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. It may contain a conductive material, specifically a metal material. Each connection via may include a ground via, a power via, a signal via, etc. Each connection via may be a fieldd type filled with a conductive material, or a conformal type in which a conductive material is disposed along the wall of the via. Each connection via may have a tapered shape in the same direction as each connection via of the first connection via layer 143.

The first and second passivation layers 160 and 170 may be disposed on the first and second connection structures 140 and 150, respectively, to protect them. When the third connection structure 195 is further disposed, the first passivation layer 160 may be disposed on the third connection structure 195. The first and second passivation layers 160 and 170 may include an insulating material, for example, a photosensitive insulating material (PID), or alternatively, may include a non-photosensitive insulating material, such as ABF. It may be possible. The first and second passivation layers 160 and 170 are the first and second wiring layers 142 and 152, respectively, or the third and second wiring layers 192 and 152 when the third connection structure 195 is further disposed. It may have an opening that exposes at least a portion of the.

The first and second electrical connection metals 180 and 190 may each be formed of a low melting point metal, for example, solder such as tin (Sn)-aluminum (Al)-copper (Cu). This is only an example and the material is not particularly limited to this. The first and second electrical connection metals 180 and 190 may be lands, balls, pins, etc. The first and second electrical connection metals 180 and 190 may be formed as multiple layers or a single layer. When formed as a multi-layer, it may contain copper pillars and solder, and when formed as a single layer, it may contain tin-silver solder or copper, but this is only an example and is not limited thereto. .

The first and second electronic components 210 and 220 may each be semiconductor chips. At this time, the semiconductor chip may include an integrated circuit (IC) in which hundreds to millions of elements are integrated into one chip. At this time, the integrated circuit is, for example, a processor such as a central processor (eg, CPU), graphics processor (eg, GPU), field programmable gate array (FPGA), digital signal processor, cryptographic processor, microprocessor, microcontroller, etc. It may be a chip, specifically an application processor (AP), but is not limited thereto, and may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and HBM (High Bandwidth Memory). Of course, it may be a memory chip such as an analog-to-digital converter, a logic chip such as an ASIC (application-specific IC), or another type such as a PMIC (Power Management IC). As a non-limiting example, the first electronic component 210 may include a processor chip such as AP, and the second electronic component 2200 may include a memory chip such as HBM, but are not limited thereto.

The first and second electronic components 210 and 220 may each be formed based on an active wafer. In this case, the base material forming each body is silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. This can be used. Various circuits may be formed in the body. A connection pad (not shown) may be formed on each body to electrically connect the first and second electronic components 210 and 220 with other components, and the connection pad (not shown) is made of aluminum (Al), It may contain a conductive material such as copper (Cu). The first and second electronic components 210 and 220 may each be a bare die, in which case a bump (not shown) is disposed on a connection pad (not shown) to form the second electrical connection metal 190. It can be surface mounted on the bridge built-in board 100 via . However, the present invention is not limited to this, and the first and second electronic components 210 and 220 may be packaged dies.

7 to 10 are process diagrams schematically showing an example of manufacturing the bridge embedded substrate of FIG. 6.

Referring to FIG. 7, first prepare the carrier 300. The carrier 300 may be a detach film in the form of a copper clad laminate (CCL). Next, an adhesive layer 130 is formed on the carrier 300. Next, the previously manufactured bridge 110 and passive component 120 are attached side by side on the adhesive layer 130.

Referring to FIG. 8, next, a first insulating layer 141 covering the bridge 110 and the passive component 120 is formed on the adhesive layer 130 using ABF, etc., and a first insulating layer 141 is formed on the first insulating layer 141. After processing the via hole using a laser drill, etc., the first wiring layer 142 and the first connection via layer 143 are formed through a plating process. Next, a series of processes are repeated as necessary to form the first connection structure 140. Next, the carrier 300 is removed, and the metal film (not shown) remaining on the adhesive layer 130 is removed by etching.

Referring to FIG. 9, next, a second insulating layer 151 is formed using PID or ABF on the side of the adhesive layer 130 opposite to the side where the first connection structure 140 is formed. If necessary, the adhesive layer 130 may be removed beforehand. In this case, the second insulating layer 151 is formed on the side of the first connection structure 140 where one surface of the bridge 110 and the passive component 120 is exposed. Next, after processing the via hole using photolithography and/or a laser drill, the second wiring layer 152 and the second connection via layer 153 are formed through a plating process.

Referring to Figure 10, next, a series of processes are repeated as necessary to form the second connection structure 150. At this time, if necessary, the third insulating layer 191, the third wiring layer 192, and the third connection via layer 193 are formed on the opposite side in the same manner to form the third connection structure 195. Next, if necessary, the first and second passivation layers 160 and 170 are formed on both sides using ABF, etc., and an opening is formed in each, to manufacture the bridge embedded substrate 100 according to the above-described example. You can.

In the present disclosure, the lower side, bottom, lower surface, etc. are used to refer to the direction toward the mounting surface of the semiconductor package including the organic interposer based on the cross section of the drawing for convenience, and the upper side, top, upper surface, etc. are used in the opposite direction. did. However, this direction is defined for convenience of explanation, and it goes without saying that the scope of the patent claims is not particularly limited by the description of this direction.

In the present disclosure, the meaning of connected is a concept that includes not only directly connected, but also indirectly connected through an adhesive layer or the like. Additionally, the meaning of being electrically connected is a concept that includes both physically connected cases and non-connected cases. Additionally, expressions such as first, second, etc. are used to distinguish one component from another component and do not limit the order and/or importance of the components. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component without departing from the scope of rights.

The expression 'example' used in the present disclosure does not mean identical embodiments, but is provided to emphasize and explain different unique features. However, the examples presented above do not exclude being implemented in combination with features of other examples. For example, even if a matter explained in a specific example is not explained in another example, it can be understood as an explanation related to the other example, as long as there is no explanation contrary to or contradictory to the matter in the other example.

The terminology used in this disclosure is used to describe examples only and is not intended to limit the disclosure. At this time, singular expressions include plural expressions, unless the context clearly indicates otherwise.

Claims (10)

A first connection structure including a first wiring layer and a first connection via layer electrically connected to the first wiring layer;
a second connection structure disposed on the first connection structure and including a second wiring layer and a second connection via layer electrically connected to the second wiring layer;
a bridge embedded in the first connection structure and electrically connected to the first and second wiring layers through the first and second connection via layers, respectively; and
Passive components embedded in the first connection structure and electrically connected to the first and second wiring layers through the first and second connection via layers, respectively; Includes,
The first and second connection via layers each include a connection via,
The connection vias of the first and second connection via layers are tapered in opposite directions,
Bridge built-in board.
According to claim 1,
The bridge and the passive component are each embedded in the first connection structure parallel to each other at the same level,
Bridge built-in board.
According to claim 2,
The first and second connection structures include first and second insulating layers on which the first and second wiring layers and the first and second connection via layers are disposed, respectively,
The uppermost side facing the second insulating layer of each of the bridge and the passive component is coplanar with the uppermost side facing the second insulating layer of the first insulating layer,
Bridge built-in board.
According to claim 2,
The first and second connection via layers each include first to third connection vias,
The first connection vias of each of the first and second connection via layers respectively connect the first and second wiring layers to the bridge in opposite directions with respect to the bridge,
The second connection vias of each of the first and second connection via layers respectively connect the first and second wiring layers to the passive component in opposite directions with respect to the passive component,
The third connection vias of each of the first and second connection via layers are connected to each other,
Bridge built-in board.
According to claim 4,
The third connection via of the first connection via layer is taller than the first and second connection vias of the first connection via layer,
The bridge and the passive component are each located at a level between the upper and lower surfaces of the third connection via of the first connection via layer,
Bridge built-in board.
According to claim 4,
an adhesive layer disposed between the first and second connection structures; It further includes,
The bridge and the passive component are each attached to the adhesive layer in parallel with each other at the same level and each embedded in the first connection structure,
Bridge built-in board.
According to claim 6,
The third connection via of the first connection via layer penetrates the adhesive layer,
The first and second connection vias of the second connection via layer each penetrate the adhesive layer,
Bridge built-in board.
According to claim 1,
The first connection structure is thicker than the second connection structure,
Bridge built-in board.
According to claim 1,
The bridge includes an organic insulating layer, a circuit layer disposed on the organic insulating layer, and a connection via layer that penetrates the organic insulating layer and is connected to the circuit layer.
Bridge built-in board.
The bridge built-in board according to any one of claims 1 to 9; and
first and second electronic components arranged side by side on the second connection structure and each electrically connected to the second wiring layer; Includes,
The first and second electronic components are electrically connected to each other through the bridge,
The passive component is arranged so that at least a portion of the passive component overlaps at least one of the first and second electronic components on a plane,
Semiconductor package.

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