KR20200125621A - Wireless receiver - Google Patents

Abstract

The present invention relates to an SDR type wireless receiver 10 for use in a power self-sufficient, preferably power self-sufficient environment for a long period of time, wherein the wireless receiver 10 includes at least one data packet or part of a data packet. Or a receiver 1 that receives data 2 in the form of a data stream having a specific data rate and provides it for further data processing. In operation mode A, data 2 is switched in receiver 1 and transmitted to microcontroller 3, preferably at a definable sampling rate, which microcontroller 3 selects some data from the sampled quantity The decimated data are decimated, and the microcontroller 3 buffers the decimated data in the memories 4 and 18 and provides this for further processing.

Description

Wireless receiver

The invention relates to a wireless receiver according to claim 1, a wireless receiver as claimed in claim 2, and a communication system for transmitting data.

A wireless receiver of the software defined radio (SDR) type of interest of the present invention is typically used in battery-powered stationary sensor devices, especially those employing unidirectional or bidirectional data transmission, for example wireless It includes a receiving device such as a chip. For example, the data to be received is data for operating the sensor device, such as update data, program data, control data, etc., transmitted from the concentrator to the wireless receiver. The smallest possible energy consumption at the wireless front-end is that the data or data messages are transmitted by the concentrator as individual data packets, or parts thereof (e.g. data subpackets), not as single pieces, but in fragmented form, And one of the reasons why it is received by the wireless receiver in this form.

Conventional radio chips are usually low-cost components with the ability to be permanently integrated within the radio chip, and can only be modified to a very limited extent. Particularly for narrowband wireless transmission, for example the sampling rate must be precisely tailored, but this cannot be precisely set in the radio chip. If the sampling rate is not precisely tailored, extensive processing effort is required for resampling, which then requires a corresponding large amount of electrical energy, and this is undesirable or possible because the environment is self-sufficient in energy. I didn't. In addition, the A/D converter (analog-to-digital converter) included in the wireless chip is typically provided with a clock by a clock generator, and thus the sampling rate of the wireless chip is bound to be set very incorrectly. At the same time, particularly for the aforementioned applications, it is an object of the present invention to provide a wireless receiver with a maximum possible distance.

Nearest prior art

EP 3 002 560 B1 discloses a battery-powered fixed terminal (or more precisely a sensor device) for performing wireless one-way transmission. The terminal includes a sensor for acquiring sensor data and providing a sensor data packet based on the sensor data. A device for generating a data packet is used to divide the sensor data packet into at least three data packets, each of which is shorter than the sensor data packet itself. Further, the sensor device comprises a device for transmitting data packets, which is intended to transmit the data packets over a communication channel spaced apart in time with a data rate of less than 50 kbit/s. Since the data rate is low compared to the conventional data rate of 100 kbit/s, it becomes possible to reduce the signal-to-noise ratio in the data receiver (concentrator). Moreover, the device for generating the data packet channel-codes the data packet such that only a subset of the data packet is required to decode the sensor data packet. Thus, the transmission distance from the terminal to the concentrator is increased by using this type of terminal. However, even with such a terminal, the data transmission efficiency transmitted from the concentrator to the terminal cannot be improved.

Accordingly, it is an object of the present invention to provide a wireless receiver having both an improved data transmission quality and an optimized power consumption, in particular a type of terminal of interest.

The above-described objects are achieved by a wireless receiver as claimed in claim 1 and a further independent claim. Further claims define preferred embodiments of the invention.

The wireless receiver according to the present invention may be an SDR-type wireless receiver. In the meaning of the present invention, "SDR type" covers designs for radio frequency transmitters and receivers, in which signal processing is to some extent implemented by software. For this purpose, the wireless receiver is a receiving device that receives data in the form of at least one data packet or part of a data packet (data subpacket) or a data stream having a specific data rate, and provides the data for further data processing. (For example, a wireless chip). In particular, the data stream may be a continuous data stream or a semi-continuous data stream (ie, including a dormant period).

In operation mode A, data is diverted within the receiving device and supplied to the microcontroller, where the microcontroller or receiving device selects the data, i.e. the microcontroller or receiving device selects only a subset of the set of samples to decimation. And, thanks to the fact that the microcontroller buffers the decimated data in memory and provides it for further processing, the microcontroller does not have great processing power and without any resampling, the data can be supplied for further processing. Only relatively little energy is used for this, and as a result, only a small load is placed on its own energy source. Through this, power consumption is reduced or optimized, while data transmission quality is improved.

The receiving device preferably includes a filter, which filters the data before feeding it to the microcontroller, in order to reduce unnecessary processing operations on the part of the microcontroller. Therefore, data transmission quality is further improved and energy consumption is further reduced.

Further, the data can be decimated by the microcontroller by the microcontroller ignoring, ie discarding, individual samples of a set of samples, and the samples are selected based on an integer decimation factor. This will reduce the transmitted set of samples, and then the bandwidth for transmitting data between the receiving device and the microcontroller can also be reduced. Thus, the sampling rate represents the maximum possible unfiltered bandwidth between the receiving device and the microcontroller, and is preferably equal to an integer factor of the bandwidth used after the filter (filtered bandwidth).

It has been found to be particularly advantageous if the bandwidth of the data provided to the microcontroller, or the bandwidth used after the filter, is preferably less than 200 kHz, preferably less than 100 kHz and more preferably less than 50 kHz.

Since different sampling rates can be specified in the microcontroller for different bandwidths, the transmission of data can be adapted to different or rapidly changing transmission conditions. In this case, different data rates may be supported within the wireless system in order to adapt the rates, for example to rapidly changing transmission conditions. Therefore, different sampling rates and hence bandwidths are required for different data rates. This further improves the data transmission quality.

It is desirable to provide an oscillator comprising a clock generator, preferably a crystal oscillator or an RF crystal or crystal oscillator. The sampling rate is preferably defined by the clock frequency (or correction frequency) of the clock generator. The clock generator can also serve as a clock for the analog-to-digital converter. As a result, by changing the clock frequency or selecting a clock generator having a certain clock frequency, the clock of the analog-to-digital converter is also changed accordingly. do. Taking into account the decimation factor, the clock frequency is specified or selected here to obtain the desired sampling rate. This avoids complicated resampling by the microcontroller.

The clock frequency of the clock generator is between 20 MHz and 50 MHz, preferably between 23 MHz and 25 MHz, between 38 MHz and 40 MHz or between 47 MHz and 49 MHz, more preferably between 24 MHz, 39 MHz or 48 MHz. It has been found that it is particularly advantageous.

It is preferable that the sampling error occurring during sampling can be changed by selecting the clock frequency of the clock generator. Advantageously, the clock frequency is reduced in this process.

It is particularly preferred if the error in the clock generator or crystal after changing the clock frequency is less than 10 ppm, preferably less than 5 ppm, more preferably less than 3 ppm.

It is preferable that the wireless receiver is capable of enabling and disabling operation mode A. Then, data reception and transmission, or additional processing can be selectively performed through operation mode A, and can be enabled and/or disabled during operation, thus flexibly responding to changes in transmission and processing procedures. The advantage of making it possible to do so is obtained as a result. Therefore, data transmission quality and processing reliability are greatly improved.

According to a preferred embodiment, operation mode C may be provided in addition to operation mode A, in which data is processed by a microprocessor or logic circuit or digital receiving circuit, which is connected after the receiving device and/ Or it is part of the receiving device. It is particularly advantageous if the wireless receiver is designed to be able to switch between operating mode A and operating mode C. This can in particular be carried out using a switchover device, for example an internal part of the receiving device.

The data is transmitted between the receiving device and the microcontroller, preferably in a fragmented manner, ie in steps, with a time interval at which no transmission occurs is provided between the data transmission steps.

According to a preferred embodiment, during a time interval in which no data is transmitted, the microcontroller can be shifted to a standby or sleep mode to reduce energy consumption within this time period. This can save energy, and therefore, can extend the service life or life of a battery-powered terminal that is energy self-sufficient, for example.

Advantageously, the microcontroller may be configured to decode the data. Then an additional decoder is economically implemented.

Alternatively or additionally, it is also possible for the microcontroller to be intended to handle higher layers (especially those of the OSI layer model). In this case, for example, the microcontroller may be responsible for programming and/or executing functions of the terminal, for example functions such as sensor control or evaluation of sensor readings. Therefore, it is possible to economically implement an additional microcontroller for controlling the sensor, thereby greatly reducing energy consumption and manufacturing cost.

It is preferred that the receiving device, microcontroller and/or decoder can be implemented as a common constituent unit. It has been found to be particularly advantageous if the receiving device, microcontroller and/or decoder are in the form of an integrated circuit (IC). The advantage is then that the IC can be easily and particularly economically installed in/on a wireless receiver.

The data is preferably processed using an I/Q technique (in-phase/orthogonal phase technique) after entering the receiving device, ie the data is digital I/Q data. This can be done, for example, by dividing the analog input signal into two signal components, where one signal component is generated within its original phase (I data) and the other signal component is a reference frequency shifted by 90°. Is generated as (Q data).

The SDR-type radio receiver is intended for use in an energy self-contained environment, preferably a long-term energy self-contained environment. Within the meaning of the present invention, energy self-sufficiency or long-term energy self-sufficiency means, in particular, an operation mode in which a radio receiver or a terminal including a radio receiver is operated without external energy supply and can independently perform or maintain an operation. Is understood to mean. It is desirable to draw the energy required for operation from an energy storage device or energy source. It is preferred that a battery fitted within the radio receiver or terminal and, where applicable, encapsulated free from dust or water is provided as the energy source. In particular, the battery has a capacity of less than 20 Ah. In addition, means for obtaining electrical energy may be provided (energy harvesting), in which case the electrical energy required for operation may be from air flow, ambient light, ambient temperature, or vibration (for example by piezoelectric effect). Is obtained. It can preferably be provided, in which case it is possible to further optimize the power consumption, especially in the case of the current SDR concept.

In addition, the present invention claims an SDR-type wireless receiver for use in an energy self-contained environment, preferably a long-term energy self-sufficient environment, which is at least one data packet or part of a data packet or a specific data rate (and/ Or a receiving device that receives data in the form of a data stream (which is a specific sampling rate) and provides it for further data processing. In this case, in operation mode B, data is supplied to a microprocessor or digital receiving circuit (logic circuit), each of which is included in the receiving device. The data is then filtered by a microprocessor or digital receiving circuit and then decimated, which is done by a microprocessor or digital receiving circuit that selects a subset from a set of samples. In practice, decimation may be performed by algorithmic procedures or signal processing (eg decoding, demodulation and/or such similar processing), for example by microprocessors and microcontrollers. However, alternatively or additionally, the microprocessor may further perform algorithmic procedures or signal processing.

It is preferable that the wireless receiver is capable of enabling and disabling operation mode B. Furthermore, in addition to operation mode B, operation mode C may also be provided, in which case the wireless receiver can switch between operation mode B and operation mode C using a switchover device.

A further radio receiver claimed in another independent claim is a radio receiver of the type in which the signal processing is implemented at least mostly, preferably entirely, by hardware (eg as a prefabricated hardware module). Consequently, it is clear that this is not an SDR-type radio receiver. For example, such a wireless receiver can be implemented entirely as an application specific integrated circuit (ASIC). Therefore, the function of the wireless receiver can no longer be changed using software. The use of such a wireless receiver can significantly reduce manufacturing costs. In this case, the wireless receiver comprises a clock generator, in particular a crystal oscillator. By selecting a clock generator with a suitable clock frequency, the sampling error is corrected, especially reduced. Therefore, the sampling error can be defined or controlled by selecting a clock frequency or by selecting a clock generator having a specific clock frequency. Advantageously, the wireless receiver can also be designed to be able to operate in operating modes A, B and/or C.

In another independent claim, the invention claims a communication system for transmitting data between at least one concentrator and a plurality of, in particular, a plurality of terminals that are energy self-sufficient. In this case, each terminal receives data from the concentrator at least one data packet, preferably in the form of a plurality of individual data packets, and at a specific data rate (and/or a specific sampling rate) for further data processing. It includes a wireless receiver having a receiving device to provide. Further, the wireless receiver according to the invention is provided as a wireless receiver that, in operation mode A, converts data in the receiving device and supplies said data to a microcontroller, preferably at a definable sampling rate. In this case, the microcontroller or receiving device decimates the data by selecting a subset from a set of samples. The microcontroller then buffers the decimated data in memory and provides the data, for example for further processing. Alternatively or additionally, the wireless receiver may also supply the data to a microprocessor or digital receiving circuit (each of which is included in the receiving device), in operation mode B, and filter the data using the microprocessor or digital receiving circuit. , We can decimate the data by selecting a subset of the set of samples.

Advantageous embodiments of the invention are described in detail with reference to the accompanying drawings:
1 is a simplified schematic diagram of a communication system including a plurality of terminals and a concentrator;
2 is a simplified schematic diagram of data transmitted in the form of a plurality of data packets;
3 is a simplified schematic diagram of a wireless receiver according to the prior art;
4 is a simplified schematic diagram of a first embodiment of a wireless receiver according to the present invention;
5 is a simplified schematic diagram of a further embodiment of a wireless receiver according to the present invention;
6 is a simplified schematic diagram of a further embodiment of a wireless receiver according to the present invention;
7 is a simplified schematic diagram of a further embodiment of a wireless receiver according to the present invention;
8 is a simplified schematic diagram of a further embodiment of a wireless receiver according to the present invention;
9 is a schematic diagram of different modes of operation;
10 is a simplified schematic diagram of a further embodiment of a wireless receiver according to the present invention; And
11 is a simplified schematic diagram of a further embodiment of a wireless receiver according to the present invention.

1 is a communication system of the present invention in which a plurality of terminals 11 each having an integrated radio receiver 10 of an SDR (software-based radio communication) type communicate wirelessly with a transceiver 13 of a data collector 12 Shows. For example, the terminal 11 may be a consumption meter such as a gas, water, heating or energy meter, for example a level sensor or a temperature measuring device, or a sensor unit such as another sensor node, for example an Internet of Things (IoT) application. Can be The receiving device 1 may be implemented with a wireless chip, a system-on-chip (SoC), a system-on-silicon (SoS), a system-in-package (SIP), or the like. Obviously, neither the terminal 11 nor the receiving device 1 is a gateway. The data collector 12 is here configured such that it can transmit the data 2 to the terminal 11 and/or receive the data from the terminal via the transceiver 13.

For example, the data 2 may be operational data or program update data or firmware update data, which is in particular transmitted from the data collector 12 to the terminal 11. The data collector 12 receives the data 2, for example from a higher level central unit (not shown in the drawing), stores the data in the data memory 14, and then stores the data in the terminal 11 ) Can be sent. In this process, the data 2 is transmitted in the form of at least one data packet, preferably a plurality of data packets 2a, as shown in FIG. 2.

3 shows a wireless receiver 110 of a type of interest known in the prior art. In this case, in operation mode C, the receiving device 101 of the wireless receiver 110 receives the data 2 or the data packet 2a as an analog input signal, and demodulates it. An analog-to-digital converter (not shown in the figure) is provided to convert an analog input signal into a digital data stream. A microprocessor 115 assigned to or connected to the receiving device 101 is used for further processing and/or delivery of the data 2. In addition, the wireless receiver 110 includes an oscillator or clock generator, which is used to specify the frequency used.

4 shows an embodiment of a wireless receiver 10 according to the present invention. The wireless receiver 10 comprises a receiving device 1 and a microcontroller 3 and is preferably implemented as a common constituent unit, for example an integrated circuit (IC). According to the invention, data 2 or data packets 2a received as analog signals are switched within the receiving device 1 and supplied to the microcontroller 3 via the interface 1a. The receiving device 1 prepares the data in a way that reduces or even avoids complex processing operations by the microcontroller 3 without any substantial deterioration, for example as a result of aliasing. This is, preferably, first digitizing the data 2 using an analog-to-digital converter (not shown in the drawing) disposed in the receiving device 1, and using the filter 6 of the receiving device 1 to It is done by filtering. In this case, the digitized data is provided to the microcontroller 3 at a bandwidth below the sampling rate, for example below 50 kHz. The filter 6 then filters the data 2 in a way that the microcontroller 3 does not need to perform any further filtering. Here, the sampling rate describes how often the second analog signal (time-continuous signal) is sampled in one second, i.e. measured and converted to a time-discrete signal. For example, a value of 2 kHz or 4 kHz indicates that each of 2000 or 4000 samples is taken within one second. Here, the sampling rate to the microcontroller 3 defines the bandwidth, that is, the sampling rate represents the maximum unfiltered bandwidth that can be set between the receiving device 1 and the microcontroller 3. For example, for a sampling rate of 20 kHz, a maximum bandwidth of 20 kHz is theoretically possible, but as a result of filtering by the filter 6, the transmission to the microcontroller 3 takes place only at a bandwidth of 10 kHz ( Factor = 2).

Therefore, the bandwidth for transmitting the data 2 from the receiving device 1 to the microcontroller 3 is less than or equal to the sampling rate. This can in particular be achieved by a microcontroller 3 decimating the data 2 in the decimation unit 7 with a definable decimation factor N, i.e. the microcontroller 3 is the receiving device 1 Select a subset of the set of samples supplied by. The decimation factor N is preferably an integer, for example 2, 3 or 4. For example, in the case of the decimation factor N=2, the microcontroller 3 omits the second sample every time, and as a result, the bandwidth becomes smaller than the sampling rate by a factor of 2.

As an alternative or in addition to the filter 6, the microcontroller 3 may further comprise a filter 8 as shown in FIG. 5. Then, the microcontroller 3 may store or buffer the decimated data in the memory 4, for example, a block, in order to provide the decimated data for further processing, for example. Here, the crystal oscillator 5 is used as a clock generator for frequency conditioning and carrier frequency, and for providing a clock to an analog-to-digital converter. One of the structures functionally belonging to the external unit or the receiving device 1 can be provided as a clock generator. In order to change the clock supplied to the analog-to-digital converter accordingly, the sampling rate is specified in particular by changing the clock frequency of the crystal oscillator 5 accordingly, or by selecting the crystal oscillator 5 based on its clock frequency. . The clock frequency is specified to cause the crystal oscillator 5 to specify the required sampling rate, along with a division or decimation factor N. Therefore, there is no need for additional filtering or energy-intensive resampling in the portion of the microcontroller 3.

The data 2 is preferably processed using an I/Q technique (positive phase/orthogonal technique) after entering the receiving device 1 and converted into I/Q data (digital data). This can be done by dividing the analog input signal into two signal components, where one signal component is demodulated to its original phase (I data) and the other signal component is demodulated to a reference frequency shifted by 90° ( Q data). Then, the I/Q data is transferred to the microcontroller 3 by the receiving device 1. Then, the microcontroller 3 can additionally process the data in an algorithm procedure or use the data for signal processing.

The operation modes shown in FIGS. 4 and 5 indicate, for example, a first operation mode A that can be selectively enabled and disabled in the wireless receiver 10 even during operation. Further, the operation mode C indicated by the dotted arrow in FIGS. 4 and 5 may be provided in addition to the operation mode A. In this embodiment of the wireless receiver 10, the selection or switchover device 9 may be used to select or switch between operation mode A and operation mode C.

The embodiment of the wireless receiver shown in Fig. 6 is operated using operation mode C. For this purpose, the receiving device 1 comprises a microprocessor 15, which can alternatively also be implemented as a digital receiving circuit. In this case, the microprocessor 15 is part of an RF front-end containing an analog-to-digital converter (not shown in the figure for clarity). Further, the microprocessor 15 may include a filter 6 and a dedicated memory, in particular a RAM memory 16. Alternatively or additionally, as shown in FIG. 7, a shared (RAM) memory 18 may be provided, which the microcontroller 3 and the microprocessor 15 can access via, for example, a BUS system. have. Furthermore, additional modes of operation may be provided, which are represented by dashed lines and arrows by way of example in FIGS. 6 and 7. Switchover between the operation mode B and the additional operation mode can be performed through the switchover device 9 even during operation.

Figure 8 shows another alternative embodiment of the invention, in which the microprocessor 15 of the receiving device 1 comprises a filter 6 and additionally has a decimator 17, i.e. the microprocessor 15 ) Filters and decimates this data before providing this data to the microcontroller 3 for signal processing and/or storing this data in the memory 18. In this case, it is optional to mount the filter 8 and decimation unit 7 on the microcontroller 3. Preferably, in this case the microcontroller 3 has better efficiency for the required task, or has better performance than the microprocessor 15. However, as long as it already has the required processing efficiency, algorithmic procedures or signal processing can also be performed by the microprocessor 15.

In addition, FIG. 9 shows different operating modes I, II and III of the wireless receiver 10. The receiving device 1 or the microprocessor 15 first performs filtering using the filter 6. In particular, the filter 6 may be a high-pass, low-pass, or band-pass filter. If the filtering is performed well enough for decimation, the data can be transmitted to the microcontroller 3 according to the operation mode I, and the microcontroller uses only the Nth samples and discards the remaining samples, thereby decimation unit Decimate these data by a decimation factor N (e.g. 2 or 4) using (7). The microcontroller 3 subsequently performs algorithmic procedures or signal processing. If it was not possible to perform the filtering well enough for decimation, the data is first filtered in the microcontroller 3 by means of a filter 8 according to operation mode II in order to achieve at least suitable filtering, and then It is decimated by the decimation unit 7. Further, according to operation mode III, the data is filtered by the microprocessor 15 of the receiving device 1 or the digital receiving circuit through the filter 6, after which the decimator 17 of the microprocessor 15 is It is also possible to be decimated using. Then, the decimated data is transmitted to the microcontroller 3 for algorithm procedure or signal processing, or the microprocessor 15 can easily perform the algorithm procedure or signal processing. In particular, operation modes I and II can be realized through operation mode A, for example, and operation mode III can be realized through operation mode B, for example.

10 shows an additional wireless receiver 210 according to the present invention, which is a type in which all signal processing is implemented by hardware. In this case, the wireless receiver 210 is all implemented as an application specific integrated circuit (ASIC). A clock generator, in particular a crystal oscillator 5 is also provided. In this case, the sampling error is corrected, especially reduced, by selecting the clock generator based on its clock frequency. Preferably, the clock generator can be preselected during the manufacturing process. In addition, the wireless receiver 210 may be designed to perform operation mode A and additionally operation mode C (dotted arrow), as shown in FIG. 11. As an alternative to the externally connected crystal oscillator 5, the wireless receiver 210 may further include an internal clock, such as an integrated oscillator circuit, as a clock generator. In practice, the present invention is a radio receiver 210 that is not shown and is configured to perform operation modes A, B and/or C and/or operation modes I, II and/or III, in particular as described above in each case. It further includes an embodiment of).

It is apparent that the present specification further includes individual feature combinations (sub-combinations) and possible combinations of individual features of different embodiments, and such possible combinations are not provided in the drawings.

List of reference numbers

One Receiving device

1a interface

2 data

2a Data packet

3 Microcontroller

4 Memory

5 Crystal oscillator

6 filter

7 Decimation unit

8 filter

9 Switchover device

10 Wireless receiver

11 Terminal

12 Concentrator

13 Transceiver

14 Data memory

15 Microprocessor

16 RAM memory

17 Decimator

18 Shared memory

101 Receiving device

105 Crystal oscillator

110 Wireless receiver

115 Microprocessor

210 Receiving device

Claims (22)

As a wireless receiver 10 for use in an environment of self-sufficient in energy, preferably long-term energy self-sufficient,
The wireless receiver 10 receives data (2) in the form of at least one data packet or part of a data packet or a data stream having a specific data rate, and provides the data for further data processing (1). ), in particular a wireless chip,
In operation mode A, the received, or received and filtered data 2 is diverted in the receiving device 1 and supplied to the microcontroller 3, preferably at a definable sampling rate. ,
The microcontroller 3 or the receiving device 1 decimates the data by selecting a subset from a set of samples,
The microcontroller (3) buffers the decimated data in the memory (4, 18) and provides it for further processing. The method of claim 1,
In operation mode B, the provided, or provided and filtered, data 2 are supplied to a microprocessor 15 or a digital receiving circuit each included in the receiving device 1,
The data (2) is filtered by the microprocessor (15) or the digital receiving circuit and then decimated by a subset selected from a set of samples. The method according to claim 1 or 2,
The wireless receiver is an SDR type, a wireless receiver. The method according to any one of claims 1 to 3,
A clock generator, in particular a crystal oscillator 5 is provided,
The sampling rate is preferably defined by the clock frequency of the clock generator. The method according to claim 1 or 2,
The wireless receiver 210 is of a type in which signal processing is implemented at least mostly, preferably entirely by hardware,
A clock generator, in particular a crystal oscillator 5 is provided,
By selecting the clock generator based on the clock frequency of the clock generator, the sampling error is corrected, particularly reduced. The method according to any one of claims 1 to 5,
The receiving device (1) comprises a filter (6) for filtering the data (2) prior to supplying it to the microcontroller (3). The method according to any one of claims 1 to 6,
The microcontroller (3) comprises a filter (8) for filtering the data (2) prior to decimation. The method according to any one of claims 1 to 7,
The data (2) is decimated by the microcontroller (3) by ignoring the individual samples of the set of samples supplied by the receiving device (1) by the microcontroller (3),
The sample is selected based on an integer decimation factor. The method of claim 7,
The bandwidth by which the data (2) is supplied to the microcontroller (3) after the filter (6) is preferably less than 200 kHz, preferably less than 100 kHz and more preferably less than 50 kHz. The method according to any one of claims 1 to 9,
A radio receiver, wherein different sampling rates can be defined for different bandwidths in the microcontroller (3). The method according to any one of claims 1 to 10,
The clock frequency of the clock generator is between 20 MHz and 50 MHz, preferably between 23 MHz and 25 MHz, between 38 MHz and 40 MHz or between 47 MHz and 49 MHz, and more preferably between 24 MHz, 39 MHz or 48. MHz, wireless receiver. The method according to any one of claims 1 to 11,
The error in the clock frequency of the clock generator is less than 10 ppm, preferably less than 5 ppm, more preferably less than 3 ppm. The method according to any one of claims 1 to 12,
Operation mode A and/or operation mode B may be enabled and/or disabled. The method according to any one of claims 1 to 13,
Operation mode C is provided in addition to operation mode A or operation mode B,
In operation mode C, the data 2 is processed by the microprocessor 15 or digital receiving circuit of the receiving device 1 before being transmitted to the microcontroller 3,
A wireless receiver capable of switching between operating mode A or operating mode B and operating mode C. The method according to any one of claims 1 to 14,
The data (2) is transferred in steps between the receiving device (1) and the microcontroller (3),
A wireless receiver, wherein a time interval during which no transmission is made is provided between transmissions of data. The method of claim 15,
During a time interval in which no data 2 is transmitted, the microcontroller 3 is shifted to sleep mode. The method according to any one of claims 1 to 16,
The microcontroller (3) is configured to decode the data (2). The method according to any one of claims 1 to 17,
The microcontroller (3) is configured to process, in addition to processing and storing the data (2), higher layers as well. The method according to any one of claims 1 to 18,
The receiving device (1) and the microcontroller (3) are implemented as a common constituent unit, in particular as an integrated circuit. The method according to any one of claims 1 to 19,
The data (2) is I/Q data. The method according to any one of claims 1 to 20,
The radio receiver (10, 210) comprises an energy source for supplying energy, in particular a battery with a capacity of less than 20 Ah. A communication system for transferring data 2 between at least one concentrator 12 and a plurality of, in particular, a plurality of terminals 11 which are energy self-sufficient,
Each terminal 12 includes a wireless receiver 10, 210 having a receiving device 1,
The receiving device (1) receives, from the concentrator (12), data (2) in the form of at least one data packet or a part of a data packet or a data stream at a specific data rate, and the data is preferably additionally Provide for data processing,
22. A communication system, wherein a wireless receiver (10, 210) as claimed in any one of claims 1 to 21 is provided as said wireless receiver.

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