DE102010056080A1 - Radio receiver and method for its operation - Google Patents

Abstract

This opens up the possibility of using a software radio receiver (11), as is used in particular for obtaining digital measured values (17) via a signal processor (15) from demodulated and digitized data received signals (16), either for operation in power-saving mode or for Initialize operation with increased range. In the latter case, a significant part of the detection algorithms is relocated to a logic gate (18) connected upstream of the signal processor (15), whose otherwise bridged function is enabled by activating its configuration memory (22), as it were, by opening a bridging switch (19).

Description

The invention relates to a radio receiver according to the preambles of the two main claims.

Such a radio receiver is about from the DE 10 2005 034 102 A1 for recording consumption values for billing, in particular water, heat or electricity consumption, without having to enter a residential building or even its individual apartments for reading measuring points, because their current measured values are transmitted via miniaturized data transmitters. These measuring point-coded consumption values are preprocessed in a read-out unit containing the radio receiver and, if appropriate, temporarily stored and transmitted therefrom to a billing center.

In particular, radio receivers for data transmission are increasingly no longer realized in hardware, but in software, taking into account the previously known nature of the expected, interesting data. For this purpose, the antenna receive signal, usually after preamplification, is scanned by means of a scan program and evaluated via adapted filter algorithms in a signal processor.

In this context, the technical problem is to be solved to increase the performance in terms of the general performance of such a radio receiver, taking into account also aspects of low power consumption.

This object is achieved by the features of the main claims. Thereafter, instead of directly, the digitized received signals can be switched to a signal processor (DSP) via a programmable digital logic gate (FPGA). The inclusion of the logic gate in the receiver circuit in front of the signal processor then results in the advantage of being able to advance numerous correlation, filtering and detection algorithms out of the processor into this gate circuit, within which parallel processing takes place in real time - in contrast to serial signal processing in FIG a processor. Such acceleration of the demodulation of digital measurements even before the final processor function allows the use of more complex criteria for a more critical evaluation of the data signals practically without loss of time, which in turn leads to an increase in detection security, resulting in a greater usable reception range because of improved immunity to interference.

However, the power consumption of such logic gates is comparatively high and, in particular, higher than with pure processor processing. Therefore, according to a development of the invention, it is provided to electrically bridge the logic gates lying in series with the signal processor-or omit them altogether-namely, if such an increased performance of the data radio receiver is not required due to the circumstances of the application scenario to be expected. This can be the case, for example, because the readout unit is to be used with its receiver in the power-saving mode as a handheld device and to be passed in the immediate vicinity of data transmitters. If the readout unit opposes. is operated in a motor vehicle, where from the electrical system sufficient energy is available, the radio receiver can be easily operated with the logic gate in front of his signal processor to detect about the road from driving in the spread over a wider terrain scattered operated data transmitter in the wide range mode.

Further features and additional developments of the invention result. from the further claims and, also with regard to their advantages, from the following description of a preferred realization example for the solution according to the invention. The sole figure of the drawing illustrates in the abstracted on the principle sketch of a single-pole block diagram signal processing in an inventively designed data radio receiver.

Such, in particular in a measured data read-out unit operated radio receiver 11 is with a connection for an internal or external antenna 12 equipped with an analog amplifier 13 fed. This is followed by an analog-to-digital converter 14 , This is usually directly to a signal processor 15 for filtering and analyzing the digitized received signals 16 connected. The measured values thus obtained 17 can be transmitted directly to a computer-equipped evaluation center or temporarily stored in the readout unit.

Such signal processing can be deepened and yet noticeably accelerated. In particular, according to the invention, without extending the processing time via further detection criteria, an increased detection reliability and consequently an increase in the reception range of the radio receiver can be achieved 11 achieve when the signal processor in series 15 at least part of the tasks of analyzing and decoding the received signals 16 is unbound by their algorithms in at least one acutely programmable complex logic gate 18 be implemented, which is the signal processor 15 in series is preceded and only weiterzuverarbeitende digital readings 17 to the signal processor 15 supplies. The radio receiver likes this 11 production side earmarked at a designated slot with the logic gate 18 to be equipped; or he is already pre-populated with it by default. The first empty in the receiver circuit and now to be populated slot or the like recording or a standard already provided logic gate 18 are now sort of opened by opening a bypass switch 19 in the signal path to the signal processor 15 effective, as it results from the block diagram functionally.

Such choice is there by a switch 20 symbolizes. When starting up at the start of operation is via this switch 20 specified whether the radio receiver 11 now with increased detection reliability, ie with increased range, or whether it should be operated in power-saving mode. In the latter case, the switch 19 for bridging the installation position of a logic gate 18 closed and at the same time a non-volatile configuration memory 21a for programming the signal processor 15 activated in this mode, in which it functions as necessary at least rudimentary signal processing tasks from the functions of the logic gate 18 takes over.

If, however, the equipment of the circuit of the radio receiver 11 including the separate logic gate 18 in front of the signal processor 15 and therefore should be effective with increased sensitivity, then the readout unit with its radio receiver 11 in that functional position of the switch 20 started up in which the bypass switch 19 is open, and thus an updatable configuration memory 22 for the logic gate 18 activated. At the same time, a configuration memory 21b activated in the signal processor 15 suppresses those functions, the logic gate which now precedes it 18 be perceived; the configuration functions 21a / 21b circuitry also in a single, differentiated readable processor configuration memory 21 can be deposited. For any future functional enhancements does not need programming in the signal processor 15 to be intervened; they become simpler in the configuration memory 22 for the logic gate 18 stored.

Thus, the invention opens up the possibility of a software radio receiver 11 , in particular, for gaining digital readings 17 via a signal processor 15 from demodulated and digitized data reception signals 16 The option is to initialize either for operation in power-saving mode or for operation with increased range. In the latter case, a significant portion of the detection algorithms will be in a signal processor 15 upstream logic gate 18 its otherwise-bridged function by enabling its configuration memory 22 in a sense, by opening a bypass switch 19 is released.

LIST OF REFERENCE NUMBERS

11

radio receiver

12

antenna

13

Amplifier (behind 12 )

14

Analog-to-digital converter (ADC) (behind 13 )

15

Signal processor (DSP)

16

(digitized) received signals (behind 13 )

17

(digital) measured values (behind 15 )

18

Logic gate (FGPA) (optional before 15 )

19

Switch (for bridging 18 )

20

switch

21

Updatable configuration memory (EPROM or FLASH) ( 21a + 21b For 15 )

22

Updatable configuration memory (EPROM or FLASH) (for 18 )

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• DE 102005034102 A1 [0002]

Claims (6)

Radio receiver ( 11 ) with signal processor ( 15 ), in particular for providing digital measured values ( 17 ) for consumption billing from digitized received signals ( 16 ), characterized in that it can be bridged to receive a logic gate ( 18 ) in front of the signal processor ( 15 ) and with the function of a changeover switch ( 20 ), according to a commissioning of the radio receiver ( 11 ) either by bridging the logic gate input ( 18 ) or activating a configuration memory ( 22 ) for the logic gate ( 18 ) is initiatable. Radio receiver according to the preceding claim, characterized in that upon activation of the configuration memory ( 22 ) for the logic gate ( 18 ) a configuration memory ( 21b ) for the signal processor ( 15 ) in this function, which is blocked by the logic gate ( 18 ) are taken over. Radio receiver according to one of the preceding claims, characterized in that in the logic gate ( 18 ), in the interest of increased reception range, additional algorithms for interference-resistant acquisition of digital measured values ( 17 ) from the digitized received signals ( 16 ) are implemented. Radio receiver according to one of the preceding claims, characterized in that, in the interest of reduced energy consumption, in the case of functionally bridgeable logic gates ( 18 ) a processor configuration memory ( 21a ) which can be activated in the signal processor ( 15 ) at least the functionally essential algorithms for converting the digitized received signals ( 16 ) into the digital measured values ( 17 ) implemented. Method for operating a radio receiver ( 11 ) according to one of the preceding claims, optionally in a wide-range mode or in a power-saving mode by switching between enabling and bridging the function of a logic gate ( 18 ) in front of the signal processor ( 15 ) for outputting the digital measured values ( 17 ). Method according to the preceding claim, characterized in that upon initiation of the radio receiver ( 11 ) in the power-saving mode, a configuration memory ( 21a ) for implementing the functionally necessary detection algorithms of the logic gate ( 18 ) in the signal processor ( 15 ) is activated.

Images