KR20200094108A - Selection device having polycrystal metal oxide layer and cross-point memory including the same - Google Patents

Abstract

The present invention is to provide a switching device or a selection device which may not adversely affect the degree of integration and a three-dimensional (3D) cross-point memory having the same. Provided are a selection device and a cross-point memory including the same. The selection device has a lower electrode. A polycrystalline metal oxide film including insulating grains and conductive nanochannels formed in grain boundaries between the grains is disposed on the lower electrode. An upper electrode is disposed on the polycrystalline metal oxide film.

Description

{Selection device having polycrystal metal oxide layer and cross-point memory including the same}

The present invention relates to a semiconductor device, and more particularly, to a selection device and a crosspoint memory including the same.

In the case of a flash memory that is currently commercialized as a non-volatile memory, a change in threshold voltage according to storage or removal of charge in the charge storage layer is used. The charge storage layer may be a floating gate that is a polysilicon film or a charge trap layer that is a silicon nitride film. Recently, new generation non-volatile memory devices having low power consumption and high integration compared to the flash memory devices have been studied. Examples of the next-generation nonvolatile memory devices include a phase change RAM (PRAM), a magnetic memory device (MRAM), and a resistance change RAM (ReRAM).

Meanwhile, in order to configure a cell array using such a memory device, a transistor electrically connected to the memory device and serving as a switch may be required. However, configuring a memory device array together with such transistors can greatly degrade the degree of integration.

Therefore, the problem to be solved by the present invention is to provide a switching element or a selection element that may not adversely affect the density improvement, and a three-dimensional crosspoint memory having the same.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above technical problem, an embodiment of the present invention provides a selection element. The selection element has a lower electrode. A polycrystalline metal oxide film including conductive nanochannels formed in insulating grains and grain boundaries between the grains is disposed on the lower electrode. An upper electrode is disposed on the polycrystalline metal oxide film.

The crystal grain may be a crystal grain of a metal oxide represented by Formula 1 below.

[Formula 1]

M _x O _y

In Chemical Formula 1, M is a metal, and x and y may be integers satisfying stoichiometry. Specifically, M may be a transition metal, a post-transition metal, a metalloid, Mg, or a combination thereof. The crystal grains are Ta ₂ O ₅ , TiO ₂ , Nb ₂ O ₅ , WO ₂ , HfO ₂ , ZnO, MoO ₂ , CoO, Cu ₂ O ₃ , AgO, CrO ₂ , Al ₂ O ₃ , Ga ₂ O ₃ , SiO ₂ , MgO or a combination thereof.

The nanochannel may be a metal oxide rich in metal compared to a metal oxide in the crystal grain. Specifically, the nano-channel may be a metal oxide represented by the following formula (2).

[Formula 2]

M _x O _yz

In Chemical Formula 2, M, x and y are the same as in Chemical Formula 1, and z may be greater than 0 and 1 or less. The nano-channel is Ta ₂ O _5-z , TiO _2-z , Nb ₂ O _5-z , WO _2-z , HfO _2-z , ZnO _1-z , MoO _2-z , CoO _1-z , Cu ₂ O _3-z , AgO _1-z , CrO _2-z , Al ₂ O _3-z , Ga ₂ O _3-z , SiO _2-z , MgO _1-z , or a combination thereof.

In one example, the lower electrode may include an inert metal layer or an inert metal compound layer. In another example, the lower electrode is a metal layer having the same metal as the metal contained in the metal oxide film, and a diffusion control layer, which is an inert metal layer or an inert metal compound layer, may be provided on the metal layer. .

The upper electrode may be the same metal film as the metal in the metal oxide film or an inert metal film.

In order to achieve the above technical problem, an embodiment of the present invention provides another example of the selection element. The selection element includes a lower electrode. It is disposed on the lower electrode, and includes a plurality of metal oxide grains and a grain boundary in which a metal-rich metal oxide nanochannel is formed in comparison to the metal oxide in the grain. An upper electrode is disposed on the polycrystalline metal oxide film.

In order to achieve the above technical problem, another embodiment of the present invention provides a method for manufacturing a selection element. First, a metal layer on the substrate, diffusion A control layer and a metal oxide film are sequentially formed. The metal layer is a layer of the same metal as the metal contained in the metal oxide film. The substrate on which the metal oxide film is formed is heat-treated in an inert gas atmosphere to crystallize the metal oxide film to change into a polycrystalline film having a large number of grains and grain boundaries therebetween, and the metal in the metal layer is passed through the diffusion control layer. Diffuse to grain boundaries. An upper electrode is formed on the heat-treated metal oxide film.

In order to achieve the above technical problem, another embodiment of the present invention provides a cross point memory. The cross point memory includes a plurality of first wires arranged in parallel in one direction. A plurality of second wirings arranged on the first wirings and intersecting the first wirings and parallel to each other are disposed. In each portion where the first wirings and the second wirings intersect, a stacked selection element and a memory element are sequentially disposed between the first wiring and the second wiring. The selection element is a polycrystalline metal oxide film including conductive nanochannels formed in insulating grains and grain boundaries between the grains.

An intermediate electrode may be disposed between the selection element and the memory element. The memory element may be a phase change memory layer, a resistance change memory layer, or a magnetoresistive memory layer.

As described above, the selection device according to embodiments of the present invention is a two-terminal device having only two electrodes, an upper electrode and a lower electrode, so that the area occupied is not large, and thus the integration degree can be improved. In addition, such a selection element may exhibit bidirectional selection characteristics, and thus may be applicable as a selection element of a bidirectional memory element. Additionally, it is possible to form a conductive nanochannel by confining within the grain boundaries of the polycrystalline metal oxide film, thereby exhibiting low off-current.

However, the effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

1A and 1B are cross-sectional views sequentially illustrating a method of manufacturing a selection device according to an embodiment of the present invention.
2 is an enlarged cross-sectional view of part A of FIG. 1B.
3 is a schematic diagram showing an IV curve of a selection element described with reference to FIGS. 1A, 1B, and 2.
4 is a schematic diagram showing a three-dimensional crosspoint memory array according to an embodiment of the present invention.
5 shows a TEM (transmission electron microscopy) image and cross-section of a Ta ₂ O ₅ film of a device according to Comparative Example 2 and an electron diffraction pattern (SAED) pattern.
6 shows a TEM image and electron diffraction pattern of a cross section of the Ta ₂ O ₅ film of the device according to Preparation Example 5.
7 is an XRD (X-Ray Diffraction) graph of Ta ₂ O ₅ films obtained in a device manufacturing process according to Preparation Examples 4 to 6 and Comparative Example 2. FIG.
8 is a graph showing the IV characteristics of a device having a Ta ₂ O ₅ film, which is an amorphous insulating layer without heat treatment according to Comparative Example 1.
9A, 9B, and 9C are graphs respectively showing IV characteristics of selector elements having polycrystalline Ta ₂ O ₅ films according to Preparation Examples 1 to 3.
10 is a graph showing IV characteristics of a selection device having a polycrystalline metal oxide layer according to Preparation Example 1 measured 10 ⁷ times.
11 shows XRD (X-Ray Diffraction) graphs for the HfO ₂ film obtained in the device manufacturing method according to Comparative Example 3 and Manufacturing Examples 7, 8, 12-14.
12 shows graphs showing IV characteristics of selector elements according to Manufacturing Examples 7 to 11.

Hereinafter, preferred embodiments according to the present invention will be described in more detail with reference to the accompanying drawings in order to describe the present invention in more detail. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. When a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed between them.

1A and 1B are cross-sectional views sequentially illustrating a method of manufacturing a selection device according to an embodiment of the present invention.

Referring to FIG. 1A, a substrate (not shown) may be provided. The substrate can be a semiconductor, metal, glass or polymer substrate.

A metal layer 11 may be formed on the substrate. The metal layer 11 may be formed to a thickness of 1 nm to 50 nm. An insulating film (not shown) may be additionally formed on the substrate before forming the metal layer 11.

A diffusion control layer 12 may be formed on the metal layer 11. The diffusion control layer 12 may contain an inert metal, an inert metal compound layer, or a combination thereof having a very low degree of chemical reaction with a layer in contact with it. The inert metal may include Ru (ruthenium), Rh (rhodium), Pd (palladium), Os (osmium), Ir (iridium), Pt (platinum), Au (gold), or a combination thereof. The inert metal compound layer may be WN. The diffusion control layer 12 may have a nanometer size. As an example, the thickness of the diffusion control layer 12 may be 10 to 100 nm, specifically 15 to 60 nm.

In addition, a metal oxide film 20 may be formed on the diffusion control layer 12. The metal oxide film 20 may be a binary metal oxide of metal and oxygen. The metal oxide film 20 may be in an amorphous state immediately after formation and may also be an insulator. The metal oxide included in the metal oxide film 20 may be represented by Formula 1 below.

[Formula 1]

M _x O _y

In Chemical Formula 1, M is a metal, and x and y are integers satisfying stoichiometry.

M may be a transition metal, a post-transition metal, a metalloid, Mg, or a combination thereof. The transition metal may be, for example, Ta, Ti, Nb, W, Hf, Zn, Mo, Co, Cu, Ag, or Cr, and the post-transition metal may be, for example, Al or Ga, semimetal May be Si.

As an example, the metal oxide may include transition metal oxides such as Ta ₂ O ₅ , TiO ₂ , Nb ₂ O ₅ , WO ₂ , HfO ₂ , ZnO, MoO ₂ , CoO, Cu ₂ O ₃ , AgO, or CrO ₂ ; Transition metal oxides such as Al ₂ O ₃ or Ga ₂ O ₃ ; Semi-metal oxides such as SiO ₂ ; Or MgO.

Meanwhile, the metal layer 11 may be a layer of the same metal as the metal included in the metal oxide film 20. Specifically, when the metal oxide film 20 is a Ta ₂ O ₅ layer, the metal layer 11 may be a Ta layer, and when the metal oxide film 20 is a HfO ₂ layer, the metal layer 11 may be an Hf layer. .

The substrate on which the metal oxide film 20 is formed may be annealed. In the heat treatment, crystallization of the metal oxide film 20 is possible, but metal in the metal layer 11, specifically metal atoms or metal ions, are diffused into the metal oxide film 20 through the diffusion control layer 12. It can be carried out in a temperature range as much as possible. As an example, the heat treatment may vary depending on the metal oxide material used. For example, when the metal layer is a Ta layer, heat treatment may be performed at 500 to 1000 degrees, and when the metal layer is an Hf layer, heat treatment may be performed at 350 to 550 degrees. The heat treatment may be carried out in an inert gas atmosphere, for example, argon, nitrogen, or a complex atmosphere thereof.

The metal layer 11, the diffusion control layer 12, and the metal oxide film 20 are physical vapor deposition methods such as sputtering and evaporation, regardless of each other; Or it can be formed using a chemical vapor deposition method. The heat treatment may be RTA (Rapid Thermal Annealing) or heat treatment using a furnace.

2 is an enlarged cross-sectional view of part A of FIG.

Referring to Figures 1b and 2 at the same time, in the heat treatment process, the metal oxide film 20 may crystallize and turn into a polycrystalline film. In this case, the polycrystalline film may mean a film including a plurality of grains G having various sizes and various crystal directions, and further, a grain boundary (GB) between the plurality of grains G ) May mean the formed film. Since the crystal grains G may have the composition of Formula 1, they may be in an insulating state.

Meanwhile, the metal in the metal layer 11 diffused into the metal oxide layer 20 through the diffusion control layer 12 in the heat treatment process is mainly diffused into the grain boundary GB to form a nanochannel (CH). have. In this case, the nano-channel (CH) may include a metal oxide represented by Chemical Formula 2 as an example of a metal oxide in a state in which the metal is rich, that is, an oxygen-poor state, that is, a state having an oxygen pore.

[Formula 2]

M _x O _yz

In Formula 2, M, x and y may be the same as in Formula 1, and z may be greater than 0 and 1 or less.

The metal oxide in the nano-channel (CH) is, for example, Ta ₂ O _5-z , TiO _2-z , Nb ₂ O _5-z , WO _2-z , HfO _2-z , ZnO _1-z , MoO ₂ transition metal oxides such as _-z , CoO _1-z , Cu ₂ O _3-z , AgO _1-z , or CrO _2-z ; Transition metal oxides such as Al ₂ O _3-z or Ga ₂ O _3-z ; Semi-metal oxides such as SiO _2-z ; MgO _1-z ; Or a combination of these.

As described above, the metal oxide film 20 may crystallize and metal may be diffused into the grain boundary GB, and the metal diffuses into the metal oxide film 20 to promote crystallization. To form the grains G and the diffused metal may be present in the grain boundary GB.

As described above, the metal oxide in the grain boundary GB, that is, the nanochannel CH, is a metal oxide having a state of oxygen vacancy, and thus may exhibit conductivity.

Thereafter, an upper electrode 30 may be formed on the metal oxide film 20. The upper electrode 30 may be a conductive film or a metal film that is the same as or not the same as the metal in the metal oxide film 20, or an inert metal film. As an example, when the metal oxide film 20 is a Ta ₂ O ₅ film, the upper electrode 30 may be a Ta film, and when the metal oxide film 20 is an HfO ₂ film, the upper electrode 30 is Ta It can be just a film. When the upper electrode 30 is an inert metal film, the upper electrode 30 is, for example, Ru (ruthenium), Rh (rhodium), Pd (palladium), Os (osmium), Ir (iridium), Pt ( platinum), Au (gold), or a combination thereof. The upper electrode 30 is a physical vapor deposition method such as sputtering or evaporation; Or it can be formed using a chemical vapor deposition method.

The metal layer 11 and/or the diffusion control layer 12 may serve as the lower electrode 10 (or the first wiring shown in FIG. 3) to which an external voltage is applied. In one example, when the diffusion control layer 12 serves as a lower electrode (or the first wiring shown in FIG. 3), the metal layer 11 may be a layer disposed for each unit cell under the lower electrode. . In another example, when the metal layer 11 serves as a lower electrode (or the first wiring shown in FIG. 3), the diffusion control layer 12 may be a layer disposed for each unit cell on the lower electrode. . In another example, the metal layer 11 and the diffusion control layer 12 may both serve as the lower electrode (or the first wiring shown in FIG. 3 ).

3 is a schematic diagram showing the I-V curve of the selection element described with reference to FIGS. 1A, 1B, and 2.

Referring to FIGS. 1B and 3 at the same time, when a positive voltage is applied to the upper electrode 30 with respect to the lower electrode 10 of the selection element, the selection element may be turned on at a certain amount of threshold voltage. In addition, when a negative voltage is applied to the upper electrode 30 to the lower electrode 10, the selection element may be turned on at a specific negative threshold voltage. Also, the current tends to increase linearly after being turned on. As such, the selection element may exhibit bipolar characteristics. This is because the nanochannel CH formed in the grain boundary GB of the selection element exhibits low conductivity in a low electric field, but high conductivity in a high electric field.

Such a selection element is a two-terminal device having only two electrodes, an upper electrode and a lower electrode, so that the area occupied is not large, and thus the degree of integration can be improved. In addition, such a selection element may exhibit bidirectional selection characteristics, and thus may be applicable as a selection element of a bidirectional memory element. In particular, in the case to apply the selection device in the cross-point memory shown in Figure 4, in the read voltage (V _R V or _R ') and a half read voltage (1 / 2V _R, or 1 / 2V _R') Since it is possible to induce a large difference in current values of, it can be predicted that the read margin can be greatly increased.

Additionally, it is possible to form a conductive nanochannel at a low voltage by limiting within the grain boundaries of the polycrystalline metal oxide film, thereby exhibiting low off-current.

4 is a schematic diagram showing a three-dimensional crosspoint memory array according to an embodiment of the present invention.

Referring to FIG. 4, as an example of a plurality of first wirings on a substrate, word lines W may be disposed. The word lines W may be arranged parallel to each other in one direction. Bit lines B may be positioned on the word lines W as an example of second lines intersecting the word lines W and arranged parallel to each other.

In portions where the word lines W and the bit lines B intersect, a selection element S and a memory element M may be stacked therebetween. An intermediate electrode IME may be disposed between the selection element S and the memory element M.

The selection element S may be the metal oxide film 20 described with reference to FIGS. 1B and 2. The word lines W may be the lower electrode 10 described with reference to FIG. 1B. Further, the intermediate electrode IME may be the upper electrode 30 described with reference to FIG. 1B.

The memory element M is a non-volatile memory element, for example, a phase change random access memory (PRAM) layer, a magnetoresistive random access memory (MRAM) layer, or a magnetoresistive memory (Resistive Random) Access Memory (ReRAM) layer.

When the memory element M is the phase change memory layer, the memory element M is a chalcogenide material, for example, Ge-Te, Ge-Sb-Te, Ge-Te-Se, Ge-Te -As, Ge-Te-Sn, Ge-Te-Ti, Ge-Bi-Te, Ge-Cu-Te, Si-Sb-Te, Ge-Sn-Sb-Te, Ge-Sb-Se-Te, Ge -Sb-Te-S, Ge-Te-Sn-O, Ge-Te-Sn-Au, Ge-Te-Sn-Pd, Sb-Te, Se-Te-Sn, Sb-Se-Bi, In-Se Or In-Sb-Te.

When the memory element (M) is the magnetoresistive memory layer, specifically, a spin transfer torque MRAM layer, the memory element (M) comprises a magnetic tunnel junction (MTJ) structure. Although provided, the MTJ structure may include a ferromagnetic pinned layer (not shown), a tunnel barrier layer (not shown), and a ferromagnetic free layer (not shown) sequentially stacked. The MTJ structure may further include a pinning layer (not shown) under the fixed layer. The fixed layer may be a CoFeB or FePt layer as a layer in which magnetization reversal does not occur. The tunnel barrier layer may be an aluminum oxide film or a magnesium oxide film. The free layer may be a CoFeB or FePt layer in which magnetization reversal occurs above a critical current density.

When the memory element M is the resistance change memory layer, the memory element M is a bipolar variable resistor layer, specifically, a resistance change memory layer having bipolar characteristics, for example, a transition metal oxide film. oxide layer), a chalcogenide film, a perovskite film, or a metal-doped solid electrolyte film. The transition metal oxide film is HfO _2-x , MnO _2-x , ZrO _2-x , Y ₂ O _3-x , TiO _2-x , NiO _1-y , Nb ₂ O _5-x , Ta ₂ O _5-x , CuO _1-y , Fe ₂ O _3-x (eg, 0≤x≤1.5, 0≤y≤0.5) or a lanthanoid oxide layer. The lanthanoid may be La (Lanthanum), Ce (Cerium), Pr (Praseodymium), Nd (Neodymium), Sm (Samarium), Gd (Gadolinium), or Dy (Dysprosium). The chalcogenide film GeSbTe film, GeTeO (e.g., Ge ₂ Te ₂ O ₅₎ may be in the perovskite film SrTiO _3, Cr or Nb-doped SrZrO ₃ film, PCMO (Pr _1-X Ca _X MnO ₃ , 0<X<1) film, or LCMO (La _1-X Ca _X MnO ₃ , 0<X<1, for example, X is 0.3) film. In addition, the metal-doped solid electrolyte film may be a film in which Ag is doped in GeSe, that is, an AgGeSe film.

The bit line B may be appropriately selected according to the memory element M among known conductive patterns.

Hereinafter, a preferred experimental example (example) is presented to help the understanding of the present invention. However, the following experimental examples are only to aid the understanding of the present invention, and the present invention is not limited by the following experimental examples.

<Device including Ta ₂ O ₅ film>

Preparation Example 1

A Ta film is formed to about 10 nm using sputtering on a silicon substrate on which a silicon oxide film is formed, a Pt film is formed to about 50 nm using sputtering as a diffusion control layer on the Ta film, and a metal oxide is formed on the Pt film. As a film, a Ta ₂ O ₅ film was formed to about 20 nm by sputtering. The substrate on which the Ta ₂ O ₅ film was formed was heated to 700° C. in an Ar atmosphere for 30 minutes, and then maintained for about 1 hour to heat treatment. After this, it was naturally cooled. On the heat-treated Ta ₂ O ₅ film, sputtering was used to form a Ta film to about 20 nm to prepare a selection device.

Preparation Example 2

A selective element was manufactured using the same method as in Preparation Example 1, except that a Ta ₂ O ₅ film was formed at about 30 nm.

Preparation Example 3

A selective element was manufactured using the same method as in Preparation Example 1, except that a Ta ₂ O ₅ film was formed at about 40 nm.

Selection device manufacturing examples 4 to 6

Except that the Ta ₂ O ₅ film was formed at about 150 nm and the substrate on which the Ta ₂ O ₅ film was formed was heat-treated at 600° C. (Production Example 4), 700° C. (Production Example 5), or 800° C. (Production Example 6). The selection device was manufactured using the same method as in Production Example 1 of the selection device.

Comparative Example 1

A device was manufactured by using the same method as in Selective Device Manufacturing Example 1, except that the step of heat-treating the substrate on which the Ta ₂ O ₅ film was formed was performed, and a Ta film was formed on the Ta ₂ O ₅ film without heat treatment.

Comparative Example 2

A device was manufactured using the same method as Comparative Example 1, except that a Ta ₂ O ₅ film was formed at about 150 nm.

Ta ₂ O ₅ film thickness Heat treatment temperature Preparation Example 1 20nm 700 ℃ Preparation Example 2 30nm 700 ℃ Preparation Example 3 40nm 700 ℃ Preparation Example 4 150nm 600 ℃ Preparation Example 5 150nm 700 ℃ Preparation Example 6 150nm 800 ℃ Comparative Example 1 20nm - Comparative Example 2 150nm -

5 shows a TEM (transmission electron microscopy) image and cross-section of a Ta ₂ O ₅ film of a device according to Comparative Example 2 and an electron diffraction pattern (SAED) pattern. 6 shows a TEM image and electron diffraction pattern of a cross section of the Ta ₂ O ₅ film of the device according to Preparation Example 5.

5 and 6, it can be seen that the Ta ₂ O ₅ film not heat-treated in the device according to Comparative Example 1 is an amorphous film, whereas the Ta ₂ O ₅ film heat-treated in the device according to Preparation Example 5 is a polycrystalline film.

7 is an XRD (X-Ray Diffraction) graph of Ta ₂ O ₅ films obtained in a device manufacturing process according to Preparation Examples 4 to 6 and Comparative Example 2. FIG.

Referring to FIG. 7, the unheated Ta ₂ O ₅ film appeared as an amorphous film (Comparative Example 2) and crystallization started at a heat treatment of 600° C. (Production Example 4), and heat treatment of 700° C. or higher (Production Example 5, Production Example 6) ), it can be seen that the Ta ₂ O ₅ film forms a polycrystalline structure.

8 is a graph showing the IV characteristics of a device having a Ta ₂ O ₅ film, which is an amorphous insulating layer without heat treatment according to Comparative Example 1.

Referring to FIG. 8, when a positive voltage is applied to the device according to the comparative example, it is set at about 1.2V and represents a low resistance state, and when a negative voltage is applied, it is reset at about -0.8V to indicate a high resistance state. It can be seen that it shows a typical hysteresis loop of a bipolar resistance change memory device.

9A, 9B, and 9C are graphs respectively showing IV characteristics of selector elements having polycrystalline Ta ₂ O ₅ films according to Preparation Examples 1 to 3.

9A, 9B, and 9C, the selection elements according to Manufacturing Examples 1 to 3 have a positive turn-on voltage and a negative turn-on voltage, and the current is turned on, unlike the hysteresis curve of FIG. 8 It tends to increase linearly.

This is due to the heat treatment process performed in the manufacturing examples, in which the Ta ₂ O ₅ film is crystallized and changed into a polycrystalline film containing a large number of grains and unstable grain boundaries between them, and also Ta atoms in the lower Ta film. Fields or Ta ions diffused through the Pt film and were introduced into the grain boundaries in the Ta ₂ O ₅ film and were estimated as a result of forming nanochannels.

Specifically, it can be seen that the selection element according to Manufacturing Example 1 shown in FIG. 9A is turned on at about 1 V when a positive voltage is applied, and turned on at about -0.1 V when a negative voltage is applied, as shown in FIG. 9B. It can be seen that the selection element according to Manufacturing Example 2 is turned on at about 1.2 V when a positive voltage is applied and turned on at about -0.3 V when a negative voltage is applied, and selection according to Manufacturing Example 3 shown in FIG. 9C. It can be seen that the device turns on at about 2V when a positive voltage is applied and turns on at about -0.4V when a negative voltage is applied. In addition, the selection elements according to Manufacturing Examples 1 to 3 indicate a leakage current or an off current of 1×10 ^-11 A or less, and further 5×10 ^-11 A or less in a turn-off state, and the turn-off section is 1V or more or 0.5V. It can be seen that it is 3 V or less as an example of the above and below 5 V.

10 is a graph showing IV characteristics of a selection device having a polycrystalline metal oxide layer according to Preparation Example 1 measured 10 ⁷ times. For the IV characteristic measurement, a voltage of -2V to 2V was swept over the device, and currents were measured at -2V, -1V, 1V, and 2V.

Referring to FIG. 10, the current value at 2V and its half current value at 1V has a ratio of about 10 ³ , and the current value at -2V and its half current value at -1V are also about 10 ³ Appeared to have a ratio of From these results, when the selection element according to the present embodiment is applied to a crosspoint memory as shown in FIG. 4, a large difference between current values according to read voltage and 1/2 read voltage can be derived, and thus a read margin It can be predicted that the can be greatly increased.

In addition, the current values measured during the measurement of the IV characteristic 10 ⁷ times appear to be almost constant, indicating that the reliability of the selection device according to this embodiment is very excellent.

<Device including HfO ₂ film>

Preparation Examples 7 to 14

An Hf film is formed to about 10 nm by sputtering on a silicon substrate on which a silicon oxide film is formed, a Pt film is formed to about 20 nm by sputtering as a diffusion control layer on the Hf film, and a metal oxide is formed on the Pt film As a film, an HfO ₂ film was formed to about 20 nm by sputtering. The substrate on which the HfO ₂ film was formed was heated in an Ar atmosphere at the temperature shown in Table 2 for 30 minutes, and then maintained for about 1 hour, followed by heat treatment. After this, it was naturally cooled. On the heat-treated HfO ₂ film, sputtering was used to form a Ta film to about 20 nm to prepare a selection device.

Comparative Example 3

A device was manufactured by using the same method as in Production Example 7, except that a step of heat-treating the substrate on which the HfO ₂ film was formed was not performed, and a Ta film was formed on the HfO ₂ film without heat treatment.

Metal oxide film Heat treatment temperature Preparation Example 7 HfO ₂ 20nm 375 ℃ Preparation Example 8 HfO ₂ 20nm 400 ℃ Preparation Example 9 HfO ₂ 20nm 425 ℃ Preparation Example 10 HfO ₂ 20nm 450 ℃ Preparation Example 11 HfO ₂ 20nm 475 ℃ Preparation Example 12 HfO ₂ 20nm 500 ℃ Preparation Example 13 HfO ₂ 20nm 600 ℃ Preparation Example 14 HfO ₂ 20nm 700 ℃ Comparative Example 3 HfO ₂ 20nm -

11 shows XRD (X-Ray Diffraction) graphs for the HfO ₂ film obtained in the device manufacturing method according to Comparative Example 3 and Manufacturing Examples 7, 8, 12-14.

Referring to FIG. 11, the HfO ₂ film (Comparative Example 3) that was not heat treated shows only the peak corresponding to the lower Pt layer, and it can be seen that the HfO ₂ film according to Comparative Example 3 is amorphous. On the other hand, it can be seen that when the heat treatment temperature is 400° C. or higher, the HfO ₂ film is crystallized to form a polycrystalline film (manufacturing examples 8, 12-14). On the other hand, in this embodiment, it can be seen that the polycrystalline HfO ₂ film has a greater intensity of the peak corresponding to (111) than the peak corresponding to (-111).

12 shows graphs showing I-V characteristics of selection elements according to Manufacturing Examples 7 to 11.

Referring to FIGS. 11 and 12, selectors (manufacturing examples 8-10) having a polycrystalline HfO ₂ film heat-treated at 400° C. or higher (manufacturing examples 8-10) have a positive turn-on voltage of 2 V or less and a negative turn-on voltage of turn-on After that, the current increases linearly, but it can be seen that the slope where the current increases is relatively large. On the other hand, it can be seen that the selection element (manufacturing example 7) having an HfO ₂ film that is not polycrystalline is very large at 2 V or more of the turn-on voltage and the slope of increasing current after turning on is not large. On the other hand, the HfO ₂ film (manufacturing example 11) heat-treated at 475° C. or higher was found to be difficult to serve as a selection device.

As described above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes by those skilled in the art within the technical spirit and scope of the present invention. This is possible.

Claims (17)

Lower electrode;
Conductivity formed on the lower electrode and formed in insulating grains and grain boundaries between the grains A polycrystalline metal oxide film including nanochannels; And
A selection element comprising an upper electrode disposed on the polycrystalline metal oxide film. The method according to claim 1,
The crystal grain is a selection device that is a crystal grain of the metal oxide represented by Formula 1:
[Formula 1]
M _x O _y
In Chemical Formula 1,
M is a metal, and x and y are integers satisfying stoichiometry. The method according to claim 2,
M is a transition metal, a post-transition metal, a metalloid, Mg, or a combination thereof. The method according to claim 1 or 2,
The crystal grains are Ta ₂ O ₅ , TiO ₂ , Nb ₂ O ₅ , WO ₂ , HfO ₂ , ZnO, MoO ₂ , CoO, Cu ₂ O ₃ , AgO, CrO ₂ , Al ₂ O ₃ , Ga ₂ O ₃ , SiO ₂ , MgO or a combination thereof. The method according to claim 1,
The nano-channel is a metal oxide-rich metal oxide selection element. The method according to claim 2,
The nano-channel is a metal oxide represented by the following formula (2):
[Formula 2]
M _x O _yz
In Formula 2, M, x and y are the same as in Formula 1, and z is greater than 0 and 1 or less. The method according to claim 1 or 6,
The nano-channel is Ta ₂ O _5-z , TiO _2-z , Nb ₂ O _5-z , WO _2-z , HfO _2-z , ZnO _1-z , MoO _2-z , CoO _1-z , Cu ₂ O _3-z , AgO _1-z , CrO _2-z , Al ₂ O _3-z , Ga ₂ O _3-z , SiO _2-z , MgO _1-z , or a combination thereof. The method according to claim 1,
The lower electrode is a selection device having an inert metal layer or an inert metal compound layer. The method according to claim 1,
The lower electrode is a metal layer having the same metal as the metal contained in the metal oxide film,
A selection device having a diffusion control layer, which is an inert metal layer or an inert metal compound layer, on the metal layer. The method according to claim 1,
The upper electrode is a selection device that is the same metal film or an inert metal film as the metal in the metal oxide film. Lower electrode;
A polycrystalline metal oxide film disposed on the lower electrode and including a plurality of metal oxide grains and a grain boundary formed with metal-rich metal oxide nanochannels compared to the metal oxide in the grains between the grains; And
A selection element comprising an upper electrode disposed on the polycrystalline metal oxide film. The method according to claim 11,
The crystal grains are metal oxide grains represented by the following formula (1),
The nano-channel is a metal oxide represented by the following formula (2):
[Formula 1]
M _x O _y
In Chemical Formula 1, M is a metal, and x and y are integers satisfying stoichiometry.
[Formula 2]
M _x O _yz
In Formula 2, M, x and y are the same as in Formula 1, and z is greater than 0 and 1 or less. The method according to claim 12,
M is Ta, Ti, Nb, W, Hf, Zn, Mo, Co, Cu, Ag, Cr, Al, Ga, Si, or Mg. A metal layer, a diffusion control layer, and a metal oxide film are sequentially formed on the substrate, wherein the metal layer is a layer of the same metal as the metal contained in the metal oxide film;
The substrate on which the metal oxide film is formed is heat-treated in an inert gas atmosphere to crystallize the metal oxide film to change into a polycrystalline film having a large number of grains and grain boundaries therebetween, and the metal in the metal layer is passed through the diffusion control layer. Diffusing to grain boundaries; And
And forming an upper electrode on the heat-treated metal oxide film. A plurality of first wires arranged in parallel in one direction;
A plurality of second wires intersecting the first wires and arranged parallel to each other on the first wires; And
In each part where the first wirings and the second wirings intersect, a selection element and a memory element that are sequentially stacked between the first wiring and the second wiring are included,
The selection element is a cross-point memory, which is a polycrystalline metal oxide film including conductive nanochannels formed in insulating grains and grain boundaries between the grains. The method according to claim 15,
And an intermediate electrode disposed between the selection element and the memory element. The method according to claim 15,
The memory element is a phase change memory layer, a resistance change memory layer, or a cross point memory that is a magnetoresistive memory layer.

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