KR20200089380A - Display apparatus and the manufacturing method thereof - Google Patents

Abstract

The present invention may provide a display device having a sensor area in which a component such as a sensor can be disposed inside a display area. According to an embodiment of the present invention, disclosed is a display device comprising: a substrate including a display area including a main pixel, and a sensor area including an auxiliary pixel and a transmission unit; and a component which transmits a signal over the substrate through the transmission unit. A blocking layer is disposed between the component and a thin film transistor of the auxiliary pixel to cover the entire semiconductor layer on a plane.

Description

Display apparatus and the manufacturing method thereof

Embodiments of the present invention relate to a display device and a method of manufacturing the same.

2. Description of the Related Art In recent years, display devices have been diversified. In addition, since the thickness of the display device is thin and the weight is light, the range of its use is widening.

As the display device is used in various ways, there may be various methods for designing the shape of the display device, and the function of grafting or linking to the display device is increasing.

Embodiments of the present invention can provide a display device having a sensor area in which a component such as a sensor can be disposed inside the display area. In particular, it is possible to provide a display device with an improved arrangement structure of a blocking layer that prevents device damage by components. However, these problems are exemplary, and the scope of the present invention is not limited thereby.

An embodiment of the present invention includes a substrate including a display area having a main pixel, an auxiliary pixel and a sensor area having a transmissive portion, and a component that sends a predetermined signal through the transmissive portion beyond the substrate, wherein the auxiliary pixel is a semiconductor. Provided is a display device including an auxiliary thin film transistor including a layer and a blocking layer covering the entire semiconductor layer of the auxiliary thin film transistor on a plane between the component and the auxiliary thin film transistor.

The blocking layer may have the same pattern as the semiconductor layer pattern of the auxiliary thin film transistor.

The pattern width of the blocking layer may be wider than that of the semiconductor layer of the auxiliary thin film transistor.

The blocking layer may include a pattern different from the pattern of the semiconductor layer of the auxiliary thin film transistor.

The thickness of the blocking layer may be 800 Å or more.

A buffer layer may be interposed between the auxiliary thin film transistor and the blocking layer and between the blocking layer and the substrate.

The auxiliary pixel may further include an organic light emitting device connected to the auxiliary thin film transistor.

The main pixel includes a main thin film transistor including a semiconductor layer, and a blocking layer covering the entire semiconductor layer of the main thin film transistor on a plane may be disposed between the component and the main thin film transistor.

The main pixel may further include an organic light emitting device connected to the main thin film transistor.

The signal may include either an optical signal or an acoustic signal.

In addition, an embodiment of the present invention includes forming a display area having a main pixel on the substrate and a sensor area having an auxiliary pixel and a transmissive part, and transmitting a predetermined signal over the substrate through the transmissive part on one side of the substrate. Disposing a sending component, and forming a blocking layer between the component and the auxiliary pixel, forming an auxiliary thin film transistor including a semiconductor layer in the auxiliary pixel, and the blocking layer on the auxiliary plane Provided is a method of manufacturing a display device that is disposed to cover the entire semiconductor layer of a thin film transistor.

The blocking layer may be formed in the same pattern as the semiconductor layer pattern of the auxiliary thin film transistor.

The blocking layer may have a larger pattern width than the semiconductor layer pattern width of the auxiliary thin film transistor.

The blocking layer may be formed in a pattern different from that of the semiconductor layer of the auxiliary thin film transistor.

The thickness of the barrier layer can be formed to 800 Å or more.

A buffer layer may be interposed between the auxiliary thin film transistor and the blocking layer and between the blocking layer and the substrate.

The auxiliary pixel may further include an organic light emitting device connected to the auxiliary thin film transistor.

A main thin film transistor including a semiconductor layer is formed in the main pixel, and a blocking layer covering the entire semiconductor layer of the main thin film transistor on a plane may be disposed between the component and the main thin film transistor.

The main pixel may further include an organic light emitting device connected to the main thin film transistor.

The signal may include either an optical signal or an acoustic signal.

Other aspects, features, and advantages other than those described above will become apparent from the following drawings, claims, and detailed description of the invention.

According to embodiments of the present invention, a pixel portion and a transmissive portion are disposed in a sensor region corresponding to a component such as a sensor, and a blocking layer disposed to correspond to the pixel portion is provided to create an environment in which the sensor can operate. At the same time, an image can be implemented in an area overlapping the component. In addition, since the entire semiconductor layer of the thin film transistor is covered with the blocking layer, the step by the blocking layer does not affect the semiconductor layer, and even if the blocking layer is formed thick enough to sufficiently prevent leakage current generation due to the signal of the component. The problem of disconnection of the semiconductor layer due to the level difference does not occur.

Accordingly, a display device having various functions and improving quality can be provided. However, the above-described effects are exemplary, and the effects according to the embodiments will be described in detail through the following.

1 is a perspective view schematically illustrating a display device according to an exemplary embodiment of the present invention.
2 is a cross-sectional view taken along line A-A' of FIG. 1.
3 is a plan view of FIG. 1.
4 is a plan view showing a schematic arrangement of an auxiliary pixel and a main pixel around the sensor area of the display panel shown in FIG. 1.
5 is an enlarged plan view of the auxiliary pixel of FIG. 4.
6 is a plan view showing only the semiconductor layer and the blocking layer in FIG. 5.
7A is a cross-sectional view of FIG. 6 taken along line B-B'.
FIG. 7B is a cross-sectional view illustrating a disconnection situation when the blocking layer is only under a partial region of the semiconductor layer as a comparative example with FIG. 7A.
8 is a cross-sectional view of FIG. 4.
9A to 9D are plan views illustrating a deformable structure of the blocking layer illustrated in FIG. 6.
10 is a schematic cross-sectional view of a display panel according to another exemplary embodiment of the present invention.

The present invention can be applied to various transformations and can have various embodiments, and specific embodiments will be illustrated in the drawings and described in detail in the detailed description. Effects and features of the present invention and methods for achieving them will be clarified with reference to embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, and the same or corresponding components will be given the same reference numerals when describing with reference to the drawings, and redundant description thereof will be omitted. .

In the following embodiments, the singular expression includes a plural expression unless the context clearly indicates otherwise.

In the examples below, terms such as include or have are meant to mean that features or components described in the specification exist, and do not preclude the possibility of adding one or more other features or components.

In the drawings, the size of components may be exaggerated or reduced for convenience of description. For example, since the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of description, the present invention is not necessarily limited to what is shown.

When an embodiment can be implemented differently, a specific process order may be performed differently from the described order. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order opposite to that described.

1 is a perspective view schematically illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the display device 1 includes a display area DA that implements an image and a non-display area NDA that does not implement an image. The display device 1 may provide a main image using light emitted from the plurality of main pixels Pm disposed in the display area DA.

The display device 1 includes a sensor area SA. The sensor area SA may be an area in which a component 20 such as a sensor using an optical signal or an acoustic signal is disposed under the sensor area SA, as described later with reference to FIG. 2. The sensor area SA may include a transmission unit TA through which an optical signal or/and an acoustic signal that is output from the component 20 to the outside or proceeds from the outside toward the component 20 can be transmitted. In one embodiment of the present invention, when infrared rays are transmitted through the sensor area SA, the light transmittance is about 10% or more, more preferably 20% or more, 25% or more, 50% or more, or 85% or more , 90% or more.

In this embodiment, a plurality of auxiliary pixels Pa may be disposed in the sensor area SA, and a predetermined image may be provided using light emitted from the plurality of auxiliary pixels Pa. The image provided in the sensor area SA is an auxiliary image, and may have a lower resolution than the image provided in the display area DA. That is, since the sensor area SA includes a transmissive unit TA through which an optical signal or/and an acoustic signal can be transmitted, the number of auxiliary pixels Pa that can be disposed per unit area is a unit area in the display area DA. It may be less than the number of main pixels (Pm) disposed per sugar.

The sensor area SA may be at least partially surrounded by the display area DA, and as an embodiment, FIG. 1 shows that the sensor area SA is entirely surrounded by the display area DA.

Hereinafter, as the display device 1 according to an embodiment of the present invention, an organic light emitting display device will be described as an example, but the display device of the present invention is not limited thereto. As another embodiment, various types of display devices may be used, such as an inorganic EL display device (Inorganic Light Emitting Display), a quantum dot light emitting display device, and the like.

In FIG. 1, the sensor area SA is disposed on one side (upper right side) of the rectangular display area DA, but the present invention is not limited thereto. The shape of the display area DA may be a circle, an ellipse, or a polygon such as a triangle or pentagon, and the position and number of the sensor areas SA may be variously changed.

2 is a schematic cross-sectional view of a display device according to some example embodiments of the present invention, and may correspond to a cross-section along line A-A' in FIG. 1.

Referring to FIG. 2, the display device 1 may include a display panel 10 including display elements and a component 20 corresponding to the sensor area SA.

The display panel 10 may include a substrate 100, a display element layer 200 disposed on the substrate 100, and a thin film encapsulation layer 300 as a sealing member for sealing the display element layer 200. . In addition, the display panel 10 may further include a lower protective film 175 disposed under the substrate 100.

The substrate 100 may include glass or polymer resin. Polymeric resins include polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), and polyethylene terephthalate (PET) , Polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC) or cellulose acetate propionate (CAP) can do. The substrate 100 including the polymer resin may have flexible, rollable, or bendable properties. The substrate 100 may have a multi-layer structure including a layer including the above-described polymer resin and an inorganic layer (not shown).

The display element layer 200 may include a circuit layer including a thin film transistor (TFT, TFT'), an organic light emitting device (OLED) as a display element, and an insulating layer IL, IL' between them.

A main pixel Pm including a main thin film transistor (TFT) and an organic light-emitting diode (OLED) connected thereto is disposed in the display area DA, and an auxiliary thin film transistor (TFT) is disposed in the sensor area SA. '), an auxiliary pixel Pa including an organic light-emitting diode (OLED) connected thereto, and wirings WL may be disposed.

Also, in the sensor area SA, an auxiliary thin film transistor TFT' and a transmissive portion TA in which a display element is not disposed may be disposed. The transmission unit TA may be understood as an area in which an optical signal or/and an acoustic signal emitted from the component 20 or an optical signal or/and an acoustic signal incident on the component 20 is transmitted.

The component 20 may be located in the sensor area SA. The component 20 may be an electronic element using light or sound. For example, the component 20 is a sensor that receives and uses light, such as an infrared sensor, a sensor that outputs and senses light or sound, measures a distance or recognizes a fingerprint, or a small lamp that outputs light, or a speaker that outputs sound Etc. Of course, in the case of an electronic element using light, light of various wavelength bands such as visible light, infrared light, and ultraviolet light can be used. The number of components 20 disposed in the sensor area SA may be provided in plural. For example, as the component 20, a light emitting element and a light receiving element may be provided together in one sensor area SA. Alternatively, the light emitting unit and the light receiving unit may be simultaneously provided in one component 20.

In this embodiment, a blocking layer BSM may be disposed in the sensor area SA. The blocking layer BSM may be disposed to correspond to the lower portions of the wirings WL and the lower portion of the auxiliary thin film transistor TFT'. The blocking layer BSM may prevent external light from reaching the auxiliary pixel Pa including the wirings WL and the auxiliary thin film transistor TFT'. For example, it prevents light emitted from the component 20 from reaching the wirings WL and the auxiliary pixel Pa.

Meanwhile, a constant voltage or a signal is applied to the blocking layer BSM, thereby preventing damage to the pixel circuit due to electrostatic discharge. In addition, the blocking layer BSM is particularly characterized by a planar arrangement relationship with respect to the auxiliary pixel Pa, which will be described in detail later.

The thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this regard, FIG. 2 shows the first and second inorganic encapsulation layers 310 and 330 and the organic encapsulation layer 320 therebetween.

The first and second inorganic encapsulation layers 310 and 330 may include one or more inorganic insulating materials such as aluminum oxide, titanium oxide, tartalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. .

The organic encapsulation layer 320 is polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (for example, polymethyl methacrylate) , Polyacrylic acid, etc.) or any combination thereof.

The lower protective film 175 is attached to the lower portion of the substrate 100, and may serve to support and protect the substrate 100. The lower protective film 175 may include an opening 175OP corresponding to the sensor area SA. By providing the opening 175OP in the lower protective film 175, it is possible to improve the light transmittance of the sensor area SA. The lower protective film 175 may be provided including polyethylene terephthalide (polyethyeleneterepthalate, PET) or polyimide (PI).

The area of the sensor area SA may be larger than the area where the component 20 is disposed. Accordingly, the area of the opening 175OP provided in the lower protective film 175 may not match the area of the sensor area SA. For example, the area of the opening 175OP may be smaller than the area of the sensor area SA.

Although not shown, components such as an input sensing member for sensing a touch input on the display panel 10, an anti-reflection member including a polarizer and a retarder or a color filter and a black matrix, and a transparent window Can be further arranged.

Meanwhile, in this embodiment, the thin film encapsulation layer 300 is used as an encapsulation member for sealing the display element layer 200, but the present invention is not limited thereto. For example, as a member for sealing the display element layer 200, a sealing substrate bonded to the substrate 100 by a sealant or frit may be used.

3 is a plan view showing the wiring structure on the plane of FIG. 1 in more detail.

Referring to FIG. 3, the display panel 10 includes a plurality of main pixels Pm disposed in the display area DA. Each of the main pixels Pm may include a display element such as an organic light emitting element. Each main pixel Pm may emit light of, for example, red, green, blue, or white through an organic light emitting device. The main pixel Pm in this specification may be understood as a pixel that emits light of any one of red, green, blue, and white colors as described above. The display area DA is covered with the sealing member described above with reference to FIG. 2 to be protected from outside air or moisture.

The sensor area SA may be disposed inside the display area DA, and a plurality of auxiliary pixels Pa are disposed in the sensor area SA. The auxiliary pixels Pa may each include a display element such as an organic light emitting element. Each auxiliary pixel Pa may emit light of, for example, red, green, blue, or white through an organic light emitting element. The auxiliary pixel Pa in this specification may be understood as a pixel that emits light of any one of red, green, blue, and white colors as described above. On the other hand, the sensor area SA may be provided with a transmissive portion TA disposed between the auxiliary pixels Pa.

In one embodiment, one main pixel Pm and one auxiliary pixel Pa may include the same pixel circuit. However, the present invention is not limited to this. It goes without saying that the pixel circuit included in the main pixel Pm and the pixel circuit included in the auxiliary pixel Pa may be different.

Since the sensor area SA includes a transmissive portion TA, the resolution of the sensor area SA may be smaller than that of the display area DA. For example, the resolution of the sensor area SA may be about 1/2 of the display area DA. In some embodiments, the resolution of the display area DA is 400 ppi or more, and the resolution of the sensor area SA may be about 200 ppi.

Each pixel Pm, Pa may be electrically connected to outer circuits disposed in the non-display area. In the non-display area NDA, the first scan driving circuit 110, the second scan driving circuit 120, the terminal 140, the data driving circuit 150, the first power supply wiring 160, and the second power Supply wiring 170 may be arranged.

The first scan driving circuit 110 may provide a scan signal to each pixel Pm, Pa through the scan line SL. The first scan driving circuit 110 may provide a light emission control signal to each pixel through the light emission control line EL. The second scan driving circuit 120 may be arranged side by side with the first scan driving circuit 110 with the display area DA interposed therebetween. Some of the pixels Pm and Pa disposed in the display area DA may be electrically connected to the first scan driving circuit 110, and the other may be connected to the second scan driving circuit 120. In another embodiment, the second scan driving circuit 130 may be omitted.

The terminal 140 may be disposed on one side of the substrate 100. The terminal 140 may be exposed without being covered by the insulating layer and electrically connected to the printed circuit board (PCB). The terminal (PCB-P) of the printed circuit board (PCB) may be electrically connected to the terminal 140 of the display panel 10. The printed circuit board (PCB) transmits a signal or power from a control unit (not shown) to the display panel 10. The control signal generated by the control unit may be transmitted to the first and second scan driving circuits 110 and 120, respectively, through a printed circuit board (PCB). The control unit is the first and second power supply to the first and second power supply wiring (160, 170) through the first and second connection wiring (161, 171), respectively (ELVDD, ELVSS, see Fig. 4a, 4b to be described later) Can provide The first power voltage ELVDD is provided to each pixel Pm, Pa through the driving voltage line PL connected to the first power supply wiring 160, and the second power voltage ELVSS is the second power supply wiring ( It may be provided on the counter electrode of each pixel (Pm, Pa) connected to (170).

The data driving circuit 150 is electrically connected to the data line DL. The data signal of the data driving circuit 150 may be provided to each pixel Pm and Pa through the connection wiring 151 connected to the terminal 140 and the data line DL connected to the connection wiring 151. 3 shows that the data driving circuit 150 is disposed on a printed circuit board (PCB), in another embodiment, the data driving circuit 150 may be disposed on the substrate 100. For example, the data driving circuit 150 may be disposed between the terminal 140 and the first power supply wiring 160.

The first power supply line 160 may include a first sub-wire 162 and a second sub-wire 163 extending side by side along the x direction with the display area DA interposed therebetween. have. The second power supply line 170 may partially surround the display area DA in a loop shape with one side open.

FIG. 4 is a plan view briefly illustrating only one sub-pixel Pa in the sensor area SA, the transmission portion TA, and the main pixel Pm adjacent to the sensor area SA, one by one, and the sub-pixel Pa and the main pixel. The semiconductor layers 1130 are disposed in (Pm), respectively. The semiconductor layer 1130 is an element that becomes an active layer of the auxiliary thin film transistor (TFT') and the main thin film transistor (TFT) provided in each of the auxiliary pixels (Pa) and the main pixels (Pm), and both sides are formed in the same pattern. It is done. Here, the reason why the semiconductor layers 1130 of the sub-pixels Pa and the main pixels Pm are excerpted and briefly displayed is, before explaining the complicated wiring shown in FIG. 5, the semiconductor layers 1130 are the components 20. This is to briefly mention the features of the present embodiment in which a blocking layer (BSM) is disposed in order to prevent it from being blocked from optical signals or acoustic signals. That is, this embodiment has a feature that the semiconductor layer 1130 is well covered with a blocking layer (BSM) so as not to generate leakage current and the like by being disturbed by the signal of the component 20. This feature will be described later in FIG. 6.

FIG. 5 is a plan view of various wirings arranged in the auxiliary pixel Pa including seven auxiliary thin film transistors (TFT': T1 to T7) having the semiconductor layer 1130 as a component. It is considered that the main pixel Pm also has such a wiring arrangement.

As illustrated in FIG. 5, the auxiliary thin film transistor TFT' includes a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, and a motion control thin film transistor. (T5), the light emission control thin film transistor T6 and the second initialized thin film transistor T7 have a structure arranged along the semiconductor layer 1130. The semiconductor layer 1130 is disposed on the substrate 100 on which the inorganic insulating material buffer layer 111a (see FIG. 8) is formed.

Some regions of the semiconductor layer 1130 include a driving thin film transistor (T1), a switching thin film transistor (T2), a compensation thin film transistor (T3), a first initialization thin film transistor (T4), a motion control thin film transistor (T5), and light emission. Corresponds to the active layer of the control thin film transistor T6 and the second initialized thin film transistor T7. In other words, the driving thin film transistor (T1), the switching thin film transistor (T2), the compensation thin film transistor (T3), the first initialization thin film transistor (T4), the motion control thin film transistor (T5), the emission control thin film transistor (T6) and the first It can be understood that the active layers of the 2 initialization thin film transistor T7 are connected to each other and curved in various shapes. Hereinafter, the active layer will be referred to as a semiconductor layer.

The seven auxiliary thin film transistors TFT' are briefly described as follows.

First, the driving thin film transistor T1 includes a driving gate electrode G1 overlapping the driving channel region, driving source electrodes S1 and driving drain electrodes D1 on both sides of the driving channel region. The driving channel region overlapping the driving gate electrode G1 has a bent shape such as an omega shape, thereby forming a long channel length in a narrow space. When the length of the driving channel region is long, a driving range of the gate voltage is widened, so that the gradation of light emitted from the organic light emitting diode (OLED) can be more precisely controlled, and display quality can be improved.

The switching thin film transistor T2 includes a switching gate electrode G2 overlapping the switching channel region, a switching source electrode S2 and a switching drain electrode D2 on both sides of the switching channel region. The switching drain electrode D2 may be connected to the driving source electrode S1.

The compensation thin film transistor T3 is a dual thin film transistor, and may include compensation gate electrodes G3 overlapping two compensation channel regions, and a compensation source electrode S3 and a compensation drain electrode D3 disposed on both sides. It may include. The compensation thin film transistor T3 may be connected to the driving gate electrode G1 of the driving thin film transistor T1 through a node connection line 1174 to be described later.

The first initialized thin film transistor T4 is a dual thin film transistor, and includes a first initialized gate electrode G4 overlapping two first initialized channel regions, and a first initialized source electrode S4 disposed on both sides and a first. One initialization drain electrode D4 may be included.

The motion control thin film transistor T5 may include a motion control gate electrode G5 overlapping the motion control channel region, and a motion control source electrode S4 and a motion control drain electrode D5 located on both sides. The operation control drain electrode D5 may be connected to the driving source electrode S1.

The emission control thin film transistor T6 may include an emission control gate electrode G6 overlapping the emission control channel region, and emission control source electrodes S6 and emission control drain electrodes D6 located on both sides. The emission control source electrode S6 may be connected to the driving drain electrode D1.

The second initialized thin film transistor T7 includes a second initialized gate electrode G7 overlapping the second initialized channel region, and a second initialized source electrode S7 and a second initialized drain electrode D7 located on both sides. can do.

The aforementioned auxiliary thin film transistors TFT' may be connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

The scan line SL, the previous scan line SL-1, the emission control line EL, and the driving gate electrode G1 may be disposed on the semiconductor layer 1130 described above with the insulating layer(s) interposed therebetween. have.

The scan line SL may extend along the first direction. One region of the scan line SL may correspond to the switching and compensation gate electrodes G4 and G7. For example, regions of the scan line SL that overlap the channel regions of the first and second initialization driving thin film transistors T4 and T7 may be first and second initialization gate electrodes G4 and G7, respectively.

The previous scan line SL-1 extends along the first direction, but some regions may correspond to the first and second initialization gate electrodes G4 and G7, respectively. For example, regions of the previous scan line SL-1 overlapping the channel regions of the first and second initialization driving thin film transistors T4 and T7 may be first and second initialization gate electrodes G4 and G7, respectively. have.

The emission control line EL extends in the first direction. One region of the emission control line EL may correspond to operation control and emission control gate electrodes G5 and G6, respectively. For example, the region of the light emission control line EL overlapping with the channel regions of the operation control and light emission control driving thin film transistors T6 and T7 may be the operation control and light emission control gate electrodes G5 and G6, respectively.

The driving gate electrode G1 is a floating electrode and may be connected to the compensation thin film transistor T3 through the node connection line 1174 described above.

The electrode voltage line HL is disposed on the scan line SL, the previous scan line SL-1, the emission control line EL, and the insulating layer(s) on the driving gate electrode G1. Can be.

The electrode voltage line HL may extend in the first direction to cross the data line DL and the driving voltage line PL. A portion of the electrode voltage line HL covers at least a portion of the driving gate electrode G1, and a storage capacitor Cst may be formed together with the driving gate electrode G1. For example, the driving gate electrode G1 becomes the first storage capacitor plate CE1 of the storage capacitor Cst, and a portion of the electrode voltage line HL becomes the second storage capacitor plate CE2 of the storage capacitor Cst. Can.

The second storage capacitor plate CE2 of the storage capacitor Cst is electrically connected to the driving voltage line PL. In this regard, the electrode voltage line HL may be connected to the driving voltage line PL disposed on the electrode voltage line HL and the contact hole CNT. Therefore, the electrode voltage line HL may have the same voltage level (constant voltage) as the driving voltage line PL. For example, the electrode voltage line HL may have a constant voltage of +5V. The electrode voltage line HL can be understood as a lateral driving voltage line.

Since the driving voltage line PL extends along the second direction, and the electrode voltage line HL electrically connected to the driving voltage line PL extends along the first direction crossing the second direction, the driving voltage line PL may extend in the display area. The driving voltage lines PL and the electrode voltage lines HL may have a mesh structure.

A data line DL, a driving voltage line PL, an initialization connection line 1173, and a node connection line 1174 may be disposed on the electrode voltage line HL with the insulating layer(s) interposed therebetween.

The data line DL extends in the second direction and may be connected to the switching source electrode S2 of the switching thin film transistor T2 through the contact hole 1154. Part of the data line DL may be understood as a switching source electrode.

The driving voltage line PL extends in the second direction and is connected to the electrode voltage line HL through the contact hole CNT as described above. Also, it may be connected to the motion control thin film transistor T5 through the contact hole 1155. The driving voltage line PL may be connected to the operation control drain electrode D5 through the contact hole 1155.

One end of the initialization connection line 1173 may be connected to the first and second initialization thin film transistors T4 and T7 through the contact hole 1152, and the other end may be connected to the initialization voltage line VL through the contact hole 1151. have.

One end of the node connection line 1174 may be connected to the compensation drain electrode D3 through the contact hole 1156, and the other end may be connected to the driving gate electrode G1 through the contact hole 1157.

The initialization voltage line VL may be disposed on the data line DL, the driving voltage line PL, the initialization connection line 1173, and the node connection line 1174 with an insulating layer(s) interposed therebetween.

The initialization voltage line VL extends in the first direction. The initialization voltage line VL may be connected to the first and second initialization driving thin film transistors T4 and T7 through the initialization connection line 1173. The initialization voltage line VL may have a constant voltage (eg, -2V, etc.).

The initialization voltage line VL is disposed on the same layer as the pixel electrode 210 of the organic light emitting diode (OLED, FIG. 8) and may include the same material. The pixel electrode 210 may be connected to the light emission control thin film transistor T6. The pixel electrode 210 is connected to the connection metal 1175 through the contact hole 1163, and the connection metal 1175 can be connected to the emission control drain electrode D6 through the contact hole 1153.

As described above, the semiconductor layer 1130 of the auxiliary thin film transistor (TFT') is disposed on the substrate 100 to form a main layer of the plurality of thin film transistors T1 to T7. However, when the optical signal or the acoustic signal of the component 20 is directly transmitted to the semiconductor layer 1130, leakage currents are generated in each of the auxiliary thin film transistors T1 to T7, which may act as an element that interferes with correct operation. have.

Therefore, to prevent this, a blocking layer BSM is formed under the semiconductor layer 1130 as illustrated in FIG. 6. The blocking layer (BSM) is disposed between the component 20 positioned below the substrate 100 and the semiconductor layer 1130 positioned above the substrate 100, so that an optical signal or an acoustic signal emitted to the component 20 is formed. Performs a function of preventing the semiconductor layer 1130 from being directly transmitted. The blocking layer (BSM) is mainly formed of a Mo material, and in order to sufficiently perform this blocking function, the thickness (t1: see FIG. 7A) should be 800 Å or more. However, if a blocking layer (BSM) having a thickness of 800 mm 2 or more is formed only at a position under some regions of the semiconductor layer 1130, for example, the auxiliary thin film transistors T1 to T7, the semiconductor layer 1130 may have a difference in thickness. The risk of disconnection increases. Therefore, in order to prevent this, in this embodiment, the blocking layer BSM is formed in the same pattern as the semiconductor layer 1130 to cover the entire area of the semiconductor layer 1130. Of course, for a more stable blocking function, the width W2 of the blocking layer BSM is formed wider than the width W1 of the semiconductor layer 1130 (W1<W2).

Here, the disconnection problem due to the step may be understood as shown in FIGS. 7A and 7B. FIG. 7A is a structure of this embodiment in which the line B-B' of FIG. 6 is cut, and FIG. 7B is a comparative example illustrating a case in which the blocking layer BSM is only below a partial region of the semiconductor layer 1130.

First, FIG. 7A is a structure of the present embodiment in which a blocking layer BSM is formed under the entire region of the semiconductor layer 1130, and the semiconductor layer 1130 does not rise or fall on a step caused by the blocking layer BSM and is on the blocking layer BSM. Since there is only one, the disconnection problem caused by the step does not occur at the source.

However, if the blocking layer BSM is only below a partial region of the semiconductor layer 1130 as shown in FIG. 7B, the semiconductor layer 1130 moves up and down the step caused by the blocking layer BSM, and at this time, the blocking layer BSM ) The thicker the step becomes, the more easily the disconnection part 1130a as shown in the drawing is likely to occur. Therefore, in the present embodiment, as shown in FIG. 6, the blocking layer BSM is formed in the same pattern as the semiconductor layer 1130 to cover the entire area of the semiconductor layer 1130, thereby fundamentally eliminating the risk of disconnection due to a step difference. Order.

Hereinafter, a cross-sectional structure of the auxiliary pixel Pa and the main pixel Pm having the thin film transistors having the above-described characteristics will be described with reference to FIG. 8. It can be considered that the laminated structure on the substrate 100 schematically illustrated in FIG. 2 is shown in more detail.

In other words, the substrate 100 may include glass or polymer resin. Polymeric resins include polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), and polyethylene terephthalate (PET) , Polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC) or cellulose acetate propionate (CAP) can do. The substrate 100 including the polymer resin may have flexible, rollable, or bendable properties. The substrate 100 may have a multi-layer structure including a layer including the above-described polymer resin and an inorganic layer (not shown).

The buffer layer 111 may be positioned on the substrate 100 to reduce or block penetration of foreign matter, moisture, or outside air from the bottom of the substrate 100 and provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material such as an oxide or a nitride, or an organic material or an organic-inorganic composite, and may be formed of a single layer or multi-layer structure of the inorganic material and the organic material. Between the substrate 100 and the buffer layer 111, a barrier layer (not shown) that blocks the penetration of outside air may be further included. The buffer layer 111 may be provided such that the first buffer layer 111a and the second buffer layer 111b are stacked.

The gate electrode G is disposed on the semiconductor layer 1130 with the first gate insulating layer 112 interposed therebetween. The gate electrode G includes molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed in a single layer or multiple layers. For example, the gate electrode G may be a single layer of Mo. The scan line SL, the previous scan line SL-1, and the emission control line EL may be formed on the same layer as the gate electrode G. That is, the gate electrode G, the scan line SL, the previous scan line SL-1, and the emission control line EL may be disposed on the first gate insulating layer 112.

The first gate insulating layer 112 includes silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), and tantalum oxide (Ta). ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ).

A second gate insulating layer 113 may be provided to cover the gate electrode G. The second gate insulating layer 113 includes silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), and tantalum oxide (Ta). ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ).

The source electrode S, the drain electrode D, and the driving voltage line PL may be disposed on the interlayer insulating layer 115. The source electrode S, the drain electrode D, and the driving voltage line PL may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and the like. It may be formed of a multi-layer or a single layer containing the above material.

The drain electrode D is connected to the pixel electrode 210 of the organic light emitting diode OLED.

The planarization layer 117 may be positioned on the source electrode S, the drain electrode D, and the driving voltage line PL, and the organic light emitting device OLED may be positioned on the planarization layer 117.

The planarization layer 117 may have a flat upper surface so that the pixel electrode 210 can be formed flat. The planarization layer 117 may be formed of a single layer or multiple layers of an organic material. The planarization layer 117 is a general-purpose polymer such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), Polymethylmethacrylate (PMMA), or Polystylene (PS), a polymer derivative having a phenolic group, an acrylic polymer , Imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers and blends thereof. The planarization layer 117 may include an inorganic material. The planarization layer 117 includes silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), and tantalum oxide (Ta _{2 ).} O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ). When the planarization layer 117 is provided with an inorganic material, chemical planarization polishing may be performed in some cases. Meanwhile, the planarization layer 117 may include both organic and inorganic materials.

The pixel electrode 210 may be a (semi)transmissive electrode or a reflective electrode. In some embodiments, the pixel electrode 210 includes a reflective film formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and a compound thereof, and a transparent or translucent electrode layer formed on the reflective film can do. The transparent or translucent electrode layer includes indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In ₂ O ₃ ; indium gallium) It may be provided with at least one selected from the group comprising an oxide (IGO; indium gallium oxide) and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 210 may be provided in a structure stacked with ITO/Ag/ITO.

A pixel defining layer 119 may be disposed on the planarization layer 117, and spin-coated organic insulating materials such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO) and phenol resin, etc. Can form.

The intermediate layer 220 of the organic light emitting device (OLED) may include an organic light emitting layer. The organic light emitting layer may include an organic material including a fluorescent or phosphorescent material that emits red, green, blue, or white light. The organic light emitting layer may be a low molecular organic material or a high molecular organic material, and under and above the organic light emitting layer, a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and A functional layer such as an electron injection layer (EIL) may be further selectively disposed. The intermediate layer 220 may be disposed corresponding to each of the plurality of pixel electrodes 210. However, it is not limited to this. The intermediate layer 220 may be variously modified, including an integral layer over a plurality of pixel electrodes 210.

The counter electrode 230 may be a transmissive electrode or a reflective electrode. In some embodiments, the counter electrode 230 may be a transparent or translucent electrode, and is a metal thin film having a small work function including Li, Ca, LiF/Ca, LiF/Al, Al, Ag, Mg, and compounds thereof. Can be formed. In addition, a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In ₂ O ₃ may be further disposed on the metal thin film. The counter electrode 230 is disposed over the display area DA and the peripheral area PA, and may be disposed over the intermediate layer 220 and the pixel defining layer 119. The counter electrode 230 may be integrally formed in a plurality of organic light emitting diodes (OLEDs) to correspond to the plurality of pixel electrodes 210.

When the pixel electrode 210 is provided as a reflective electrode and a counter electrode 230 as a light-transmitting electrode, light emitted from the intermediate layer 220 is emitted to the counter electrode 230 side, so that the display device has a front emission type. Can be. When the pixel electrode 210 is composed of a transparent or semi-transparent electrode, and the counter electrode 230 is composed of a reflective electrode, light emitted from the intermediate layer 220 is emitted toward the substrate 100, so that the display device has a back light emission type. Can be However, this embodiment is not limited to this. The display device of this embodiment may be of a double-sided emission type that emits light in both front and rear directions.

In this embodiment, the blocking layer BSM is disposed between the substrate 100 and the semiconductor layer 1130 of the auxiliary pixel Pa and between the substrate 100 and the wiring portion DW. More precisely, the blocking layer BSM is disposed between the above-described component 20 and the semiconductor layer 1130 and between the component 20 and the wiring part DW to be assisted by the optical or acoustic signals of the component 20. The thin film transistor TFT' and the wiring part DW are not disturbed. In particular, for the semiconductor layer 1130 of the auxiliary thin film transistor TFT', the entire region of the semiconductor layer 1130 is shown in FIG. The barrier layer (BSM) is completely covered and protected.

Therefore, according to such a structure, it is possible to prevent the risk that a leakage current may be generated by the optical signal or the acoustic signal of the component 20 by blocking the blocking layer (BSM). Particularly, since the semiconductor layer 1130 of the auxiliary thin film transistor (TFT') is sensitive to leakage current generation, the thickness of the blocking layer (BSM) should be 800 Å or more in order to sufficiently prevent this, wherein the thickness of the blocking layer (BSM) The risk of disconnection of the semiconductor layer 1130, which may occur due to the step by, is eliminated by covering the entire region of the semiconductor layer 1130 as the blocking layer BSM follows the same pattern as described in FIG. 6.

Therefore, the blocking layer (BSM) sufficiently prevents leakage current generated by the signal of the component 20, so that the sensor 20 can perform the operation and image implementation of the component 20 smoothly in the sensor area SA, and the semiconductor by the step difference The disconnection problem of the layer 1130 can also be prevented from occurring.

Meanwhile, in the present exemplary embodiment, a case where the blocking layer BSM is formed in the same pattern as the pattern of the semiconductor layer 1130 is illustrated. As illustrated in FIGS. 9A to 9D, the blocking layer BSM may be configured to have some different pattern regions It might be. That is, as long as it can cover the entire area of the semiconductor layer 1130, it has been shown that even if the blocking layer BSM does not necessarily have the same pattern, the function of preventing leakage current generation and suppressing disconnection can be sufficiently performed.

In addition, in the above-described embodiment, as illustrated in FIG. 8, the case where the blocking layer BSM is only below the auxiliary thin film transistor TFT' of the sensor area SA is illustrated, as illustrated in FIG. 10. A blocking layer BSM may be disposed under the main thin film transistor TFT of (Pm) in the same pattern with the same material as the blocking layer BSM of the auxiliary thin film transistor TFT'. That is, since the main pixel Pm is not in the sensor area SA in which the component 20 is located, it is not a big problem without the blocking layer BSM, but the degree of noise mixing due to external light other than the component 20 For the purpose of thorough blocking, a blocking layer BSM may be disposed under the main thin film transistor TFT of the main pixel Pm to cover the entire area of the semiconductor layer 1130.

As described above, the present invention has been described with reference to one embodiment shown in the drawings, but this is only an example, and those skilled in the art will understand that various modifications and modifications of the embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

1: Display device 10: Display panel
100: substrate 1130: semiconductor layer
TFT: Main thin film transistor TFT': Secondary thin film transistor
SA: Sensor area DA: Display area
NDA: Non-display area Pa: Secondary pixel
Pm: Main pixel BSM: Barrier layer

Claims (20)

A substrate comprising a display area having a main pixel and a sensor area having a secondary pixel and a transmissive portion, and a component for transmitting a predetermined signal over the substrate through the transmissive portion,
The auxiliary pixel includes an auxiliary thin film transistor including a semiconductor layer,
A display device including a blocking layer covering the entire semiconductor layer on a plane between the component and the auxiliary thin film transistor.
According to claim 1,
The blocking layer is a display device having the same pattern as the semiconductor layer pattern of the auxiliary thin film transistor.
According to claim 2,
A display device having a larger pattern width of the blocking layer than that of the semiconductor layer pattern of the auxiliary thin film transistor.
According to claim 1,
The blocking layer includes a pattern different from the semiconductor layer pattern of the auxiliary thin film transistor.
According to claim 1,
A display device having a thickness of the barrier layer of 800 mm or more.
According to claim 1,
A display device having a buffer layer interposed between the auxiliary thin film transistor and the blocking layer and between the blocking layer and the substrate.
According to claim 1,
The auxiliary pixel further includes an organic light emitting device connected to the auxiliary thin film transistor.
According to claim 1,
The main pixel includes a main thin film transistor including a semiconductor layer,
A display device including a blocking layer covering the entire semiconductor layer of the main thin film transistor on a plane between the component and the main thin film transistor.
The method of claim 8,
The main pixel further includes an organic light emitting device connected to the main thin film transistor.
According to claim 1,
The signal is a display device including any one of an optical signal and an acoustic signal.
Forming a display area having a main pixel and a sensor area having a secondary pixel and a transmissive portion on a substrate, and disposing a component that transmits a predetermined signal over the substrate through the transmissive portion on one side of the substrate; And forming a blocking layer between the component and the auxiliary pixel,
An auxiliary thin film transistor including a semiconductor layer is formed in the auxiliary pixel,
A method of manufacturing a display device in which the blocking layer is disposed to cover the entire semiconductor layer of the auxiliary thin film transistor on a plane.
The method of claim 11,
A method of manufacturing a display device in which the blocking layer is formed in the same pattern as the semiconductor layer pattern of the auxiliary thin film transistor.
The method of claim 12,
A method of manufacturing a display device in which the pattern width of the blocking layer is wider than that of the semiconductor layer pattern of the auxiliary thin film transistor.
The method of claim 11,
A method of manufacturing a display device that forms the blocking layer in a pattern different from the semiconductor layer pattern of the auxiliary thin film transistor.
The method of claim 11,
A method of manufacturing a display device for forming the thickness of the blocking layer to 800Å or more.
The method of claim 11,
A method of manufacturing a display device, wherein a buffer layer is interposed between the auxiliary thin film transistor and the blocking layer and between the blocking layer and the substrate.
The method of claim 11,
The auxiliary pixel further comprises an organic light emitting device connected to the auxiliary thin film transistor.
The method of claim 11,
A main thin film transistor including a semiconductor layer is formed in the main pixel,
A method of manufacturing a display device in which a blocking layer covering the entire semiconductor layer of the main thin film transistor is disposed on a plane between the component and the main thin film transistor.
The method of claim 18,
The main pixel is a method of manufacturing a display device further comprising an organic light emitting device connected to the main thin film transistor.
The method of claim 11,
The signal is a method of manufacturing a display device including any one of an optical signal and an acoustic signal.

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