KR20200072782A - Flexible electroluminesence display - Google Patents

Abstract

The present application relates to a flexible electroluminescent display device. The flexible electroluminescent display device according to one embodiment of the present application comprises a flexible substrate, a scan line, a data line, a pixel driving power line, a driving element, and a light emitting element. The flexible substrate includes a base layer and a partition wall protruding at a predetermined thickness to define a plurality of pixels arranged in a matrix manner on a surface of a base layer. The scan line is provided in a horizontal direction of the flexible substrate over the partition wall. The data line and the pixel driving power line are provided in a vertical direction of the flexible substrate over the partition wall. The driving element is disposed in the pixel and connected to the scan line, the data line, and the pixel driving power line. The light emitting element is disposed in the pixel and connected to the driving element. According to the present invention, even if a repeated bending operation is performed, cracking or damage does not occur.

Description

Flexible EL display {FLEXIBLE ELECTROLUMINESENCE DISPLAY}

The present application relates to a flexible electroluminescent display device. In particular, the present application relates to a flexible electroluminescent display device having a structure robust against bending stress when the display area is folded or unfolded or rolled out.

Among the display devices, the electroluminescent display device is a self-emission type, and has excellent viewing angle, contrast ratio, and the like, and does not require a separate backlight, so that it can be lightweight and thin, and has an advantage in that power consumption is advantageous. In particular, among the electroluminescent display devices, the organic light emitting display device has advantages such as DC low voltage driving, fast response speed, and low manufacturing cost.

The electroluminescent display device includes a plurality of electroluminescent diodes. The electroluminescent diode includes an anode electrode, a light emitting layer formed on the anode electrode, and a cathode electrode formed on the light emitting layer. When a high potential voltage is applied to the anode electrode and a low potential voltage is applied to the cathode electrode, holes are transferred from the anode electrode and electrons are transferred from the cathode electrode to the light emitting layer, respectively. When holes and electrons are combined in the light emitting layer, excitons are formed in the excitation process, and light is generated due to energy from the excitons. The electroluminescent display device displays an image by electrically controlling the amount of light generated in the light emitting layers of the plurality of electroluminescent diodes individually divided by the bank.

The electroluminescent display device can be implemented in an ultra-thin form, and has the advantage of making the most of the flexibility characteristic of organic materials. Using excellent flexibility, it is easy to develop into a foldable display device that can be folded and unfolded as needed or a rollable display device that is rolled, stored, and opened in a rolled manner. However, if the folding and unfolding operation is repeated repeatedly, cracking or breakage may occur in the folded portion due to bending stress. When such a break occurs, moisture or foreign matter penetrates into the inside of the rollable or foldable electroluminescent display device from the outside through the damaged defect portion, which may shorten the life of the electroluminescent display device.

An object of the present application is to provide a flexible electroluminescent display device capable of preventing cracking or damage by minimizing bending stress even when bending and unfolding operations are repeated. In addition, the present application is to provide a flexible electroluminescent display device having a structure capable of absorbing stress due to repeated bending operation and suppressing moisture penetration from the outside.

The flexible electroluminescent display device according to an exemplary embodiment of the present application includes a flexible substrate, a scan wiring, a data wiring, a pixel driving power supply wiring, a driving element, and a light emitting element. The flexible substrate includes a base layer and a partition wall protruding a certain thickness to define a plurality of pixels arranged in a matrix manner on the surface of the base layer. The scan wiring travels across the partition wall in the horizontal direction of the flexible substrate. The data wiring and the pixel driving power supply wiring travel across the partition wall in the vertical direction of the flexible substrate. The driving element is disposed in the pixel and connected to the scan wiring, data wiring, and pixel driving power supply wiring. The light emitting element is disposed in the pixel and connected to the driving element.

In one example, the base layer has a thickness thinner than the partition wall. The base layer and the partition wall are integrally formed.

In one example, the driving element and the light emitting element are disposed inside a pixel surrounded by a partition wall. The scan wiring, data wiring and pixel driving current wiring are arranged to pass over the partition wall and over the base layer.

In one example, a spacer having a reverse tapered cross-sectional shape and stacked on the partition wall is further included. The light emitting layer is separated for each pixel by a spacer. The common electrode is commonly stacked on the light emitting layer of neighboring pixels in a horizontal direction beyond the spacer.

In one example, a planarization film stacked between the driving element and the light emitting element is further included. The side surface of the insulating film made of an inorganic material included in the driving element contacts the side surface of the partition wall.

In one example, the planarizing film is stacked higher than the height of the partition wall to cover the upper surface of the partition wall.

In one example, the planarizing film is stacked lower than the height of the partition wall so that the side surface of the planarizing film contacts the side surface of the partition wall.

In one example, the flexible substrate includes a display area in which pixels are disposed, and a non-display area surrounding the display area. The non-display area includes a gate driving element disposed on the base layer, a common power wiring disposed on the base layer, a dam structure disposed on the base layer, and protrudes upward along an outermost edge of the base layer, and an external partition wall surrounding the dam structure. Includes.

In one example, the inorganic material layer is not laminated on the upper surface of the outer partition wall.

As an example, a first inorganic encapsulation layer stacked on a light emitting device over a partition wall, an organic encapsulation layer laminated on the first inorganic encapsulation layer, and a second inorganic encapsulation layer laminated on the organic encapsulation layer are further included.

In one example, the organic encapsulation layer is limited to the region inside the dam structure. The first inorganic encapsulation layer and the second inorganic encapsulation layer seal the organic encapsulation layer, make surface contact from outside the dam structure, and contact the inner surface of the outer partition wall.

For example, a buffer layer stacked under the base layer and a lower substrate stacked under the buffer layer are further included.

The flexible electroluminescent display device according to the present application has a structure capable of alleviating or absorbing stress even when a bending and unfolding operation is repeated. As a result, even if a repeated bending operation is performed, no crack or breakage occurs. The flexible electroluminescent display device according to the present application is robust to bending stress and has a structure capable of preventing penetration of moisture and foreign substances from the outside.

In addition to the effects of the present application mentioned above, other features and advantages of the present application are described below, or will be clearly understood by those skilled in the art from the description and description.

1 is a plan view showing a flexible electroluminescent display device according to a preferred embodiment of the present application.
2 is an enlarged plan view showing a structure of a single pixel in a flexible electroluminescent display device according to an exemplary embodiment of the present application.
3 illustrates a structure of a flexible electroluminescent display device according to an exemplary embodiment of the present application, and is a cross-sectional view of FIG. 2 along line I-I'.
4 illustrates a structure of a flexible electroluminescent display device according to another exemplary embodiment of the present application, and is a cross-sectional view of FIG. 2 along line I-I'.
5 is a cross-sectional view illustrating a structure of a flexible electroluminescent display device according to another exemplary embodiment of the present application taken along the line II-II' of FIG. 1.

Advantages and features of the present application, and a method of achieving them will be clarified with reference to examples described below in detail together with the accompanying drawings. However, the present application is not limited to the examples disclosed below, but will be implemented in various different forms, and only the examples of the present application allow the disclosure of the present application to be complete, and are generally in the art to which the invention of the present application pertains. It is provided to fully inform the person of knowledge of the scope of the invention, and the invention of the present application is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining an example of the present application are exemplary, and the present application is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. In addition, in describing an example of the present application, when it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present application, the detailed description will be omitted.

When'include','have','consist of' and the like mentioned in this specification are used, other parts may be added unless'~man' is used. When a component is expressed as a singular number, the plural number is included unless otherwise specified.

In interpreting the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, when the positional relationship of two parts is described as'~top','~upper','~bottom','~side', etc.,'right' Alternatively, one or more other parts may be located between the two parts unless'direct' is used.

In the case of a description of a time relationship, for example,'after','following','~after','~before', etc. When a temporal sequential relationship is described,'right' or'direct' It may also include cases that are not continuous unless it is used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. Accordingly, the first component mentioned below may be the second component within the technical spirit of the present application.

It should be understood that the term “at least one” includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item, and the third item" means 2 of the first item, the second item, or the third item, as well as the first item, the second item, and the third item, respectively. It can mean any combination of items that can be presented from more than one dog.

Each of the features of the various examples of the present application may be partially or totally combined or combined with each other, technically various interlocking and driving may be possible, and each of the examples may be independently implemented with respect to each other or may be implemented together in an associative relationship. .

Hereinafter, an example of the flexible electroluminescent display device according to the present application will be described in detail with reference to the accompanying drawings. In adding reference numerals to the components of each drawing, the same components may have the same reference numerals as possible, even if they are displayed on different drawings.

1 is a plan view showing a flexible electroluminescent display device according to a preferred embodiment of the present application. Referring to FIG. 1, the flexible electroluminescent display device according to the present application may include a flexible substrate FS, a pixel P, a partition wall PD, a common power wiring CPL, and a dam structure DM.

The flexible substrate FS is a base substrate (or base layer), and includes a plastic material or a glass material. In particular, in the case of a flexible display device, it is preferable to form a plastic material having excellent flexibility. However, even if it is a glass material, it can be formed in an ultra-thin shape to implement a flexible display device.

The flexible substrate FS according to an example may have a square shape in a planar shape, a square shape in which each corner portion is rounded with a constant curvature radius, or a non-square shape having at least six sides. Here, the flexible substrate FS having a non-square shape may include at least one protrusion or at least one notch portion.

The flexible substrate FS according to an example may be divided into a display area AA and a non-display area IA. The display area AA is provided in the central area of the flexible substrate FS, and may be defined as an area for displaying an image. The display area AA according to an example may have a planar square shape, a square shape rounded so that each corner portion has a constant radius of curvature, or a non-square shape having at least six sides. Here, the display area AA having a non-square shape may include at least one protrusion or at least one notch.

The non-display area IA is provided in an edge area of the flexible substrate FS to surround the display area AA, and may be defined as an area in which an image is not displayed or a peripheral area. The non-display area IA according to an example includes a first non-display area IA1 provided on a first edge of the flexible substrate FS, and a second edge of the flexible substrate FS parallel to the first non-display area IA1. The second non-display area IA2 provided on the third non-display area IA3 provided on the third edge of the flexible substrate FS, and the fourth non-display area IA3 provided on the third edge of the flexible substrate FS parallel to the third non-display area A fourth non-display area IA4 may be included. For example, the first non-display area IA1 is an upper (or lower) edge area of the flexible substrate FS, and the second non-display area IA2 is a lower (or upper) edge area of the flexible substrate FS, The third non-display area IA3 may be the left (or right) edge area of the flexible substrate FS, and the fourth non-display area IA4 may be the right (or left) edge area of the flexible substrate FS, It is not necessarily limited to this.

The pixel P may be provided on the display area AA of the flexible substrate FS. A plurality of pixels P according to an example may be arranged in a matrix arrangement and may be disposed in the display area AA of the flexible substrate FS. The pixel P may be defined by the partition wall PD. The partition wall PD has a constant width and surrounds the pixel P. For example, a plurality of pixels P are partitioned and defined in a matrix manner by a mesh-shaped partition wall PD having a constant width.

The pixel P according to an example may be disposed to have a stripe structure on the display area AA. In this case, one unit pixel may include a red pixel, a green pixel, and a blue pixel, and further, one unit pixel may further include a white pixel.

The pixel P according to another example may be arranged to have a pentile structure on the display area AA. In this case, one unit pixel may include at least one red pixel, at least two green pixels, and at least one blue pixel arranged in a planar polygonal shape. For example, one unit pixel having a pentile structure may be disposed such that one red pixel, two green pixels, and one blue pixel have an octagonal shape in a plane, in which case the blue pixel is relatively A large sized opening area (or a light emitting area) may be provided, and the green pixel may have a relatively smallest sized opening area.

The pixel P is a pixel circuit PC electrically connected to the scan wiring SL, the sensing wiring RL, the data wiring DL and the pixel driving power supply wiring PL, and is electrically connected to the pixel circuit PC. It may include a light emitting element (ED).

The scan wiring SL, the sensing wiring RL, the data wiring DL, and the pixel driving power wiring PL may be disposed on the edge of the pixel P. These wirings extend over a plurality of pixels P. Therefore, these wirings extend across the pixels P over the partition wall PD.

The scan wiring SL is elongated along the first direction X and is disposed at regular intervals along the second direction Y intersecting the first direction X. The display area AA of the flexible substrate FS includes a plurality of scan wirings SL spaced from each other along the second direction Y while being parallel to the first direction X. Here, the first direction X may be defined in the horizontal direction of the flexible substrate FS, and the second direction Y may be defined in the vertical direction of the flexible substrate FS, but is not limited thereto. Conversely, it can also be defined.

The sensing wiring RL is disposed on the flexible substrate FS to be parallel to the scan wiring SL. The display area AA of the flexible substrate FS includes a plurality of sensing wires RL parallel to the scan wires SL. In some cases, the sensing wiring RL may further include a vertical sensing wiring parallel to the data wiring DL.

The data wiring DL extends long along the second direction Y and is arranged at regular intervals along the first direction X. The display area AA of the flexible substrate FS includes a plurality of data lines DL spaced apart from each other along the first direction X while being parallel to the second direction Y.

The pixel driving power supply line PL is disposed on the flexible substrate FS to be parallel to the data line DL. The display area AA of the flexible substrate FS includes a plurality of pixel driving power supply lines PL parallel to the data line DL. Alternatively, the pixel driving power supply wiring PL may be arranged to be parallel to the scan wiring SL.

The pixel circuit PC is disposed in an area inside the pixel P surrounded by the partition PD, and inside the pixel P in response to a scan signal supplied from one scan line SL passing through the area inside the pixel P The current Ied flowing from the pixel driving power supply line PL to the light emitting element ED is controlled based on the data voltage supplied from the data line DL passing through the region.

The pixel circuit PC according to an example may include at least two thin film transistors and one capacitor. For example, the pixel circuit PC according to an example drives the driving thin film transistor that supplies the data current Ied based on the data voltage to the light emitting element ED, and drives the data voltage supplied from the data line DL. A switching thin film transistor supplied to the thin film transistor and a capacitor storing the gate-drain voltage of the driving thin film transistor may be included.

The pixel circuit PC according to another example may include at least three thin film transistors and at least one capacitor. For example, the pixel circuit PC according to an example may include a current supply circuit, a data supply circuit, and a compensation circuit according to the operation (or function) of each of the at least three thin film transistors. Here, the current supply circuit may include a driving thin film transistor that supplies the data current Ied based on the data voltage to the light emitting device ED. The data supply circuit may include at least one switching thin film transistor that supplies the data voltage supplied from the data line DL to the current supply circuit in response to the at least one scan signal. The compensation circuit may include at least one compensation thin film transistor that compensates for a change in a characteristic value (threshold voltage and/or mobility) of the driving thin film transistor in response to at least one sensing signal.

The light emitting element ED is disposed inside the pixel P area surrounded by the partition PD, and emits light by the data current Ied supplied from the pixel circuit PC to emit light corresponding to the data current Ied. Emits. In this case, the data current Ied may flow from the pixel driving power supply wiring PL to the common power supply wiring CPL through the driving thin film transistor and the light emitting device ED.

The light emitting device ED according to an example includes a pixel driving electrode (or first electrode or anode) electrically connected to the pixel circuit PC, a light emitting layer formed on the pixel driving electrode, and a common electrode (or a second electrode) electrically connected to the light emitting layer. 2 electrode or cathode).

In the electroluminescent display device according to an exemplary embodiment of the present application, the wirings SL, RL, DL, and PL cross the partition wall PD and cross the region inside the pixel P defined by the partition wall PD. It is disposed on the flexible substrate FS while being struck. On the other hand, the pixel circuit PC and the light emitting element ED are arranged only in the region inside the pixel P divided by the partition wall PD.

The common power wiring CPL is disposed on the non-display area IA of the flexible substrate FS and is electrically connected to the common electrode disposed on the display area AA. The common power wiring CPL according to an example is disposed along the second to fourth non-display areas IA2, IA3, and IA4 adjacent to the display area IA of the flexible substrate FS while having a constant wiring width, A portion of the display area AA adjacent to the first non-display area IA1 of the flexible substrate FS is enclosed. One end of the common power wiring CPL may be disposed on one side of the first non-display area IA1, and the other end of the common power wiring CPL may be disposed on the other side of the first non-display area IA1. In addition, the second to fourth non-display areas IA2, IA3, and IA4 may be disposed between one end and the other end of the common power wiring CPL. Accordingly, the common power wiring CPL according to an example may have a “∩” shape in which one side corresponding to the first non-display area IA1 of the flexible substrate FS is planarly opened.

The encapsulation layer may be formed on the flexible substrate FS to surround the upper and side surfaces of the display area AA and the common power wiring CPL. On the other hand, the encapsulation layer may expose one end and the other end of the common power wiring CPL in the first non-display area IA1. The encapsulation layer may prevent oxygen or moisture from penetrating into the light emitting element ED provided in the display area AA. The encapsulation layer according to an example may include at least one inorganic film. The encapsulation layer according to another example may include a plurality of inorganic films and an organic film between the plurality of inorganic films.

The flexible electroluminescent display according to an example of the present application may further include a pad unit PP, a gate driving circuit 200 and a driving integrated circuit 300.

The pad part PP may include a plurality of pads provided in the non-display area IA of the flexible substrate FS. The pad unit PP according to an example may include a plurality of common power supply pads, a plurality of data input pads, a plurality of power supply pads, and a plurality of control signal input provided in the first non-display area IA1 of the flexible substrate FS. And pads.

The gate driving circuit 200 is provided in the third non-display area IA3 and/or the fourth non-display area IA4 of the flexible substrate FS in a one-to-one correspondence with the scan wirings SL provided in the display area AA. Connected. The gate driving circuit 200 is integrated in the third non-display area IA3 and/or the fourth non-display area IA4 of the flexible substrate FS together with the manufacturing process of the pixel P, that is, the manufacturing process of the thin film transistor. do. The gate driving circuit 200 generates a scan signal based on a gate control signal supplied from the driving integrated circuit 300 and outputs the scan signal according to a predetermined order, thereby driving each of the scan lines SL in a predetermined order. The gate driving circuit 200 according to an example may include a shift register.

The dam structure DM is provided in the first non-display area IA1, the second non-display area IA2, the third non-display area IA3, and the fourth non-display area IA4 of the flexible substrate FS for display. A closed curve structure surrounding the area AA may be provided. In one example, the dam structure DM is disposed on the outside of the common power wiring CPL to be located on the outermost portion of the flexible substrate FS. The pad portion PP and the driving integrated circuit 300 are preferably disposed in an outer region of the dam structure DM.

In FIG. 1, a case where the dam structure DM is disposed at the outermost is illustrated, but is not limited thereto. As another example, the dam structure DM may be disposed between the common power wiring CPL and the gate driving circuit 200. As another example, the dam structure DM may be disposed between the display area AA and the gate driving circuit 300.

The driving integrated circuit 300 is mounted in the chip mounting area defined in the first non-display area IA1 of the flexible substrate FS through a chip mounting (or bonding) process. The output terminals of the driving integrated circuit 300 are electrically connected to the pad portion PP, and the output terminals of the driving integrated circuit 300 drive a plurality of data lines DL and a plurality of pixels provided in the display area AA. It is electrically connected to the power supply line PL. The driving integrated circuit 300 receives various power sources, timing synchronization signals, and digital image data input from the display driving circuit unit (or host circuit) through the pad unit PP, and receives a gate control signal according to the timing synchronization signal. It generates and controls the driving of the gate driving circuit 200, and at the same time, converts digital image data into an analog pixel data voltage and supplies it to a corresponding data line DL.

When the driving integrated circuit 300 is mounted in the form of a chip, it is preferable that the driving integrated circuit 300 does not become a folded portion in a foldable or rollable display device. For example, in the case shown in FIG. 1, when the flexible substrate FS is bent such that the upper and lower sides meet each other with respect to the X axis, the driving integrated circuit 300 is set to be parallel to the lower side that does not need to be folded or rolled. It is desirable to do.

Hereinafter, preferred embodiments will be described in detail with reference to enlarged drawings and/or cross-sectional views showing well the structural features in order to explain the main features of the present application. In particular, an organic partition wall and a pixel structure that can prevent damage due to bending stress in a foldable or rollable display device will be described in detail.

2 and 3, an embodiment of the present application will be described. If necessary, reference is also made to FIG. 1. 2 is an enlarged plan view showing a structure of a single pixel in a flexible electroluminescent display device according to an exemplary embodiment of the present application. 3 illustrates a structure of a flexible electroluminescent display device according to an exemplary embodiment of the present application, and is a cross-sectional view of FIG. 2 along line I-I'.

The flexible electroluminescent display device according to an exemplary embodiment of the present application illustrated in FIG. 2 includes a plurality of pixels P arranged in a matrix manner on the flexible substrate FS. The flexible substrate FS includes a partition wall PD and a base layer PS. The partition wall PD has a certain width and height. The partition wall PD has a mesh shape and is connected on the upper surface of the base layer PS. For example, after forming an organic material such as polyimide as a plate-shaped substrate, the substrate made of an organic material is etched at a certain depth by using a net pattern having a predetermined width as a mask to form a base layer (PS) and a partition (PD). Can form. The partition wall PD and the base layer PS are integrally made of the same material. On the surface of the base layer PS having a thin thickness, partition walls PD having a predetermined width and a thickness thicker than the base layer PS protrude, and an inner region surrounded by the partition walls PD is defined as the pixel P.

Since the base layer PS is formed by etching the organic substrate, the thickness may be very thin. If the thickness is too thin, it may be difficult to secure the stability of the elements formed thereon. To prevent this, the flexible substrate FS may further include a lower substrate BS and a lower buffer layer MB. For example, a lower substrate BS is first formed, a lower buffer layer MB is deposited thereon, and a substrate is formed of an organic material on the lower buffer layer MB. Then, the organic substrate is patterned to form the base layer PS and the partition wall PD.

The flexible substrate FS includes scan lines SL and sensing lines RL arranged in the horizontal direction, and data lines DL and pixel driving power lines PL arranged in the vertical direction. These wirings are disposed on the flexible substrate FS while traversing the inner region of the region of the pixel P. In FIG. 2, one sensing line RL, one scan line SL, one data line DL, and one pixel driving power supply line PL pass through one pixel P. In particular, the wirings extend over a plurality of pixels P over the partition wall PD.

The switching thin film transistor ST, the driving thin film transistor DT, the compensation thin film transistor ET, the capacitor Cst, and the pixel driving electrode AE are disposed inside the pixel P area surrounded by the partition PD. The light emitting layer EL and the common electrode CE are sequentially stacked on the pixel driving electrode AE to form the light emitting element ED.

The switching thin film transistor ST operates to switch the data signal supplied through the data line DL to be stored as a data voltage in the capacitor Cst in response to the scan signal supplied through the scan line SL. The driving thin film transistor DT operates to flow a driving current between the pixel driving power supply line PL and the common power supply line CPL according to the data voltage stored in the capacitor Cst. The light emitting element ED emits light according to the driving current formed by the driving thin film transistor DT. The compensation thin film transistor ET is a circuit disposed in the pixel P to compensate for the threshold voltage of the driving thin film transistor DT. The compensation thin film transistor ET is connected to the drain electrode of the driving thin film transistor DT and the pixel driving electrode AE (or sensing node) of the light emitting element ED. The compensation thin film transistor ET is operated to supply an initialization voltage transmitted through the sensing wire RL to the sensing node or to detect the voltage or current of the sensing node.

In the switching thin film transistor ST, the source electrode SS is connected to the data line DL, and the drain electrode SD is connected to the gate electrode DG of the driving thin film transistor DT. In the driving thin film transistor DT, the source electrode DS is connected to the pixel driving power line PL, and the drain electrode DD is connected to the pixel driving electrode AE of the light emitting element ED. The first electrode is connected to the gate electrode DG of the driving thin film transistor DT and the second electrode is connected to the pixel driving electrode AE of the light emitting element ED.

The above description has been mainly focused on the case of the p-type thin film transistor. However, it is not limited thereto, and an n-type thin film transistor may be used. In the case of the N-type thin film transistor, the source electrode and the drain electrode may be changed.

In the light emitting device ED, the pixel driving electrode AE is connected to the drain electrode DD of the driving thin film transistor DT, and the common electrode CE is connected to the common wiring CPL. In the compensation thin film transistor ET, the source electrode ES is connected to the sensing wire RL, and the drain electrode ED is connected to the pixel driving electrode AE of the light emitting element ED, which is a sensing node.

The scan wiring SL overlaps the semiconductor layers SA and EA of the switching thin film transistor ST and the compensation thin film transistor ET. A portion of the scan wiring SL overlapping the scan semiconductor layer SA is a scan gate electrode SG, and a region of the scan semiconductor layer SA overlapping the scan gate electrode SG is defined as a channel region. Similarly, a portion of the sensing wiring RL that overlaps the sensing semiconductor layer EA is a sensing gate electrode EG, and an area overlapping the scan gate electrode EG in the sensing semiconductor layer EA is defined as a channel region. . Meanwhile, one side of the driving semiconductor layer DG of the driving thin film transistor DT contacts the driving source electrode DS and overlaps the driving gate electrode DG, and the other end is connected to the driving drain electrode DD.

Referring to FIG. 3 further, a cross-sectional structure of a flexible electroluminescent display device according to an exemplary embodiment of the present application will be described in detail. The flexible electroluminescent display according to an exemplary embodiment of the present application may include a flexible substrate FS, a pixel array layer 120, and an encapsulation layer 130.

The flexible substrate FS is a base layer and includes a plastic material or a glass material. The flexible substrate FS according to an example may include an opaque or colored polyimide material. For example, the flexible substrate FS made of a polyimide material may be a polyimide resin coated with a predetermined thickness on the front surface of a release layer provided on a relatively thick carrier substrate. In this case, the carrier glass substrate is separated from the substrate SUB by the release of the release layer using a laser release process.

The flexible substrate FS according to an example includes a partition wall PD and a base layer PS formed by etching a substrate made of an organic material. In some cases, a lower buffer layer MB and a lower substrate BS may be attached to the bottom surface of the base layer PS. In this case, after depositing the lower buffer layer MB on the upper surface of the lower substrate BS, an organic material is applied. Thereafter, the organic material is etched in a net-like pattern to form a partition wall PD and a base layer PS. As a result, the base layer PS has a thickness thinner than the partition PD. In addition, the partition wall PD has a mesh shape protruding from the base layer PS, and the base layer PS has a recessed shape surrounded by the partition PD. The partition wall PD and the base layer PS include the same material and are integrally formed.

The flexible substrate FS according to an example may further include a back plate (not shown) coupled to the rear surface of the flexible substrate FS based on the thickness direction Z. The back plate keeps the flexible substrate FS in a flat state. The back plate according to an example may include a plastic material, for example, polyethylene terephthalate. The back plate may be laminated on the back side of the flexible substrate FS separated from the carrier glass substrate.

Most preferably, the flexible substrate FS is preferably a material having excellent flexibility that can be freely folded or unfolded. The flexible substrate FS may include a display area AA and a non-display area IA surrounding the display area AA.

An upper buffer layer BUF is formed on the upper surface of the base layer PS of the pixel P surrounded by the partition PD in the flexible substrate FS. The upper buffer layer BUF is formed on the surface of the base layer PS to block moisture from penetrating the pixel array layer 120 through the flexible substrate FS that is vulnerable to moisture permeation. The upper buffer layer BUF according to an example may be formed of a plurality of inorganic layers alternately stacked. For example, the upper buffer layer BUF may be formed of a multilayer film in which one or more inorganic films of silicon oxide film (SiOx), silicon nitride film (SiNx), and silicon oxynitride film (SiON) are alternately stacked. When the upper buffer layer BUF is an insulating film made of an inorganic material, the upper buffer layer BUF is preferably formed on the surface of the base layer PS inside the pixel P region surrounded by the partition PD. Therefore, the lower end of the partition wall PD contacts the upper buffer layer BUF. The upper buffer layer BUF may be stacked on the upper surface of the partition wall PD. However, the present application is characterized in that the inorganic layer is formed for each pixel P in order to secure flexibility of the display panel in the flexible display device. To this end, it is preferable that the inorganic material layer is not laminated on the partition wall PD.

The pixel array layer 120 may include a thin film transistor layer, a planarization layer (PLN), a bank pattern (BN), and a light emitting device (ED). For example, the pixel array layer 120 may be formed by being divided for each pixel P area surrounded by the partition PD. Therefore, the thin film transistor layer, the planarization layer PLN, and the bank pattern BN are formed above the lower end of the partition PD.

The thin film transistor layers are respectively provided in the plurality of pixels P defined in the display area AA of the flexible substrate FS and the gate driving circuit 200 defined in the fourth non-display area IA4 of the flexible substrate FS, respectively. Is prepared.

The thin film transistor layer according to an example includes a switching thin film transistor ST formed on the upper buffer layer BUF, a driving thin film transistor DT, a compensation thin film transistor ET, a gate insulating film GI, and an interlayer insulating film ILD. . Here, in FIG. 3, for convenience, the switching thin film transistor ST and the driving thin film transistor DT are mainly shown.

The switching thin film transistor ST includes a switching semiconductor layer SA formed on the upper buffer layer BUF, a switching gate electrode SG, a switching source electrode SS, and a switching drain electrode SD. The driving thin film transistor DT includes a driving semiconductor layer DA formed on the upper buffer layer BUF, a driving gate electrode DG, a driving source electrode DS, and a driving drain electrode DD. In FIG. 3, the thin film transistors ST and DT illustrate upper gate (top gate) structures in which the gate electrodes SG and DG are positioned on the semiconductor layers SA and DA, but are not limited thereto. . As another example, the thin film transistors ST and DT have a lower gate (bottom gate) structure or a gate electrode (SG, DG) in which the gate electrodes SG and DG are located under the semiconductor layers SA and DA. It may have a double gate structure located on both the upper and lower portions of the semiconductor layers SA and DA.

The semiconductor layers SA and DA may include a silicon-based semiconductor material, an oxide-based semiconductor material, or an organic-based semiconductor material, and may have a single-layer structure or a multi-layer structure.

The gate insulating layer GI may be formed on the flexible substrate FS to cover the semiconductor layers SA and DA, particularly on the base layer PS. The gate insulating film GI may be formed of an inorganic film, for example, a silicon oxide film (SiOx), a silicon nitride film (SiNx), or multiple films thereof. Particularly, when the gate insulating film GI is an insulating film containing an inorganic material, it is preferable to form it separately in each pixel P region surrounded by the partition PD. When the gate insulating layer GI is made of an inorganic material, it is preferable that the gate insulating layer GI is not stacked on the upper surface of the partition wall PD made of an organic material in order to secure flexibility of the flexible display device.

The switching gate electrode SG may be formed on the gate insulating layer GI so as to overlap the switching semiconductor layer SA and the driving gate electrode DG may overlap the driving semiconductor layer DA. The gate electrodes SG and DG may be formed together with the scan wiring SL. Gate electrodes (SG, DG) according to an example include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) ) May be formed of a single layer or multiple layers of any one or alloys thereof.

The interlayer insulating film ILD is stacked on the flexible substrate FS to cover the gate electrodes SG and DG and the gate insulating film GI. When the interlayer insulating film ILD is an insulating film containing an inorganic material, it may be formed separately in each pixel P region surrounded by the partition wall PD. In this case, in order to secure flexibility of the flexible display device, it is preferable that an interlayer insulating layer ILD is not laminated on the upper surface of the partition wall PD made of an organic material. In particular, in one embodiment of the present application, it is preferable that the upper surface of the interlayer insulating film ILD has a lower height than the upper surface of the partition wall PD. As a result, the inorganic materials are characterized by being disposed only on the upper surface of the base layer PS of the inner region surrounded by the partition PD.

The interlayer insulating film (ILD) and the gate insulating film (GI) are patterned to expose one end and the other end of the semiconductor layer SA. GA. A metal material is deposited and patterned on the interlayer insulating layer ILD to form source electrodes SS and DS and drain electrodes SD and DD. At this time, the data wiring DL shown in FIG. 2, the pixel driving power supply wiring PL, and the first electrode of the capacitor Cst may be formed together.

The switching source electrode SS and the switching drain electrode SD may be formed on the interlayer insulating layer ILD so as to overlap the switching semiconductor layer SA with the switching gate electrode SG interposed therebetween. The driving source electrode DS and the driving drain electrode DD may be formed on the interlayer insulating layer ILD to overlap the driving semiconductor layer DA with the driving gate electrode DG therebetween. The source electrodes SS and DS and the drain electrodes SD and DD may be formed together with the data line DL, the pixel driving power supply line PL, and the common power supply line CPL. That is, each of the source electrodes SS and DS, the drain electrodes SD and DD, the data wiring DL, the pixel driving power supply wiring PL and the common power supply wiring CPL are each formed by a patterning process for the source drain electrode material. It can be formed at the same time.

Each of the source electrodes SS, DS and the drain electrodes SD and DD may be connected to the semiconductor layers SA and DA through electrode contact holes penetrating the interlayer insulating film ILD and the gate insulating film GI. Source electrodes (SS, DS) and drain electrodes (SD, DD) are molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) And copper (Cu), or a single layer or a multi-layer made of an alloy thereof. Here, the driving source electrode DS of the driving thin film transistor DT shown in FIGS. 2 and 3 may be electrically connected to the pixel driving power supply line PL.

As described above, the thin film transistors ST and DT. ET provided in the pixel P of the flexible substrate FS constitute a pixel circuit PC. In addition, the gate driving circuit 200 disposed in the fourth non-display area IA4 of the flexible substrate FS may include a thin film transistor that is the same as or similar to the thin film transistors ST, DT, and ET provided in the pixel P. Can.

The planarization layer PLN is formed over the flexible substrate FS to cover the thin film transistor layer. The planarization layer PLN provides a flat surface on the surface of the flexible substrate FS on which the thin film transistor layer is formed. The planarization layer according to an example (PLN) is an acrylic resin (acryl resin), epoxy resin (epoxy resin), phenolic resin (phenolic resin), polyamide resin (polyamide resin), or an organic such as polyimide resin (polyimide resin) It can be formed into a film.

In one embodiment of the present application, the planarization layer PLN may also be stacked on the partition wall PD. The scan wiring SL, the data wiring DL, and the pixel driving current wiring PL are disposed on the partition wall PD to connect the pixels P. Therefore, a planarization layer PLN may be stacked on the partition wall PD for the purpose of protecting and insulating the wirings. Since the planarization layer PLN is made of an organic material, even if it is stacked on the partition wall PD made of an organic material, there is no problem in flexibility of the flexible display device. In this case, the planarization layer PLN covers the wirings SL, DL, and PL passing over the partition wall PD. Also, the planarization layer PLN may include a pixel contact hole PH for exposing the driving drain electrode DD of the driving thin film transistor DT provided in the pixel P.

A conductive material is deposited and patterned on the planarization layer PLN to form a pixel driving electrode AE. The pixel driving electrode AE is formed to have a size limited within the pixel P region. A bank (or bank pattern) BN is formed on the pixel driving electrode AE. The bank BN is disposed on the planarization layer PLN to define an opening area (or light emitting area) in the pixel P of the display area AA. The bank BN may be represented by a pixel defining layer. The bank BN may be made of an organic material. In this case, the bank BN may be formed to cover the partition wall PD.

The light emitting element ED includes a pixel driving electrode AE, a light emitting layer EL, and a common electrode CE. The pixel driving electrode AE is formed on the planarization layer PLN and is electrically connected to the drain electrode D of the driving thin film transistor through the pixel contact hole PH provided in the planarization layer PLN. In this case, the remaining edge portions except for the middle portion of the pixel driving electrode AE overlapping the opening region of the pixel P may be covered by the bank BN. The bank BN may define an opening area of the pixel P by covering an edge portion of the pixel driving electrode AE.

The pixel driving electrode AE according to an example may include a metal material having high reflectance. For example, the pixel driving electrode AE is a stacked structure of aluminum (Al) and titanium (Ti) (Ti/Al/Ti), and a stacked structure of aluminum (Al) and ITO (Indium Tin Oxide) (ITO/Al/ ITO), APC (Ag/Pd/Cu) alloys, and multilayer structures such as APC alloys and ITO stacked structures (ITO/APC/ITO), or silver (Ag), aluminum (Al), molybdenum (Mo) , Gold (Au), magnesium (Mg), calcium (Ca), or barium (Ba) may include a single layer structure made of any one material or two or more alloy materials.

The emission layer EL is formed on the entire display area AA of the flexible substrate FS to cover the pixel driving electrode AE and the bank pattern BN. The light emitting layer EL according to an example may include two or more light emitting units vertically stacked to emit white light. For example, the light emitting layer EL according to an example may include a first light emitting unit and a second light emitting unit for emitting white light by mixing the first light and the second light. Here, the first light emitting unit emits the first light and may include any one of a blue light emitting unit, a green light emitting unit, a red light emitting unit, a yellow light emitting unit, and a yellow green light emitting unit. The second light emitting unit may include a blue light emitting unit, a green light emitting unit, a red light emitting unit, a yellow light emitting unit, and a light emitting unit that emits a second light that optically complements the first light among the yellow green. For example, the first light emitting part may be a blue light emitting part, and the second light emitting part may be a combination of a yellow light emitting part and a green light emitting part, or a combination of a red light emitting part and a green light emitting part. Alternatively, the first light emitting unit may be a combination of a yellow light emitting unit and a green light emitting unit, or a combination of a red light emitting unit and a green light emitting unit, and the second light emitting unit may be a blue light emitting unit according to a direction of emitting light around the substrate.

The light emitting layer EL according to another example may include any one of a blue light emitting part, a green light emitting part, and a red light emitting part for emitting color light corresponding to a color set in the pixel P. For example, the light emitting layer EL according to another example may include any one of an organic light emitting layer, an inorganic light emitting layer, and a quantum dot light emitting layer, or may include a stacked or mixed structure of an organic light emitting layer (or inorganic light emitting layer) and a quantum dot light emitting layer.

Additionally, the light emitting device ED according to an example may further include a functional layer for improving light emission efficiency and/or lifetime of the light emitting layer EL.

The common electrode CE is formed to be electrically connected to the light emitting layer EL. The common electrode CE is formed in the entire display area AA of the flexible substrate FS so as to be commonly connected to the light emitting layer EL provided in each pixel P.

The common electrode CE according to an example may include a transparent conductive material or semi-transmissive conductive material capable of transmitting light. When the common electrode CE is formed of a semi-transmissive conductive material, light emission efficiency of light emitted from the light emitting device ED may be improved through a micro cavity structure. The semi-permeable conductive material according to an example may include magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). Additionally, a capping layer may be further formed on the common electrode CE to adjust the refractive index of the light emitted from the light emitting element ED to improve the light output efficiency.

The encapsulation layer 130 may be further stacked on the light emitting element ED. The encapsulation layer 130 is formed to surround the pixel array layer 120. The encapsulation layer 130 serves to prevent oxygen or moisture from penetrating the light emitting device ED.

The encapsulation layer 130 according to an example includes a first inorganic encapsulation layer (PAS1), an organic encapsulation layer (PCL) on the first inorganic encapsulation layer (PAS1), and a second inorganic encapsulation layer (PAS2) on the organic encapsulation layer (PCL). It may include.

The first inorganic encapsulation layer (PAS1) and the second inorganic encapsulation layer (PAS2) serve to block the penetration of moisture or oxygen. The first inorganic encapsulation layer (PAS1) and the second inorganic encapsulation layer (PAS2) according to an example include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. It can be made of minerals. The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 may be formed by a chemical vapor deposition process or an atomic layer deposition process.

The organic encapsulation layer (PCL) is surrounded by the first inorganic encapsulation layer (PAS1) and the second inorganic encapsulation layer (PAS2). The organic encapsulation layer (PCL) may be formed to have a relatively thick thickness compared to the first inorganic encapsulation layer (PAS1) and/or the second inorganic encapsulation layer (PAS2) so as to cover particles that may occur during the manufacturing process. have. The organic encapsulation layer (PCL) may be made of an organic material such as silicone oxycarbon (SiOCz) acrylic or epoxy-based resin. The organic encapsulation layer 133 may be formed by a coating process, for example, an inkjet coating process or a slit coating process.

In the flexible display device according to an exemplary embodiment of the present application, each pixel P has a structure divided by a partition wall PD. That is, since each pixel P is divided into partitions PD having excellent flexibility, the flexibility of the flexible display device can be secured even when bent in any direction. In particular, the upper buffer layer BUF, the gate insulating layer GI, and the intermediate insulating layer ILD, which are insulating layers made of an inorganic material stacked with the components of the thin film transistor, are not stacked on the partition PD. Therefore, the problem that the thin film transistor is damaged by the bending operation does not occur. The lower buffer layer MB stacked on the bottom of the base layer PS and the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 included in the encapsulation layer 130 are inorganic material layers. Since it is not an inorganic material layer directly contacting the same driving elements, it does not directly affect the elements in a bending operation. Accordingly, the flexible display device according to an exemplary embodiment of the present application has excellent flexibility and may have a robust structure that prevents the device from being damaged due to repeated bending stress.

Hereinafter, a cross-sectional structure of a flexible electroluminescent display device according to another exemplary embodiment of the present application will be described in detail with reference to FIG. 4. The flexible electroluminescence display according to another embodiment of the present application may include a flexible substrate FS, a pixel array layer 120, and an encapsulation layer 130. In the description of other embodiments of the present application, descriptions of components that are the same as or different from the previous embodiments are omitted or briefly described.

The flexible substrate FS is a base layer and includes a plastic material or a glass material. The flexible substrate FS according to an example may include an opaque or colored polyimide material. The flexible substrate FS according to an example includes a partition wall PD formed by etching an organic layer and a base layer PS. In some cases, a lower buffer layer MB and a lower substrate BS may be attached to the bottom surface of the base layer PS. In this case, after depositing the lower buffer layer MB on the upper surface of the lower substrate BS, an organic layer is applied. Thereafter, the organic layer is etched in a net-like pattern to form a partition wall PD and a base layer PS. The flexible substrate FS according to an example may further include a back plate (not shown) coupled to the rear surface of the flexible substrate FS based on the thickness direction Z.

Most preferably, the flexible substrate FS is preferably a material having excellent flexibility that can be freely folded or unfolded. The flexible substrate FS may include a display area AA and a non-display area IA surrounding the display area AA.

The upper buffer layer BUF is formed on the upper surface of the base layer PS in the flexible substrate FS. The upper buffer layer BUF is formed on the surface of the base layer PS to block moisture from penetrating the pixel array layer 120 through the flexible substrate FS that is vulnerable to moisture permeation. The upper buffer layer BUF according to an example may be formed of a plurality of inorganic layers alternately stacked. The upper buffer layer BUF is preferably formed only on the surface of the base layer PS for each pixel P surrounded by the partition PD. The present application is characterized in that, in order to secure the flexibility of the display panel in the flexible display device. To this end, it is preferable that the inorganic material layer is not laminated on the partition wall PD.

The pixel array layer 120 may include a thin film transistor layer, a planarization layer (PLN), a bank (BN), and a light emitting device (ED).

The thin film transistor layer includes a plurality of pixels P defined in the display area AA of the flexible substrate FS and gates defined in the third and/or fourth non-display areas IA3 and IA4 of the flexible substrate FS. Each is provided in the driving circuit 200.

The thin film transistor layer according to an example includes a switching thin film transistor ST formed on the upper buffer layer BUF, a driving thin film transistor DT, a compensation thin film transistor ET, a gate insulating film GI, and an interlayer insulating film ILD. . The switching thin film transistor ST includes a switching semiconductor layer SA formed on the upper buffer layer BUF, a switching gate electrode SG, a switching source electrode SS, and a switching drain electrode SD. The driving thin film transistor DT includes a driving semiconductor layer DA formed on the upper buffer layer BUF, a driving gate electrode DG, a driving source electrode DS, and a driving drain electrode DD.

The semiconductor layers SA and DA may include a silicon-based semiconductor material, an oxide-based semiconductor material, or an organic-based semiconductor material, and may have a single-layer structure or a multi-layer structure.

The gate insulating layer GI may be formed on the flexible substrate FS to cover the semiconductor layers SA and DA. The gate insulating film GI may be formed of an inorganic film, for example, a silicon oxide film (SiOx), a silicon nitride film (SiNx), or multiple films thereof. Particularly, when the gate insulating film GI is made of an inorganic material, it is preferable to form it separately in each pixel P region surrounded by the partition PD. In this case, in order to secure flexibility of the flexible display device, it is preferable that the gate insulating layer GI is not stacked on the upper surface of the partition wall PD.

The switching gate electrode SG may be formed on the gate insulating layer GI so as to overlap the switching semiconductor layer SA and the driving gate electrode DG may overlap the driving semiconductor layer DA. The gate electrodes SG and DG may be formed together with the scan wiring SL. Gate electrodes (SG, DG) according to an example include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) ) May be formed of a single layer or multiple layers of any one or alloys thereof.

The interlayer insulating film ILD is stacked on the flexible substrate FS to cover the gate electrodes SG and DG and the gate insulating film GI. When the interlayer insulating layer ILD is made of an inorganic material, it may be formed separately in each pixel P region surrounded by the partition PD. In this case, in order to secure flexibility of the flexible display device, it is preferable that an interlayer insulating film ILD is not stacked on the upper surface of the partition wall PD. In particular, in one embodiment of the present application, it is preferable that the upper surface of the interlayer insulating film ILD has a lower height than the upper surface of the partition wall PD. As a result, the inorganic materials are characterized by being disposed only on the upper surface of the base layer PS of the inner region surrounded by the partition PD.

The interlayer insulating film (ILD) and the gate insulating film (GI) are patterned to expose one end and the other end of the semiconductor layer SA. GA. A metal material is deposited and patterned on the interlayer insulating layer ILD to form source electrodes SS and DS and drain electrodes SD and DD. At this time, the data wiring DL shown in FIG. 2, the pixel driving power supply wiring PL, and the first electrode of the capacitor Cst may be formed together.

The switching source electrode SS and the switching drain electrode SD may be formed on the interlayer insulating layer ILD so as to overlap the switching semiconductor layer SA with the switching gate electrode SG interposed therebetween. The driving source electrode DS and the driving drain electrode DD may be formed on the interlayer insulating layer ILD to overlap the driving semiconductor layer DA with the driving gate electrode DG therebetween. Each of the source electrode SS, DS, the drain electrodes SD, DD, the data line DL, the pixel driving power supply line PL, and the common power supply line CPL are simultaneously formed by a patterning process for the source drain electrode material. Can be.

Each of the source electrodes SS, DS and the drain electrodes SD and DD may be connected to the semiconductor layers SA and DA through electrode contact holes penetrating the interlayer insulating film ILD and the gate insulating film GI. Source electrodes (SS, DS) and drain electrodes (SD, DD) are molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) And copper (Cu), or a single layer or a multi-layer made of an alloy thereof. Here, the driving source electrode DS of the driving thin film transistor DT shown in FIGS. 2 and 4 may be electrically connected to the pixel driving power supply line PL.

As described above, the thin film transistors ST and DT. ET provided in the pixel P of the flexible substrate FS constitute a pixel circuit PC. In addition, the gate driving circuit 200 disposed in the third and/or fourth non-display areas IA3 and IA4 of the flexible substrate FS is the same as the thin film transistors ST, DT, and ET provided in the pixel P. Or similar thin film transistors.

The planarization layer PLN is formed in each pixel P area surrounded by the partition wall PD to cover the thin film transistor layer. The planarization layer PLN provides a flat surface on the surface of the flexible substrate FS on which the thin film transistor layer is formed. The planarization layer according to an example (PLN) is an acrylic resin (acryl resin), epoxy resin (epoxy resin), phenolic resin (phenolic resin), polyamide resin (polyamide resin), or an organic such as polyimide resin (polyimide resin) It can be formed into a film.

In another embodiment of the present application illustrated in FIG. 4, the planarization layer PLN is not laminated on the partition wall PD, but is applied only to the inner region between the partition walls PD. The scan wiring SL, the data wiring DL, and the pixel driving current wiring PL are disposed on the partition wall PD to connect the pixels P. In this case, the wirings SL, DL, and PL passing over the partition wall PD remain exposed. Also, the planarization layer PLN may include a pixel contact hole PH for exposing the driving drain electrode DD of the driving thin film transistor DT provided in the pixel P.

A conductive material is deposited and patterned on the planarization layer PLN to form a pixel driving electrode AE. The pixel driving electrode AE is formed to have a size limited within the pixel P area surrounded by the partition PD. The bank BN is formed on the pixel driving electrode AE. The bank BN is disposed on the planarization layer PLN to define an opening area (or light emitting area) in the pixel P of the display area AA. The bank BN may be represented by a pixel defining layer. In another embodiment of the present application, the bank BN is also not stacked on the partition PD, but is formed by being divided for each pixel P region, which is an inner region between the partitions PD. For example, the upper surface of the bank BN may have a lower height than the upper surface of the partition wall PD.

The light emitting element ED includes a pixel driving electrode AE, a light emitting layer EL, and a common electrode CE. The pixel driving electrode AE is formed on the planarization layer PLN and is electrically connected to the drain electrode D of the driving thin film transistor through the pixel contact hole PH provided in the planarization layer PLN. In this case, the remaining edge portions except for the middle portion of the pixel driving electrode AE overlapping the opening region of the pixel P may be covered by the bank BN. The bank BN may define an opening area of the pixel P by covering an edge portion of the pixel driving electrode AE.

The emission layer EL is formed in the display area AA of the flexible substrate FS to cover the pixel driving electrode AE and the bank BN. The common electrode CE is formed to be electrically connected to the light emitting layer EL. The common electrode CE according to an example may include a transparent conductive material or semi-transmissive conductive material capable of transmitting light. When the common electrode CE is formed of a semi-transmissive conductive material, light emission efficiency of light emitted from the light emitting device ED may be improved through a micro cavity structure. The semi-permeable conductive material according to an example may include magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). Additionally, a capping layer may be further formed on the common electrode CE to adjust the refractive index of the light emitted from the light emitting element ED to improve the light output efficiency.

In another embodiment of the present application, features of the cross-sectional structure of the light emitting element ED will be described. The spacer SP is formed on the flexible substrate FS on which the bank BN is formed. In particular, the spacer SP is formed on the partition PD. The partition wall PD has a mesh shape connected on the flexible substrate FS. The spacer SP may have the same shape as the partition wall PD. As another example, the spacer SP has a column shape and may be disposed scattered on the partition wall PD. The scan wiring SL, the data wiring DL, and the pixel driving power supply wiring PL are disposed on the partition wall PD. For the purpose of protecting these wires, it is preferable that the spacer SP has the same mesh shape as the partition wall PD. In particular, it is preferable that the spacer SP has an inverse tapered shape.

The light emitting layer EL including the organic material is applied on the surface of the flexible substrate FS on which the spacer SP is formed. The light emitting layer EL has a disconnected structure for each pixel P region due to the inverse taper structure of the spacer SP. That is, the light emitting layer EL has a structure that is independent of each pixel P and is stacked on the pixel electrode AE. However, a residue of the light emitting layer EL may be stacked on the upper surface of the spacer SP. However, this residue is not connected to the light emitting layer EL covering the surrounding pixel P area.

The common electrode CE is applied on the surface of the flexible substrate FS on which the light emitting layer EL is formed. The common electrode CE includes a metal oxide having transparent properties. For example, the common electrode CE may have a band shape connecting the pixels P in the horizontal direction. The scan wiring SL extending in the horizontal direction is disposed on the partition wall PD. Since the scan wiring SL and the common electrode CE should not be electrically connected, the common electrode CE is spaced apart from the scan wiring SL by a predetermined distance, runs in the horizontal direction, and is opened by the bank BN. It may have a strip shape covering all the pixel electrodes AE.

As another example, the common electrode CE may have a band shape connecting the pixels P in the vertical direction. The data wiring DL and the pixel driving power supply wiring PL are disposed on the partition wall PD in the vertical direction. The common electrode CE should not be electrically connected to the data line DL and the pixel driving power supply line PL. Therefore, the common electrode CE is spaced apart from the data line DL and the pixel driving power supply line PL by a predetermined distance, runs in the vertical direction, and covers the pixel electrode AE opened by the bank BN. It can have a shape.

The encapsulation layer 130 may be further stacked on the light emitting element ED. The encapsulation layer 130 is formed to surround the pixel array layer 120. The encapsulation layer 130 serves to prevent oxygen or moisture from penetrating the light emitting device ED.

The encapsulation layer 130 according to an example includes a first inorganic encapsulation layer (PAS1), an organic encapsulation layer (PCL) on the first inorganic encapsulation layer (PAS1), and a second inorganic encapsulation layer (PAS2) on the organic encapsulation layer (PCL). It may include.

The first inorganic encapsulation layer PAS1 rides over the spacer SP and covers the entire surface of the flexible substrate FS. Since the first inorganic encapsulation layer PAS1 includes an inorganic material, the first inorganic encapsulation layer PAS1 has a shape that covers all of the shapes of the reverse tapered spacers SP.

In the flexible display device according to another exemplary embodiment of the present application, each pixel P has a structure divided by a partition wall PD. That is, since each pixel P is divided into partitions PD having excellent flexibility, the flexibility of the flexible display device can be secured even when bent in any direction. In particular, the upper buffer layer BUF, the gate insulating layer GI, and the interlayer insulating layer ILD, which are inorganic materials stacked with the components of the thin film transistor, are not stacked on the partition wall PD. Therefore, the problem that the thin film transistor is damaged by the bending operation does not occur. The lower buffer layer MB stacked on the rear surface of the base layer PS and the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 included in the encapsulation layer 130 are inorganic material layers, but the thin film transistor and Since it is not an inorganic material layer directly contacting the same driving elements, it does not directly affect the elements in a bending operation. Accordingly, the flexible display device according to the present application has excellent flexibility and may have a robust structure that prevents the device from being damaged due to repeated bending stress.

Hereinafter, a flexible electroluminescent display device according to another exemplary embodiment of the present application will be described with reference to FIGS. 2 and 5. 5 illustrates a structure of a flexible electroluminescent display device according to another exemplary embodiment of the present application, and is a cross-sectional view of FIG. 1 taken along line II-II'. In another embodiment of the present application, a partition wall made of an organic material is further added to the outermost portion of the flexible electroluminescent display device to provide a structure capable of effectively preventing moisture and foreign matter from entering the outside. In the description of another embodiment of the present application, descriptions of components that are the same as or not distinguished from the previous embodiments are omitted or briefly described.

The flexible substrate FS is a base layer and includes a plastic material or a glass material. In some cases, a lower buffer layer MB and a lower substrate BS may be attached to the bottom surface of the base layer PS. In this case, after depositing the lower buffer layer MB on the upper surface of the lower substrate BS, an organic layer is applied. Thereafter, the organic layer is etched in a net-like pattern to form a partition wall PD and a base layer PS. The partition wall PD and the base layer PS are integrally made of the same material. On the surface of the base layer PS having a thin thickness, partition walls PD having a predetermined width and a thickness thicker than the base layer PS protrude, and an inner region surrounded by the partition walls PD is defined as the pixel P.

Most preferably, the flexible substrate FS is preferably a material having excellent flexibility that can be freely folded or unfolded. The flexible substrate FS may include a display area AA and a non-display area IA surrounding the display area AA. In particular, the partition wall PD is also protruded on the outermost edge of the flexible substrate FS. The partition PD disposed at the outermost portion is included in the non-display area IA.

The upper buffer layer BUF is formed on the upper surface of the base layer PS in the flexible substrate FS. The upper buffer layer BUF is formed on the surface of the base layer PS to block moisture from penetrating the pixel array layer 120 through the flexible substrate FS that is vulnerable to moisture permeation. The upper buffer layer BUF is preferably laminated on the base layer PS surface excluding the upper surface of the partition PD. Therefore, even in the third non-display area IA3 in which the gate driving circuit 200 is disposed, the upper buffer layer BUF may be coated on the surface of the base layer PS. The present application is characterized in that, in order to secure the flexibility of the display panel in the flexible display device. To this end, it is preferable that the inorganic material layer is not laminated on the partition wall PD.

The pixel array layer 120 may include a thin film transistor layer, a planarization layer (PLN), a bank (BN), and a light emitting device (ED).

The thin film transistor layers are respectively provided in the plurality of pixels P defined in the display area AA of the flexible substrate FS and the gate driving circuit 200 defined in the third non-display area IA3 of the flexible substrate FS, respectively. Is prepared.

The thin film transistor layer according to an example includes a switching thin film transistor formed on the upper buffer layer BUF, a driving thin film transistor, a compensation thin film transistor, a gate insulating film GI, and an interlayer insulating film ILD. Hereinafter, for convenience of description, the thin film transistor T will be simply described. The thin film transistor T includes a semiconductor layer A formed on the upper buffer layer BUF, a gate electrode G, a source electrode S, and a drain electrode D.

The semiconductor layer (A) may include a silicon-based semiconductor material, an oxide-based semiconductor material, or an organic-based semiconductor material, and may have a single-layer structure or a multi-layer structure.

The gate insulating layer GI may be formed on the flexible substrate FS to cover the semiconductor layer A. The gate insulating film GI may be formed of an inorganic film, for example, a silicon oxide film (SiOx), a silicon nitride film (SiNx), or multiple films thereof. Particularly, when the gate insulating film GI is made of an inorganic material, it is preferable to form it separately in each pixel P region surrounded by the partition PD. Also, in the non-display area IA, the gate insulating layer GI may be stacked on the surface of the base layer PS. In this case, in order to secure flexibility of the flexible display device, it is preferable that the gate insulating layer GI is not stacked on the upper surface of the partition wall PD.

The gate electrode G may be formed on the gate insulating layer GI so as to overlap the semiconductor layer A. The gate electrode G may be formed together with the scan wiring SL. Gate electrode (G) according to an example of the molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) of It may be formed of a single layer or multiple layers made of any one or alloys thereof.

The interlayer insulating film ILD is stacked on the flexible substrate FS to cover the gate electrode G and the gate insulating film GI. When the interlayer insulating layer ILD is made of an inorganic material, it may be formed separately in each pixel P region surrounded by the partition PD. In this case, in order to secure flexibility of the flexible display device, it is preferable that an interlayer insulating film ILD is not stacked on the upper surface of the partition wall PD. In particular, in one embodiment of the present application, it is preferable that the upper surface of the interlayer insulating film ILD has a lower height than the upper surface of the partition wall PD. In addition, the interlayer insulating layer ILD may be stacked on the base layer PS inside the outermost partition wall PD. As a result, the inorganic materials are characterized by being disposed only on the upper surface of the base layer PS of the inner region surrounded by the partition PD.

The interlayer insulating film (ILD) and the gate insulating film (GI) are patterned to expose one end and the other end of the semiconductor layer (A). A metal material is deposited and patterned on the interlayer insulating layer ILD to form a source electrode S and a drain electrode D. At this time, the data wiring DL shown in FIG. 2, the pixel driving power supply wiring PL, and the first electrode of the capacitor Cst may be formed together.

The source electrode S and the drain electrode D may be formed on the interlayer insulating layer ILD to overlap the semiconductor layer A with the gate electrode G therebetween. The source electrode S and the drain electrode D may be formed on the interlayer insulating layer ILD to overlap the semiconductor layer A with the gate electrode G therebetween. Each of the source electrode S, the drain electrode D, the data line DL, the pixel driving power supply line PL, and the common power supply line CPL may be simultaneously formed by a patterning process for the source drain electrode material.

Each of the source electrode S and the drain electrode D may be connected to the semiconductor layer A through an electrode contact hole penetrating the interlayer insulating film ILD and the gate insulating film GI. The source electrode S and the drain electrode D are molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) ) May be formed of a single layer or multiple layers of any one or alloys thereof.

As described above, the thin film transistors T provided in the pixel P of the flexible substrate FS constitute a pixel circuit PC. In addition, the gate driving circuit 200 disposed in the third non-display area IA3 of the flexible substrate FS may have a thin film transistor that is the same as or similar to the thin film transistor T provided in the pixel P.

The planarization layer PLN is formed in each pixel P region to cover the thin film transistor layer. The planarization layer PLN provides a flat surface on the surface of the flexible substrate FS on which the thin film transistor layer is formed.

In another embodiment of the present application, the planarization layer PLN is not laminated on the partition wall PD, but is applied only to the inner region between the partition walls PD. The scan wiring SL, the data wiring DL, and the pixel driving current wiring PL are disposed on the partition wall PD to connect the pixels P. In this case, the wirings SL, DL, and PL passing over the partition wall PD remain exposed. Also, the planarization layer PLN may include a pixel contact hole PH for exposing the driving drain electrode DD of the driving thin film transistor DT provided in the pixel P. On the other hand, nothing is formed on the upper surface of the partition wall PD disposed on the outermost side.

A conductive material is deposited and patterned on the planarization layer PLN to form a pixel driving electrode AE. The pixel driving electrode AE is formed to have a size limited within the pixel P region. The bank BN is formed on the pixel driving electrode AE. The bank BN is disposed on the planarization layer PLN to define an opening area (or light emitting area) in the pixel P of the display area AA. The bank BN may be represented by a pixel defining layer. In another embodiment of the present application, the bank BN is also not stacked on the partition PD, but is formed by being divided for each pixel P region, which is an inner region between the partitions PD. For example, the upper surface of the bank BN may have a lower height than the upper surface of the partition wall PD.

The light emitting element ED includes a pixel driving electrode AE, a light emitting layer EL, and a common electrode CE. The pixel driving electrode AE is formed on the planarization layer PLN and is electrically connected to the drain electrode D of the driving thin film transistor through the pixel contact hole PH provided in the planarization layer PLN. In this case, the remaining edge portions except for the middle portion of the pixel driving electrode AE overlapping the opening region of the pixel P may be covered by the bank BN. The bank BN may define an opening area of the pixel P by covering an edge portion of the pixel driving electrode AE.

The emission layer EL is formed to cover the pixel driving electrode AE and the bank BN. The common electrode CE is formed to be electrically connected to the light emitting layer EL. The common electrode CE according to an example may include a transparent conductive material or semi-transmissive conductive material capable of transmitting light.

In FIG. 5, which shows another embodiment of the present application, the cross-sectional structure of the light emitting element ED has the same structure as the embodiment of FIG. 4. However, the present invention is not limited thereto, and may have, for example, the same structure as the embodiment illustrated in FIG. 3.

The spacer SP is formed on the flexible substrate FS on which the bank BN is formed. In particular, the spacer SP is formed on the partition PD. The partition wall PD has a mesh shape connected on the flexible substrate FS. The spacer SP may have the same shape as the partition wall PD. On the other hand, the spacer SP is not formed on the partition wall PD disposed on the outermost side.

The scan wiring SL, the data wiring DL, and a portion of the pixel driving power supply wiring PL are disposed on the partition wall PD. For the purpose of protecting these wires, it is preferable that the spacer SP has the same mesh shape as the partition wall PD. In particular, it is preferable that the spacer SP has an inverse tapered shape.

The light emitting layer EL including the organic material is applied on the surface of the flexible substrate FS on which the spacer SP is formed. The light emitting layer EL has a disconnected structure for each pixel P region due to the inverse taper structure of the spacer SP. That is, the light emitting layer EL has a structure that is independent of each pixel P and is stacked on the pixel electrode AE. However, a residue of the light emitting layer EL may be stacked on the upper surface of the spacer SP. However, this residue is not connected to the light emitting layer EL covering the surrounding pixel P area.

The common electrode CE is applied on the surface of the flexible substrate FS on which the light emitting layer EL is formed. The common electrode CE includes a metal oxide having transparent properties. For example, the common electrode CE may have a band shape connecting the pixels P in the horizontal direction. The scan wiring SL extending in the horizontal direction is disposed on the partition wall PD. Since the scan wiring SL and the common electrode CE should not be electrically connected, the common electrode CE is spaced apart from the scan wiring SL by a predetermined distance, runs in the horizontal direction, and is opened by the bank BN. The pixel driving electrode AE may have a strip shape.

As another example, the common electrode CE may have a band shape connecting the pixels P in the vertical direction. A portion of the data line DL and the pixel driving power supply line PL that are traveling in the vertical direction are disposed on the partition wall PD. The common electrode CE should not be electrically connected to the data line DL and the pixel driving power supply line PL. Therefore, the common electrode CE is spaced apart from the data line DL and the pixel driving power supply line PL by a predetermined distance, runs in the vertical direction, and covers the pixel electrode AE opened by the bank BN. It can have a shape.

The encapsulation layer 130 may be further stacked on the light emitting element ED. The encapsulation layer 130 is formed to surround the pixel array layer 120. The encapsulation layer 130 serves to prevent oxygen or moisture from penetrating the light emitting device ED.

The encapsulation layer 130 according to an example includes a first inorganic encapsulation layer (PAS1), an organic encapsulation layer (PCL) on the first inorganic encapsulation layer (PAS1), and a second inorganic encapsulation layer (PAS2) on the organic encapsulation layer (PCL). It may include. The first inorganic encapsulation layer (PAS1) and the second inorganic encapsulation layer (PAS2) serve to block the penetration of moisture or oxygen. The first inorganic encapsulation layer (PAS1) and the second inorganic encapsulation layer (PAS2) according to an example include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. It can be made of minerals. The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 may be formed by a chemical vapor deposition process or an atomic layer deposition process.

The first inorganic encapsulation layer PAS1 rides over the spacer SP and covers the entire surface of the flexible substrate FS. Since the first inorganic encapsulation layer PAS1 includes an inorganic material, the first inorganic encapsulation layer PAS1 has a shape that covers all of the shapes of the reverse tapered spacers SP. Therefore, the first inorganic encapsulation layer PAS1 is also laminated on the partition wall PD disposed in the display area AA.

The organic encapsulation layer PCL is surrounded by the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2. The organic encapsulation layer (PCL) is relatively thicker than the first inorganic encapsulation layer (PAS1) and/or the second inorganic encapsulation layer (PAS2) so as to adsorb and/or block particles that may occur during the manufacturing process. It can be formed of. The organic encapsulation layer (PCL) may be made of an organic material such as silicone oxycarbon (SiOCz) acrylic or epoxy-based resin. The organic encapsulation layer (PCL) may be formed by a coating process, for example, an inkjet coating process or a slit coating process.

The flexible electroluminescent display device according to another exemplary embodiment of the present application may further include a dam structure DM adjacent to the outermost organic partition wall PD. The dam structure DM is a structure disposed in the non-display area IA of the flexible substrate FS to prevent the organic encapsulation layer PCL from overflowing to the outside.

The dam structure DM according to an example includes the display area AA, the gate driving circuit 200 disposed outside the display area AA, and the outside of the common power wiring CPL disposed outside the gate driving circuit 200. Can be placed on. In some cases, the dam structure DM may be disposed to overlap the outer portion of the common power wiring CPL. In this case, the width of the non-display area IA on which the gate driving circuit 200 and the common power wiring CPL are disposed may be reduced to reduce the bezel width.

In one example, the dam structure DM may have a triple layer structure formed perpendicular to the flexible substrate FS. For example, it may include a first layer formed of a planarization film (PLN), a second layer formed of a bank pattern (BN), and a third layer formed of a spacer (SP). The spacer SP included in the dam structure DM may have a forward tapered structure.

The first layer may have a cross-sectional structure having a pattern trapezoidal shape of the planarization film PLN. The second layer may have a trapezoidal cross-sectional structure stacked on the first layer. The third layer may have a trapezoidal cross-sectional structure stacked on the second layer. When the thickness of the organic encapsulation layer (PCL) is thin and it is easy to control the spreadability of the organic encapsulation layer (PCL), it may be sufficient even if the height of the dam structure DM is not high. In this case, the third layer can be omitted.

The height from the edge region of the organic encapsulation layer (PCL) to the upper surface is preferably applied lower than the overall height of the dam structure (DM). As a result, the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 have a surface-contacting structure on the upper surface and the outer sidewall of the dam structure DM.

The outside of the dam structure DM further includes a partition wall PD disposed on the outermost side. As illustrated in FIG. 5, the end faces of the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 abut the vertical surfaces of the outermost partition wall PD. That is, a cross-sectional gap between the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 has a structure sealed by a partition wall PD. As a result, there is no problem that the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 are peeled or damaged.

In the flexible display device according to another exemplary embodiment of the present application, each pixel P has a structure separated by a partition wall PD. That is, since each pixel P is divided into a partition wall PD including an organic material having excellent flexibility, the flexibility of the flexible display device can be secured even when bent in any direction. In particular, the upper buffer layer BUF, the gate insulating layer GI, and the intermediate insulating layer ILD, which are inorganic materials stacked with the components of the thin film transistor, are not stacked on the partition wall PD. Therefore, the problem that the thin film transistor is damaged by the bending operation does not occur. The lower buffer layer MB stacked on the lower portion of the base layer PS and the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 included in the encapsulation layer 130 are inorganic material layers. Since it is not an inorganic material layer directly contacting the same driving elements, it does not directly affect the elements in a bending operation. Accordingly, the flexible display device according to an exemplary embodiment of the present application has excellent flexibility and may have a robust structure that prevents the device from being damaged due to repeated bending stress.

In particular, the outermost part of the flexible substrate FS also has a structure in which the partition wall PD protrudes with a thicker thickness than the base layer PS to block the external environment. Particularly, the outermost partition wall PD includes the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 extending from the lower end portion of the sidewall in the display area AA and extending over the dam structure DM. It makes contact with the end. As a result, the bonded ends of the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 that are in surface contact from outside the dam structure DM have a structure sealed by the outermost partition wall PD. Therefore, it is possible to prevent moisture or foreign substances from penetrating from the outside. In addition, it is possible to prevent the problem of separating or lifting the stacked thin films.

The foldable or rollable electroluminescent display device according to the present application absorbs and/or disperses stress caused by repeated bending operations, prevents major elements from being damaged, and at the same time suppresses water infiltration from outside. It provides a structure.

Such an electric field display device according to an example of the present application includes an electronic notebook, an electronic book, a portable multimedia player (PMP), navigation, an Ultra Mobile PC (UMPC), a smart phone, a mobile communication terminal, a mobile phone, and a tablet. Portable electronic devices such as personal computers (PCs), smart watches, watch phones, or wearable devices, as well as televisions, laptops, monitors, refrigerators, microwave ovens, washing machines, cameras, etc. It can be applied to various products.

Features, structures, effects, etc. described in various embodiments of the present application described above are included in at least one example of the present application, and are not limited to only one example. Furthermore, features, structures, effects, and the like exemplified in at least one example of the present application may be combined or modified with respect to other examples by a person having ordinary knowledge in the field to which this application belongs. Therefore, contents related to such combinations and modifications should be interpreted as being included in the scope of the present application.

The present application described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which this application pertains that various substitutions, modifications, and changes are possible without departing from the technical details of the present application. It will be obvious to those who have the knowledge of Therefore, the scope of the present application is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be interpreted to be included in the scope of the present application.

SUB: Substrate T: Thin film transistor
PLN: planarization layer BN: bank pattern
200: gate driving circuit 300: driving integrated circuit
120: pixel array layer FS: flexible substrate
ED: Light emitting element AE: Pixel driving electrode
EL: emitting layer CE: common electrode
CPL: Common power wiring BS: Bottom board
BSL: lower metal layer TR: trench
M1: first metal layer M2: second metal layer
W: depression
ORL: organic material layer INO: inorganic material layer
BD: bending direction BX: bending axis

Claims (12)

A flexible substrate having a base layer and partition walls protruding by a predetermined thickness to define a plurality of pixels arranged in a matrix manner on the surface of the base layer;
A scan wiring over the partition wall and running in a horizontal direction of the flexible substrate;
A data wiring and a pixel driving power wiring traveling in the vertical direction of the flexible substrate over the partition wall;
A driving element disposed in the pixel and connected to the scan wiring, the data wiring, and the pixel driving power wiring; And
A flexible electroluminescent display device comprising a light emitting element disposed in the pixel and connected to the driving element.
According to claim 1,
The base layer has a thickness thinner than the partition wall,
The base layer and the partition wall are flexible electroluminescent display devices formed integrally.
According to claim 1,
The driving element and the light emitting element are disposed inside the pixel surrounded by the partition wall,
The scan wiring, the data wiring, and the pixel driving current wiring are disposed to pass over the partition wall and over the base layer.
The method of claim 3,
Further comprising a spacer stacked with a reverse tapered cross-sectional shape on the partition wall,
The emission layer is separated for each pixel by the spacer,
The common electrode is a flexible electroluminescent display device commonly stacked on the light emitting layer of pixels neighboring in the horizontal direction beyond the spacer.
According to claim 1,
Further comprising a planarization film laminated between the driving element and the light emitting element,
The side surface of the insulating film made of an inorganic material included in the driving element is a flexible electroluminescent display device in contact with the side surface of the partition wall.
The method of claim 5,
The planarization film,
A flexible electroluminescent display device stacked higher than the height of the partition wall to cover the upper surface of the partition wall.
The method of claim 5,
The planarization film,
An electroluminescent display device which is stacked lower than the height of the partition wall so that a side surface of the flattening film contacts the side surface of the partition wall.
According to claim 1,
The flexible substrate,
A display area in which the pixels are disposed; And
A non-display area surrounding the display area,
The non-display area,
A gate driving element disposed on the base layer;
A common power wiring disposed on the base layer;
A dam structure disposed on the base layer; And
A flexible electroluminescent display device that protrudes upward along an outermost edge of the base layer and includes an outer partition wall surrounding the dam structure.
The method of claim 8,
A flexible electroluminescent display device in which an inorganic material layer is not stacked on an upper surface of the outer partition wall.
The method of claim 8,
A first inorganic encapsulation layer stacked on the light emitting device over the partition wall;
An organic encapsulation layer stacked on the first inorganic encapsulation layer;
A flexible electroluminescent display device further comprising a second inorganic encapsulation layer stacked on the organic encapsulation layer.
The method of claim 10,
The organic encapsulation layer is limited to an area inside the dam structure,
The first inorganic encapsulation layer and the second inorganic encapsulation layer seal the organic encapsulation layer, make surface contact from outside the dam structure, and contact a flexible electroluminescent display device.
According to claim 1,
A lower buffer layer stacked under the base layer;
A flexible electroluminescent display device further comprising a lower substrate stacked on a lower surface of the lower buffer layer.

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