KR102574813B1 - Flexible electroluminesence display - Google Patents

Abstract

The present application relates to a flexible electroluminescent display device. A flexible electroluminescent display device according to an exemplary embodiment of the present application includes a flexible substrate, a scan wire, a data wire, a pixel driving power supply wire, a driving element, and a light emitting element. The flexible substrate includes a base layer and barrier ribs protruding with a certain thickness to define a plurality of pixels arranged in a matrix manner on a surface of the base layer. The scan wiring crosses over the barrier rib and proceeds in the horizontal direction of the flexible substrate. The data wiring and the pixel driving power supply wiring go over the barrier rib in the vertical direction of the flexible substrate. The driving element is disposed in the pixel and connected to the scan wiring, the data wiring and the pixel driving power supply wiring. A light emitting element is disposed in a pixel and connected to a driving element.

Description

Flexible electroluminescence display {FLEXIBLE ELECTROLUMINESENCE DISPLAY}

The present application relates to a flexible electroluminescent display device. In particular, the present application relates to a flexible electroluminescent display device having a structure that is robust against bending stress when the display area is folded and unfolded or rolled and unfolded.

Among display devices, an electroluminescent display device is a self-luminous type, and has excellent viewing angles and contrast ratios, and has advantages such as light weight and thinness as it does not require a separate backlight, and advantageous power consumption. In particular, among the electroluminescent display devices, the organic light emitting display device can be driven at a low DC voltage, has a fast response speed, and has low manufacturing cost.

An electroluminescent display device includes a plurality of electroluminescent diodes. The light emitting diode includes an anode electrode, a light emitting layer formed on the anode electrode, and a cathode electrode formed on the light emitting layer. When a high potential voltage is applied to the anode electrode and a low potential voltage is applied to the cathode electrode, holes from the anode electrode and electrons from the cathode electrode move to the light emitting layer, respectively. When holes and electrons are combined in the light emitting layer, excitons are formed in an excitation process, and light is generated due to energy from the excitons. An electroluminescent display device displays an image by electrically controlling the amount of light emitted from light emitting layers of a plurality of electroluminescent diodes individually divided by banks.

The electroluminescent display device has the advantage of being ultra-thin and maximally utilizing flexibility, which is a characteristic of organic materials. Using excellent flexibility, it is easy to develop a foldable display device that can be folded and unfolded as needed or a rollable display device that can be rolled up, stored, and unfolded for use. However, when repeated folding and unfolding operations are repeated, cracks or damage may occur at the folded portion due to bending stress. When such damage occurs, moisture or foreign matter penetrates into the rollable or foldable electroluminescent display from the outside through the damaged defective portion, which may shorten the lifespan of the electroluminescent display.

A technical problem of the present application is to provide a flexible electroluminescent display capable of preventing cracking or breakage by minimizing bending stress even when bending and unfolding operations are repeated. In addition, a technical problem of the present application is to provide a flexible electroluminescent display device having a structure capable of absorbing stress caused by repeated bending operations and suppressing moisture permeation from the outside.

A flexible electroluminescent display device according to an exemplary embodiment of the present application includes a flexible substrate, a scan wire, a data wire, a pixel driving power supply wire, a driving element, and a light emitting element. The flexible substrate includes a base layer and barrier ribs protruding with a certain thickness to define a plurality of pixels arranged in a matrix manner on a surface of the base layer. The scan wiring crosses over the barrier rib and proceeds in the horizontal direction of the flexible substrate. The data wiring and the pixel driving power supply wiring go over the barrier rib in the vertical direction of the flexible substrate. The driving element is disposed in the pixel and connected to the scan wiring, the data wiring and the pixel driving power supply wiring. A light emitting element is disposed in a pixel and connected to a driving element.

For example, the base layer has a thickness smaller than that of the barrier rib. The base layer and the barrier rib are integrally formed.

For example, a driving element and a light emitting element are arranged inside a pixel surrounded by partition walls. The scan wires, data wires, and pixel driving current wires are arranged to pass over the barrier rib and the base layer.

For example, a spacer having an inverted taper cross-sectional shape and stacked on the barrier rib is further included. The light emitting layer is separated for each pixel by spacers. The common electrode is commonly stacked on light emitting layers of horizontally adjacent pixels over the spacer.

For example, a planarization film stacked between the driving element and the light emitting element is further included. A side surface of the insulating film made of an inorganic material included in the driving element is in contact with a side surface of the barrier rib.

In one example, the planarization film is stacked higher than the height of the barrier rib and covers the upper surface of the barrier rib.

In one example, the planarization film is stacked lower than the height of the barrier rib so that the side surface of the planarization film is in contact with the side surface of the barrier rib.

For example, the flexible substrate includes a display area in which pixels are disposed, and a non-display area surrounding the display area. The non-display area includes a gate driving element disposed on the base layer, a common power supply wire disposed on the base layer, a dam structure disposed on the base layer, and an external partition wall protruding upward along an outermost edge of the base layer and surrounding the dam structure. include

For example, an inorganic material layer is not laminated on an upper surface of the external barrier rib.

For example, it further includes a first inorganic encapsulation layer stacked on the light emitting element over the barrier rib, an organic encapsulation layer stacked on the first inorganic encapsulation layer, and a second inorganic encapsulation layer stacked on the organic encapsulation layer.

For example, the organic encapsulation layer is limited to the inner region of the dam structure. The first inorganic encapsulation layer and the second inorganic encapsulation layer seal the organic encapsulation layer, make surface contact outside the dam structure, and contact the inner surface of the external partition wall.

For example, a buffer layer stacked under the base layer and a lower substrate stacked under the buffer layer are further included.

The flexible electroluminescent display device according to the present application has a structure capable of alleviating or absorbing stress even when bending and unfolding operations are repeated. As a result, even if repeated bending operations are performed, no cracks or breakages occur. The flexible electroluminescent display device according to the present application has a structure that is robust against bending stress and can prevent penetration of moisture and foreign substances from the outside.

In addition to the effects of the present application mentioned above, other features and advantages of the present application will be described below, or will be clearly understood by those skilled in the art from such description and description.

1 is a plan view illustrating a flexible electroluminescent display device according to a preferred embodiment of the present application.
2 is an enlarged plan view showing the structure of a single pixel in a flexible electroluminescent display device according to a preferred embodiment of the present application.
3 is a cross-sectional view taken along the line II′ of FIG. 2 showing the structure of a flexible electroluminescent display device according to an exemplary embodiment of the present application.
4 is a cross-sectional view taken along the line II′ of FIG. 2 showing the structure of a flexible electroluminescent display device according to another embodiment of the present application.
5 is a cross-sectional view taken along the line II-II′ of FIG. 1 showing the structure of a flexible electroluminescent display device according to another embodiment of the present application.

Advantages and features of the present application, and methods of achieving them, will become clear with reference to examples described below in detail in conjunction with the accompanying drawings. However, the present application is not limited to the examples disclosed below and will be implemented in a variety of different forms, and only the examples of the present application make the disclosure of the present application complete, and common in the technical field to which the invention of the present application belongs. It is provided to completely inform those who have knowledge of the scope of the invention, and the invention of this application is only defined by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining an example of the present application are exemplary, the present application is not limited to the matters shown. Like reference numbers designate like elements throughout the specification. In addition, in describing examples of the present application, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present application, the detailed description will be omitted.

When 'includes', 'has', 'consists', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal precedence relationship is described in terms of 'after', 'following', 'next to', 'before', etc. It can also include non-continuous cases unless is used.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present application.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, "at least one of the first item, the second item, and the third item" means not only the first item, the second item, or the third item, respectively, but also two of the first item, the second item, and the third item. It may mean a combination of all items that can be presented from one or more.

Each feature of the various examples of the present application can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each example can be implemented independently of each other or can be implemented together in a related relationship. .

Hereinafter, an example of a flexible electroluminescent display device according to the present application will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings.

1 is a plan view illustrating a flexible electroluminescent display device according to a preferred embodiment of the present application. Referring to FIG. 1 , a flexible electroluminescent display device according to the present application may include a flexible substrate FS, a pixel P, a barrier rib PD, a common power line CPL, and a dam structure DM.

The flexible substrate FS is a base substrate (or base layer) and includes a plastic material or a glass material. In particular, in the case of a flexible display device, it is preferable to form a plastic material having excellent flexibility. However, even if it is made of glass, it is possible to realize a flexible display device by forming it into an ultra-thin shape.

The flexible substrate FS according to an example may have a rectangular shape in plan view, a quadrangular shape in which each corner portion is rounded with a constant radius of curvature, or a non-rectangular shape having at least six sides. Here, the flexible substrate FS having a non-square shape may include at least one protrusion or at least one notch portion.

The flexible substrate FS according to an example may be divided into a display area AA and a non-display area IA. The display area AA is provided in the central area of the flexible substrate FS and may be defined as an area for displaying an image. The display area AA according to an example may have a quadrangular shape in plan view, a quadrangular shape in which corners are rounded to have a constant radius of curvature, or a non-rectangular shape having at least six sides. Here, the display area AA having a non-rectangular shape may include at least one protrusion or at least one notch.

The non-display area IA is provided on the edge area of the flexible substrate FS to surround the display area AA, and may be defined as an area where no image is displayed or a peripheral area. The non-display area IA according to an example includes a first non-display area IA1 provided at a first edge of the flexible substrate FS and a second edge of the flexible substrate FS parallel to the first non-display area IA1. A second non-display area IA2 provided on, a third non-display area IA3 provided on a third edge of the flexible substrate FS, and provided on a fourth edge of the flexible substrate FS parallel to the third non-display area. A fourth non-display area IA4 may be included. For example, the first non-display area IA1 is an upper (or lower) edge area of the flexible substrate FS, the second non-display area IA2 is a lower (or upper) edge area of the flexible substrate FS, The third non-display area IA3 may be the left (or right) edge area of the flexible substrate FS, and the fourth non-display area IA4 may be the right (or left) edge area of the flexible substrate FS. It is not necessarily limited to this.

The pixel P may be provided on the display area AA of the flexible substrate FS. A plurality of pixels P according to an example form a matrix arrangement and may be disposed in the display area AA of the flexible substrate FS. The pixel P may be defined by the barrier rib PD. The barrier rib PD has a constant width and surrounds the pixel P. For example, a plurality of pixels P are partitioned and defined in a matrix manner by a net-shaped barrier rib PD having a constant width.

Pixels P according to an example may be arranged to have a stripe structure on the display area AA. In this case, one unit pixel may include a red pixel, a green pixel, and a blue pixel, and furthermore, one unit pixel may further include a white pixel.

Pixels P according to another example may be arranged to have a pentile structure on the display area AA. In this case, one unit pixel may include at least one red pixel, at least two green pixels, and at least one blue pixel arranged in a polygonal shape in a planar view. For example, in one unit pixel having a pentile structure, one red pixel, two green pixels, and one blue pixel may be arranged to have an octagonal shape in plan view. In this case, the blue pixel is relatively the largest. It may have a large opening area (or light emitting area), and the green pixel may have a relatively small opening area.

The pixel P is electrically connected to a pixel circuit PC electrically connected to a scan line SL, a sensing line RL, a data line DL, and a pixel driving power supply line PL, and electrically connected to the pixel circuit PC. A light emitting device (ED) may be included.

The scan line SL, the sensing line RL, the data line DL, and the pixel driving power line PL may be disposed at an edge of the pixel P. These wires extend over a plurality of pixels P. Accordingly, these wires cross over the barrier rib PD and extend across the pixels P.

The scan lines SL extend along the first direction X and are disposed at regular intervals along the second direction Y crossing the first direction X. The display area AA of the flexible substrate FS includes a plurality of scan lines SL parallel to the first direction X and spaced apart from each other along the second direction Y. Here, the first direction X may be defined as the horizontal direction of the flexible substrate FS, and the second direction Y may be defined as the vertical direction of the flexible substrate FS, but is not necessarily limited thereto. It can also be defined conversely.

The sensing line RL is disposed on the flexible substrate FS parallel to the scan line SL. The display area AA of the flexible substrate FS includes a plurality of sensing lines RL parallel to the scan lines SL. In some cases, the sensing line RL may further include a vertical sensing line parallel to the data line DL.

The data lines DL extend along the second direction Y and are disposed at regular intervals along the first direction X. The display area AA of the flexible substrate FS includes a plurality of data lines DL parallel to the second direction Y and spaced apart from each other along the first direction X.

The pixel driving power line PL is disposed on the flexible substrate FS parallel to the data line DL. The display area AA of the flexible substrate FS includes a plurality of pixel driving power lines PL parallel to the data lines DL. Optionally, the pixel driving power line PL may be arranged parallel to the scan line SL.

The pixel circuit PC is disposed in the inner region of the pixel P surrounded by the barrier rib PD, and responds to a scan signal supplied from one scan line SL passing through the inner region of the pixel P to the inside of the pixel P. A current Ied flowing from the pixel driving power supply line PL to the light emitting element ED is controlled based on the data voltage supplied from the data line DL passing through the region.

The pixel circuit PC according to an example may include at least two thin film transistors and one capacitor. For example, the pixel circuit PC according to an exemplary embodiment drives a data voltage supplied from a driving thin film transistor supplying a data current Ied based on the data voltage to the light emitting device ED and a data line DL. It may include a switching thin film transistor that supplies the thin film transistor, and a capacitor that stores the gate-drain voltage of the driving thin film transistor.

A pixel circuit PC according to another example may include at least three thin film transistors and at least one capacitor. For example, the pixel circuit PC according to an example may include a current supply circuit, a data supply circuit, and a compensation circuit according to the operation (or function) of each of at least three thin film transistors. Here, the current supply circuit may include a driving thin film transistor that supplies the data current Ied based on the data voltage to the light emitting element ED. The data supply circuit may include at least one switching thin film transistor supplying the data voltage supplied from the data line DL to the current supply circuit in response to at least one scan signal. The compensation circuit may include at least one compensation thin film transistor that compensates for a change in characteristic values (threshold voltage and/or mobility) of the driving thin film transistor in response to at least one sensing signal.

The light emitting element ED is disposed inside the pixel P region surrounded by the barrier rib PD, and emits light with a luminance corresponding to the data current Ied by emitting light according to the data current Ied supplied from the pixel circuit PC. emits In this case, the data current Ied may flow from the pixel driving power line PL through the driving thin film transistor and the light emitting element ED to the common power line CPL.

The light emitting element ED according to an example includes a pixel driving electrode (or first electrode or anode) electrically connected to the pixel circuit PC, a light emitting layer formed on the pixel driving electrode, and a common electrode (or second electrode) electrically connected to the light emitting layer. 2 electrodes or cathodes).

In the electroluminescence display device according to an exemplary embodiment of the present application, the wires SL, RL, DL, and PL cross over the barrier rib PD and cross the inner area of the pixel P defined by the barrier rib PD. It is placed on the flexible substrate FS while holding it. On the other hand, the pixel circuit PC and the light emitting element ED are disposed only in the inner region of the pixel P partitioned by the barrier rib PD.

The common power line CPL is disposed on the non-display area IA of the flexible substrate FS and electrically connected to a common electrode disposed on the display area AA. The common power line CPL according to an example has a constant wiring width and is disposed along second to fourth non-display areas IA2, IA3, and IA4 adjacent to the display area IA of the flexible substrate FS, It surrounds the rest of the display area AA adjacent to the first non-display area IA1 of the flexible substrate FS except for a portion. One end of the common power line CPL may be disposed on one side of the first non-display area IA1, and the other end of the common power line CPL may be disposed on the other side of the first non-display area IA1. Also, between one end and the other end of the common power line CPL may be disposed to surround the second to fourth non-display areas IA2 , IA3 , and IA4 . Accordingly, the common power line CPL according to an example may have a '∩' shape in which one side corresponding to the first non-display area IA1 of the flexible substrate FS is open in plan view.

The encapsulation layer may be formed on the flexible substrate FS to surround upper and side surfaces of the display area AA and the common power line CPL. Meanwhile, the encapsulation layer may expose one end and the other end of the common power supply line CPL in the first non-display area IA1 . The encapsulation layer may prevent oxygen or moisture from penetrating into the light emitting device ED provided in the display area AA. An encapsulation layer according to an example may include at least one inorganic layer. An encapsulation layer according to another example may include a plurality of inorganic layers and an organic layer between the plurality of inorganic layers.

The flexible electroluminescent display device according to an example of the present application may further include a pad part PP, a gate driving circuit 200, and a driving integrated circuit 300.

The pad part PP may include a plurality of pads provided in the non-display area IA of the flexible substrate FS. The pad unit PP according to an example includes a plurality of common power supply pads, a plurality of data input pads, a plurality of power supply pads, and a plurality of control signal inputs provided in the first non-display area IA1 of the flexible substrate FS. pads and the like.

The gate driving circuit 200 is provided in the third non-display area IA3 and/or the fourth non-display area IA4 of the flexible substrate FS and is one-to-one with the scan wires SL provided in the display area AA. Connected. The gate driving circuit 200 is integrated into the third non-display area IA3 and/or the fourth non-display area IA4 of the flexible substrate FS along with the manufacturing process of the pixel P, that is, the thin film transistor manufacturing process. do. The gate driving circuit 200 generates scan signals based on the gate control signal supplied from the driving integrated circuit 300 and outputs them in a predetermined order, thereby driving each of the plurality of scan lines SL in a predetermined order. The gate driving circuit 200 according to an example may include a shift register.

The dam structure DM is provided in the first non-display area IA1, the second non-display area IA2, the third non-display area IA3, and the fourth non-display area IA4 of the flexible substrate FS. It may have a closed curve structure surrounding the area AA. For example, the dam structure DM may be disposed outside the common power supply line CPL and may be located at the outermost portion on the flexible substrate FS. It is preferable that the pad part PP and the driving integrated circuit 300 are disposed on the outer region of the dam structure DM.

Although FIG. 1 shows the case where the dam structure DM is disposed at the outermost part, it is not limited thereto. As another example, the dam structure DM may be disposed between the common power line CPL and the gate driving circuit 200 . As another example, the dam structure DM may be disposed between the display area AA and the gate driving circuit 300 .

The driving integrated circuit 300 is mounted in the chip mounting area defined in the first non-display area IA1 of the flexible substrate FS through a chip mounting (or bonding) process. Output terminals of the driving integrated circuit 300 are electrically connected to the pad part PP, and the output terminals of the driving integrated circuit 300 are connected to a plurality of data lines DL provided in the display area AA and driving a plurality of pixels. It is electrically connected to the power line (PL). The driving integrated circuit 300 receives various types of power, timing synchronization signals, digital image data, etc. input from the display driving circuit unit (or host circuit) through the pad unit PP, and generates a gate control signal according to the timing synchronization signal. generated to control the driving of the gate driving circuit 200, and at the same time, digital image data is converted into an analog pixel data voltage and supplied to the corresponding data line DL.

When the drive integrated circuit 300 is mounted in a chip form, it is preferable that the drive integrated circuit 300 does not form a foldable portion in a foldable or rollable display device. For example, in the case shown in FIG. 1, when the flexible substrate FS is bent so that the upper and lower sides meet each other with respect to the X axis, the drive integrated circuit 300 is set to be parallel to the lower side that does not need to be folded or rolled It is desirable to do

Hereinafter, preferred embodiments will be described in detail with reference to enlarged drawings and/or cross-sectional views showing structural features in order to explain the main features of the present application. In particular, it will be described in detail, focusing on organic partition walls and pixel structures that can prevent breakage due to bending stress in a foldable or rollable display device.

Referring to Figures 2 and 3, an embodiment of the present application will be described. If necessary, refer to FIG. 1 together. 2 is an enlarged plan view showing the structure of a single pixel in a flexible electroluminescent display device according to a preferred embodiment of the present application. 3 is a cross-sectional view taken along the line II′ of FIG. 2 showing the structure of a flexible electroluminescent display device according to an exemplary embodiment of the present application.

A flexible electroluminescent display according to an exemplary embodiment of the present application shown in FIG. 2 includes a plurality of pixels P arranged in a matrix manner on a flexible substrate FS. The flexible substrate FS includes a barrier rib PD and a base layer PS. The barrier rib PD has a predetermined width and height. The barrier rib PD has a mesh shape and is connected on the upper surface of the base layer PS. For example, after forming an organic material such as polyimide into a plate-shaped substrate, the substrate made of the organic material is etched to a certain depth using a net pattern having a certain width as a mask to form a base layer (PS) and a barrier rib (PD). can form The barrier rib PD and the base layer PS are integrally formed and made of the same material. Barrier ribs PD having a certain width and a thickness greater than that of the base layer PS protrude on the surface of the base layer PS having a small thickness, and an inner region surrounded by the barrier ribs PD is defined as a pixel P.

Since the base layer PS is formed by etching an organic substrate, it may have a very thin thickness. If the thickness is too thin, it may be difficult to secure the stability of elements formed thereon. To prevent this, the flexible substrate FS may further include a lower substrate BS and a lower buffer layer MB. For example, a lower substrate BS is first formed, a lower buffer layer MB is deposited thereon, and a substrate is formed of an organic material on the lower buffer layer MB. After that, the organic substrate is patterned to form the base layer PS and the barrier rib PD.

On the flexible substrate FS, scan lines SL and sensing lines RL are arranged in a horizontal direction, and data lines DL and pixel driving power lines PL are arranged in a vertical direction. These wires are disposed on the flexible substrate FS while crossing the inner region of the pixel P region. In FIG. 2 , one sensing line RL, one scan line SL, one data line DL, and one pixel driving power supply line PL pass through one pixel P. In particular, the lines extend over the barrier rib PD through a plurality of pixels P.

A switching thin film transistor ST, a driving thin film transistor DT, a compensation thin film transistor ET, a capacitor Cst, and a pixel driving electrode AE are disposed in the pixel P region surrounded by the barrier rib PD. The light emitting layer EL and the common electrode CE are sequentially stacked on the pixel driving electrode AE to form the light emitting element ED.

The switching thin film transistor ST performs a switching operation so that the data signal supplied through the data line DL is stored as a data voltage in the capacitor Cst in response to the scan signal supplied through the scan line SL. The driving thin film transistor DT operates to allow a driving current to flow between the pixel driving power line PL and the common power line CPL according to the data voltage stored in the capacitor Cst. The light emitting element ED emits light according to a driving current formed by the driving thin film transistor DT. The compensation thin film transistor ET is a circuit disposed in the pixel P to compensate for the threshold voltage of the driving thin film transistor DT. The compensation thin film transistor ET is connected to the drain electrode of the driving thin film transistor DT and the pixel driving electrode AE (or sensing node) of the light emitting element ED. The compensation thin film transistor ET supplies an initialization voltage transmitted through the sensing line RL to a sensing node or operates to detect a voltage or current of the sensing node.

The source electrode SS of the switching thin film transistor ST is connected to the data line DL, and the drain electrode SD is connected to the gate electrode DG of the driving thin film transistor DT. In the driving thin film transistor DT, the source electrode DS is connected to the pixel driving power line PL, and the drain electrode DD is connected to the pixel driving electrode AE of the light emitting element ED. A first electrode of the capacitor Cst is connected to the gate electrode DG of the driving thin film transistor DT, and a second electrode is connected to the pixel driving electrode AE of the light emitting element ED.

The above description has been centered on the case of a p-type thin film transistor. However, it is not limited thereto, and an n-type thin film transistor may be used. In the case of an N-type thin film transistor, the source electrode and drain electrode may be swapped.

In the light emitting element ED, the pixel driving electrode AE is connected to the drain electrode DD of the driving thin film transistor DT and the common electrode CE is connected to the common line CPL. In the compensation thin film transistor ET, the source electrode ES is connected to the sensing line RL and the drain electrode ED is connected to the pixel driving electrode AE of the light emitting element ED as a sensing node.

The scan line SL overlaps the semiconductor layers SA and EA of the switching thin film transistor ST and the compensation thin film transistor ET. A portion of the scan line SL overlapping the scan semiconductor layer SA is the scan gate electrode SG, and a region of the scan semiconductor layer SA overlapping the scan gate electrode SG is defined as a channel region. Similarly, a portion of the sensing line RL overlapping the sensing semiconductor layer EA is the sensing gate electrode EG, and a region of the sensing semiconductor layer EA overlapping the scan gate electrode EG is defined as a channel region. . Meanwhile, one end of the driving semiconductor layer DG of the driving thin film transistor DT contacts the driving source electrode DS, overlaps the driving gate electrode DG, and the other end is connected to the driving drain electrode DD.

Further referring to FIG. 3 , a cross-sectional structure of a flexible electroluminescent display according to an exemplary embodiment of the present application will be described in detail. A flexible electroluminescent display device according to an exemplary embodiment of the present application may include a flexible substrate FS, a pixel array layer 120 and an encapsulation layer 130 .

The flexible substrate FS is a base layer and includes a plastic material or a glass material. The flexible substrate FS according to an example may include an opaque or colored polyimide material. For example, the flexible substrate FS made of polyimide may be a cured polyimide resin coated to a certain thickness on the front surface of a release layer provided on a relatively thick carrier substrate. In this case, the carrier glass substrate is separated from the substrate SUB by releasing the release layer using a laser release process.

The flexible substrate FS according to an example includes barrier ribs PD and a base layer PS formed by etching a substrate made of an organic material. In some cases, a lower buffer layer MB and a lower substrate BS may be attached to a lower surface of the base layer PS. In this case, after depositing the lower buffer layer MB on the upper surface of the lower substrate BS, an organic material is applied. After that, the organic material is etched in a net pattern to form the barrier rib PD and the base layer PS. As a result, the base layer PS has a thickness smaller than that of the barrier rib PD. In addition, the barrier rib PD has a mesh shape protruding above the base layer PS, and the base layer PS has a shape of a depression surrounded by the barrier rib PD. The barrier rib PD and the base layer PS include the same material and are integrally formed.

The flexible substrate FS according to an example may further include a back plate (not shown) coupled to a rear surface of the flexible substrate FS in the thickness direction Z. The back plate maintains the flexible substrate FS in a flat state. The back plate according to an example may include a plastic material, for example, a polyethylene terephthalate material. Such a back plate may be laminated on the rear surface of the flexible substrate FS separated from the carrier glass substrate.

Most preferably, the flexible substrate FS is a material having excellent flexibility that can be freely folded or unfolded. The flexible substrate FS may include a display area AA and a non-display area IA surrounding the display area AA.

An upper buffer layer BUF is formed on the upper surface of the base layer PS of the pixel P surrounded by the barrier rib PD in the flexible substrate FS. The upper buffer layer BUF is formed on the surface of the base layer PS to block moisture penetrating into the pixel array layer 120 through the flexible substrate FS, which is vulnerable to moisture permeation. The upper buffer layer BUF according to an example may include a plurality of inorganic layers alternately stacked. For example, the upper buffer layer BUF may be formed of a multilayer in which one or more inorganic layers of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), and a silicon oxynitride layer (SiON) are alternately stacked. When the upper buffer layer BUF is an insulating film made of an inorganic material, the upper buffer layer BUF is preferably formed entirely on the surface of the base layer PS in the pixel P region surrounded by the barrier rib PD. Accordingly, the lower end of the barrier rib PD contacts the upper buffer layer BUF. The upper buffer layer BUF may be stacked on the upper surface of the barrier rib PD. However, the present application is characterized in that the inorganic layer is formed separately for each pixel (P) in order to secure flexibility of the display panel in the flexible display device. To this end, it is preferable that the inorganic material layer is not stacked on the barrier rib PD.

The pixel array layer 120 may include a thin film transistor layer, a planarization layer PLN, a bank pattern BN, and a light emitting element ED. For example, the pixel array layer 120 may be formed separately for each pixel P region surrounded by the barrier rib PD. Therefore, the thin film transistor layer, the planarization layer PLN, and the bank pattern BN are formed above the lower end of the barrier rib PD.

The thin film transistor layer is applied to the plurality of pixels P defined in the display area AA of the flexible substrate FS and the gate driving circuit 200 defined in the fourth non-display area IA4 of the flexible substrate FS. provided

The thin film transistor layer according to an example includes a switching thin film transistor (ST), a driving thin film transistor (DT), a compensation thin film transistor (ET), a gate insulating film (GI) and an interlayer insulating film (ILD) formed on the upper buffer layer (BUF). . Here, in FIG. 3, for convenience, the switching thin film transistor ST and the driving thin film transistor DT are mainly shown.

The switching thin film transistor ST includes a switching semiconductor layer SA, a switching gate electrode SG, a switching source electrode SS, and a switching drain electrode SD formed on the upper buffer layer BUF. The driving thin film transistor DT includes a driving semiconductor layer DA, a driving gate electrode DG, a driving source electrode DS, and a driving drain electrode DD formed on the upper buffer layer BUF. In FIG. 3, the thin film transistors ST and DT show a top gate structure in which the gate electrodes SG and DG are positioned on top of the semiconductor layers SA and DA, but is not necessarily limited thereto. . As another example, the thin film transistors ST and DT have a bottom gate structure in which the gate electrodes SG and DG are positioned below the semiconductor layers SA and DA, or the gate electrodes SG and DG are It may have a double gate structure located both above and below the semiconductor layers SA and DA.

The semiconductor layers SA and DA may include a silicon-based semiconductor material, an oxide-based semiconductor material, or an organic material-based semiconductor material, and may have a single-layer structure or a multi-layer structure.

The gate insulating film GI may be formed on the flexible substrate FS, particularly on the base layer PS, to cover the semiconductor layers SA and DA. The gate insulating layer GI may be formed of an inorganic layer, for example, a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof. In particular, when the gate insulating film GI is an insulating film containing an inorganic material, it is preferable to form the insulating film separately in each pixel P region surrounded by the barrier rib PD. When the gate insulating layer GI is made of an inorganic material, it is preferable that the gate insulating layer GI is not stacked on the upper surface of the barrier rib PD made of an organic material in order to secure flexibility of the flexible display device.

The switching gate electrode SG may be formed on the gate insulating layer GI so as to overlap the switching semiconductor layer SA, and the driving gate electrode DG may overlap the driving semiconductor layer DA. The gate electrodes SG and DG may be formed together with the scan line SL. The gate electrodes SG and DG according to an exemplary embodiment include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). ) may be formed of a single layer or multiple layers made of any one or an alloy thereof.

An interlayer insulating layer ILD is stacked on the flexible substrate FS to cover the gate electrodes SG and DG and the gate insulating layer GI. When the interlayer insulating layer ILD is an insulating layer containing an inorganic material, it may be formed separately in each pixel P region surrounded by the barrier rib PD. In this case, in order to secure the flexibility of the flexible display device, it is preferable that the interlayer insulating layer ILD is not stacked on the upper surface of the barrier rib PD made of an organic material. In particular, in an exemplary embodiment of the present application, it is preferable that the upper surface of the interlayer insulating layer ILD has a lower height than the upper surface of the barrier rib PD. As a result, the inorganic materials are disposed only on the upper surface of the base layer PS in the inner region surrounded by the barrier rib PD.

One end and the other end of the semiconductor layers SA and GA are exposed by patterning the interlayer insulating film ILD and the gate insulating film GI. A metal material is deposited and patterned on the interlayer insulating layer ILD to form source electrodes SS and DS and drain electrodes SD and DD. At this time, the data line DL shown in FIG. 2 , the pixel driving power supply line PL, and the first electrode of the capacitor Cst may be formed together.

The switching source electrode SS and the switching drain electrode SD may be formed on the interlayer insulating layer ILD to overlap the switching semiconductor layer SA with the switching gate electrode SG interposed therebetween. The driving source electrode DS and the driving drain electrode DD may be formed on the interlayer insulating layer ILD to overlap the driving semiconductor layer DA with the driving gate electrode DG interposed therebetween. The source electrodes SS and DS and the drain electrodes SD and DD may be formed together with the data line DL, the pixel driving power line PL, and the common power line CPL. That is, each of the source electrodes SS and DS, the drain electrodes SD and DD, the data line DL, the pixel driving power line PL, and the common power line CPL is formed by a patterning process for the source-drain electrode material. can be formed simultaneously.

Each of the source electrodes SS and DS and the drain electrodes SD and DD may be connected to the semiconductor layers SA and DA through an electrode contact hole penetrating the interlayer insulating layer ILD and the gate insulating layer GI. Source electrodes (SS, DS) and drain electrodes (SD, DD) are made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) And copper (Cu) may be formed of a single layer or multiple layers made of any one or an alloy thereof. Here, the driving source electrode DS of the driving thin film transistor DT shown in FIGS. 2 and 3 may be electrically connected to the pixel driving power line PL.

As such, the thin film transistors ST, DT, and ET provided in the pixel P of the flexible substrate FS constitute the pixel circuit PC. In addition, the gate driving circuit 200 disposed in the fourth non-display area IA4 of the flexible substrate FS may include thin film transistors identical to or similar to the thin film transistors ST, DT, and ET provided in the pixel P. can

The planarization layer PLN is formed over the entire flexible substrate FS to cover the thin film transistor layer. The planarization layer PLN provides a flat surface on the surface of the flexible substrate FS on which the thin film transistor layer is formed. According to an embodiment, the planarization layer (PLN) may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. It can be formed into a film.

In one embodiment of the present application, the planarization layer PLN may also be deposited on the barrier rib PD. A scan line SL, a data line DL, and a pixel driving current line PL are disposed on the barrier rib PD to connect the pixels P to each other. Accordingly, a planarization layer PLN may be stacked on the barrier rib PD for the purpose of protecting and insulating the wires. Since the planarization layer PLN is made of an organic material, even if it is stacked on the barrier rib PD made of an organic material, flexibility of the flexible display device is not a problem. In this case, the planarization layer PLN covers the wires SL, DL, and PL passing over the barrier rib PD. In addition, the planarization layer PLN may include a pixel contact hole PH for exposing the driving drain electrode DD of the driving thin film transistor DT provided in the pixel P.

A conductive material is deposited and patterned on the planarization layer PLN to form the pixel driving electrode AE. The pixel driving electrode AE is formed to have a size limited to the inside of the pixel P region. A bank (or bank pattern) BN is formed on the pixel driving electrode AE. The bank BN is disposed on the planarization layer PLN to define an opening area (or light emitting area) within the pixel P of the display area AA. Such a bank BN may be expressed as a pixel defining layer. The bank BN may be made of an organic material. In this case, the bank BN may be formed to cover the partition wall PD.

The light emitting element ED includes a pixel driving electrode AE, a light emitting layer EL, and a common electrode CE. The pixel driving electrode AE is formed on the planarization layer PLN and is electrically connected to the drain electrode D of the driving thin film transistor through a pixel contact hole PH provided in the planarization layer PLN. In this case, an edge portion other than a middle portion of the pixel driving electrode AE overlapping the opening area of the pixel P may be covered by the bank BN. The bank BN may define an opening area of the pixel P by covering an edge portion of the pixel driving electrode AE.

The pixel driving electrode AE according to an example may include a metal material having high reflectivity. For example, the pixel driving electrode AE may have a stacked structure of aluminum (Al) and titanium (Ti/Al/Ti) or a stacked structure of aluminum (Al) and indium tin oxide (ITO/Al/Ti). ITO), APC (Ag/Pd/Cu) alloy, and a multilayer structure such as a laminated structure of APC alloy and ITO (ITO/APC/ITO), or silver (Ag), aluminum (Al), molybdenum (Mo) , Gold (Au), magnesium (Mg), calcium (Ca), or barium (Ba) may include a single layer structure made of any one material or two or more alloy materials selected.

The emission layer EL is formed over the entire display area AA of the flexible substrate FS to cover the pixel driving electrode AE and the bank pattern BN. The light emitting layer EL according to an example may include two or more vertically stacked light emitting units to emit white light. For example, the light emitting layer EL according to an example may include a first light emitting part and a second light emitting part for emitting white light by mixing the first light and the second light. Here, the first light emitting unit emits the first light and may include any one of a blue light emitting unit, a green light emitting unit, a red light emitting unit, a yellow light emitting unit, and a yellow-green light emitting unit. The second light emitting unit may include a blue light emitting unit, a green light emitting unit, a red light emitting unit, a yellow light emitting unit, and a light emitting unit that emits second light optically supplementing the first light in a yellow-green color. For example, the first light emitting part may be a blue light emitting part, and the second light emitting part may be a combination of a yellow light emitting part and a green light emitting part, or a combination of a red light emitting part and a green light emitting part. Alternatively, the first light emitting unit may be a combination of a yellow light emitting part and a green light emitting part or a combination of a red light emitting part and a green light emitting part, and the second light emitting part may be a blue light emitting part according to a light emitting direction centered on the substrate.

The light emitting layer EL according to another example may include any one of a blue light emitting part, a green light emitting part, and a red light emitting part for emitting color light corresponding to a color set in the pixel P. For example, the light emitting layer EL according to another example may include any one of an organic light emitting layer, an inorganic light emitting layer, and a quantum dot light emitting layer, or may include a stacked or mixed structure of an organic light emitting layer (or an inorganic light emitting layer) and a quantum dot light emitting layer.

Additionally, the light emitting device ED according to an example may further include a functional layer for improving light emitting efficiency and/or lifetime of the light emitting layer EL.

The common electrode CE is formed to be electrically connected to the light emitting layer EL. The common electrode CE is formed over the entire display area AA of the flexible substrate FS to be commonly connected to the light emitting layer EL provided in each pixel P.

The common electrode CE according to an example may include a transparent conductive material or a semi-transmissive conductive material capable of transmitting light. When the common electrode CE is formed of a transflective conductive material, light emission efficiency of light emitted from the light emitting device ED may be increased through a micro cavity structure. The transflective conductive material according to an example may include magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). Additionally, a capping layer may be further formed on the common electrode CE to improve light emission efficiency by adjusting the refractive index of light emitted from the light emitting element ED.

An encapsulation layer 130 may be further stacked on the light emitting device ED. The encapsulation layer 130 is formed to surround the pixel array layer 120 . The encapsulation layer 130 serves to prevent oxygen or moisture from penetrating into the light emitting device ED.

The encapsulation layer 130 according to an example includes a first inorganic encapsulation layer (PAS1), an organic encapsulation layer (PCL) on the first inorganic encapsulation layer (PAS1), and a second inorganic encapsulation layer (PAS2) on the organic encapsulation layer (PCL). can include

The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 serve to block penetration of moisture or oxygen. The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 according to an embodiment may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. of inorganic materials. The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 may be formed by a chemical vapor deposition process or an atomic layer deposition process.

The organic encapsulation layer PCL is surrounded by the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2. The organic encapsulation layer (PCL) may be formed to have a relatively thick thickness compared to the first inorganic encapsulation layer (PAS1) and/or the second inorganic encapsulation layer (PAS2) so as to cover particles that may occur during the manufacturing process. there is. The organic encapsulation layer PCL may be formed of an organic material such as silicon oxycarbon (SiOCz) acrylic or epoxy-based resin. The organic encapsulation layer 133 may be formed by a coating process, for example, an inkjet coating process or a slit coating process.

In the flexible display device according to an exemplary embodiment of the present application, each pixel P has a structure divided by a barrier rib PD. That is, since each pixel P is divided into partition walls PD having excellent flexibility, flexibility of the flexible display device can be secured regardless of bending in any direction. In particular, the upper buffer layer BUF, the gate insulating layer GI, and the intermediate insulating layer ILD, which are insulating layers made of inorganic materials, are not stacked on the barrier rib PD. Therefore, the problem of damaging the thin film transistor due to the bending operation does not occur. Although the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 included in the lower buffer layer MB stacked under the base layer PS and the encapsulation layer 130 are inorganic material layers, the thin film transistor and Since it is not an inorganic material layer in direct contact with the same driving elements, it does not directly adversely affect the elements in a bending operation. Accordingly, the flexible display device according to an exemplary embodiment of the present application may have excellent flexibility and a robust structure that prevents damage to elements due to repeated bending stress.

Hereinafter, a cross-sectional structure of a flexible electroluminescent display according to another embodiment of the present application will be described in detail with reference to FIG. 4 and FIG. 2 . A flexible electroluminescent display device according to another exemplary embodiment of the present application may include a flexible substrate FS, a pixel array layer 120 and an encapsulation layer 130 . In the description of other embodiments of the present application, descriptions of components that are the same as or indistinguishable from the previous embodiments are omitted or briefly described.

The flexible substrate FS is a base layer and includes a plastic material or a glass material. The flexible substrate FS according to an example may include an opaque or colored polyimide material. The flexible substrate FS according to an example includes barrier ribs PD and a base layer PS formed by etching an organic layer. In some cases, a lower buffer layer MB and a lower substrate BS may be attached to a lower surface of the base layer PS. In this case, after depositing the lower buffer layer MB on the upper surface of the lower substrate BS, the organic layer is applied. Thereafter, the organic layer is etched in a net-like pattern to form the barrier rib PD and the base layer PS. The flexible substrate FS according to an example may further include a back plate (not shown) coupled to a rear surface of the flexible substrate FS in the thickness direction Z.

Most preferably, the flexible substrate FS is a material having excellent flexibility that can be freely folded or unfolded. The flexible substrate FS may include a display area AA and a non-display area IA surrounding the display area AA.

An upper buffer layer BUF is formed on the upper surface of the base layer PS in the flexible substrate FS. The upper buffer layer BUF is formed on the surface of the base layer PS to block moisture penetrating into the pixel array layer 120 through the flexible substrate FS, which is vulnerable to moisture permeation. The upper buffer layer BUF according to an example may include a plurality of inorganic layers alternately stacked. The upper buffer layer BUF is preferably formed only on the surface of the base layer PS for each pixel P surrounded by the barrier rib PD. The present application is characterized in that in order to secure flexibility of a display panel in a flexible display device, it is possible. To this end, it is preferable that the inorganic material layer is not stacked on the barrier rib PD.

The pixel array layer 120 may include a thin film transistor layer, a planarization layer PLN, a bank BN, and a light emitting element ED.

The thin film transistor layer includes a plurality of pixels P defined in the display area AA of the flexible substrate FS and gates defined in the third and/or fourth non-display areas IA3 and IA4 of the flexible substrate FS. Each is provided in the driving circuit 200 .

The thin film transistor layer according to an example includes a switching thin film transistor (ST), a driving thin film transistor (DT), a compensation thin film transistor (ET), a gate insulating film (GI) and an interlayer insulating film (ILD) formed on the upper buffer layer (BUF). . The switching thin film transistor ST includes a switching semiconductor layer SA, a switching gate electrode SG, a switching source electrode SS, and a switching drain electrode SD formed on the upper buffer layer BUF. The driving thin film transistor DT includes a driving semiconductor layer DA, a driving gate electrode DG, a driving source electrode DS, and a driving drain electrode DD formed on the upper buffer layer BUF.

The semiconductor layers SA and DA may include a silicon-based semiconductor material, an oxide-based semiconductor material, or an organic material-based semiconductor material, and may have a single-layer structure or a multi-layer structure.

The gate insulating layer GI may be formed on the flexible substrate FS to cover the semiconductor layers SA and DA. The gate insulating layer GI may be formed of an inorganic layer, for example, a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof. In particular, when the gate insulating film GI is made of an inorganic material, it is preferable to form the gate insulating film GI separately in each pixel P region surrounded by the barrier rib PD. In this case, in order to secure the flexibility of the flexible display device, it is preferable that the gate insulating film GI is not stacked on the upper surface of the barrier rib PD.

The switching gate electrode SG may be formed on the gate insulating layer GI so as to overlap the switching semiconductor layer SA, and the driving gate electrode DG may overlap the driving semiconductor layer DA. The gate electrodes SG and DG may be formed together with the scan line SL. The gate electrodes SG and DG according to an exemplary embodiment include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). ) may be formed of a single layer or multiple layers made of any one or an alloy thereof.

An interlayer insulating layer ILD is stacked on the flexible substrate FS to cover the gate electrodes SG and DG and the gate insulating layer GI. When the interlayer insulating layer ILD is made of an inorganic material, it may be formed separately in each pixel P area surrounded by the barrier rib PD. In this case, in order to secure the flexibility of the flexible display device, it is preferable that the interlayer insulating layer ILD is not laminated on the upper surface of the barrier rib PD. In particular, in an exemplary embodiment of the present application, it is preferable that the upper surface of the interlayer insulating layer ILD has a lower height than the upper surface of the barrier rib PD. As a result, the inorganic materials are disposed only on the upper surface of the base layer PS in the inner region surrounded by the barrier rib PD.

One end and the other end of the semiconductor layers SA and GA are exposed by patterning the interlayer insulating film ILD and the gate insulating film GI. A metal material is deposited and patterned on the interlayer insulating layer ILD to form source electrodes SS and DS and drain electrodes SD and DD. At this time, the data line DL shown in FIG. 2 , the pixel driving power supply line PL, and the first electrode of the capacitor Cst may be formed together.

The switching source electrode SS and the switching drain electrode SD may be formed on the interlayer insulating layer ILD to overlap the switching semiconductor layer SA with the switching gate electrode SG interposed therebetween. The driving source electrode DS and the driving drain electrode DD may be formed on the interlayer insulating layer ILD to overlap the driving semiconductor layer DA with the driving gate electrode DG interposed therebetween. Each of the source electrodes SS and DS, the drain electrodes SD and DD, the data line DL, the pixel driving power line PL, and the common power line CPL are simultaneously formed by a patterning process for the source and drain electrode materials. It can be.

Each of the source electrodes SS and DS and the drain electrodes SD and DD may be connected to the semiconductor layers SA and DA through an electrode contact hole penetrating the interlayer insulating layer ILD and the gate insulating layer GI. Source electrodes (SS, DS) and drain electrodes (SD, DD) are made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) And copper (Cu) may be formed of a single layer or multiple layers made of any one or an alloy thereof. Here, the driving source electrode DS of the driving thin film transistor DT shown in FIGS. 2 and 4 may be electrically connected to the pixel driving power line PL.

As such, the thin film transistors ST, DT, and ET provided in the pixel P of the flexible substrate FS constitute the pixel circuit PC. In addition, the gate driving circuit 200 disposed in the third and/or fourth non-display areas IA3 and IA4 of the flexible substrate FS is the same as the thin film transistors ST, DT and ET provided in the pixel P. or a similar thin film transistor.

The planarization layer PLN is formed in each pixel P region surrounded by the barrier rib PD to cover the thin film transistor layer. The planarization layer PLN provides a flat surface on the surface of the flexible substrate FS on which the thin film transistor layer is formed. According to an embodiment, the planarization layer (PLN) may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. It can be formed into a film.

In another embodiment of the present application shown in FIG. 4 , the planarization layer PLN is not laminated on the barrier ribs PD, but is applied only to the inner region between the barrier ribs PD. A scan line SL, a data line DL, and a pixel driving current line PL are disposed on the barrier rib PD to connect the pixels P to each other. In this case, the wires SL, DL, and PL passing over the barrier rib PD remain exposed. In addition, the planarization layer PLN may include a pixel contact hole PH for exposing the driving drain electrode DD of the driving thin film transistor DT provided in the pixel P.

A conductive material is deposited and patterned on the planarization layer PLN to form the pixel driving electrode AE. The pixel driving electrode AE is formed to have a size limited to the inside of the pixel P region surrounded by the barrier rib PD. A bank BN is formed on the pixel driving electrode AE. The bank BN is disposed on the planarization layer PLN to define an opening area (or light emitting area) within the pixel P of the display area AA. Such a bank BN may be expressed as a pixel defining layer. In another embodiment of the present application, the banks BN are not stacked on the barrier ribs PD, but are formed separately for each pixel P region, which is an inner region between the barrier ribs PD. For example, an upper surface of the bank BN may have a lower height than an upper surface of the barrier rib PD.

The light emitting element ED includes a pixel driving electrode AE, a light emitting layer EL, and a common electrode CE. The pixel driving electrode AE is formed on the planarization layer PLN and is electrically connected to the drain electrode D of the driving thin film transistor through a pixel contact hole PH provided in the planarization layer PLN. In this case, an edge portion other than a middle portion of the pixel driving electrode AE overlapping the opening area of the pixel P may be covered by the bank BN. The bank BN may define an opening area of the pixel P by covering an edge portion of the pixel driving electrode AE.

The light emitting layer EL is formed in the display area AA of the flexible substrate FS to cover the pixel driving electrode AE and the bank BN. The common electrode CE is formed to be electrically connected to the light emitting layer EL. The common electrode CE according to an example may include a transparent conductive material or a semi-transmissive conductive material capable of transmitting light. When the common electrode CE is formed of a transflective conductive material, light emission efficiency of light emitted from the light emitting device ED may be increased through a micro cavity structure. The transflective conductive material according to an example may include magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). Additionally, a capping layer may be further formed on the common electrode CE to improve light emission efficiency by adjusting the refractive index of light emitted from the light emitting device ED.

In another embodiment of the present application, characteristics of the cross-sectional structure of the light emitting device ED will be described. A spacer SP is formed on the flexible substrate FS on which the bank BN is formed. In particular, the spacer SP is formed on the barrier rib PD. The barrier rib PD has a mesh shape connected on the flexible substrate FS. The spacer SP may have the same shape as the barrier rib PD. As another example, the spacers SP may have a columnar shape and may be distributed and disposed on the partition wall PD. A scan line SL, a data line DL, and a pixel driving power supply line PL are disposed on the barrier rib PD. For the purpose of protecting these wires, the spacer SP preferably has the same mesh shape as the barrier rib PD. In particular, the spacer SP preferably has a reverse taper shape.

An emission layer EL including an organic material is applied on the surface of the flexible substrate FS on which the spacer SP is formed. The light emitting layer EL has a disconnected structure for each pixel P region due to the inverse tapered structure of the spacer SP. That is, the light emitting layer EL has a structure that is independent for each pixel P and stacked on the pixel electrode AE. However, the remainder of the light emitting layer EL may be stacked on the upper surface of the spacer SP. However, this residue is not connected to the light emitting layer EL covering the surrounding pixel P area.

A common electrode CE is applied on the surface of the flexible substrate FS on which the light emitting layer EL is formed. The common electrode CE includes a metal oxide having a transparent property. For example, the common electrode CE may have a strip shape connecting pixels P in a horizontal direction. A scan line SL extending in a horizontal direction is disposed on the barrier rib PD. Since the scan line SL and the common electrode CE must not be electrically connected, the common electrode CE is spaced apart from the scan line SL by a predetermined distance, runs in a horizontal direction, and is opened by the bank BN. It may have a band shape covering all of the pixel electrodes AE.

As another example, the common electrode CE may have a strip shape connecting the pixels P in the vertical direction. A data line DL and a pixel driving power line PL are disposed on the barrier rib PD, which run in a vertical direction. The common electrode CE should not be electrically connected to the data line DL and the pixel driving power supply line PL. Therefore, the common electrode CE is spaced apart from the data line DL and the pixel driving power supply line PL by a predetermined distance, runs in a vertical direction, and covers all of the pixel electrodes AE opened by the bank BN. can have a shape.

An encapsulation layer 130 may be further stacked on the light emitting device ED. The encapsulation layer 130 is formed to surround the pixel array layer 120 . The encapsulation layer 130 serves to prevent oxygen or moisture from penetrating into the light emitting device ED.

The encapsulation layer 130 according to an example includes a first inorganic encapsulation layer (PAS1), an organic encapsulation layer (PCL) on the first inorganic encapsulation layer (PAS1), and a second inorganic encapsulation layer (PAS2) on the organic encapsulation layer (PCL). can include

The first inorganic encapsulation layer PAS1 climbs over the spacer SP and covers the entire surface of the flexible substrate FS. Since the first inorganic encapsulation layer PAS1 includes an inorganic material, it has a shape covering the entire shape of the reverse tapered spacer SP.

In the flexible display device according to another embodiment of the present application, each pixel P has a structure partitioned by a barrier rib PD. That is, since each pixel P is divided into partition walls PD having excellent flexibility, flexibility of the flexible display device can be secured regardless of bending in any direction. In particular, the upper buffer layer BUF, the gate insulating layer GI, and the interlayer insulating layer ILD, which are inorganic materials, are not stacked on the barrier rib PD. Therefore, the problem of damaging the thin film transistor due to the bending operation does not occur. Although the lower buffer layer MB stacked on the rear surface of the base layer PS and the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 included in the encapsulation layer 130 are inorganic material layers, the thin film transistor and Since it is not an inorganic material layer in direct contact with the same driving elements, it does not directly adversely affect the elements in a bending operation. Accordingly, the flexible display device according to the present application may have excellent flexibility and a robust structure that prevents breakage of elements due to repeated bending stress.

Hereinafter, a flexible electroluminescent display device according to another exemplary embodiment of the present application will be described with reference to FIGS. 2 and 5 . 5 is a cross-sectional view taken along the line II-II′ of FIG. 1 showing the structure of a flexible electroluminescent display device according to another embodiment of the present application. In another embodiment of the present application, a barrier rib made of an organic material is further added to the outermost portion of the flexible electroluminescent display to provide a structure capable of effectively preventing penetration of moisture and foreign substances from the outside. In the description of another embodiment of the present application, descriptions of components that are the same as or indistinguishable from the previous embodiments are omitted or briefly described.

The flexible substrate FS is a base layer and includes a plastic material or a glass material. In some cases, a lower buffer layer MB and a lower substrate BS may be attached to a lower surface of the base layer PS. In this case, after depositing the lower buffer layer MB on the upper surface of the lower substrate BS, the organic layer is applied. Thereafter, the organic layer is etched in a net-like pattern to form the barrier rib PD and the base layer PS. The barrier rib PD and the base layer PS are integrally formed and made of the same material. Barrier ribs PD having a certain width and a thickness greater than that of the base layer PS protrude on the surface of the base layer PS having a small thickness, and an inner region surrounded by the barrier ribs PD is defined as a pixel P.

Most preferably, the flexible substrate FS is a material having excellent flexibility that can be freely folded or unfolded. The flexible substrate FS may include a display area AA and a non-display area IA surrounding the display area AA. Particularly, the barrier rib PD is also protruded from the outermost edge of the flexible substrate FS. The outermost barrier rib PD is included in the non-display area IA.

An upper buffer layer BUF is formed on the upper surface of the base layer PS in the flexible substrate FS. The upper buffer layer BUF is formed on the surface of the base layer PS to block moisture penetrating into the pixel array layer 120 through the flexible substrate FS, which is vulnerable to moisture permeation. The upper buffer layer BUF is preferably stacked on the surface of the base layer PS except for the upper surface of the barrier rib PD. Therefore, even in the third non-display area IA3 where the gate driving circuit 200 is disposed, the upper buffer layer BUF may be coated on the surface of the base layer PS. The present application is characterized in that in order to secure flexibility of a display panel in a flexible display device, it is possible. To this end, it is preferable that the inorganic material layer is not stacked on the barrier rib PD.

The pixel array layer 120 may include a thin film transistor layer, a planarization layer PLN, a bank BN, and a light emitting element ED.

The thin film transistor layer is applied to the plurality of pixels P defined in the display area AA of the flexible substrate FS and the gate driving circuit 200 defined in the third non-display area IA3 of the flexible substrate FS. provided

The thin film transistor layer according to an example includes a switching thin film transistor, a driving thin film transistor, a compensation thin film transistor, a gate insulating film GI, and an interlayer insulating film ILD formed on the upper buffer layer BUF. Hereinafter, for convenience of description, a thin film transistor T will be simply described. The thin film transistor T includes a semiconductor layer A, a gate electrode G, a source electrode S, and a drain electrode D formed on the upper buffer layer BUF.

The semiconductor layer (A) may include a silicon-based semiconductor material, an oxide-based semiconductor material, or an organic material-based semiconductor material, and may have a single-layer structure or a multi-layer structure.

The gate insulating layer GI may be formed on the flexible substrate FS to cover the semiconductor layer A. The gate insulating layer GI may be formed of an inorganic layer, for example, a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof. In particular, when the gate insulating film GI is made of an inorganic material, it is preferable to form the gate insulating film GI separately in each pixel P region surrounded by the barrier rib PD. Also, a gate insulating layer GI may be stacked on the surface of the base layer PS in the non-display area IA. In this case, in order to secure the flexibility of the flexible display device, it is preferable that the gate insulating film GI is not stacked on the upper surface of the barrier rib PD.

The gate electrode G may be formed on the gate insulating layer GI so as to overlap the semiconductor layer A. The gate electrode G may be formed together with the scan line SL. The gate electrode G according to an embodiment is selected from among molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be formed as a single layer or multiple layers made of any one or an alloy thereof.

An interlayer insulating layer ILD is stacked on the flexible substrate FS to cover the gate electrode G and the gate insulating layer GI. When the interlayer insulating layer ILD is made of an inorganic material, it may be formed separately in each pixel P area surrounded by the barrier rib PD. In this case, in order to secure the flexibility of the flexible display device, it is preferable that the interlayer insulating layer ILD is not laminated on the upper surface of the barrier rib PD. In particular, in an exemplary embodiment of the present application, it is preferable that the upper surface of the interlayer insulating layer ILD has a lower height than the upper surface of the barrier rib PD. In addition, the interlayer insulating layer ILD may also be stacked on the base layer PS inside the outermost barrier rib PD. As a result, the inorganic materials are disposed only on the upper surface of the base layer PS in the inner region surrounded by the barrier rib PD.

One end and the other end of the semiconductor layer (A) are exposed by patterning the interlayer insulating film (ILD) and the gate insulating film (GI). A metal material is deposited and patterned on the interlayer insulating layer ILD to form a source electrode S and a drain electrode D. At this time, the data line DL shown in FIG. 2 , the pixel driving power supply line PL, and the first electrode of the capacitor Cst may be formed together.

The source electrode S and the drain electrode D may be formed on the interlayer insulating layer ILD to overlap the semiconductor layer A with the gate electrode G interposed therebetween. The source electrode S and the drain electrode D may be formed on the interlayer insulating layer ILD to overlap the semiconductor layer A with the gate electrode G interposed therebetween. Each of the source electrode S, the drain electrode D, the data line DL, the pixel driving power line PL, and the common power line CPL may be simultaneously formed by a patterning process for the source and drain electrode materials.

Each of the source electrode S and the drain electrode D may be connected to the semiconductor layer A through an electrode contact hole penetrating the interlayer insulating layer ILD and the gate insulating layer GI. The source electrode (S) and the drain electrode (D) are made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). ) may be formed of a single layer or multiple layers made of any one or an alloy thereof.

As such, the thin film transistors T provided in the pixel P of the flexible substrate FS constitute the pixel circuit PC. In addition, the gate driving circuit 200 disposed in the third non-display area IA3 of the flexible substrate FS may include a thin film transistor identical to or similar to the thin film transistor T provided in the pixel P.

A planarization layer PLN is formed in each pixel P region to cover the thin film transistor layer. The planarization layer PLN provides a flat surface on the surface of the flexible substrate FS on which the thin film transistor layer is formed.

In another embodiment of the present application, the planarization layer PLN is not laminated on the barrier ribs PD, but is applied only to an inner region between the barrier ribs PD. A scan line SL, a data line DL, and a pixel driving current line PL are disposed on the barrier rib PD to connect the pixels P to each other. In this case, the wires SL, DL, and PL passing over the barrier rib PD remain exposed. In addition, the planarization layer PLN may include a pixel contact hole PH for exposing the driving drain electrode DD of the driving thin film transistor DT provided in the pixel P. On the other hand, nothing is formed on the upper surface of the outermost partition wall PD.

A conductive material is deposited and patterned on the planarization layer PLN to form the pixel driving electrode AE. The pixel driving electrode AE is formed to have a size limited to the inside of the pixel P region. A bank BN is formed on the pixel driving electrode AE. The bank BN is disposed on the planarization layer PLN to define an opening area (or light emitting area) within the pixel P of the display area AA. Such a bank BN may be expressed as a pixel defining layer. In another embodiment of the present application, the banks BN are not stacked on the barrier ribs PD, but are formed separately for each pixel P region, which is an inner region between the barrier ribs PD. For example, an upper surface of the bank BN may have a lower height than an upper surface of the barrier rib PD.

The light emitting element ED includes a pixel driving electrode AE, a light emitting layer EL, and a common electrode CE. The pixel driving electrode AE is formed on the planarization layer PLN and is electrically connected to the drain electrode D of the driving thin film transistor through a pixel contact hole PH provided in the planarization layer PLN. In this case, an edge portion other than a middle portion of the pixel driving electrode AE overlapping the opening area of the pixel P may be covered by the bank BN. The bank BN may define an opening area of the pixel P by covering an edge portion of the pixel driving electrode AE.

The light emitting layer EL is formed to cover the pixel driving electrode AE and the bank BN. The common electrode CE is formed to be electrically connected to the light emitting layer EL. The common electrode CE according to an example may include a transparent conductive material or a semi-transmissive conductive material capable of transmitting light.

In FIG. 5 showing another embodiment of the present application, the cross-sectional structure of the light emitting device ED has the same structure as the embodiment of FIG. 4 . However, it is not limited thereto, and may have, for example, the same structure as the embodiment of FIG. 3 .

A spacer SP is formed on the flexible substrate FS on which the bank BN is formed. In particular, the spacer SP is formed on the barrier rib PD. The barrier rib PD has a mesh shape connected on the flexible substrate FS. The spacer SP may have the same shape as the barrier rib PD. On the other hand, the spacer SP is not formed on the outermost barrier rib PD.

Part of the scan line SL, the data line DL, and the pixel driving power line PL are disposed on the barrier rib PD so as to pass therethrough. For the purpose of protecting these wires, the spacer SP preferably has the same mesh shape as the barrier rib PD. In particular, the spacer SP preferably has a reverse taper shape.

An emission layer EL including an organic material is applied on the surface of the flexible substrate FS on which the spacer SP is formed. The light emitting layer EL has a disconnected structure for each pixel P region due to the inverse tapered structure of the spacer SP. That is, the light emitting layer EL has a structure that is independent for each pixel P and stacked on the pixel electrode AE. However, the remainder of the light emitting layer EL may be stacked on the upper surface of the spacer SP. However, this residue is not connected to the light emitting layer EL covering the area of the pixel P around it.

A common electrode CE is applied on the surface of the flexible substrate FS on which the light emitting layer EL is formed. The common electrode CE includes a metal oxide having a transparent property. For example, the common electrode CE may have a strip shape connecting pixels P in a horizontal direction. A scan line SL extending in a horizontal direction is disposed on the barrier rib PD. Since the scan line SL and the common electrode CE must not be electrically connected, the common electrode CE is spaced apart from the scan line SL by a predetermined distance, runs in a horizontal direction, and is opened by the bank BN. It may have a band shape covering all of the pixel driving electrodes AE.

As another example, the common electrode CE may have a strip shape connecting the pixels P in the vertical direction. A portion of the data line DL and the pixel driving power line PL extending in the vertical direction are disposed on the barrier rib PD so as to pass therethrough. The common electrode CE should not be electrically connected to the data line DL and the pixel driving power supply line PL. Therefore, the common electrode CE is spaced apart from the data line DL and the pixel driving power supply line PL by a predetermined distance, runs in a vertical direction, and covers all of the pixel electrodes AE opened by the bank BN. can have a shape.

An encapsulation layer 130 may be further stacked on the light emitting device ED. The encapsulation layer 130 is formed to surround the pixel array layer 120 . The encapsulation layer 130 serves to prevent oxygen or moisture from penetrating into the light emitting device ED.

The encapsulation layer 130 according to an example includes a first inorganic encapsulation layer (PAS1), an organic encapsulation layer (PCL) on the first inorganic encapsulation layer (PAS1), and a second inorganic encapsulation layer (PAS2) on the organic encapsulation layer (PCL). can include The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 serve to block penetration of moisture or oxygen. The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 according to an embodiment may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. of inorganic materials. The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 may be formed by a chemical vapor deposition process or an atomic layer deposition process.

The first inorganic encapsulation layer PAS1 climbs over the spacer SP and covers the entire surface of the flexible substrate FS. Since the first inorganic encapsulation layer PAS1 includes an inorganic material, it has a shape covering the entire shape of the reverse tapered spacer SP. Therefore, the first inorganic encapsulation layer PAS1 is also stacked on the barrier rib PD disposed in the display area AA.

The organic encapsulation layer PCL is surrounded by the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2. The organic encapsulation layer (PCL) has a relatively thick thickness compared to the first inorganic encapsulation layer (PAS1) and/or the second inorganic encapsulation layer (PAS2) to adsorb and/or block particles that may occur during the manufacturing process. can be formed as The organic encapsulation layer PCL may be formed of an organic material such as silicon oxycarbon (SiOCz) acrylic or epoxy-based resin. The organic encapsulation layer (PCL) may be formed by a coating process, for example, an inkjet coating process or a slit coating process.

The flexible electroluminescent display device according to another exemplary embodiment of the present application may further include a dam structure DM adjacent to the outermost organic barrier rib PD. The dam structure DM is a structure disposed in the non-display area IA of the flexible substrate FS to prevent the organic encapsulation layer PCL from overflowing to the outside.

The dam structure DM according to an example includes the display area AA, the gate driving circuit 200 disposed outside the display area AA, and the outside of the common power line CPL disposed outside the gate driving circuit 200. can be placed in In some cases, the dam structure DM may be disposed to overlap the outer portion of the common power line CPL. In this case, the width of the bezel may be reduced by reducing the width of the non-display area IA where the gate driving circuit 200 and the common power line CPL are disposed.

For example, the dam structure DM may have a triple layer structure formed perpendicular to the flexible substrate FS. For example, a first layer formed of a planarization layer PLN, a second layer formed of a bank pattern BN, and a third layer formed of a spacer SP may be included. The spacer SP included in the dam structure DM may have a regular taper structure.

The first layer may have a trapezoidal cross-sectional structure in which the planarization layer PLN is patterned. The second layer may have a trapezoidal cross-sectional structure stacked on the first layer. The third layer may have a trapezoidal cross-sectional structure stacked on the second layer. When the thickness of the organic encapsulation layer PCL is thin and it is easy to control the spreadability of the organic encapsulation layer PCL, it may be sufficient even if the height of the dam structure DM is not high. In this case, the third layer may be omitted.

It is preferable that the height of the organic encapsulation layer PCL from the edge area to the upper surface is lower than the entire height of the dam structure DM. As a result, the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 are in surface contact with each other on the upper surface and the outer sidewall of the dam structure DM.

The outermost part of the dam structure DM further includes a partition wall PD. As shown in FIG. 5 , end faces of the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 are in contact with the vertical surface of the outermost barrier rib PD. That is, it has a structure in which the cross-sectional gap between the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 is sealed by the partition wall PD. As a result, a problem in which the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 are separated or damaged does not occur.

In the flexible display device according to another embodiment of the present application, each pixel P has a structure divided by a barrier rib PD. That is, since each pixel (P) is divided by a partition wall (PD) containing an organic material having excellent flexibility, flexibility of the flexible display device can be secured regardless of bending in any direction. In particular, the upper buffer layer BUF, the gate insulating layer GI, and the intermediate insulating layer ILD, which are inorganic materials, are not stacked on the barrier rib PD. Therefore, the problem of damaging the thin film transistor due to the bending operation does not occur. Although the lower buffer layer MB stacked under the base layer PS and the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 included in the encapsulation layer 130 are inorganic material layers, the thin film transistor and Since it is not an inorganic material layer in direct contact with the same driving elements, it does not directly adversely affect the elements in a bending operation. Accordingly, the flexible display device according to an exemplary embodiment of the present application may have excellent flexibility and a robust structure that prevents damage to elements due to repeated bending stress.

Particularly, the barrier rib PD protrudes thicker than the base layer PS even at the outermost part of the flexible substrate FS to block the external environment. Particularly, the outermost barrier rib PD extends from the display area AA and extends over the dam structure DM with the lower portion of the side wall of the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2. make contact with the end As a result, the bonded ends of the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 that are in surface contact outside the dam structure DM have a structure in which the outermost partition wall PD seals them. Therefore, it is possible to prevent penetration of moisture or foreign substances from the outside. In addition, it is possible to prevent problems in that the stacked thin films are separated or lifted.

The foldable or rollable electroluminescent display device according to the present application can absorb and/or disperse stress caused by repeated bending operations, prevent damage to main elements, and suppress penetration of moisture from the outside. provides a structure that is

Such an electric field display device according to an example of the present application is electronic notebook, electronic book, PMP (Portable Multimedia Player), navigation, UMPC (Ultra Mobile PC), smart phone, mobile communication terminal, mobile phone, tablet Portable electronic devices such as PC (personal computer), smart watch, watch phone, or wearable device, as well as televisions, laptops, monitors, refrigerators, microwave ovens, washing machines, cameras, etc. It can be applied to various products.

Features, structures, effects, etc. described in various embodiments of the present application described above are included in at least one example of the present application, and are not necessarily limited to only one example. Furthermore, the features, structures, effects, etc. exemplified in at least one example of this application can be combined or modified with respect to other examples by those skilled in the art to which this application belongs. Therefore, contents related to these combinations and variations should be construed as being included in the scope of the present application.

The present application described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which this application belongs that various substitutions, modifications, and changes are possible without departing from the technical details of the present application. It will be clear to those who have knowledge of Therefore, the scope of the present application is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be construed as being included in the scope of the present application.

SUB: Substrate T: Thin Film Transistor
PLN: planarization layer BN: bank pattern
200: gate driving circuit 300: driving integrated circuit
120: pixel array layer FS: flexible substrate
ED: light emitting element AE: pixel driving electrode
EL: light emitting layer CE: common electrode
CPL: common power wiring BS: lower board
BSL: bottom metal layer TR: trench
M1: first metal layer M2: second metal layer
W: depression
ORL: organic material layer INO: inorganic material layer
BD: bending direction BX: bending axis

Claims (12)

a flexible substrate having a base layer and barrier ribs protruding from the base layer with a predetermined thickness integrally with the base layer to surround a plurality of pixels arranged in a matrix manner on a surface of the base layer;
a scan line extending in a transverse direction of the flexible substrate while crossing the inside of the pixels surrounded by the barrier ribs and crossing the barrier ribs;
a data wire and a pixel driving power supply wire extending in a vertical direction of the flexible substrate while crossing the inside of the pixels surrounded by the barrier rib;
a driving element disposed within the pixel and connected to the scan wiring, the data wiring, and the pixel driving power supply wiring; and
A flexible electroluminescent display comprising a light emitting element disposed within the pixel and connected to the driving element.
According to claim 1,
The base layer has a thickness smaller than that of the barrier rib.
According to claim 1,
The scan line, the data line, and the pixel driving power line are arranged to pass over the barrier rib and the base layer.
According to claim 3,
Further comprising a stacked spacer having an inverse tapered cross-sectional shape on the partition wall,
The light emitting element,
a pixel electrode connected to the driving element;
a light emitting layer over the pixel electrode; and
Including a common electrode on the light emitting layer,
The light emitting layer is separated for each pixel by the spacer,
The common electrode is commonly stacked on the light emitting layers of horizontally adjacent pixels over the spacer.
According to claim 1,
Further comprising a planarization film laminated between the driving element and the light emitting element,
A side surface of an insulating film made of an inorganic material included in the driving element is in contact with a side surface of the barrier rib.
According to claim 5,
The planarization film,
A flexible electroluminescent display device stacked higher than the height of the barrier rib and covering an upper surface of the barrier rib.
According to claim 5,
The planarization film,
The flexible electroluminescent display device of claim 1 , wherein a side surface of the planarization layer contacts a side surface of the barrier rib by being stacked lower than a height of the barrier rib.
According to claim 1,
The flexible substrate,
a display area in which the pixels are disposed; and
a non-display area surrounding the display area;
The non-display area is
a gate driving element disposed on the base layer;
a common power wiring disposed above the base layer;
a dam structure disposed above the base layer; and
A flexible electroluminescent display comprising an external barrier rib protruding upward along an outermost edge of the base layer and surrounding the dam structure.
According to claim 8,
A flexible electroluminescent display device in which an inorganic material layer is not stacked on an upper surface of the external barrier rib.
According to claim 8,
a first inorganic encapsulation layer stacked on the light emitting element over the barrier rib;
an organic encapsulation layer laminated on the first inorganic encapsulation layer;
A flexible electroluminescent display device further comprising a second inorganic encapsulation layer stacked on the organic encapsulation layer.
According to claim 10,
The organic encapsulation layer is limited to the inner region of the dam structure,
The first inorganic encapsulation layer and the second inorganic encapsulation layer seal the organic encapsulation layer, make surface contact outside the dam structure, and contact the inner surface of the external barrier rib.
According to claim 1,
a lower buffer layer stacked under the base layer;
A flexible electroluminescent display device further comprising a lower substrate stacked on a lower surface of the lower buffer layer.

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