KR20200063954A - Wireless communication apparatus and operation method thereof - Google Patents

Abstract

The present invention relates to a wireless communication device to increase memory use efficiency and an operation method thereof. According to one technical aspect of the present invention, the operation method comprises the following steps of: receiving a physical downlink control channel (PDCCH) including a plurality of control chamber elements (CCE); storing a plurality of log likelihood ratios (LLR) generated by demodulating the PDCCH in a data buffer; storing an address of the data buffer, in which the LLRs corresponding to each of a plurality of candidate PDCCHs in accordance with an aggregation level for the CCEs, in a plurality of address buffers; and using the data buffer and the address buffers to perform blind decoding for the candidate PDCCHs.

Description

Wireless communication device and its operation method {WIRELESS COMMUNICATION APPARATUS AND OPERATION METHOD THEREOF}

The technical idea of the present disclosure relates to a wireless communication device, and in particular, is an invention related to a method for managing data necessary for decoding.

Recent 5G (or NR (New Radio)) communication system is a new radio access technology (new radio access technology) to provide ultra-high-speed data services of several Gbps using an ultra-wide bandwidth of more than 100MHz bandwidth compared to the existing LTE and LTE-A Aim for that. However, in the frequency bands of hundreds of MHz or several GHz used in LTE and LTE-A, it is difficult to secure an ultra-wideband frequency of 100 MHz or higher, so the 5G communication system uses a wide frequency band existing in the frequency band of 6 GHz or higher to signal. A method of transmitting is being considered. Specifically, in a 5G communication system, a transmission rate may be increased using a millimeter wave band, such as a 28 GHz band or a 60 GHz band.

Meanwhile, the wireless communication device may decode a physical downlink control channel (PDCCH) received from the base station in order to perform communication with the base station in a 5G communication system. At this time, a method for efficiently managing data required for PDCCH decoding using a buffer configuration in a wireless communication device has been studied to conform to a 5G communication system.

The technical idea of the present disclosure provides a wireless communication device capable of improving memory usage efficiency by preventing redundant storage of data necessary for PDCCH decoding and a method of operating the same.

In order to achieve the above object, an operation method of a wireless communication device according to an aspect of the technical idea of the present disclosure includes receiving a physical downlink control channel (PDCCH) including a plurality of control channel elements (CCEs), the Storing a plurality of LLRs generated by demodulating a PDCCH in a data buffer, and addressing the address of the data buffer in which LLRs corresponding to each of the plurality of candidate PDCCHs according to the aggregation level for the CCEs are stored And storing in a plurality of address buffers and performing blind decoding on the candidate PDCCHs using the data buffer and the address buffers.

A method of operating a wireless communication device managing data required for blind decoding according to an aspect of the technical spirit of the present disclosure includes generating a CCE index and corresponding LLRs from a PDCCH including a plurality of CCEs, and the LLRs. And storing in the data buffer and storing the address of the data buffer in which the LLRs are stored in at least one address buffer selected from among a plurality of address buffers based on the CCE index.

An RF integrated circuit configured to receive a PDCCH including a plurality of CCEs from a base station according to an aspect of the technical idea of the present disclosure, and a controller configured to perform blind decoding of each of a plurality of candidate PDCCHs according to an aggregation level for the CCEs Including, the controller stores the LLRs generated from the PDCCH in a data buffer, and the LLRs are stored in at least one address buffer selected from among a plurality of address buffers based on a CCE index corresponding to the LLRs. It characterized in that it further comprises a data management circuit configured to store the address of the data buffer.

According to a wireless communication apparatus and an operation method thereof according to an embodiment of the present disclosure, LLRs necessary for decoding and LLRs required for decoding are individually stored by using a data buffer and a plurality of address buffers, thereby overlapping LLRs. It is possible to prevent storage, thereby effectively improving memory usage.

Effects obtained in one embodiment of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned are those skilled in the art from the following description. Can be clearly drawn and understood. That is, unintended effects of implementing one embodiment of the present disclosure may also be derived by one of ordinary skill in the art from one embodiment of the present disclosure.

1 is a schematic block diagram of a wireless communication system according to an exemplary embodiment of the present disclosure.
2 is a diagram showing the basic structure of a time-frequency domain in a wireless communication system.
3 is a diagram illustrating a PDCCH in a wireless communication system.
4 is a diagram illustrating a resource mapping method of a PDCCH in a wireless communication system.
5 is a diagram for explaining a search space of a PDCCH in a wireless communication system and a blind decoding method therefor.
Fig. 6 is a flow chart showing a method for buffering data necessary for decoding a wireless communication device according to an exemplary embodiment of the present disclosure.
7 is a block diagram specifically illustrating a controller of a wireless communication device according to an exemplary embodiment of the present disclosure.
8 is a diagram for explaining information stored in a data buffer and first to third address buffers according to an exemplary embodiment of the present disclosure.
9A to 9F are diagrams for describing a resource mapping pattern of CCEs of a PDCCH.
10 is a diagram for describing a method of storing an address in a first address buffer according to an exemplary embodiment of the present disclosure.
11 is a flowchart illustrating a method of performing decoding of a wireless communication device according to an exemplary embodiment of the present disclosure.
12 is a block diagram specifically illustrating a controller of a wireless communication device according to an exemplary embodiment of the present disclosure.
13 is a block diagram illustrating an electronic device according to an exemplary embodiment of the present disclosure.

1 is a schematic block diagram of a wireless communication system 1 according to an exemplary embodiment of the present disclosure, FIG. 2 is a diagram showing a basic structure of a time-frequency domain in a wireless communication system, and FIG. 3 is wireless communication A diagram showing a PDCCH in a system, FIG. 4 is a diagram showing a resource mapping method of a PDCCH in a wireless communication system, and FIG. 5 is a diagram illustrating a search space of the PDCCH in the wireless communication system and a blind decoding method therefor. .

The wireless communication system 1 is, for example, a Long Term Evolution (LTE) system, a 5G system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Wireless Local Area Network (WLAN) system, or It can be any other wireless communication system. Hereinafter, the wireless communication system 1 will be described with reference mainly to the 5G system, but it will be understood that the exemplary embodiments of the present disclosure are not limited thereto.

Referring to FIG. 1, the wireless communication system 1 may include a wireless communication device 100 and a base station 20, and the wireless communication device 100 and the base station 20 may include a downlink channel 2 ) And an uplink (4) channel. The wireless communication device 100 may include a plurality of antennas 110_1-110_n, an RF integrated circuit 120, a modem 130, and a buffer 140.

The wireless communication device 100 may refer to various devices that can communicate with the base station 20 to transmit and receive data signals and/or control information. For example, the wireless communication device 100 may be variously referred to as a user equipment (UE), a mobile station (MS), a mobile terminal (MT), a user terminal (UT), a subscriber station (SS), or a mobile device. have. The base station 20 may refer to a fixed station communicating with the wireless communication device 100 and/or other base stations. The base station 20 may be referred to as a Node B, an evolved-Node B (eNB), a Base Transceiver System (BTS), and an access point (AP).

The wireless communication network between the wireless communication device 100 and the base station 20 can support multiple users communicating by sharing available network resources. For example, in a wireless communication network, code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), orthogonal frequency division multiple access (OFDMA), and single carrier frequency division multiple (SC-FDMA) Information can be delivered in various ways, such as access). Hereinafter, the wireless communication between the wireless communication device 100 and the base station 20 is mainly described that 5G communication technology is applied, but this is only exemplary, and thus, implementation of the present disclosure is applied to next-generation communication technologies other than 5G communication technology. It is clear that examples can be applied.

The RF integrated circuit 120 may receive a downlink signal including control information and/or data signals from the base station 20 through a plurality of antennas 110_1-110_n. The RF integrated circuit 20 may include a low noise amplifier for amplifying the downlink signal and a mixer for downconverting the frequency of the downlink signal. The RF integrated circuit 20 may down-convert the downlink signal in the RF band to the base band and provide it to the controller 130.

The controller 130 according to an embodiment may include a data management circuit 131 and a decoder 132. The data management circuit 131 may manage data necessary for decoding a Physical Downlink Control Channel (PDCCH) received from the base station 20, and the data management circuit 131 may include a plurality of buffers ( 131a, 131b). Hereinafter, the operation of the data management circuit 131 stores (or buffers) data necessary for decoding for the PDCCH in buffers, and provides appropriate data to the decoder 132 according to the decoding operation of the decoder 132 It may include a series of actions.

In the following, FIGS. 2 to 5 are preferentially described to help understanding the operation of the data management circuit 131. However, FIGS. 2 to 5 are only exemplary examples of the wireless communication system 1, and it will be understood that the present invention is not limited thereto.

Referring to FIG. 2, the horizontal axis may represent the time domain, and the vertical axis may represent the frequency domain. The minimum transmission unit in the time domain is an Orthogonal Frequency Division Multiplexing (OFDM) symbol, and N _symb (202) OFDM symbols can be aggregated to form one slot 206, and two slots are aggregated to form one subframe ( 205). For example, the length of the slot 206 may be 0.5 ms, and the length of the subframe may be 1.0 ms. Also, the radio frame 214 may be a time domain unit composed of 10 subframes 205.

The minimum transmission unit in the frequency domain is a subcarrier, and the bandwidth of the entire system transmission bandwidth may consist of a total of N _BW 204 subcarriers. In the time-frequency domain, a basic unit of a resource is a resource element 212 (resource element, RE), and may be represented by an OFDM symbol index and a subcarrier index. The resource block (208, Resource Block, RB) may be defined as N _symb (202) consecutive OFDM symbols in the time domain and N _RB (210) consecutive subcarriers in the frequency domain. Therefore, one RB 208 may be composed of (N _symb * N _RB ) REs 212. An RB pair may be composed of (N _symb * 2N _RB ) REs 212 in a _contiguous unit of two RBs on a time axis. Meanwhile, PDCCH may be transmitted from a base station in a wireless communication system to a wireless communication device through a resource in the time-frequency domain as shown in FIG. 2, and DCI (Downlink Control Information) may be transmitted through the PDCCH. The DCI may include information on downlink scheduling assignment including physical downlink shared channel (PDSCH) resource designation, transmission format, HARQ information, and control information related to spatial multiplexing.

Referring to FIG. 3, the PDCCH 302 may be transmitted after being multiplexed with the PDSCH 303. The base station can appropriately allocate the resources of the PDCCH 302 and the PDSCH 303 through scheduling, thereby effectively supporting coexistence with data transmission for a wireless communication device. The plurality of PDCCHs 302 may constitute one PDCCH set 306, and the allocation of the PDCCH set 306 may be performed in units of RB pairs. The location information for the PDCCH set 306 is terminal-specific and can be signaled through RRC (Remote Radio Control). Up to two PDCCH sets 306 may be set for each wireless communication device, and one PDCCH set 306 may be set by multiplexing to different terminals simultaneously. Meanwhile, in the PDCCH 302, a Demodulation Reference Signal (DMRS) 305 may be used as a reference signal for decoding.

Referring to FIG. 4, one RB pair is illustrated as an example, and one RB may include 16 REGs 401. REs included in one RB pair may be mapped to a REG 401 index corresponding to {0, 1, 2, ?, 15}. At this time, the REs to which the DMRS 403 is mapped are excluded from the numbering.

A set of REs corresponding to each index may constitute one REG 401. For example, there are 9 REs 407 mapped to index 0 in the RB pair illustrated in FIG. 4, and these 9 REs may constitute REG0 404. That is, REs numbered by each index x (x={0, 1, 2, ?, 15}) may constitute REGx, respectively. In describing embodiments according to the present disclosure, for convenience, it is assumed that a logical mapping scheme such as 405 of FIG. 4 is performed with respect to REG 301 existing in one RB pair.

The resource allocation of the PDCCH is based on a Control Channel Element (CCE) 402, and one CCE 402 may consist of 4 or 8 REGs 401. However, the number of REGs 401 per CCE 402 may vary according to CP (Cyclic Prefix) length and subframe configuration information. 4, an example in which four REGs 401 constitute one CCE 402 is illustrated. More specifically, REG0, REG4, REG8, REG12 are CCE0, REG1, REG5, REG9, REG13 are CCE1, REG2, REG6, REG10, REG14 are CCE2 according to the logical mapping scheme as 305 of FIG. REG3, REG7, REG11, and REG15 may be mapped to CCE3, respectively.

Accordingly, when the four REGs 401 constitute one CCE 402, one RB pair may include a total of four CCEs 402. In describing embodiments according to the present disclosure, a logical mapping scheme such as 406 of FIG. 4 is assumed for the CCE 402 existing in one RB pair for convenience. The PDCCH transmission method may be divided into localized or distributed transmission according to a mapping method between CCE 402 and REG 401.

Next, when describing the search space in the PDCCH, the PDCCH can support a terminal-specific search space, and the search space is a wireless communication device on a given aggregation level (hereinafter referred to as CCE aggregation level). It is a set of candidate PDCCHs composed of CCEs to attempt decoding, and the PDCCH may have an aggregation level of 1, 2, 4, 8, 16, 32, which is CP length, subframe setting, PDCCH format, localized/distributed It can be variously determined by system parameters such as the transmission method and the total number of CCEs. Since there are various aggregation levels that make a plurality of CCEs into one bundle, the wireless communication device may have a plurality of search spaces according to the aggregation level. That is, the number of candidate PDCCHs that the wireless communication device needs to perform decoding according to the aggregation level in the PDCCH may vary.

5 shows an example in which one PDCCH set 501 is composed of four RB pairs. Referring to FIG. 5, one RB pair 502 includes four CCEs 510, and for convenience in describing embodiments according to the present disclosure, a logical mapping method 406 for the CCE of FIG. 4 Presupposes

5 shows an example of a search space for aggregation level-1 (503), aggregation level-2 (504), and aggregation level-4 (505). At aggregation level-1 503, one candidate PDCCH 506 can be mapped to one CCE 510, and at aggregation level-2 504, one candidate PDCCH 507 is two CCEs 510. In the aggregation level-4 (505), one candidate PDCCH (508) may be mapped to four CCEs (510). According to this, there are four candidate PDCCHs 506 at aggregation level-1 503 (CCE0, CCE4, CCE8, CCE12), and four candidate PDCCHs 507 at aggregation level-2 504 ({ CCE0, CCE1}, {CCE4, CCE5}, {CCE8, CCE9}, {CCE12, CCE13}) exist, and two aggregation PDCCHs 508 at aggregation level-4 505 ({CCE0, CCE1, CCE2) , CCE3}, {CCE8, CCE9, CCE10, CCE11}) may be present.

Returning to FIG. 1, in order to obtain the DCI included in the PDCCH, the decoder 132 may perform blind decoding on candidate PDCCHs determined according to the aggregation level. For example, when there are candidate PDCCHs 506, 507, and 508 as shown in FIG. 5, the decoder 132 performs a decoding operation on four candidate PDCCHs 506 at aggregation level-1 503. And performs decoding operations on four candidate PDCCHs 507 at aggregation level-2 504, and performs decoding operations on two candidate PDCCHs 508 at aggregation level-4 505. can do. For the blind decoding operation of the decoder 132, the candidate PDCCHs 506, 507, and 508 must be stored in a buffer (or memory) in the wireless communication device 100. Conventionally, when performing the blind decoding operation of the decoder 132, although some data (CCE0, CCE1, CCE4, CCE8, CCE9, CCE12) are used at least twice, candidate PDCCHs ( 506, 507, 508). That is, CCE0, CCE4, CCE8, and CCE12 are stored as candidate PDCCHs 506 of aggregation level-1 504 in the first area of the buffer, and candidates of aggregation level-2 505 are stored in the second area of the buffer. {CCE0, CCE1}, {CCE4, CCE5}, {CCE8, CCE9}, {CCE12, CCE13} are stored as PDCCHs 507, and a candidate PDCCH 508 of aggregation level-4 506 is stored in the third area of the buffer. ), {CCE0, CCE1, CCE2, CCE3}, {CCE8, CCE9, CCE10, CCE11} were stored. For this reason, CCE0, CCE1, CCE4, CCE8, CCE9, and CCE12 are duplicated in the buffer, causing an inefficient use of the buffer.

In order to overcome the above, the data management circuit 131 according to an embodiment of the present disclosure may include a data buffer 131a and a plurality of address buffers 131b and prevent redundant storage of data. To this end, data necessary for decoding may be stored in the data buffer 131a, and the address of the data buffer 131a in which the data is stored may be stored in the address buffers 130b. The data management circuit 131 reads data required when the decoder 132 performs blind decoding from the data buffer 131a by referring to the address stored in the address buffers 131b and provides it to the decoder 132. .

Specifically, the data management circuit 131 may store a plurality of LLRs (Log Likelihood Rations) generated by demodulating the PDCCH from the controller 130 in the data buffer 131a, and a Control Channel Element (CCE) included in the PDCCH. The address of the data buffer 131a in which LLRs corresponding to each of the plurality of candidate PDCCHs according to their aggregation level are stored may be stored in the plurality of address buffers 131b.

Referring to FIG. 5 for ease of understanding, the data management circuit 131 generates a plurality of LLRs generated by demodulating CCE0 to CCE15 included in the PDCCH in the data buffer 131a (or in a predetermined order). Can be saved as In addition, the data management circuit 131 stores the LLRs corresponding to the candidate PDCCH 506 of the aggregation level-1 503 in the first address buffer among the address buffers 132b, CCE0, CCE4, CCE8, and CCE12. Addresses of (131a) can be stored, and the candidate PDCCH (507) of aggregation level-2 (504) in the second address buffer among the address buffers (132b) {CCE0, CCE1}, {CCE4, CCE5}, {CCE8 , CCE9}, LLRs corresponding to {CCE12, CCE13} may store addresses of the data buffer 131a stored therein, and a candidate PDCCH of aggregation level-4 505 in the third address buffer of the address buffers 132b ( 508), LLRs corresponding to {CCE0, CCE1, CCE2, CCE3}, {CCE8, CCE9, CCE10, and CCE11} may store addresses of the data buffer 131a stored therein. According to embodiments, the operation of storing the LLRs in the data buffer and the address of storing the LLRs in the address buffers may be performed in parallel. According to embodiments, the data buffer 131a and the address buffers 131b may be physically divided or virtually divided within one buffer configuration. In addition, the number of address buffers 131b may be configured to match the number of CCE aggregation level supportable. For example, when it is possible to support three aggregation levels 504, 505, 506 as shown in FIG. 5, the data management circuit 131 is configured to include three address buffers (first to third address buffers). Can be. That is, the first address buffer is allocated to store the address of the data buffer 131a in which LLRs of the candidate PDCCH 506 of the aggregation level-1 503 are stored, and the second address buffer is of the aggregation level-2 504. The LLRs of the candidate PDCCH 507 are allocated to store the address of the stored data buffer 131a, and the third address buffer is of the data buffer 131a where the LLRs of the candidate PDCCH 508 of the aggregation level-4 505 are stored. It can be assigned to store an address. However, this is only an exemplary embodiment, and when more aggregation level support is possible, the data management circuit 131 may be configured to include more address buffers.

The data management circuit 131 according to an embodiment may at least one address buffer of the address of the target LLR among the address buffers 131b based on the CCE index corresponding to the target LLR stored in the data buffer 131a. Can be stored in. For example, the data management circuit 131 refers to the address of the data buffer 131a in which LLRs corresponding to CCE0 in FIG. 5 are stored by referring to the index of CCE0, and the first address buffer, the second address buffer, and the third Each can be stored in the address buffer. According to embodiments, the CCE index may be generated together with LLRs corresponding to the CCE index during demodulation operation for the PDCCH. That is, when performing a demodulation operation on CCE0 of FIG. 5, a CCE index indicating that CCE0 is generated together with LLRs corresponding to CCE0 may be generated.

The data management circuit 131 according to an embodiment may provide necessary data when the decoder 132 performs blind decoding on candidate PDCCHs using the data buffer 131a and the address buffers 131b. . For example, when the decoder 132 performs decoding on candidate PDCCHs 506 of aggregation level-1 503, the data management circuit 131 is a candidate PDCCH 506 from the first address buffer. LLRs corresponding to CCE0, CCE4, CCE8, and CCE12 are stored (or read) and LLRs corresponding to CCE0, CCE4, CCE8, and CCE12 are obtained (or read) from the data buffer 131a using the obtained addresses. ) To the decoder 132.

The data management circuit 131 according to an embodiment considers LLRs continuously stored in the data buffer 131a according to the resource mapping pattern of CCEs of the PDCCH, and addresses only the representative address of the LLR group in which continuity is guaranteed. ). Details of this will be described later in FIG. 10.

The data management circuit 131 may be implemented in hardware such as a specific application integrated circuit, a field-programmable gate array, a combination of logic gates, a system on chip, and various types of processing circuits (or control circuits). Can be. Furthermore, the data management circuit 131 may be implemented with software, such as instructions or codes, that can be executed by a processor, such as the controller 130. Further, as an example embodiment, the data buffer 131a and the address buffers 131b included in the data management circuit 131 are implemented with volatile memory such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRMA). Or, it may be implemented as a non-volatile memory such as phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), resistive random access memory (ReRAM), and ferroelectrice random access memory (FeRAM).

Fig. 6 is a flow chart showing a method for buffering data necessary for decoding a wireless communication device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 6, the wireless communication device may receive a PDCCH including CCEs (S100), and generate a CCE index and corresponding LLRs from the received PDCCH (S110). Thereafter, the data management circuit may store the LLRs in the data buffer (S120), and store the address of the data buffer in which the LLRs are stored in at least one address buffer selected from the address buffers based on the CCE index (S130). According to embodiments, steps S120 and S130 may be performed in parallel.

7 is a block diagram specifically illustrating a controller 600 of a wireless communication device according to an exemplary embodiment of the present disclosure.

The wireless communication device 600 may include a demodulator 610 and a data management circuit 620. The demodulator 610 may generate LLRs (LLRs) and a CCE index (CCE_IDX) corresponding to each LLR by receiving a PDCCH converted from a radio frequency (RF) band to a baseband and performing a demodulation operation. That is, the CCE index (CCE_IDX) may be information indicating the CCE corresponding to the currently output LLRs (LLRs). The data management circuit 620 may include a data buffer circuit (DBUF_C), a first multiplexer 623, a plurality of address buffer circuits (ABUF_C1 to ABUF_Cn), and a first control logic 626. The data buffer circuit DBUF_C may include a second control logic 624 and a data buffer 625. The address buffer circuit ABUF_C1 may include a third control logic 624 and an address buffer 625, and the configuration of the address buffer circuit ABUF_C1 may be applied to other address buffer circuits ABUF_C2 to ABUF_Cn. The number of address buffer circuits (ABUF_C1 to ABUF_Cn) may depend on the number of possible support levels of the aggregation level for CCEs included in the PDCCH. For example, in a wireless communication system capable of supporting up to 32 CCE aggregation levels, the data management circuit 620 may be implemented to include 32 address buffer circuits (ABUF_C1 to ABUF_Cn).

When the operation of the data buffer circuit 622 is first described, the second control logic 621 may sequentially store LLRs LLLs received from the demodulator 610 in the data buffer 622. According to embodiments, the second control logic 621 may classify LLRs LLLs for each CCE with reference to the CCE index CCE_IDX and store the data in the data buffer 622. When the LLRs LLLs are stored in the data buffer circuit 622, the first control logic 626 refers to the CCE index CCE_IDX to provide the first multiplexer 623 with the first control signal MUX_CS1. At least one of the address buffer circuits ABUF_C1 to ABUF_Cn may be connected to the data buffer circuit DBUF_C.

For example, when the address buffer circuit ABUF_C1 and the data buffer circuit DBUF_C are connected through the first multiplexer 623, the third control logic 624 is a candidate for the CCE aggregation level assigned to the address buffer circuit ABUF_C1. The second control logic 621 may request an address in which LLRs corresponding to CCEs of PDCCHs are stored. In response, the second control logic 621 may provide the address where the LLRs are stored to the third control logic 624, and the third control logic 624 may store the received address in the address buffer 625. .

In one embodiment, the second control logic 621 of the data buffer circuit DBUF_C stores the LLRs LLLs generated from the demodulator 610 in the data buffer 622, and the address where each LLRs LLLs is stored May be provided to at least one of the address buffer circuits ABUF_C1 to ABUF_Cn based on the CCE index (CCE_IDX) corresponding to each LLR. As a result, the address buffer circuits ABUF_C1 to ABUF_Cn may store addresses in which LLRs corresponding to CCEs of candidate PDCCHs of the CCE aggregation level allocated to each of them are stored.

8 is a diagram for explaining information stored in the data buffer 622 and the first to third address buffers 625a to 625c according to an exemplary embodiment of the present disclosure. 8 is described with reference to FIGS. 5 and 7 to facilitate understanding.

5, on the premise of receiving a PDCCH to which three CCE aggregation levels 503, 504, and 505 are applied, three address buffer circuits ABUF_C1~ among the address buffer circuits ABUF_C1 to ABUF_Cn of FIG. ABUF_C3) can be used.

Referring to FIG. 8, all LLRs generated by demodulating the PDCCH may be stored in the data buffer 622, and CCE0 to CCE15 represented in the data buffer 622 of FIG. 8 are LLRs corresponding to CCE0 to CCE15, respectively. It shows the saved configuration. According to embodiments, LLRs may be classified and stored for each CCE in the data buffer 622, or LLRs may be stored without separate classification. The second control logic 621 may manage data related to the address of the data buffer 622 in which LLRs corresponding to the CCE are stored, and provide the data in response to requests from the address buffer circuits ABUF_C1 to ABUF_Cn. can do. In another embodiment, the second control logic 621 may actively provide the data to at least one address buffer circuit connected through the first multiplexer 623.

The first address buffer 625a is allocated to store addresses regarding candidate PDCCHs 506 of aggregation level-1 503, and the second address buffer 625b is a candidate PDCCH of aggregation level-2 504 ( 507), and the third address buffer 625c may be allocated to store addresses regarding candidate PDCCHs 508 of aggregation level-4 505. Accordingly, addresses (CCE0_Addr, CCE4_Addr, CCE8_Addr, CCE12_Addr) of CCE0, CCE4, CCE8, and CCE12, which are candidate PDCCHs 506 of aggregation level-1 503, may be stored in the first address buffer 625a, and the first The address PCCHs 507 of aggregation level-2 504 are {CCE0, CCE1}, {CCE4}, {CCE8}, {CCE8, CCE9}, {CCE12, CCE13} addresses (CCE0_Addr,) in the 2 address buffer 625b. CCE1_Addr, CCE4_Addr, CCE5_Addr, CCE8_Addr, CCE9_Addr, CCE12_Addr, CCE13_Addr) may be stored, and the third address buffer 625c includes {CCE0, CCE1, CCE2, CCE3, candidate PDCCHs 508 of aggregation level-4 505. }, {CCE8, CCE9, CCE10, CCE11} addresses (CCE0_Addr, CCE1_Addr, CCE2_Addr, CCE3_Addr, CCE8_Addr, CCE9_Addr, CCE10_Addr, CCE11_Addr) may be stored.

Through the configuration of the address buffers 625a to 625c and the data buffer 622 as described above, it is possible to prevent redundant storage of LLRs, thereby effectively improving memory usage.

9A to 9F are diagrams for describing a resource mapping pattern of CCEs of a PDCCH, and FIG. 10 is a diagram for explaining a method of storing an address in a first address buffer 625a according to an exemplary embodiment of the present disclosure. to be. The REG bundle described below may be defined as a minimum unit including a plurality of REGs in which the same precoding is performed and interleaved.

9A, a first REG bundle REG_BDa may be applied as a resource mapping pattern of CCEs of a PDCCH, and the first REG bundle REG_BDa may include two REGs connected in a frequency axis.

Referring to FIG. 9B, a second REG bundle (REG_BDb) may be applied as a resource mapping pattern of CCEs of the PDCCH, and the second REG bundle (REG_BDb) may include six REGs connected in a frequency axis.

Referring to FIG. 9C, a third REG bundle REG_BDc may be applied as a resource mapping pattern of CCEs of the PDCCH, and the third REG bundle REG_BDc may include two REGs connected in a time axis.

Referring to FIG. 9D, a fourth REG bundle (REG_BDd) may be applied as a resource mapping pattern of CCEs of a PDCCH, and the fourth REG bundle (REG_BDd) may include six REGs connected in a frequency axis and a time axis. .

Referring to FIG. 9E, the fifth REG bundle REG_BDe may be applied as a resource mapping pattern of CCEs of the PDCCH, and the fifth REG bundle REG_BDe may include three REGs connected in a time axis.

Referring to FIG. 9F, a sixth REG bundle (REG_BDf) may be applied as a resource mapping pattern of CCEs of the PDCCH, and the sixth REG bundle (REG_BDf) may include six REGs connected in a frequency axis and a time axis. .

9A to 9F, REG bundles (REG_BDa to REG_BDf) are determined to configure a resource mapping pattern of the PDCCH, and resources are mapped to the time axis and de-mapped to the frequency axis for PDCCH to perform decoding. Even considering the shape of the REG bundles (REG_BDa to REG_BDf), continuous LLR output in one REG unit can be guaranteed as a result of demodulation operation for the PDCCH. For example, when one REG includes 12 resource elements, continuity of 24-bit LLRs corresponding to any one CCE may be guaranteed in a demodulation operation for a PDCCH. LLRs in which continuity is guaranteed are sequentially input to the decoder 132 (FIG. 1) and decoding may be performed. In FIG. 10, a method of storing an address in an address buffer based on LLR continuity as described above is described.

Referring to FIG. 10, LLRs corresponding to CCE0 may be divided into m LLR groups (CCE0_0 to CCE0_m-1) in which continuity is guaranteed and stored in the data buffer 622. For example, the first LLR group CCE0_0 may include LLRs that are generated by demodulation from the demodulator 610 (FIG. 7) to ensure continuity, and between Addr_n0 addresses and Addr_n0+k addresses of the data buffer 622. Can be stored continuously. In addition, the m-1 LLR group (CCE0_m-1) may include LLRs to which continuity generated by demodulation from the demodulator 610 (FIG. 7) is guaranteed. From Addr_nm-1 address of the data buffer 622, Addr_nm- Can be stored consecutively between 1+k addresses.

In the first address buffer 625a, the addresses CCE0_Addr corresponding to CCE0 may include only the representative addresses of addresses in which LLR groups CCE0_0 to CCE0_m-1 are respectively stored. According to one embodiment, the representative address may be the start address or the last address of the LLR groups CCE0_0 to CCE0_m-1. For example, start addresses (Addr_n0 to Addr_nm-1) of LLR groups CCE0_0 to CCE0_m-1 may be stored in the first address buffer 625a. In this way, the addresses (CCE4_Addr, CCE8_Addr, CCE12_Addr) of the LLRs corresponding to CCE4, CCE8, and CCE12 may be implemented in the first address buffer 625a to include only the representative address for each LLR group. According to an embodiment, the size GS of the LLR group CCE0_0 may be variable according to the resource mapping pattern of CCEs of the PDCCH.

As described above, the first address buffer 625a is stored in the first address buffer 625a by storing only the representative address of the LLR group, rather than storing all LLR addresses of the LLR group in which continuity is guaranteed by considering the resource mapping pattern of CCEs of the PDCCH. It is clear that the memory usage of) can be improved more efficiently, and this method can be applied to other address buffers.

11 is a flowchart illustrating a method of performing decoding of a wireless communication device according to an exemplary embodiment of the present disclosure. Hereinafter, an operation when decoding one target candidate PDCCH will be described.

Referring to FIG. 11, the data management circuit may acquire LLRs of the target candidate PDCCH from the data buffer by using an address buffer corresponding to the CCE aggregation level of the target candidate PDCCH among the address buffers (S200 ). The data management circuit may provide the obtained LLRs to the decoder, and the decoder may decode the target candidate PDCCH using the obtained LLRs (S210). The above operation can be repeated until the decoder completes decoding for all candidate PDCCHs.

12 is a block diagram specifically illustrating a controller 600 of a wireless communication device according to an exemplary embodiment of the present disclosure. Hereinafter, the content overlapping with FIG. 7 will be omitted.

Referring to FIG. 12, the wireless communication device 600 may include a data management circuit 620 and a decoder 630. The decoder 630 may receive data (eg, LLRs) for candidate PDCCHs required for decoding from the data management circuit 620 and perform blind decoding. To this end, the data management circuit 620 may further include a second multiplexer 627 compared to FIG. 7, and the first control logic 626 may provide data for a target candidate PDCCH required by the decoder 630. It can be controlled to provide to the decoder 630. Specifically, when performing blind decoding of the decoder 630, the first control logic 626 may provide a first multiplexer 623 to provide data for at least one candidate PDCCH of a target aggregation level to be decoded at an appropriate timing. ), the second multiplexer 627 and the address buffer circuits ABUF_C1 to ABUF_C2.

For example, the first control logic 626 provides a buffer control signal BUF_CS to the address buffer circuit ABUF_C1 to provide data for candidate PDCCHs of a predetermined aggregation level stored in the address buffer circuit ABUF_C1. To enable and provide the first control signal MUX_CS1 to the first multiplexer 623 to connect the address buffer circuit ABUF_C1 and the data buffer circuit DBUF_C. In addition, the first control logic 626 may provide the second control signal MUX_CS2 to the second multiplexer 627 to connect the address buffer circuit ABUF_C1 and the decoder 630. At this time, the third control logic 624 may request LLRs from the data buffer circuit 622 using the address of data for candidate PDCCHs stored in the address buffer 625, and the second control logic 621 may The LLRs read from the data buffer 622 may be provided to the address buffer circuit ABUF_C1 with reference to the data address. In addition, when only the representative address of the LLR group is stored in the address buffer 625 as shown in FIG. 10, the second control logic 621 reads the LLRs from the data buffer 622 in consideration of the size (GS) of the LLR group. Can be. The address buffer circuit ABUF_C1 may provide LLRs received from the data buffer circuit DBUF_C to the decoder 630 as data for candidate PDCCHs. However, the configuration of FIG. 12 is only an exemplary embodiment, and is not limited thereto. The data buffer circuit DBUF_C may provide data for the target candidate PDCCH to the decoder 630 directly.

As such, the data management circuit 620 uses the data buffer circuit DBUF_C and the plurality of address buffer circuits ABUF_C1 to ABUF_Cn to transmit data for candidate PDCCHs for blind decoding to the decoder 630 at an appropriate timing. Can provide.

13 is a block diagram illustrating an electronic device 1000 according to an exemplary embodiment of the present disclosure.

Referring to FIG. 13, the electronic device 1000 includes a memory 1010, a processor unit 1020, an input/output control unit 1040, a display unit 1050, an input device 1060, and a communication processing unit 1090. It can contain. Here, a plurality of memory 1010 may be present. Looking at each component is as follows.

The memory 1010 may include a program storage unit 1011 for storing a program for controlling the operation of the electronic device, and a data storage unit 1012 for storing data generated during program execution. The data storage unit 1012 may store data necessary for the operation of the application program 1013 and the data management program 1014. The program storage unit 1011 may include an application program 1013 and a data management program 1014. Here, the program included in the program storage unit 1011 may be expressed as an instruction set as a set of instructions.

The application program 1013 includes an application program running on the electronic device. That is, the application program 1013 includes instructions of an application driven by the processor 1022. The data management program 1014 may control data storage and data management operations required for decoding according to embodiments of the present disclosure. That is, through the data management program 1014, the processor 1422 stores data necessary for decoding (eg, LLRs generated by demodulating the PDCCH) in a data buffer (not shown), and multiple addresses of the data Can be individually stored in the address buffers (not shown) according to the CCE aggregation level, and can perform blind decoding operations on candidate PDCCHs using a data buffer (not shown) and address buffers (not shown). . Memory interface 1021 may control access to memory 1010 of components such as processor 1022 or peripheral interface 1023.

The peripheral device interface 1023 may control the connection between the input/output peripheral device of the base station and the processor 1022 and the memory interface 1021. The processor 1022 controls the base station to provide the corresponding service using at least one software program. At this time, the processor 1022 may execute at least one program stored in the memory 1010 to provide a service corresponding to the corresponding program.

The input/output control unit 1040 may provide an interface between an input/output device such as the display unit 1050 and the input device 1060 and a peripheral device interface 1023. The display unit 1050 displays status information, input text, moving picture, and still picture. For example, the display unit 1050 may display application program information driven by the processor 1022.

The input device 1060 may provide input data generated by the selection of the electronic device to the processor unit 1020 through the input/output control unit 1040. In this case, the input device 1060 may include a keypad including at least one hardware button and a touch pad for sensing touch information. For example, the input device 1060 may provide touch information such as touch, touch movement, and touch release detected through the touch pad to the processor 1022 through the input/output control unit 1040. The electronic device 1000 may include a communication processing unit 1090 that performs a communication function for voice communication and data communication.

As described above, exemplary embodiments have been disclosed in the drawings and the specification. Although embodiments have been described using specific terminology in this specification, they are only used for the purpose of describing the technical spirit of the present disclosure, and are not used to limit the scope of the present disclosure as defined in the claims or the claims. . Therefore, those of ordinary skill in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

Claims (10)

Receiving a physical downlink control channel (PDCCH) including a plurality of control channel elements (CCEs);
Storing a plurality of LLRs generated by demodulating the PDCCH in a data buffer;
Storing the address of the data buffer in which the LLRs corresponding to each of the plurality of candidate PDCCHs according to the aggregation level for the CCEs are stored in a plurality of address buffers; And
And performing blind decoding on the candidate PDCCHs using the data buffer and the address buffers. According to claim 1,
The step of storing in the address buffers,
And storing the address of the target LLR in at least one of the address buffers among the address buffers based on a CCE index corresponding to the target LLR. According to claim 1,
The step of storing in the data buffer and the step of storing in the address buffers are performed in parallel. According to claim 1,
When the supported number of aggregation levels is N (where N is an integer of 1 or more), the number of address buffers is N, and the address buffers are LLRs of at least one candidate PDCCH of the aggregation level corresponding to each. A method of operating a wireless communication device, characterized in that it is configured to store an address. According to claim 1,
The address buffers are configured to store a representative address of an LLR group including LLRs continuously stored in the data buffer according to a resource mapping pattern of CCEs of the PDCCH. According to claim 1,
The step of performing blind decoding on the candidate PDCCHs is:
Obtaining LLRs of the target candidate PDCCH from the data buffer by referring to an address buffer corresponding to the aggregation level of the target candidate PDCCH among the address buffers; And
And decoding the target candidate PDCCH using the obtained LLRs. An RF integrated circuit configured to receive a PDCCH including a plurality of CCEs from a base station; And
And a controller configured to perform blind decoding of each of a plurality of candidate PDCCHs according to the aggregation level for the CCEs,
The controller,
The LLRs generated from the PDCCH are stored in a data buffer, and the address of the data buffer in which the LLRs are stored is stored in at least one address buffer selected from among a plurality of address buffers based on a CCE index corresponding to the LLRs. A wireless communication device further comprising a data management circuit. The method of claim 7,
Each of the address buffers is configured to store addresses of LLRs corresponding to CCEs included in at least one candidate PDCCH corresponding to a different level of aggregation. The method of claim 7,
The data management circuit,
And a representative address of an LLR group including LLRs continuously stored in the data buffer according to a resource mapping pattern of CCEs of the PDCCH, in the at least one selected address buffer. The method of claim 7,
The controller,
And performing blind decoding on the candidate PDCCHs using the data buffer and the address buffers.

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