TWI830824B - Method of operating wireless communication device - Google Patents

Abstract

Systems and methods are described for a method of operating a wireless communication device includes receiving a physical downlink control channel (PDCCH) including a plurality of control channel elements (CCE), storing a plurality of LLRs generated by demodulating the PDCCH in a data buffer, storing at least one address of the LLRs, corresponding to a plurality of PDCCH candidates in accordance with an aggregation level for the CCEs, in a plurality of address buffers, and performing blind decoding on the PDCCH candidates by using the data buffer and the address buffers.

Description

How to operate wireless communication device [Cross-reference to related applications]

This application claims Korean Patent Application No. 10-2018-0150088, which was filed with the Korean Intellectual Property Office on November 28, 2018, and Korean Patent Application No. 10-2018-0150088, which was filed with the Korean Intellectual Property Office on April 19, 2019. No. 10-2019-0046085, the disclosure contents of the Korean patent application are all incorporated into this application for reference.

The inventive concept relates to a wireless communication device, and more particularly, to a method of managing data required for decoding.

Wireless communications (the transfer of information or power between two or more devices) have become an essential tool for individuals and businesses. As file sizes and the number of devices increase, the demand for high-speed data services in wireless communication devices increases.

Fifth Generation (5G) or new radio (NR) communication systems aim to provide ultra-high speeds at gigabit per second (Gbps) using ultra-wide bandwidth greater than 100 megahertz (MHz) Information Services. In contrast, traditional long-term evolution (LTE) and advanced long-term evolution Advanced long term evolution (LTE-A) technology cannot meet these needs. Therefore, a method of transmitting signals using a wide frequency band is needed to meet current needs. However, it may be difficult to secure frequencies for ultra-wideband communications. In some cases, millimeter wave frequency bands, such as the 28 gigahertz band or the 60 gigahertz band, may be used to achieve the desired transmission rate.

In the 5G system, the wireless communication device can decode the physical downlink control channel (PDCCH) received from the base station to perform communication. However, there is a need for a method of efficiently managing data required for decoding the PDCCH using buffer configuration in a wireless communication device for a 5G communication system.

The inventive concept provides a wireless communication device and an operating method thereof that can improve memory usage efficiency by preventing data required for decoding a physical downlink control channel (PDCCH) from being repeatedly stored.

According to aspects of the inventive concept, a method of operating a wireless communication device is provided. The method includes: receiving a physical downlink control channel including a plurality of control channel elements (CCEs); and storing a plurality of log-likelihood ratios (LLRs) in a data buffer, wherein the log-likelihood ratios are calculated by Demodulating the physical downlink control channel results in and corresponds to a plurality of physical downlink control channel candidates, each of the physical downlink control channel candidates having a number equal to the number of control channel elements. corresponding aggregation level; storing at least one address of the log-likelihood ratio in a plurality of address buffers; and using the data buffer The processor and the address buffer perform blind decoding on the physical downlink control channel candidate.

According to aspects of the inventive concept, a method of operating a wireless communication device for managing data required to perform blind decoding is provided. The method includes: generating a control channel element index and a log-likelihood ratio corresponding to the control channel element index from a physical downlink control channel including a plurality of control channel elements; and storing the log-likelihood ratio in a data buffer. and storing at least one address of the log-likelihood ratio in at least one address buffer selected from a plurality of address buffers based on the control channel element index.

According to an aspect of the inventive concept, a wireless communication device is provided, the wireless communication device includes: a radio frequency (RF) integrated circuit configured to receive a physical downlink control channel including a plurality of control channel elements from a base station; and a controller configured to blindly decode a plurality of physical downlink control channel candidates based on an aggregation level of the control channel element. The controller further includes a data management circuit configured to store a log-likelihood ratio generated by the physical downlink control channel in a data buffer, and based on the log-likelihood ratio corresponding to the The control channel element index stores at least one address of the log-likelihood ratio in at least one address buffer selected from a plurality of address buffers.

According to aspects of the concept of the present invention, a wireless communication method is provided. The method includes: receiving a physical downlink control channel; and storing physical downlink control channel data in a data buffer, wherein the physical downlink control channel The channel information corresponds to a plurality of physical downlink control channel candidates; the physical downlink The address of the downlink control channel data is stored in a plurality of address buffers, wherein each of the plurality of address buffers corresponds to one of the physical downlink control channel candidates; based on storage Blind decoding is performed on each of the physical downlink control channel candidates at an address of physical downlink control channel data in a corresponding address buffer of the plurality of address buffers.

1: Wireless communication system

2: Downlink channel

4: Uplink channel

20:Base station

100, 600: Wireless communication device

110_1~110_n:antenna

120: Radio frequency (RF) integrated circuits

130:Controller

131, 620: Data management circuit

131a: Data buffer/buffer

131b: Address buffer/buffer

132:Decoder

202: OFDM symbols

204:Subcarrier

205: Subframe

206:Slot

208: Resource Block (RB)

210:N _RB subcarrier

212: Resource Element (RE)

214:Wireless frame

302. PDCCH: Physical downlink control channel

303:PDSCH

305, 403: Demodulation reference signal (DMRS)

306, 501: PDCCH set

401, 407: Resource element group (REG)

402, 510: Control Channel Element (CCE)

404:REG0

405, 406: Logical mapping method

502:RB pair

503: Aggregation level-1/aggregation level

504: Aggregation level-2/aggregation level

505: Aggregation level-4/aggregation level

506, 507, 508: PDCCH candidates

610:Demodulator

621: Second control logic

622: Data buffer circuit

623:First multiplexer

624: Third control logic

625:Address buffer

625a: Address buffer/first address buffer

625b: Address buffer/second address buffer

625c: Address buffer/third address buffer

626: First control logic

627: Second multiplexer

630:Decoder

1000:Electronic devices

1010:Memory

1011: Program storage unit

1012:Data storage unit

1020: Processor unit

1021:Memory interface

1022: Processor

1023: Peripheral device interface

1040:Input and output controller

1050:Display unit

1060:Input device

1090: Communication processing unit

ABUF_C1~ABUF_Cn: address buffer circuit

Addr_n0: address/starting address

Address

BUF_CS: buffer control signal

{CCE0, CCE1}, {CCE4, CCE5}, {CCE8, CCE9}, {CCE12, CCE13}, {CCE0, CCE1, CCE2, CCE3}, {CCE8, CCE9, CCE10, CCE11}: CCE pair

CCE0~CCE15:CCE

CCE0_0:LLR group/first LLR group

CCE0_1~CCE0_m-1:LLR group

CCE_IDX:CCE index

DBUF_C: data buffer circuit

GS: magnitude

LLR: log likelihood ratio

MUX_CS1: first control signal

MUX_CS2: second control signal

REG: Resource element group

REG 401:REG0~REG15

REG_BDa: first REG bundle

REG_BDb: second REG bundle

REG_BDc: The third REG bundle

REG_BDd: The fourth REG bundle

REG_BDe: The fifth REG bundle

REG_BDf: The sixth REG bundle

S100, S110, S120, S130, S200, S210: Operation

The following detailed description, taken in conjunction with the accompanying drawings, will more clearly explain embodiments of the inventive concept.

FIG. 1 is a schematic block diagram of a wireless communication system according to an exemplary embodiment of the inventive concept.

2 is a view showing a basic structure of a time-frequency zone in a wireless communication system according to an exemplary embodiment of the present invention.

3 is a view illustrating a physical downlink control channel (PDCCH) in a wireless communication system according to an exemplary embodiment of the inventive concept.

4 is a view illustrating a resource mapping method of PDCCH in a wireless communication system according to an exemplary embodiment of the present concept.

5 is a view illustrating a search space of a PDCCH in a wireless communication system and a blind decoding method for the search space according to an exemplary embodiment of the present inventive concept.

FIG. 6 is a flowchart illustrating a method of buffering data required for decoding by a wireless communication device according to an exemplary embodiment of the present invention.

FIG. 7 is a detailed illustration of a wireless communication device according to an exemplary embodiment of the present invention. Block diagram of the configured controller.

8 is a view illustrating information stored in a data buffer and first to third address buffers according to an exemplary embodiment of the present invention.

9A to 9F are views showing a resource mapping pattern of a control channel element (CCE) of the PDCCH.

FIG. 10 is a view illustrating a method of storing an address in a first address buffer according to an exemplary embodiment of the present concept.

FIG. 11 is a flowchart illustrating a method of performing decoding of a wireless communication device according to an exemplary embodiment of the present inventive concept.

12 is a block diagram illustrating in detail a controller of a wireless communication device according to an exemplary embodiment of the present invention.

FIG. 13 is a block diagram illustrating an electronic device according to an exemplary embodiment of the inventive concept.

The present disclosure sets forth systems and methods for efficiently managing data used in decoding the physical downlink control channel (PDCCH). Exemplary embodiments may include wireless communication devices and operating methods capable of improving memory usage efficiency by preventing data required to decode the PDCCH from being repeatedly stored.

FIG. 1 is a schematic block diagram of a wireless communication system 1 according to an exemplary embodiment of the inventive concept. FIG. 2 is a view showing the basic structure of a time-frequency zone in a wireless communication system. FIG. 3 is a view showing a physical downlink control channel (PDCCH) in a wireless communication system. Figure 4 shows a PDCCH in a wireless communication system A view of the resource mapping method. FIG. 5 is a view illustrating a search space of PDCCH in a wireless communication system and a blind decoding method for the search space.

The wireless communication system 1 may be, for example, a long-term evolution (LTE) system, a 5G system, a code division multiple access (CDMA) system, a global system for mobile communications (GSM) system, or a wireless local area network (wireless local area network, WLAN) system or another arbitrary wireless communication system. In the following, the wireless communication system 1 will refer to the 5G system. However, exemplary embodiments of the inventive concept are not limited thereto.

Referring to FIG. 1 , a wireless communication system 1 may include a wireless communication device 100 and a base station 20 . The wireless communication device 100 and the base station 20 can communicate through the downlink channel 2 and the uplink channel 4. The wireless communication device 100 may include a plurality of antennas 110_1 to 110_n, a radio frequency (RF) integrated circuit 120, a controller 130 and a buffer 140.

The wireless communication device 100 may refer to different devices that communicate with the base station 20 and may transmit and receive data signals or control information. For example, the wireless communication device 100 may be called user equipment (UE), mobile station (MS), mobile terminal (MT), user terminal (UT), Subscriber station (SS) or portable device. The base station 20 may refer to a stationary station that communicates with the wireless communication device 100 or another base station. The base station 20 may be called a node B, an evolved-node B (eNB), a base transceiver system (BTS) or an access point (AP).

The wireless communication network between the wireless communication device 100 and the base station 20 can support multiple users to communicate with each other by sharing available network resources. For example, in wireless communication networks, information can be transmitted through different methods such as: code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (time division multiple access, TDMA), orthogonal frequency division multiple access (orthogonal frequency division multiple access, OFDMA) or single carrier frequency division multiple access (single carrier frequency division multiple access, SC-FDMA). In the following, 5G communication technology will be explained as being applied to wireless communication between the wireless communication device 100 and the base station 20 , for example. Therefore, embodiments of the inventive concept may be applied to next-generation communication technologies in addition to 5G communication technology.

The RF integrated circuit 120 can receive downlink signals including control information or data signals from the base station 20 through the plurality of antennas 110_1 to 110_n. The RF integrated circuit 120 may include a low-noise amplifier for amplifying the downlink signal and a mixer for down-converting the frequency of the downlink signal. The RF integrated circuit 120 down-converts the downlink signal of the RF band into a base frequency, and can provide the base frequency to the controller 130 .

According to embodiments, the controller 130 may include a data management circuit 131 and a decoder 132. The data management circuit 131 may manage data required for decoding the PDCCH received from the base station 20 and may include a plurality of buffers 131a and 131b for managing the data. In the following, the data management circuit 131 may perform a series of the following operations: store (or buffer) the data operations required to decode the PDCCH in the buffer; and providing appropriate data to the decoder 132 according to the decoding operation of the decoder 132 .

In the following, in order to help understand the operation of the data management circuit 131, FIGS. 2 to 5 will be explained first. It should be fully understood that FIG. 2 to FIG. 5 are examples of the wireless communication system 1, and the concept of the present invention is not limited thereto.

Referring to Figure 2, the horizontal axis represents the time zone, and the vertical axis may represent the frequency zone. The smallest transmission unit in the time zone is an orthogonal frequency division multiplexing (OFDM) symbol. N _symb OFDM symbols 202 may form a slot 206, and two slots may form a subframe 205. For example, the length of slot 206 is 0.5 milliseconds, and the length of the subframe can be 1.0 milliseconds. In addition, the wireless frame 214 may be a time zone unit composed of ten sub-frames 205 .

The smallest transmission unit in a frequency area is a subcarrier. The bandwidth of the entire system transmission band may be composed of N _BW subcarriers 204. The basic unit of resources as the resource element (RE) 212 in the time-frequency region can be represented by an OFDM symbol index and a subcarrier index. A resource block (RB) 208 may be defined by N _symb OFDM symbols in the time zone and N _RB subcarriers 210 in the frequency zone. Therefore, the one RB 208 may be composed of N _symb * N _RB REs 212. An RB pair, which is a unit in which two RBs can be connected on the time axis, may be composed of N _symb * 2N _RB REs 212 . On the other hand, the PDCCH can be transmitted to the wireless communication device in the base station in the wireless communication system through the resources in the time-frequency zone of Figure 2. Downlink control information (DCI) can be transmitted via PDCCH. DCI may include downlink scheduling assignment related information and spatial multiplexing related control information. The downlink scheduling assignment related information includes physical downlink shared channel (PDSCH) resource name, transmission format and Hybrid Automatic Repeat request (HARQ) information item.

Referring to Figure 3, PDCCH 302 and PDSCH 303 can be frequency multiplexed and transmitted. In the base station, the resources of PDCCH 302 and PDSCH 303 can be allocated appropriately through scheduling. Therefore, coexistence of data transmission with the wireless communication device can be effectively supported. Multiple PDCCHs 302 may constitute one PDCCH set 306, and the PDCCH set 306 may be assigned in units of RB pairs. The location information of the PDCCH set 306 is terminal-specific and can be signaled through remote radio control (RRC). Up to two PDCCH sets 306 can be set in each wireless communication device. One PDCCH set 306 can be multiplexed and configured in different terminals at the same time. On the other hand, in the PDCCH 302, a demodulation reference signal (DMRS) 305 can be used as a reference signal.

Referring to FIG. 4 , one RB pair is shown as an example, and one RB may include 16 resource element groups (Resource Element Group, REG) 401. REGs included in the RB pair may be mapped to REG 401 indexes corresponding to {0, 1, 2, ..., and 15}. At this time, the REG in which DMRS 403 is mapped is excluded from the numbering.

A set of REGs corresponding to corresponding indexes may constitute one REG 401. For example, nine REGs 407 are mapped to index 0 in the RB pair shown in FIG. 4 and may constitute REGO 404. REGx can be composed of REGs numbered by the corresponding index x (x={0, 1, 2, ..., and 15}). When describing the embodiments, it is basically According to the concept of the present invention, for convenience, for the REG 401 existing in the RB pair, it is assumed that the same logical mapping method as 405 in Figure 4 is used.

Resource assignment for PDCCH is based on Control Channel Element (CCE) 402. A CCE 402 may be composed of four or eight REGs 401. The number of REG 401 of CCE 402 may vary according to the cyclic prefix (CP) length and sub-frame setting information. In Figure 4, an example is shown in which the four REGs 401 constitute one CCE 402. In more detail, through the same logical mapping method as 405 in Figure 4, REG0, REG4, REG8 and REG12 can be mapped to CCE0, REG1, REG5, REG9 and REG13 can be mapped to CCE1, REG2, REG6, REG10 and REG14 are mapped to CCE2, and REG3, REG7, REG11 and REG15 can be mapped to CCE3.

Therefore, when the four REGs 401 constitute one CCE 402, the RB pair may include four CCEs 402. When describing the embodiment, according to the concept of the present invention, for the sake of convenience, it is assumed that the CCE 402 existing in the RB pair adopts the same logical mapping method as 406 in Figure 4 . According to the mapping method between CCE 402 and REG 401, the PDCCH transmission method can be classified into localized transmission and distributed transmission.

Describes the search space in PDCCH. PDCCH can support terminal-particular search space. The search space is a set of PDCCH candidates consisting of CCEs that the wireless communication device attempts to decode at a given aggregation level (hereinafter referred to as CCE aggregation level). The PDCCH can have features that can be configured based on system parameters (e.g., CP length, subframe settings, The aggregation level is 1, 2, 4, 8, 16 or 32 determined by the PDCCH format, local transmission or distributed transmission method, or the total number of CCEs). Since there are various aggregation levels for bundling the plurality of CCEs, the wireless communication device may have multiple search spaces according to the aggregation level. The number of PDCCH candidates in the PDCCH that can be decoded by the wireless communication device according to the aggregation level may vary.

In FIG. 5 , an example is shown in which one PDCCH set 501 is composed of four RB pairs. Referring to Figure 5, RB pair 502 includes four CCEs 510. When explaining the embodiment, according to the inventive concept, it is assumed that the logical mapping method 406 of the CCE of Figure 4 is adopted.

In Figure 5, examples of search spaces for aggregation level-1 503, aggregation level-2 504, and aggregation level-4 505 are shown. At aggregation level-1 503, PDCCH candidate 506 may be mapped to CCE 510. At aggregation level-2 504, PDCCH candidate 507 may be mapped to two CCEs 510. At aggregation level-4 505, PDCCH candidates 508 may be mapped to four CCEs 510. Therefore, at aggregation level-1 503, there are four CCEs (CCE 0, CCE4, CCE8, and CCE12) in PDCCH candidates 506, and at aggregation level-2 504, there are four CCE pairs in PDCCH candidates 507 ({CCE0, CCE1}, {CCE4, CCE5}, {CCE8, CCE9} and {CCE12, CCE13}), and at aggregation level -4 505, there can be two CCE pairs ({CCE0, CCE1, CCE2, CCE3 } and {CCE8, CCE9, CCE10, CCE11}).

Returning to FIG. 1 , after obtaining the DCI included in the PDCCH, the decoder 132 may perform blind decoding on the PDCCH candidates determined according to the aggregation level. For example In other words, as shown in Figure 5, when there are PDCCH candidates 506, 507 and 508, the decoder 132 performs decoding operations on the four PDCCH candidates 506 at aggregation level -1 503. Decoder 132 may also perform decoding operations on four PDCCH candidates 507 at aggregation level-2 504 and may perform decoding operations on two PDCCH candidates 508 at aggregation level-4 505. For the above blind decoding operation of the decoder 132, the PDCCH candidates 506, 507 and 508 must be stored in the buffer (or memory) in the wireless communication device 100. In the conventional technology, when the blind decoding operation of the decoder 132 is performed, although some of the data (CCE0, CCE1, CCE4, CCE8, CCE9 and CCE12) are reused at least twice, the reuse of the part of the data is not allowed. PDCCH candidates 506, 507 and 508 are stored with consideration. In the traditional technology, CCE0, CCE4, CCE8 and CCE12 are stored in the first area of the buffer as PDCCH candidates 506 of aggregation level-1 503, and {CCE0, CCE1}, {CCE4, CCE5}, {CCE8, CCE9} and {CCE12, CCE13} are stored in the second area of the buffer as PDCCH candidates 507 of aggregation level-2 504, and {CCE0, CCE1, CCE2, CCE3} and {CCE8, CCE9, CCE 10, CCE 11} is stored in the third area of the buffer as a PDCCH candidate 508 for aggregation level-4 505. Therefore, CCE0, CCE1, CCE4, CCE8, CCE9 and CCE12 are repeatedly stored in the buffer, and the buffer usage efficiency is low.

As a solution, the data management circuit 131 according to the embodiment of the present invention may include a data buffer 131a and a plurality of address buffers 131b. In addition, in order to prevent data from being repeatedly stored, the data required for decoding is stored in the data buffer 131a. Then, the address of the data buffer 131a (i.e., stored in the data buffer 131a (the address of the LLR in the buffer) is stored in the address buffer 131b. To perform blind decoding from the data buffer 131a, with reference to the address stored in the address buffer 131b, the data management circuit 131 reads the data required by the decoder 132 and may provide the read data to the decoder 132.

Specifically, the data management circuit 131 can store multiple log-likelihood ratios (LLRs). The LLR is generated by the controller 130 by demodulating the PDCCH in the data buffer 131a and the address of the data buffer 131a. According to the aggregation levels of CCEs included in the PDCCH being stored, LLRs respectively corresponding to the plurality of PDCCH candidates may be stored in the address buffer 131b.

In FIG. 5 , the data management circuit 131 may store a plurality of LLRs generated by demodulating CCE0 to CCE15 included in the PDCCH in the data buffer 131a in a generation order (or in a prescribed order). In addition, the data management circuit 131 may store the address of the LLR corresponding to CCE0, CCE4, CCE8 and CCE12 as the PDCCH candidate 506 of the aggregation level-1 503 in the data buffer 131a in the address buffer 131b. In the first address buffer, the data buffer 131a may store {CCE0, CCE1}, {CCE4, CCE5}, {CCE8, CCE9} and {CCE12 as the PDCCH candidates 507 of the aggregation level-2 504. The address of the LLR corresponding to CCE13} is stored in the second address buffer in the address buffer 131b, and the data buffer 131a may be stored with the {{ The addresses of the LLRs corresponding to CCE0, CCE1, CCE2, CCE3} and {CCE8, CCE9, CCE10, CCE11} are stored in the third address buffer in the address buffer 131b. According to an embodiment, the LLR is stored in the data buffer The operations in can be performed in parallel with the operation of storing the address of the LLR in the address buffer. According to embodiments, in a buffer configuration, the data buffer 131a and the address buffer 131b are physically separated from each other or may be virtually separated from each other. In addition, the number of address buffers 131b may be configured to be suitable for the number of CCE aggregation levels that can be supported. For example, as shown in FIG. 5, when the three aggregation levels 503, 504 and 505 can be supported, the data management circuit 131 may be configured to include three address buffers (a first address buffer to third address buffer). The first address buffer is assigned to store the address of the LLR of the data buffer 131a where the PDCCH candidate 506 of aggregation level-1 503 is stored. The second address buffer is assigned to store the address of the LLR of the data buffer 131a where the PDCCH candidate 507 of aggregation level-2 504 is stored. As an exemplary embodiment, the third address buffer may be assigned to store the address of the LLR of the data buffer 131a in which the PDCCH candidate 508 of the aggregation level-4 505 is stored. When more aggregation levels can be supported, the data management circuit 131 can be configured to include more address buffers.

The data management circuit 131 according to an embodiment may store the address of the target LLR in the address buffer 131b in the at least one address buffer based on the CCE index corresponding to the target LLR stored in the data buffer 131a. For example, the data management circuit 131 may refer to the index of CCE0 to store the address of the LLR corresponding to CCE0 shown in FIG. 5 in the data buffer 131a in the first address buffer, the second address buffer and the third address buffer. in the three address buffer. According to an embodiment, when performing a demodulation operation on the PDCCH, the LLR corresponding to the CCE index may be used to generate the CCE index. When performing demodulation operation on CCE0 in Figure 5, CCE0 can be used The corresponding LLR is used to generate the CCE index representing CCE0.

According to an embodiment, the data management circuit 131 may use the data buffer 131a and the address buffer 131b to provide the decoder 132 with the data required to perform blind decoding on the PDCCH candidates. For example, when the decoder 132 performs decoding of aggregation level-1 503 on the PDCCH candidate 506, the data management circuit 131 obtains (or reads) the PDCCH candidates 506 CCE0, CCE4, The addresses of the LLRs corresponding to CCE8 and CCE12. In addition, the data management circuit 131 uses the obtained address to obtain (or read) the LLRs corresponding to CCE0, CCE4, CCE8, and CCE12 from the data buffer 131a, and may provide the obtained LLRs to the decoder 132.

According to an embodiment, the data management circuit 131 may store representative addresses of LLR groups. According to the resource mapping mode of the CCE of the PDCCH, continuity of the LLR group is ensured in the address buffer 131b (taking into account the LLRs continuously stored in the data buffer 131a). This will be explained in detail with reference to FIG. 10 .

The data management circuit 131 may be implemented in hardware such as a combination of application specific integrated circuits, field programmable gate arrays, logic gates, system on a chip, or different types of processing circuits (or control circuits). ). In addition, the data management circuit 131 may be implemented by software, such as instructions or code executable by a processor (eg, the controller 130). In addition, as an exemplary embodiment, the data buffer 131a and the address buffer 131b in the data management circuit 131 may be composed of, for example, a dynamic random access memory (DRAM) or a static random access memory (static random access memory). access memory, SRAM) and other volatile memories. In addition, the data buffer 131a and the address buffer 131b may also be composed of, for example, phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), Implemented using non-volatile memory such as resistive random access memory (ReRAM) or ferroelectric random access memory (FeRAM).

FIG. 6 is a flowchart illustrating a method of buffering data required for decoding by a wireless communication device according to an exemplary embodiment of the present invention.

Referring to FIG. 6 , the wireless communication device receives a PDCCH including a CCE in operation S100, and may generate a CCE index and an LLR corresponding to the CCE index from the received PDCCH in operation S110. Then, the data management circuit stores the LLR in the data buffer in operation S120, and may store the address of the LLR in at least one address buffer selected from the address buffer based on the CCE index in operation S130. According to embodiments, operations S120 and S130 may be performed in parallel.

FIG. 7 is a block diagram illustrating in detail the controller of the wireless communication device 600 according to an exemplary embodiment of the present invention.

The wireless communication device 600 may include a demodulator 610 and a data management circuit 620. The demodulator 610 may generate the LLR and the CCE index CCE_IDX corresponding to the LLR by receiving the PDCCH converted from the RF band into the baseband and performing a demodulation operation. The CCE index CCE_IDX may be information representing the CCE corresponding to the output LLR. The data management circuit 620 may include a data buffer circuit DBUF_C, a first multiplexer 623. Multiple address buffer circuits ABUF_C1 to ABUF_Cn and the first control logic 626. The data buffer circuit DBUF_C may include a second control logic 621 and a data buffer circuit 622. The address buffer circuit ABUF_C1 may include a third control logic 624 and an address buffer 625. The configuration of address buffer circuit ABUF_C1 can also be applied to other address buffer circuits ABUF_C2 to ABUF_Cn. The number of address buffer circuits ABUF_C1 to ABUF_Cn may be determined according to the number of supportable aggregation levels of CCEs included in the PDCCH. For example, in a wireless communication system that can support up to 32 CCE aggregation levels, the data management circuit 620 can be implemented to include 32 address buffer circuits ABUF_C1 to ABUF_Cn.

When first describing the operation of the data buffer circuit DBUF_C, the second control logic 621 can sequentially store the LLRs received from the demodulator 610 in the data buffer circuit 622 . According to an embodiment, the second control logic 621 classifies the LLRs by CCE with reference to the CCE index CCE_IDX and may store the classified LLRs in the data buffer circuit 622 . When the LLR is stored in the data buffer circuit DBUF_C, the first control logic 626 may provide the first control signal MUX_CS1 to the first multiplexer 623 by referring to the CCE index CCE_IDX to change the address buffer circuits ABUF_C1 to ABUF_Cn. At least one is connected to data buffer circuit DBUF_C.

For example, when the address buffer circuit ABUF_C1 and the data buffer circuit DBUF_C are connected through the first multiplexer 623, the third control logic 624 may request an address. Store the LLR corresponding to the CCE of the PDCCH candidate assigned to the CCE aggregation level of the address buffer circuit ABUF_C1 to the second control logic 621. The second control logic 621 may provide the address where the LLR is stored to the third control logic 624 in response to the request. The third control logic 624 may store the received address in the address buffer 625 .

As an example, the second control logic 621 of the data buffer circuit DBUF_C stores the LLR generated by the demodulator 610 in the data buffer circuit 622 and can provide the address of the stored LLR to the bit based on the CCE index CCE_IDX corresponding to the LLR. at least one of the address buffer circuits ABUF_C1 to ABUF_Cn. Therefore, the address buffer circuits ABUF_C1 to ABUF_Cn may respectively store addresses of LLRs corresponding to CCEs in which PDCCH candidates of the assigned CCE aggregation level are stored.

FIG. 8 is a diagram illustrating information stored in the data buffer circuit 622 and the first to third address buffers 625a to 625c according to an exemplary embodiment of the present invention. For clarity, Figure 8 will be explained with reference to Figures 5 and 7 .

In Figure 5, the three CCE aggregation levels 503, 504 and 505 are applied to the PDCCH. When a PDCCH is received, the three address buffer circuits ABUF_C1 to ABUF_C3 among the address buffer circuits ABUF_C1 to ABUF_Cn shown in FIG. 7 may be used. Referring to FIG. 8 , LLR represents a configuration in which LLRs corresponding to CCE0 to CCE15 are stored, the LLRs being generated by demodulating the PDCCH and CCE0 to CCE15 stored in the data buffer circuit 622 and in the data of FIG. 8 shown in buffer circuit 622. Depending on the embodiment, the LLR may be sorted by CCE and stored in the data buffer circuit 622 or may be stored without additional sorting. The second control logic 621 can manage the data buffer circuit 622 The data at the address of the LLR corresponding to the CCE is stored therein and the data can be provided in response to a request from the address buffer circuits ABUF_C1 to ABUF_Cn. In another embodiment, the second control logic 621 may actively provide the data to at least one address buffer circuit connected through the first multiplexer 623 .

The first address buffer 625a is assigned to store the address of the PDCCH candidate 506 of aggregation level-1 503. The second address buffer 625b is assigned to store the address of the PDCCH candidate 507 of aggregation level-2 504. The third address buffer 625c may be assigned to store the address of the PDCCH candidate 508 of aggregation level-4 505. Therefore, the addresses CCE0_Addr, CCE4_Addr, CCE8_Addr and CCE12_Addr of CCE0, CCE4, CCE8 and CCE12 as PDCCH candidates 506 of aggregation level-1 503 may be stored in the first address buffer 625a as the addresses of CCE0, CCE4, CCE8 and CCE12 of aggregation level-2 504. The addresses CCE0_Addr, CCE1_Addr, CCE4_Addr, CCE5_Addr, CCE8_Addr, CCE9_Addr, CCE12_Addr and CCE13_Addr of the PDCCH candidate 507 of {CCE0, CCE1}, {CCE4, CCE5}, {CCE8, CCE9} and {CCE12, CCE13} may be stored in the first In the two address buffer 625b, the addresses CCE0_Addr, CCE1_Addr, CCE2_Addr, CCE3_Addr of {CCE0, CCE1, CCE2, CCE3} and {CCE8, CCE9, CCE10, CCE11} which are the PDCCH candidates 508 of aggregation level-4 505 , CCE8_Addr, CCE9_Addr, CCE10_Addr and CCE11_Addr may be stored in the third address buffer 625c.

Therefore, according to aspects of the inventive concept, the UE may receive the PDCCH and store the PDCCH data in the data buffer 622 (where the PDCCH data corresponds to PDCCH candidates 506, 507 and 508), and stores the address of the PDCCH data in the address buffers 625a, 625b and 625c. Each of the address buffers may correspond to one of the PDCCH candidates. Additionally or alternatively, each of the address buffers may correspond to an aggregation level. Then, the UE may perform blind decoding on the PDCCH candidate based on the address of the PDCCH data stored in the corresponding address buffer.

In some cases, the UE may identify PDCCH candidates for blind decoding, select an address buffer from the plurality of address buffers based on the identified PDCCH candidates, and store the identification in the selected address buffer. One or more of the addresses of the PDCCH data in , and retrieving a portion of the PDCCH data from the data buffer based on the identified one or more addresses.

By using the above configuration of the first address buffer 625a to the third address buffer 625c and the data buffer circuit 622, the LLR can be prevented from being repeatedly stored and the memory can be used more efficiently. For example, the address of a CCE (such as CCE0) can be stored in different address buffers multiple times. For example, a single CCE may be associated with multiple PDCCH candidates (eg, associated with different PDCCH candidates with different aggregation levels). However, data associated with a CCE may be stored in the data buffer only once. If the size of the address is smaller than the size of the data itself, it may be more efficient to store the address multiple times than to store the data multiple times.

9A to 9F are views showing resource mapping patterns of control CCEs of PDCCH. FIG. 10 is a view illustrating a method of storing an address in the first address buffer 625a according to an exemplary embodiment of the present concept. REG as explained below A bundle may be defined as the smallest unit including a plurality of interleaved REGs on which the same precoding is performed.

Referring to FIG. 9A , the first REG bundle REG_BDa may be applied as the resource mapping pattern of the CCE of the PDCCH, and the first REG bundle REG_BDa may include two REGs connected on the frequency axis.

Referring to FIG. 9B , the second REG bundle REG_BDb may be applied as the resource mapping pattern of the CCE of the PDCCH, and the second REG bundle REG_BDb may include six REGs connected on the frequency axis.

Referring to FIG. 9C , the third REG bundle REG_BDc may be applied as the resource mapping pattern of the CCE of the PDCCH, and the third REG bundle REG_BDc may include two REGs connected on the time axis.

Referring to FIG. 9D , the fourth REG bundle REG_BDd may be applied as the resource mapping pattern of the CCE of the PDCCH, and the fourth REG bundle REG_BDd may include six REGs connected on the frequency axis and the time axis.

Referring to FIG. 9E , the fifth REG bundle REG_BDe may be applied as the resource mapping pattern of the CCE of the PDCCH, and the fifth REG bundle REG_BDe may include three REGs connected on the time axis.

Referring to FIG. 9F , the sixth REG bundle REG_BDf may be applied as the resource mapping pattern of the CCE of the PDCCH, and the sixth REG bundle REG_BDf may include six REGs connected on the frequency axis and the time axis.

As shown in FIGS. 9A to 9F , the resource mapping mode of the PDCCH may be configured by determining the first to sixth REG bundles REG_BDa to REG_BDf. Although consider and various shapes of the first REG bundle REG_BDa to the sixth REG bundle REG_BDf, but the PDCCH is decoded while mapping the resources on the time axis and demapping the resources on the frequency axis. Since the PDCCH is demodulated, the REG unit can be used to ensure continuous output of the LLR. For example, when a REG includes 12 resource elements, the continuity of the 24-bit LLR corresponding to a certain CCE can be guaranteed while performing the demodulation operation on the PDCCH. LLRs guaranteed to have continuity may be sequentially input to decoder 132 (FIG. 1), and may be decoded by decoder 132. In Figure 10, a method of storing addresses in an address buffer based on the above-mentioned continuity of LLR will be explained.

Referring to FIG. 10 , the LLR corresponding to CCE0 is divided into m LLR groups CCE0_0 to CCE0_m-1 that ensure continuity, and the LLRs may be stored in the data buffer circuit 622 . For example, the first LLR group CCE0_0 may include LLRs generated by demodulation by the demodulator 610 (FIG. 7) to ensure continuity, and the LLRs may be continuously stored at addresses of the data buffer circuit 622 Between Addr_n0 and address Addr_n0+k. In addition, the (m-1)th LLR group CCE0_m-1 may include LLRs generated by demodulation by the demodulator 610 (FIG. 7) to ensure continuity, and the LLRs may be continuously stored in the data buffer Between the address Addr_nm-1 and the address Addr_nm-1+k of the circuit 622.

In the first address buffer 625a, the address CCE0_Addr of the LLR corresponding to CCE0 may include representative addresses in which the addresses of the LLR groups CCE0_0 to CCE0_m-1 are respectively stored. According to an embodiment, the representative addresses may be starting addresses or final addresses of the LLR groups CCE0_0 to CCE0_m-1. For example In other words, the starting addresses Addr_n0 to Addr_nm-1 of the LLR groups CCE0_0 to CCE0_m-1 may be stored in the first address buffer 625a. In this way, in the first address buffer 625a, the addresses CCE4_Addr, CCE8_Addr and CCE12_Addr of the LLRs corresponding to CCE4, CCE8 and CCE12 can be implemented to include representative addresses of the LLR group. In an embodiment, the magnitude GS of the LLR group CCE0_0 may vary according to the resource mapping mode of the PDCCH CCE.

By not storing all the addresses in the LLR addresses of the LLR group with guaranteed continuity, the memory utilization of the first address buffer 625a can be effectively improved. Specifically, the representative address of the LLR group is stored taking into account the resource mapping mode of the CCE of the PDCCH. This method can be applied to other address buffers.

FIG. 11 is a flowchart illustrating a method of performing decoding of a wireless communication device according to an exemplary embodiment of the present inventive concept. In the following, the operation of decoding a target PDCCH candidate will be explained.

Referring to FIG. 11, at S200, the data management circuit may obtain the LLR of the target PDCCH candidate from the data buffer using the address buffer in the address buffer corresponding to the CCE aggregation level of the target PDCCH candidate. At S210, the data management circuit may provide the obtained LLR to the decoder, and the decoder may use the obtained LLR to decode the target PDCCH candidate. The above operations can be repeated until the PDCCH candidate is decoded.

FIG. 12 is a block diagram illustrating in detail the controller of the wireless communication device 600 according to an exemplary embodiment of the present invention. Hereinafter, the description given with reference to FIG. 7 is omitted.

Referring to FIG. 12 , the wireless communication device 600 may include a data management circuit 620 and a decoder 630 . The decoder 630 receives data (eg, LLR) on the PDCCH candidates required for decoding from the data management circuit 620 and can perform blind decoding on the received data. In addition, compared with FIG. 7 , the data management circuit 620 may further include a second multiplexer 627 , and the first control logic 626 may perform control so that the data on the target PDCCH candidate required by the decoder 630 may be provided to Decoder 630. In detail, the first control logic 626 can control the first multiplexer 623, the second multiplexer 627, and the address buffer circuits ABUF_C1 and ABUF_C2. The first control logic 626 controls these components so that the information on at least one PDCCH candidate of the target aggregation level to be decoded when the decoder 630 performs blind decoding can be provided in appropriate timing.

For example, to provide information regarding PDCCH candidates specifying an aggregation level, first control logic 626 enables address buffer circuit ABUF_C1 by providing buffer control signal BUF_CS to address buffer circuit ABUF_C1 and may The address buffer circuit ABUF_C1 is connected to the data buffer circuit DBUF_C by providing the first control signal MUX_CS1 to the first multiplexer 623 . The specified aggregation level is stored in the address buffer circuit ABUF_C1. Additionally, the first control logic 626 may connect the address buffer circuit ABUF_C1 to the decoder 630 by providing the second control signal MUX_CS2 to the second multiplexer 627 . At this time, the third control logic 624 may use the address of the data on the PDCCH candidate stored in the address buffer 625 to request the LLR from the data buffer circuit 622, and the second control logic 621 may refer to the data address. Address buffer circuit ABUF_C1 is provided with the LLR read from data buffer circuit 622 . In addition, as in Figure 10, when the LLR group When the representative address is stored in the address buffer 625, the second control logic 621 may read the LLR from the data buffer circuit 622 taking into account the magnitude GS of the LLR group. The address buffer circuit ABUF_C1 may provide the LLR received from the data buffer circuit DBUF_C as data on the PDCCH candidate to the decoder 630. The configuration of Figure 12 is an exemplary embodiment. The inventive concept is not limited to this. The data buffer circuit DBUF_C may directly provide the decoder 630 with data on the target PDCCH candidate.

The data management circuit 620 may use the data buffer circuit DBUF_C and the plurality of address buffer circuits ABUF_C1 to ABUF_Cn to provide the decoder 630 with data regarding the PDCCH candidates for blind decoding in appropriate timing.

FIG. 13 is a block diagram illustrating an electronic device 1000 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 13 , the electronic device 1000 may include a memory 1010 , a processor unit 1020 , an input and output controller 1040 , a display unit 1050 , an input device 1060 and a communication processing unit 1090 . Here, the memory 1010 may constitute multiple memory units. The individual components are explained below.

The memory 1010 may include a program storage unit 1011 for storing programs for controlling operations of the electronic device 1000 and a data storage unit 1012 for storing data generated during execution of the programs. The data storage unit 1012 can store data required for the operation of the application program 1013 and the data management program 1014. The program storage unit 1011 may include an application program 1013 and a data management program 1014. Here, the program included in the program storage unit 1011 as a set of instructions may be expressed as an instruction set.

The application program 1013 includes an application program operating in the electronic device 1000 . Application 1013 includes instructions for the application driven by processor 1022 . According to an embodiment of the inventive concept, the data management program 1014 may control the storage and management of data required to perform decoding. The processor 1022 stores the data required for decoding (for example, the LLR generated by demodulating the PDCCH) in a data buffer (not shown) through the data management program 1014, and the data can be allocated according to the CCE aggregation level. The addresses are respectively stored in a plurality of address buffers (not shown), and a data buffer (not shown) and an address buffer (not shown) can be used to perform a blind decoding operation on the PDCCH candidate. Memory interface 1021 may control access to components such as processor 1022 or peripheral device interface 1023 of memory 1010 .

The peripheral device interface 1023 can control the connection between the base station's input and output peripheral devices, the processor 1022 and the memory interface 1021 . The processor 1022 uses at least one software program to control the base station to provide corresponding services. At this time, the processor 1022 executes at least one program stored in the memory 1010 and can provide services corresponding to the program.

The input and output controller 1040 may provide an interface between the input and output devices (eg, the display unit 1050 and the input device 1060 ) and the peripheral device interface 1023 . The display unit 1050 displays status information, input characters, moving pictures and still pictures. For example, the display unit 1050 may display information about applications driven by the processor 1022 .

The input device 1060 may provide input data generated by selection of the electronic device to the processor unit 1020 via the input and output controller 1040 . At this time, enter the The device 1060 may include a keyboard including at least one hardware button and a touchpad for sensing touch information. For example, the input device 1060 may provide the processor 1022 with touch information sensed by the touch pad, such as touch, touch motion, and touch release, through the input and output controller 1040 . The electronic device 1000 may include a communication processing unit 1090 for performing communication functions of voice communication and data communication.

While the inventive concepts have been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the claims as claimed below.

1: Wireless communication system

2: Downlink channel

4: Uplink channel

20:Base station

100:Wireless communication device

110_1~110_n:antenna

120: Radio frequency (RF) integrated circuits

130:Controller

131: Data management circuit

131a: Data buffer/buffer

131b: Address buffer/buffer

132:Decoder

Claims (10)

A method of operating a wireless communication device, the method comprising: receiving a physical downlink control channel (PDCCH) including a plurality of control channel elements (CCE); storing a plurality of log likelihood ratios (LLR) in a data buffer , wherein the plurality of log-likelihood ratios are generated by demodulating the physical downlink control channel and correspond to a plurality of physical downlink control channel candidates, the plurality of physical downlink control channel Each of the channel candidates has an aggregation level corresponding to the number of the plurality of control channel elements; storing at least one address of the plurality of log-likelihood ratios in a plurality of address buffers in; and performing blind decoding on the plurality of physical downlink control channel candidates using the data buffer and the plurality of address buffers. The method of claim 1, wherein: storing the at least one address of the plurality of log-likelihood ratios in the plurality of address buffers further includes: based on the target log-likelihood ratio corresponding to The channel element index is controlled to store the address of the target log-likelihood ratio in at least one of the plurality of address buffers. The method of claim 2, wherein the control channel element is obtained by demodulating the physical downlink control channel. The method of claim 1, wherein: storing the plurality of log-likelihood ratios in the data buffer and storing the at least one address of the plurality of log-likelihood ratios in the plurality of log-likelihood ratios Each address buffer is executed in parallel. The method of claim 1, wherein: when the number of supportable aggregation levels is a natural number N, the number of the plurality of address buffers is N, and each of the plurality of address buffers An address buffer stores an address having a log-likelihood ratio of at least one physical downlink control channel candidate at an aggregation level corresponding to each address buffer. The method of claim 1, wherein: the plurality of address buffers store representations of log-likelihood ratio groups according to resource mapping patterns of the plurality of control channel elements of the physical downlink control channel. Address, the log-likelihood ratio group includes log-likelihood ratios continuously stored in the data buffer. The method according to claim 1, wherein: performing the blind decoding on the physical downlink control channel candidate further includes: referring to the target physical downlink control channel candidate in the plurality of address buffers. The address buffer corresponding to the aggregation level, obtaining the log-likelihood ratio of the target physical downlink control channel candidate from the data buffer; and using the obtained log-likelihood ratio to compare the target physical Downlink control channel candidates are decoded. The method of claim 1, wherein the data buffer and the plurality of address buffers are divided physically or virtually. A method of operating a wireless communications device for managing data required to perform blind decoding, the method comprising: generating from a physical downlink control channel (PDCCH) including a plurality of control channel elements (CCEs) Control channel element index and log-likelihood ratio corresponding to the control channel element index; store the log-likelihood ratio in a data buffer; and convert the log-likelihood ratio based on the control channel element index. At least one address is stored in at least one address buffer selected from a plurality of address buffers. The method of claim 9, wherein: the plurality of address buffers are respectively assigned to store control channels included in at least one physical downlink control channel candidate corresponding to different control channel element aggregation levels. The address of the log-likelihood ratio corresponding to the element.