KR20200057178A - Thin film transistor - Google Patents

Abstract

According to an embodiment of the present invention, a thin film transistor with improved switching performance may comprise: a first source/drain electrode on a substrate; a second source/drain electrode on an upper surface of the first source/drain electrode; an insulating pattern disposed between the upper surface of the first source/drain electrode and a lower surface of the second source/drain electrode; an active pattern extended from the upper surface of the first source/drain electrode and an upper surface of the second source/drain electrode; and a gate electrode disposed on the active pattern and partially overlapping the active pattern.

Description

Thin film transistor {THIN FILM TRANSISTOR}

The present invention relates to a thin film transistor, and more particularly, to a thin film transistor having an increased channel length.

The thin film transistor is a device having three terminals: a gate electrode, a drain electrode, and a source electrode, like a field effect transistor. The main function of the thin film transistor is the switching operation. The thin film transistor may turn on or off the channel between the source electrode and the drain electrode according to the voltage applied to the gate electrode. The thin film transistor can be used as a backplane element of a display device. Recently, as display devices having ultra-high resolution have been proposed, high integration of thin film transistors in a backplane element is required. Accordingly, research on a vertical channel transistor has been conducted.

The problem to be solved by the present invention is to provide a vertical channel type thin film transistor with reduced leakage current and improved switching performance.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

The problem to be solved by the present invention is to provide a vertical channel type thin film transistor with reduced leakage current and improved switching performance.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to embodiments of the present invention, a transistor having an improved degree of integration may be provided. Also, as the gate electrode has side surfaces and offset sides of the active pattern, leakage current of the gate electrode and the active pattern may be reduced. In addition, the parasitic power storage capacity may be reduced as the gate electrode and the active pattern do not completely overlap.

1 is a plan view illustrating a thin film transistor according to embodiments of the present invention.
2A and 2B are cross-sectional views taken along lines A-A 'and B-B' of FIG. 1, respectively.
3 is a plan view illustrating a thin film transistor according to embodiments of the present invention.
4A is a plan view illustrating a display device according to some example embodiments of the present invention.
4B is a cross-sectional view taken along line A-A 'in FIG. 4A.
5A is a plan view illustrating a display device according to some example embodiments of the present invention.
5B is a cross-sectional view taken along line A-A 'in FIG. 5A.
6A is a plan view illustrating a display device according to some example embodiments of the present invention.
6B is a cross-sectional view taken along line A-A 'in FIG. 6A.

Advantages and features of the present invention, and methods for achieving them will be clarified with reference to embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present invention to be complete, and have ordinary knowledge in the art to which the present invention pertains. It is provided to fully inform the person of the scope of the invention, and the invention is only defined by the scope of the claims. The same reference numerals refer to the same components throughout the specification.

Embodiments described herein will be described with reference to plan and cross-sectional views, which are ideal schematic views of the present invention. Therefore, the shape of the exemplary diagram may be modified by manufacturing technology and / or tolerance. Therefore, the embodiments of the present invention are not limited to the specific shapes shown, but also include changes in shapes generated according to the manufacturing process. Accordingly, the regions illustrated in the figures have schematic properties, and the shapes of the regions illustrated in the figures are intended to illustrate a particular form of region of the device, and are not intended to limit the scope of the invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 is a plan view illustrating a thin film transistor according to embodiments of the present invention. 2A and 2B are cross-sectional views taken along lines A-A 'and B-B' of FIG. 1, respectively. 3 is an enlarged cross-sectional view corresponding to part AA of FIG. 2.

1, 2A and 2B, a thin film transistor according to embodiments of the present invention includes a substrate 100, first and second source / drain electrodes 130 and 140, an active pattern 150 and a gate Electrodes 160 may be included. The first and second source / drain electrodes 130 and 140 may be stacked on the substrate 100. The first source / drain electrode 130 and the second source / drain electrode 140 may be disposed vertically spaced from each other. The active pattern 150 may extend from the top surface of the first source / drain electrode 130 to the top surface of the second source / drain electrode 140. Therefore, the active pattern 150 may have a vertically extending portion. The gate electrode 160 may be disposed on the active pattern 150 to partially overlap the active pattern 150.

The gate electrode 160 may have side surfaces 150s and offset side surfaces 160s of the active pattern 150. In other words, the side surfaces 160s of the gate electrode 160 may not be aligned with the side surfaces 150s of the active pattern 150. Accordingly, a leakage current between the gate electrode 160 and the active pattern 150 can be reduced.

In detail, the first source / drain electrode 130 may be disposed on the substrate 100. The substrate 100 may be an insulating substrate. The substrate 100 may include, for example, glass, plastic, or silicon. The first source / drain electrode 130 may include metal. The first source / drain electrode 130 may include, for example, molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti).

The insulating pattern 114 may be disposed on the substrate 100 and the first source / drain electrodes 130. The insulating pattern 114 is disposed between the first source / drain electrode 130 and the second source / drain electrode 140 to electrically separate them. By adjusting the thickness of the insulating pattern 114, the distance between the first source / drain electrode 130 and the second source / drain electrode 140 may be increased. Accordingly, the length of the active pattern 150 to be described later can be increased. The insulating pattern 114 may cover a portion of the top surface of the first source / drain electrode 130 and expose another portion.

The second source / drain electrode 140 may be disposed on the insulating pattern 114. The second source / drain electrodes 140 may be disposed on the upper surface of the insulating pattern 114 to vertically space the first source / drain electrodes 130. Also, the second source / drain electrode 140 may have a side surface aligned with the side surface of the insulating pattern 114. In plan view, the second source / drain electrode 140 may extend in a first direction D1 parallel to the top surface of the substrate 100. The second source / drain electrode 140 may overlap at least partially with the first source / drain electrode 130. The second source / drain electrode 140 may include the same material as the first source / drain electrode 130.

The active pattern 150 may extend from the top surface of the first source / drain electrode 130 to the top surface of the second source / drain electrode 140. In addition, the active pattern 150 may cover the side surface of the insulating pattern 114 and the side surface of the second source / drain electrode 140. The active pattern 150 may include a channel region forming a conductive channel between the first source / drain electrode 130 and the second source / drain electrode 140 depending on whether a voltage is applied to the gate electrode 160. The active pattern 150 may include an oxide semiconductor. The active pattern 150 includes, for example, zinc oxide (ZnO), indium oxide (InO), indium-gallium-zinc oxide (In-Ga-Zn-O), and zinc-tin oxide (Zn-Sn-O). can do. In addition, the oxide semiconductor may include an oxide containing at least two or more elements of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and aluminum (Al).

The gate insulating layer 162 may be disposed on the active pattern 150. The gate insulating layer 162 may completely cover the top surface of the active pattern 150. The gate insulating layer 162 is disposed between the active pattern 150 and the gate electrode 160 to be described later to electrically insulate them. The gate insulating layer 162 may be formed entirely on the substrate 100. In other words, the gate insulating layer 162 includes a top surface of the substrate 100, a top surface of the first source / drain electrode 130, a top surface of the active pattern 150, a top surface of the second source / drain electrode 140, and an insulating pattern The top surface of 114 may be covered. In the manufacturing process of the thin film transistor, the gate insulating layer 162 may not be patterned together with the active pattern 150. That is, the gate insulating layer 162 may be formed after the active pattern 150 is patterned. Accordingly, side surfaces of the gate insulating layer 162 and the active pattern 150 may not be aligned, and leakage current between the active pattern 150 and the gate electrode 160 may be reduced.

The gate electrode 160 may be disposed on the active pattern 150. The gate electrode 160 may partially overlap the active pattern 150. That is, the gate electrode 160 may not completely overlap the active pattern 150. The gate electrode 160 may extend in a second direction D2 perpendicular to the first direction D1 from a planar viewpoint. The gate electrode 160 may intersect the active pattern 150 in plan view. The gate electrode 160 may cover a portion of the upper surface of the first insulating layer 112 and a portion of the upper surface of the second insulating layer. The gate electrode 160 may be formed by a different patterning process from the active pattern 150 to have side surfaces and offset sides of the active pattern 150. The side surfaces of the gate electrode 160 may not be aligned with the side surfaces of the active pattern 150. The gate electrode 160 may include the same material as the first source / drain electrode 130. According to embodiments, as illustrated in FIG. 1, the width of the first direction D1 of the gate electrode 160 may be smaller than the width of the first direction D1 of the active pattern 150. The width of the second direction D2 of the gate electrode 160 may be greater than the width of the second direction D2 of the active pattern 150.

The interlayer insulating film 122 may be formed on the entire surface of the substrate 100. The interlayer insulating layer 122 may cover the gate insulating layer 162 and the gate electrode 160. The interlayer insulating layer 122 may have a substantially flat top surface.

3 is a plan view of a thin film transistor according to embodiments of the present invention. For the sake of simplicity, the differences from the thin film transistors described above are mainly described, and detailed descriptions of overlapping components are omitted.

Referring to FIG. 3, the active pattern 150 may completely overlap the gate electrode 160. In this case, the active pattern 150 may have side surfaces offset from the side surfaces of the gate electrode 160. The width of the first pattern D1 of the active pattern 150 may be smaller than the width of the first direction D1 of the gate electrode 160. The width of the active pattern 150 in the second direction D2 may be smaller than the width of the second direction D2 of the gate electrode 160.

4A is a plan view illustrating a display device according to some example embodiments of the present invention. 4B is a cross-sectional view taken along line A-A 'in FIG. 4A.

4A and 4B, the display device according to embodiments of the present invention includes data lines DL, gate lines GL, source / drain patterns 240, active patterns 250, and Pixel electrodes PE may be included.

The data lines DL extend in the second direction D2 and may be arranged in the first direction D1. The gate lines GL extend in the first direction D1 and may be arranged in the second direction D2. The data lines DL and the gate lines GL may cross each other in an insulated state. The active pattern 250 and the source / drain pattern 240 may be disposed adjacent to the gate line GL and data line DL. The active pattern 250 and the source / drain pattern 240 may be formed to at least partially overlap the intersection of the data lines DL and the gate lines GL. The pixel electrode PE may be disposed between the data lines DL and the gate lines GL. The side surfaces GLs of the gate line GL may be offset from the side surfaces 250s of the active patterns 250.

In detail, a data line DL may be provided on the substrate 200. The data line DL may transmit a data voltage to the pixel electrode PE according to a gate signal applied to the gate line GL. The data line DL functions as a source or drain electrode, and may constitute a transistor together with the source / drain pattern 240 and the gate line GL. The data line DL may include a metal having a low specific resistance to reduce signal delay or voltage drop. Data lines DL include, for example, magnesium (Mg), aluminum (Al), chromium (Cr), cobalt (Co), nickel (Ni), palladium (Pd), silver (Ag), gold (Au), platinum And metal materials such as (Pt), molybdenum (Mo), and titanium (Ti), and at least one of these compounds.

The insulating pattern 214 and the source / drain pattern 240 may be sequentially stacked on the substrate 200. The insulating pattern 214 may cover the top surface of the substrate 200 and the top surface of the data line DL. The source / drain pattern 240 is disposed on the top surface of the insulating pattern 214 and may have an island shape. One side of the source / drain pattern 240 may be aligned with the side of the insulating pattern 214. The source / drain pattern 240 may include a metal having low specific resistance.

The active pattern 250 may extend from the top surface of the data line DL to the top surface of the source / drain pattern 240. In plan view, the active pattern 250 may be disposed to overlap the intersection of the data line DL and the gate line GL. The width of the first direction D1 of the active pattern 250 may be smaller than the width of the first direction D1 of the data line DL. The width of the active pattern 250 in the second direction D2 may be smaller than the width of the second direction D2 of the gate line GL. 4A, side surfaces 250s of the active pattern 250 may be offset from side surfaces GLs of the gate line GL and side surfaces DLs of the data line DL. In other words, the side surfaces 250s of the active pattern 250 may not be aligned with the side surfaces GLs of the gate lines GL or the side surfaces DLs of the data line DL.

The gate insulating layer 262 and the gate line GL may be sequentially formed on the active pattern 250. The gate insulating layer 162 may be disposed between the active pattern 150 and the gate line GL to electrically insulate them. The gate insulating layer 162 may be formed entirely on the substrate 200. The gate insulating layer 162 may cover the data line DL, the top surface of the source / drain pattern 240, and the top surface of the insulating pattern 214. The gate insulating layer 262 may be formed to completely cover the exposed surfaces of the active pattern 250 after the active pattern 250 is patterned. Accordingly, leakage current between the active pattern 250 and the gate line GL may be reduced.

An interlayer insulating film 222 may be formed on the entire surface of the substrate 200. The interlayer insulating layer 222 may cover the gate line GL and the gate insulating layer 162. The interlayer insulating film 222 may have a substantially flat top surface.

The pixel electrode PE may be disposed on the interlayer insulating layer 222. The pixel electrode PE may be connected to the source / drain pattern 240 through a contact hole CH passing through the interlayer insulating layer 222. In plan view, the pixel electrode PE may be disposed between the data lines DL and the gate lines GL, but is not limited thereto. The pixel electrode PE may be disposed to overlap the data lines DL or the gate lines GL. The pixel electrode PE may receive a data voltage from the data line DL to form an electric field with a common electrode (not shown) disposed on the pixel electrode PE. The pixel electrode PE is, for example, magnesium (Mg), aluminum (Al), chromium (Cr), cobalt (Co), nickel (Ni), palladium (Pd), silver (Ag), gold (Au), platinum And metal materials such as (Pt), molybdenum (Mo), and titanium (Ti), and at least one of these compounds.

5A is a plan view illustrating a display device according to some example embodiments of the present invention. 5B is a cross-sectional view taken along line A-A 'in FIG. 5A. 6A is a plan view illustrating a display device according to some example embodiments of the present invention. 6B is a cross-sectional view taken along line A-A 'in FIG. 6A. For the sake of simplicity, the differences from the display device described above are mainly described, and detailed descriptions of overlapping components are omitted.

5A to 6B, the active pattern 250 may not completely overlap with the gate lines GL and the data lines DL. In this case, the side surfaces 250s of the active pattern 250 may be offset from the side surfaces GLs of the gate line GL and the side surfaces DLs of the data line DL. In other words, the side surfaces 250s of the active pattern 250 may not be aligned with the side surfaces GLs of the gate lines GL or the side surfaces DLs of the data line DL.

According to embodiments, as illustrated in FIGS. 5A and 5B, the width of the first direction D1 of the active pattern 250 may be greater than the width of the first direction D1 of the data line DL. . The width of the active pattern 250 in the second direction D2 may be greater than the width of the second direction D2 of the gate line GL.

According to embodiments, as illustrated in FIGS. 6A and 6B, the width of the first direction D1 of the active pattern 250 may be greater than the width of the first direction D1 of the data line DL. . The width of the active pattern 250 in the second direction D2 may be smaller than the width of the second direction D2 of the gate line GL.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but those of ordinary skill in the art to which the present invention pertains can implement the present invention in other specific forms without changing its technical spirit or essential features. You will understand that there is. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (1)

A first source / drain electrode on the substrate;
A second source / drain electrode disposed on an upper surface of the first source / drain electrode;
An insulating pattern disposed between the top surface of the first source / drain electrode and the bottom surface of the second source / drain electrode;
An active pattern extending from an upper surface of the first source / drain electrode to an upper surface of the second source / drain electrode; And
A thin film transistor including a gate electrode disposed on the active pattern and partially overlapping the active pattern.

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