KR20200052733A - Driving circuit unit for image display panel, and image display device using the same - Google Patents

Abstract

Disclosed are a driving circuit unit of an image display panel and an image display device using the same. According to an embodiment of the present invention, the driving circuit unit comprises: a first clock generation unit generating a first clock signal at a preset frequency and period and outputting the first clock signal to a first load unit; and a first delay circuit unit delaying a phase of the first clock signal outputted from the first clock generation unit for a predetermined period to generate a second clock signal and transmit the second clock signal to a second load unit. The electro magnetic interference (EMI) may be reduced.

Description

DRIVING CIRCUIT UNIT FOR IMAGE DISPLAY PANEL, AND IMAGE DISPLAY DEVICE USING THE SAME

The present invention relates to a driving circuit portion of an image display panel capable of reducing the effect of electromagnetic interference (EMI), and an image display device using the same.

Recently, an organic light emitting diode display is mainly used in a mobile communication device such as a smartphone or tablet pad as a flat panel display for displaying an image.

Since the organic light emitting diode display has a high luminance, a low driving voltage, and is capable of ultra-thinning, a backlight unit is more usefully applied to a mobile communication device than a liquid crystal display, which had to be additionally configured.

A flat panel display device such as an organic light emitting diode display includes an image display panel in which pixel areas displaying red, green, and blue are arranged in a matrix, and an organic light emitting diode and pixels of an organic light emitting diode configured in pixel areas of the image display panel And driving integrated circuits that control the circuits.

The driving integrated circuits driving the pixel circuits in each pixel area operate according to high frequency clock signals. For example, driving integrated circuits generate control signals in response to high frequency clock signals and convert digital image data input from the outside into an analog image signal (current or voltage signal). In addition, by supplying analog video signals to the pixel circuits of each pixel in units of horizontal lines according to control signals, an image is displayed through each pixel.

In general, driving integrated circuits are mounted in close contact with one side of a printed circuit board or a video display panel, and are driven by a plurality of high-frequency clock signals, so driving integrated circuits are electromagnetic (EMI) ) It is greatly affected by interference. Particularly, when the phases of the high-frequency clock signals overlap, the electromagnetic wave is amplified as much as the overlapping number, which inevitably increases electromagnetic interference.

Accordingly, in the related art, a scheme has been proposed to reduce the EMI effect by spreading or de-spreading the energy spectrum of high-frequency clock signals, or by shifting the phase of high-frequency clock signals and transmitting them to driving integrated circuits.

However, the conventional EMI reduction scheme has a problem in that its design area and manufacturing cost increase because a spectrum modulation unit or a phase modulation unit for spreading or despreading the energy spectrum of high frequency clock signals has to be additionally configured.

An object of the present invention is to delay the phase of the clock signal generated by the clock generation unit, and to drive the circuit unit of the image display panel so that clock signals before and after the phase delay can be used in different loads or circuits, and an image display device using the same Is to provide.

In addition, the driving circuit unit of the image display panel to allow each clock generating unit to generate clock signals having different phases at different timings, and to use clock signals generated in different phases in different loads or circuits, and It is to provide an image display device using the same.

In addition, the energy spectrum of clock signals generated by each clock generator is varied differently, and the driving circuit unit of the image display panel is configured to use clock signals having different energy spectrums in different loads or circuits. It is to provide a video display device used.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention not mentioned can be understood by the following description, and will be more clearly understood by embodiments of the present invention. In addition, it will be readily appreciated that the objects and advantages of the present invention can be realized by means of the appended claims and combinations thereof.

The driving circuit part of the video display panel according to the present invention generates a first clock signal at a preset frequency and period and outputs the first clock signal to the first load part. The first clock generator and the first clock generator output the first clock signal. And a first delay circuit unit generating a second clock signal by delaying the phase of the clock signal for a predetermined period and transmitting the second clock signal to the second load unit.

In addition, the image display apparatus using the driving circuit portion of the image display panel according to the present invention, a plurality of sub-pixels are arranged in the crossing regions of the gate and the data line, the image display panel for displaying an image, and synchronization signals from the outside It includes a driving circuit unit that controls a gate and a data line using at least one clock signal and delays at least one clock signal phase or generates a plurality of clock signals having different phases.

The driving circuit portion of the image display panel according to the present invention modulates the energy spectrum of the first clock signal input from the external or first clock generator using the first RC time constant of the first RC circuit, and the energy spectrum is modulated. The energy spectrum of the second clock signal input from the first filter unit, the external or second clock generator, which transmits the clock signal to the first load unit is modulated using the second RC time constant of the second RC circuit, and the energy spectrum is modulated. Modulates the energy spectrum of the third clock signal input from the second filter unit and the external or third clock generator to transmit the second clock signal to the second load unit using the third RC time constant of the third RC circuit. And a third filter unit transmitting the third clock signal modulated with the energy spectrum to the third load unit.

In addition, the image display apparatus using the driving circuit portion of the image display panel according to the present invention, a plurality of sub-pixels are arranged in the crossing regions of the gate and the data line, the image display panel for displaying an image, and synchronization signals from the outside It includes a driving circuit unit that controls a gate and a data line using a plurality of clock signals and modulates and outputs energy spectra for each clock signal.

The driving circuit part of the video display panel according to the present invention and the video display device using the same can delay the phase of the clock signal by simply adding a phase delay circuit. In addition, EMI interference can be reduced by allowing clock signals before and after the phase delay to be used in different loads or circuits.

In addition, it is possible to generate clock signals having different phases at different timings by simply adding a power supply delay circuit that simply supplies power by delaying the power supply.

In addition, by adding an RC filter circuit capable of varying the RC time constant to each clock signal output terminal, the energy spectrum of each clock signal can be varied differently. Accordingly, EMI interference can be reduced by allowing clock signals having different energy spectrums to be used in different loads or circuits.

1 is a configuration diagram specifically showing an image display device according to an embodiment of the present invention.
2 is a block diagram showing a driving circuit of the image display panel according to the first embodiment of the present invention.
3 is a circuit diagram specifically showing the first delay circuit shown in FIG. 2.
4 is a waveform diagram illustrating a first clock signal output from the first clock generator shown in FIG. 3 and a second clock signal whose phase is delayed by the first delay circuit unit, respectively.
5 is a block diagram specifically showing various application examples of a driving circuit according to the present invention.
6 is another configuration diagram showing a driving circuit unit of the type shown in FIGS. 1 and 5 (a).
7 is a waveform diagram showing the first clock signal generated by the first clock generator, the second clock signal phase-delayed by the first delay circuit unit, and the third clock signal phase-delayed by the second delay circuit unit, respectively.
8 is a block diagram illustrating a driving circuit portion of an image display panel according to a second embodiment of the present invention.
9 is a waveform diagram illustrating first to third power signals and first to third clock signals of FIG. 8, respectively.
10 is a block diagram showing a driving circuit part of an image display panel according to a third embodiment of the present invention.
11 is a circuit diagram specifically illustrating the first to third filter units illustrated in FIG. 10.
12 is a graph showing energy attenuation characteristics of each of the first to third filter units illustrated in FIG. 1 and energy spectrums of the first to third clock signals.

The above-described objects, features, and advantages will be described in detail below with reference to the accompanying drawings, and accordingly, a person skilled in the art to which the present invention pertains can easily implement the technical spirit of the present invention. In the description of the present invention, when it is determined that detailed descriptions of known technologies related to the present invention may unnecessarily obscure the subject matter of the present invention, detailed descriptions will be omitted. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

An image display device to which the main technology of the present invention is applied includes a liquid crystal display, a field emission display, an organic light emitting display, and a quantum dot display device Dot Display). Hereinafter, an organic light emitting diode display device will be described as an example.

1 is a configuration diagram specifically showing an image display device according to an embodiment of the present invention.

The image organic light emitting diode display device illustrated in FIG. 1 includes an image display panel 100, a driving circuit unit 200, and a power supply unit 300.

In the image display panel 100, each sub-pixel P is configured in each pixel area arranged in a matrix form to display an image. Each sub-pixel P includes an organic light emitting diode and a diode driving circuit that independently drives the organic light emitting diode. The form in which each sub-pixel P is arranged in each pixel area is not limited to a matrix form, and may be variously arranged in a stripe form, a pixel sharing form, a diamond form, and the like.

The diode driving circuit of each sub-pixel P has respective gate lines GL, data lines DL and power in pixel regions defined by respective gate lines GL1 to GLn and data lines DL1 to DLm. It is configured to be connected to the line PL. In addition, an organic light emitting diode is configured between the diode driving circuit and the first and second power signals VDD and GND.

The diode driving circuits supply the analog data signal from the connected data line DL to the light emitting diode, while allowing the analog data signal to be charged to maintain the light emission state.

The driving circuit unit 200 of the organic light emitting diode display applied to the mobile communication device includes gates and data lines GL1 to GLn of the image display panel 100 so that image data of red, green, and blue is displayed as images of every frame. DL1 to DLm).

Specifically, the driving circuit unit 200 generates gate control signals for driving the plurality of gate lines GL1 to GLn using at least one synchronization signal DCLK, Hsync, Vsync, DE. Then, a gate-on signal (for example, a gate voltage of low or high logic) is sequentially generated using the data control signal and output to the gate lines GL1 to GLn. Here, the gate-off voltage is supplied during a period in which the gate-on voltage is not supplied to the gate lines GL1 to GLn. Accordingly, the driving circuit unit 200 sequentially drives the diode driving circuits connected to the gate lines GL1 to GLn in units of each gate line GL.

In addition, the driving circuit unit 200 converts digital image data (RGB) input from the outside into an analog image signal using at least one synchronization signal (DCLK, Hsync, Vsync, DE). Specifically, the driving circuit unit 200 generates a gamma voltage set by subdividing the reference gamma voltages of a plurality of levels so as to correspond to the grayscale values (eg, 0 grayscale values to 255 grayscale values) of digital image data RGB. . Then, the digital image data (RGB) is converted into an analog image signal using a gamma voltage set. The converted analog image signals are sequentially supplied to each data line DL1 to DLm in units of horizontal lines and displayed as an image.

The driving circuit unit 200 generates gate and data control signals in response to a plurality of clock signals generated from external synchronizing signals (DCLK, Hsync, Vsync, DE) and internal oscillators, and generates gate and data lines GL1. To GLn, DL1 to DLm). Therefore, the driving circuit unit 200 is greatly affected by EMI generation due to phase overlap between the synchronization signals DCLK, Hsync, Vsync, DE and the self-generated high-frequency clock signals.

Accordingly, in the present invention, in order to prevent phase overlap between clock signals, the phase of the clock signal generated by a clock generator such as an oscillator is delayed and clock signals before and after the phase delay can be used in different loads or processing circuits. . In addition, clock signals having different phases are generated at different timings, and clock signals having different phases can be used for data processing. Hereinafter, a driving circuit unit according to an embodiment of the present invention will be described in more detail.

2 is a block diagram showing a driving circuit of the image display panel according to the first embodiment of the present invention.

The driving circuit unit 200 illustrated in FIG. 2 includes a first clock generator 11, a data encoding unit 201, a data processing unit 202, a first delay circuit unit 111, and a data decoding unit 203. .

Specifically, the first clock generator 11 generates a first clock signal CLK1 at a preset frequency and period, and generates the first clock signal CLK1 as a data encoding unit 201 and a first delay circuit unit ( 111).

The data encoding unit 201 encodes the image data RGB input from the outside in response to the first clock signal CLK1 input from the first clock generator 11. The data encoding unit 201 may store the image data RGB input from the outside in at least one horizontal line or frame unit in the internal memory according to the first clock signal CLK1 and transmit the image data RGB to the data processing unit 202.

The data processing unit 202 processes or compensates image data input through the data encoding unit 201 with a preset algorithm. The data processing unit 202 reads a compensation value for compensating for brightness or chromaticity of the image data from the internal memory, and compensates for the gradation value of the image data using the corresponding algorithm and the compensation value.

The first delay circuit unit 111 generates a second clock signal CLK2 by delaying the first clock signal CLK1 input from the first clock generator 11 for a period of a predetermined period. That is, the first delay circuit unit 111 delays the first clock signal CLK1 input in real time from the first clock generator 11 for a period of a predetermined 1/2 cycle or 1 cycle, and the delayed first The clock signal CLK1 is output as the second clock signal CLK2.

The phase of the second clock signal CLK2 output from the first delay circuit unit 111 is delayed for a period of 1/2 cycle or 1 cycle compared to the phase of the first clock signal CLK1, so that the second clock signal ( The phase of CLK2) may be output and maintained in an inverted state to that of the first clock signal CLK1. When the phases of the first clock signal CLK1 and the phases of the second clock signal CLK2 are output and maintained in an inverted state, EMI according to the first clock signal CLK1 and the second clock signal CLK2 is Can cancel each other.

The data decoding unit 203 may decode the compensated image data and transmit it to another internal memory or image processing circuit using the second clock signal CLK2 from the first delay circuit unit 111.

3 is a circuit diagram specifically showing the first delay circuit shown in FIG. 2. And, FIG. 4 is a waveform diagram showing a first clock signal output from the first clock generator shown in FIG. 3 and a second clock signal whose phase is delayed by the first delay circuit unit, respectively.

The first delay circuit 111 shown in FIG. 3 receives the first clock signal CLK1 through the first resistor element R1 to the inverting terminal (-), and non-inverted through the first capacitor C. The first clock signal CLK1 is input to the terminal (+), and the first clock signal CLK1 is delayed for a predetermined period and output according to a clock signal fed back through the second resistor element R2. And an amplifying element OP1.

The delay period of the first clock signal CLK1 of the amplifying element OP1 is a clock that is fed back through the variable resistance value of the third resistor element R3 and the second resistor element R2 connected in parallel to the non-inverting terminal +. It can be set by the period of the signal. Accordingly, the RC time constant according to the capacities of the first to third resistive elements R1 to R3 and the first capacitor C is the first time during the period d1 of 2/1 cycle or 1 cycle of the amplification element OP1. The clock signal CLK1 is set in advance so as to be delayed and output.

With this circuit configuration, the first delay circuit unit 111 delays the first clock signal CLK1 for 1/2 period or 1 period period d1 and outputs it as the second clock signal CLK2. As illustrated in FIG. 4, the phase of the first clock signal CLK1 and the phase of the second clock signal CLK2 may be output and maintained in an inverted state.

Therefore, the data encoding unit 201 encodes the image data RGB input from the outside using the first clock signal CLK1, and the data decoding unit 203 is out of phase with the first clock signal CLK1. Image data may be decoded using the second clock signal CLK2. In this way, since the data encoding unit 201 and the data decoding unit 203 use the first clock signal CLK1 and the second clock signal CLK2 whose phases are inverted to each other and the EMI is canceled, respectively, the data encoding unit ( Even if the 201) and the data decoding unit 203 are arranged adjacently, the influence of EMI can be minimized.

5 is a block diagram specifically showing various application examples of a driving circuit according to the present invention.

Referring first to FIG. 5 (a), the driving circuit unit 200 is not integrated and configured in a single chip form, and is divided into a plurality of first to second blocks BL1, BL2, and BL3 regions. It may be. For example, the driving circuit unit 200 is divided into respective integrated circuits, and is separated into different printed circuit boards or printed circuit films separated into first to second block areas BL1, BL2, and BL3. It can be mounted. In this case, a delay circuit unit for delaying and outputting the first clock signal CLK1 or the second clock signal CLK2 may be additionally configured in each integrated circuit. That is, the integrated circuit of the first block region BL1 generates and uses the first clock signal CLK1, and the second clock signal CLK2 that delays the first clock signal CLK1 is used as the second block region BL1. ). In addition, the integrated circuit of the second block region BL2 uses the second clock signal CLK2, and the third clock signal CLK3 delaying the second clock signal CLK2 is integrated in the third block region BL3. The clock signals can be delayed and transmitted in a manner that is transmitted to the circuit.

In addition, referring to FIG. 5 (b), the driving circuit units 200, 200 + 1 and 200 + 2 may be configured in plural rather than singular, and may be configured in different printed circuit boards or image display panels 100. That is, the plurality of driving circuit units 200, 200 + 1, and 200 + 2 may be separately configured on different printed circuit boards or image display panels 100 to drive the multi-type image display panel 100. have. Similarly, a delay circuit unit for delaying and outputting the first clock signal CLK1 or the second clock signal CLK2 may be additionally configured in the driving circuit units 200, 200 + 1, and 200 + 2. That is, the first driving circuit unit 200 generates and uses the first clock signal CLK1, and transmits the second clock signal CLK2 delaying the first clock signal CLK1 to the second driving circuit unit 200 + 1. Can be. In addition, the second driving circuit unit 200 + 1 uses the second clock signal CLK2 and transmits the third clock signal CLK3 delaying the second clock signal CLK2 to the third driving circuit unit 200 + 2. In this way, clock signals can be delayed and transmitted.

6 is another configuration diagram showing a driving circuit unit of the type shown in FIGS. 1 and 5 (a).

As shown in FIG. 6, the driving circuit unit 200 may further include a latch unit 204, a second delay circuit unit 222, a second data processing unit 205, and an output buffer unit 206.

Specifically, the latch unit 204 configured in the second block BL2 area may latch the image data into the latch memory using the second clock signal CLK2 output from the first delay circuit unit 111. Here, the latch unit 204 may latch the image data decoded by the data decoding unit 203 in at least one horizontal line in the latch memory.

The second delay circuit unit 222 generates a third clock signal CLK3 by delaying the phase of the second clock signal CLK2 output from the first delay circuit unit 111 for a predetermined period of time, and generates a third clock signal CLK3. The signal CLK3 is output to the second data processing unit 205.

The second data processing unit 205 may read the image data stored in the latch memory by at least one horizontal line by using the third clock signal CLK3, and convert the image data by at least one horizontal line into an analog image signal. . Accordingly, the analog image signals of at least one horizontal line may be transmitted to the data lines DL1 to DLm of the image display panel 100 through the output buffer unit 206.

7 is a waveform diagram showing the first clock signal generated by the first clock generator, the second clock signal phase-delayed by the first delay circuit unit, and the third clock signal phase-delayed by the second delay circuit unit, respectively.

Referring to FIG. 7, the second delay circuit unit 222 sets the second clock signal CLK2 input in real time from the first delay circuit unit 111 during a period d2 such as a preset 1/2 cycle or 1 cycle. By delaying, the delayed second clock signal CLK2 is output as the third clock signal CLK3.

Accordingly, the phase of the third clock signal CLK3 output from the second delay circuit unit 222 is delayed for a period d2 such as 1/2 cycle or 1 cycle compared to the phase of the second clock signal CLK2. The phase of the second clock signal CLK2 and the phase of the third clock signal CLK3 may be output and maintained in an inverted state. When the phase of the second clock signal CLK2 and the phase of the third clock signal CLK3 are output and maintained in an inverted state, EMI according to the second clock signal CLK2 and the third clock signal CLK3 is Can cancel each other.

8 is a block diagram illustrating a driving circuit portion of an image display panel according to a second embodiment of the present invention.

Referring to FIG. 8, the driving circuit unit 200 according to the second embodiment of the present invention includes a power input unit 301, a first power delay supply unit 310, a first amplification unit 211, and a second clock generation unit ( 22), a second power delay supply unit 320, a second amplifying unit 212, a third clock generator 33 further includes.

Specifically, the power input unit 301 configured in the first block BL1 region converts commercial power from the outside into rated power such as DC to generate a first power signal Vcc1. Accordingly, the power input unit 301 supplies the first power signal Vcc1 to the first clock generator 11 so that the first clock generator 11 is the first clock at the input timing of the first power signal Vcc1. It is driven to generate the signal CLK1.

The power input unit 301 supplies the first power signal Vcc1 to the first clock generator 11 and supplies it to the first power delay supply unit 310. The first clock generator 11 may transmit the first clock signal CLK1 to the first load unit 210 such as the data encoding unit 201.

The first power delay supply unit 310 delays the first power signal Vcc1 input from the power input unit 301 for a predetermined period and outputs the second power signal Vcc2. Specifically, the first power delay supply unit 310 delays the first power signal Vcc1 for a period of 1/2 cycle or 1 cycle of the first clock signal CLK1, and then the second power signal (Vcc2) is output.

The first amplifying unit 211 may amplify and output the voltage level of the second power signal Vcc2 output from the first power delay supply unit 310 to be the same as the voltage of the first power signal Vcc1. .

The second clock generator 22 configured in the second block BL2 region is second to the timing at which the second power signal Vcc2 is input from the first power delay supply unit 310 or the first amplification unit 211. The clock signal CLK2 is generated and output. The second clock generation unit 22 may transmit the second clock signal CLK2 to the second load unit 220 such as the data decoding unit 203.

The second power delay supply unit 320 receives the second power signal Vcc2 through the first power delay supply unit 310 or the first amplification unit 211. Accordingly, the second power delay supply unit 320 delays the second power signal Vcc2 input through the first power delay supply unit 310 or the first amplification unit 211 for a predetermined period to thereby generate a third power signal ( Vcc3). Specifically, the second power delay supply unit 320 delays the second power signal Vcc2 for a period of 1/2 cycle or 1 cycle of the second clock signal CLK2, and then the third power signal (Vcc3) is output.

The second amplifying unit 212 may amplify and output the voltage level of the third power signal Vcc3 output from the second power delay supply unit 320 to be the same as the voltage of the second power signal Vcc2. .

The third clock generator 33 configured in the third block BL3 region is third at a timing at which the third power signal Vcc3 is input from the second power delay supply unit 320 or the second amplification unit 212. The clock signal CLK3 is generated and output. The third clock generator 33 may transmit the third clock signal CLK3 to the third load unit 230 such as the latch unit 204.

9 is a waveform diagram illustrating first to third power signals and first to third clock signals of FIG. 8, respectively.

Referring to FIG. 9, the first clock generator 11 generates a first clock signal CLK2 at the input timing of the first power signal Vcc1 from the power input unit 301. Accordingly, the timing of outputting the first power signal Vcc1 of the power input unit 301 and the timing of outputting the first clock signal CLK2 of the first clock generator 11 are synchronized.

The second power delay supply unit 320 may transmit the first power signal Vcc1 input from the power input unit 301 for a period d1 of one cycle of one half cycle or one cycle of the first clock signal CLK1. After the delay, the second power signal Vcc2 is generated and transmitted to the second clock generator 22.

Therefore, in response to the input timing of the second power signal Vcc2 input to the second clock generator 22, the second clock generator 22 is 1/2 cycle or 1 cycle from the first clock signal CLK1. The second clock signal CLK2 is output after being delayed for a period d1 of one of the periods.

Thereafter, the third power delay supply unit 330 also delays the second power signal Vcc2 for a period d2 of 1/2 cycle or 1 cycle of the second clock signal CLK2, and then the third power The signal Vcc3 is generated and transmitted to the third clock generator 33.

Accordingly, in response to the input timing of the third power signal Vcc3 input to the third clock generator 33, the third clock generator 33 is 1/2 cycle or more than the second clock signal CLK2. The third clock signal CLK3 is output after being delayed for a period d2 of any one period.

Thus, according to the second embodiment of the present invention, the first to third power delay supply units 310, 320, and 330 sequentially delay the power signals Vcc1, Vcc2, Vcc3, respectively, and then each of the first to third clock generators By transmitting to (11,22,33), each of the first to third clock generators 11,22,33 can sequentially output the first to third clock signals CLK1 to CLK3. Accordingly, only the first to third power delay supply units 310, 320 and 330, which are supplied by simply supplying power by delay, are added, so that each of the first to third clock generators 11, 22, and 33 have different phases at different timings. The first to third clock signals CLK1 to CLK3 may be generated.

10 is a block diagram showing a driving circuit part of an image display panel according to a third embodiment of the present invention.

Referring to FIG. 10, the driving circuit unit 200 modulates the energy spectrums of the first to third clock signals CLK1 to CLK3 by using RC time constants of different RC circuits, respectively, so that the first to third load units ( 210,220,230 further includes first to third filter units F1, F2, and F3.

Specifically, the first filter unit F1 modulates the energy spectrum of the first clock signal CLK1 generated by the first clock generator 11 using the first RC time constant of the first RC circuit. The energy spectrum modulated first clock signal CLK1 is transmitted to a first load unit 210 such as a data encoding unit 201.

The second filter unit F2 modulates the energy spectrum of the second clock signal CLK2 using the second RC time constant of the second RC circuit. The energy spectrum modulated second clock signal CLK2 is transmitted to a second load unit 220 such as a data decoding unit 203.

The third filter unit F3 modulates the energy spectrum of the third clock signal CLK3 using the third RC time constant of the third RC circuit. Then, the third clock signal CLK3 having the modulated energy spectrum is transmitted to the third load unit 230 such as the latch unit 204.

11 is a circuit diagram specifically illustrating the first to third filter units illustrated in FIG. 10. 12 is a graph showing the energy attenuation characteristics of each of the first to third filter units shown in FIG. 1 and the energy spectrums of the first to third clock signals.

11 (a) The first filter unit F1 has a first clock signal CLK1 in parallel with the first resistor element R1 and the first resistor element R1 connected in series to the first clock signal CLK1 transmission line. ) A first RC circuit including a first capacitor (C1) connected between the transmission line and the low potential voltage stage. Accordingly, the first filter part F1 is the first RC time constant is set according to the capacity of the first resistor element R1 and the first capacitor C1 composed of the first RC circuit, and according to the first RC time constant The energy spectrum of the first clock signal CLK1 is modulated and output.

Accordingly, according to the filtering energy attenuation characteristic of the first filter unit F1 shown in FIG. 12 (a), the energy spectrum of the first clock signal CLK1 output through the first filter unit F1 has a specific frequency ( MHz) The energy is variable and attenuated in units of a period and output. The first RC time constant may be set to be the lowest in the 200 MHz (f2) period fa among the preset frequency periods (for example, 100 MHz (f1), 200 MHz (f2), and 300 MHz (f3)) periods.

Accordingly, the energy (xdBm) for each clock pulse of the first clock signal CLK1 output through the first filter unit F1 is varied in period units of 100 MHz (f1), 200 MHz (f2), and 300 MHz (f3). It may be output to attenuate the lowest in the 200MHz (f2) period.

11 (b) The second filter unit F2 is provided in parallel with the first and second resistance elements R1 and R2 connected to the second clock signal CLK2 transmission line, and the first resistance element R1. 2 clock signal CLK2 and a second RC circuit including a first capacitor C1 connected between a transmission line and a low potential voltage stage. Accordingly, the second filter part F2 is configured with a second RC time constant according to the capacities of the first and second resistor elements R1 and R2 and the first capacitor C1 composed of the second RC circuit, and the second The energy spectrum of the second clock signal CLK2 is modulated and output according to the RC time constant.

Accordingly, according to the filtering energy attenuation characteristic of the second filter unit F2 shown in FIG. 12 (b), the energy spectrum of the second clock signal CLK2 output through the second filter unit F2 has a specific frequency ( MHz) The energy is variable and attenuated in units of a period and output. For example, the second RC time constant may be set to be the lowest in a 100 MHz (f2) period fb of a preset frequency period (eg, 100 MHz (f1), 200 MHz (f2), 300 MHz (f3)) period Can be.

Accordingly, the energy (xdBm) for each clock pulse of the second clock signal CLK2 output through the second filter unit F2 is varied in period units of 100 MHz (f1), 200 MHz (f2), and 300 MHz (f3). It may be output so as to be the lowest attenuation in the 100MHz (f1) period.

11 (c) The third filter unit F3 includes first resistor elements R1 and R2 connected in series to the third clock signal CLK3 transmission line, and first and second ends of the first resistor element R1. And a third RC circuit including first and second capacitors C1 and C2 connected in parallel with the resistance element R1. Thus, the third filter unit F3 is a third RC time constant is set according to the capacity of the first resistor element R1 and the first and second capacitors C1 and C2 composed of the third RC circuit, and the third The energy spectrum of the third clock signal CLK3 is modulated and output according to the RC time constant.

Accordingly, according to the filtering energy attenuation characteristics of the third filter unit F3 illustrated in FIG. 12 (c), the energy spectrum of the third clock signal CLK3 output through the third filter unit F3 is a specific frequency ( MHz) The energy is variable and attenuated in units of a period and output. For example, the third RC time constant may be set to be lowest in a 300 MHz (f3) period (fc) of a preset frequency period (eg, 100 MHz (f1), 200 MHz (f2), 300 MHz (f3)) period Can be.

Accordingly, the energy (xdBm) for each clock pulse of the third clock signal CLK3 output through the third filter unit F3 is varied in cycle units of 100 MHz (f1), 200 MHz (f2), and 300 MHz (f3). It may be output to be the lowest attenuation in the 300MHz (f3) period.

like this. The driving circuit unit 200 may modulate the energy spectrums of the first to third clock signals CLK1 to CLK3, respectively, by using the first to third filter units F1, F2, and F3 having different RC circuits. . Accordingly, EMI interference can be reduced by allowing clock signals having different energy spectrums to be used in different loads or circuits.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications and changes are possible without departing from the technical details of the present invention. It will be clear to those who have the knowledge of Therefore, the scope of the present invention is indicated by the following claims, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted to be included in the scope of the present invention.

100: video display panel
111: first delay circuit unit
200: driving circuit part
201: data encoding unit
202: first data processing unit
203: data decoding unit
204: latch part
205: second data processing unit
206: output buffer unit
222: first delay circuit unit
300: power supply

Claims (13)

In the driving circuit for driving the gate and data lines of the video display panel,
The driving circuit part
A first clock generator which generates a first clock signal at a preset frequency and period and outputs the first clock signal to a first load unit;
And a first delay circuit unit generating a second clock signal by delaying a phase of the first clock signal output from the first clock generator for a predetermined period and transmitting the second clock signal to a second load unit.
The driving circuit portion of the video display panel.
According to claim 1,
The first delay circuit unit
The first clock signal is input to the inverting terminal through the first resistor element, and the first clock signal is input to the non-inverting terminal through the first capacitor, and according to the clock signal fed back through the second resistor element. And an amplifying element for delaying and outputting the first clock signal for a predetermined period,
The first clock signal delay period of the amplification element is preset by a variable resistance value of a third resistance element connected in parallel to the non-inverting terminal and a period of a clock signal fed back through the second resistance element,
The driving circuit portion of the video display panel.
According to claim 1,
The driving circuit part
A third load unit that latches image data into a latch memory by using a second clock signal output from the first delay circuit unit;
A second delay circuit unit delaying a phase of the second clock signal output from the first delay circuit unit for a predetermined period to generate a third clock signal and outputting the generated third clock signal; And
And a data processing unit to output the latched image data to the outside using a third clock signal output from the second delay circuit unit.
The driving circuit portion of the video display panel.
The method of claim 3,
The first delay circuit unit
The first clock signal is delayed for a period of one of 1/2 preset periods or 1 period, and is output as the second clock signal.
The second delay circuit unit
The second clock signal is delayed for a period of one of 1/2 preset periods or 1 period and output as the third clock signal.
The driving circuit portion of the video display panel.
According to claim 1,
A power input unit supplying a first power signal to the first clock generator to control the first clock generator to generate the first clock signal at the first power signal supply timing;
A first power delay supply unit delaying the first power signal input from the power input unit for a predetermined period and outputting the second power signal as a second power signal; And
Further comprising a second clock generator for outputting a second clock signal at a timing at which the second power signal is input through the first power delay supply unit,
The driving circuit portion of the video display panel.
The method of claim 5,
A second power delay supply unit delaying the second power signal input from the first power delay supply unit for a predetermined period and outputting the second power signal as a third power signal; And
Further comprising a third clock generator for outputting a third clock signal at a timing at which the third power signal is input through the second power delay supply unit,
The driving circuit portion of the video display panel.
The method of claim 6,
The first power delay supply unit
The first power signal is delayed for a period of 1/2 cycle or 1 cycle of the first clock signal, and then output as the second power signal.
The second power delay supply unit outputs the second power signal as the third power signal after delaying for a period of 1/2 cycle or 1 cycle of the second clock signal.
The driving circuit portion of the video display panel.
The method of claim 6,
An energy spectrum of the first clock signal generated by the first clock generator and modulated using a first RC time constant of the first RC circuit, and transmitting the first clock signal modulated with the energy spectrum to a first load unit 1 filter unit;
A second filter unit for modulating the energy spectrum of the second clock signal using a second RC time constant of the second RC circuit and transmitting the second clock signal modulated with the energy spectrum to a second load unit; And
Further comprising a third filter unit for modulating the energy spectrum of the third clock signal using a third RC time constant of the third RC circuit, and transmitting the third clock signal modulated by the energy spectrum to a third load unit,
The driving circuit portion of the video display panel.
An image display panel in which a plurality of sub-pixels are disposed at intersections of the gate and the data line to display an image;
The gate and data lines are controlled using the synchronization signals from the outside and at least one clock signal, and the first to delay the at least one clock signal phase or generate a plurality of clock signals having different phases. It comprises the drive circuit part in any one of Claims 8 thru | or 8,
Video display device.
In the driving circuit for driving the gate and data lines of the video display panel,
The driving circuit part
The energy spectrum of the first clock signal input from an external or first clock generator is modulated using a first RC time constant of the first RC circuit, and the first clock signal modulated with the energy spectrum is transmitted to a first load unit A first filter unit;
The energy spectrum of the second clock signal input from the external or second clock generator is modulated using a second RC time constant of the second RC circuit, and the second clock signal modulated with the energy spectrum is transmitted to the second load unit A second filter unit; And
The energy spectrum of the third clock signal input from the external or third clock generator is modulated using a third RC time constant of the third RC circuit, and the third clock signal modulated with the energy spectrum is transmitted to a third load unit. Including a third filter unit,
The driving circuit portion of the video display panel.
The method of claim 10,
The first RC circuit
A first resistor element connected in series with a first clock signal transmission line, and a first capacitor connected between the first clock signal transmission line and a low potential voltage stage in parallel with the first resistance element,
The second RC circuit
First and second resistance elements connected in series to the second clock signal transmission line, and first capacitors connected between the second clock signal transmission line and the low potential voltage stage in parallel with the first resistance element, ,
The third RC circuit
A first resistor element connected in series with the third clock signal transmission line, and first and second capacitors connected in parallel with the first resistor element at front and rear ends of the first resistor element,
The driving circuit portion of the video display panel.
The method of claim 9,
The first RC time constant is set so that the energy for each clock pulse of the first clock signal is variable in preset first to third period units, and is output at the lowest attenuation in the second period among the first to third periods. ,
The second RC time constant is set such that the energy of each clock pulse of the second clock signal is varied in preset first to third period units, and is output at the lowest attenuation in the first period among the first to third periods. ,
The third RC time constant is set so that the energy for each clock pulse of the third clock signal is variable in preset first to third period units, and is set to be output with the lowest attenuation in the third period among the first to third periods.
The driving circuit portion of the video display panel.
An image display panel in which a plurality of sub-pixels are disposed at intersections of the gate and the data line to display an image;
Controlling the gate and data line using the external synchronization signals and a plurality of clock signals, and modulating and outputting the energy spectrum for each of the plurality of clock signals, any one of the 10th to 12th terms. Including the drive circuit portion described in,
Video display device.

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