KR20200043999A - Imaging elements, stacked imaging elements and solid-state imaging devices - Google Patents

Abstract

The solid-state imaging element has a pixel having a first imaging element, a second imaging element, a third imaging element, and an on-chip micro-lens 90, and the first imaging element includes a first electrode 11 and a third An electrode 12 and a second electrode 16 are provided, and the pixels are provided in a third electrode control line (VOA) connected to the third electrode 12, a second imaging element and a third imaging element. A plurality of control lines 62B, which are connected to each of the transistors and different from the third electrode control line VAO, are also provided, and the pixel has a center of the on-chip micro-lens 90 provided in the pixel, The distance between any one of the plurality of control lines 62B provided in the pixel is the center of the on-chip micro lens 90 provided in the pixel and the third electrode control line provided in the pixel ( VOA).

Description

Imaging elements, stacked imaging elements and solid-state imaging devices

The present disclosure relates to an imaging device, a stacked imaging device, and a solid-state imaging device.

An imaging element using an organic semiconductor material for the photoelectric conversion layer can photoelectrically convert a specific color (wavelength band). And, since it has such characteristics, when used as an imaging element in a solid-state imaging device, a sub-pixel is formed by a combination of an on-chip color filter (OCCF) and an imaging element, and the sub-pixels are two-dimensionally arranged. It is possible to obtain a structure in which subpixels are stacked (stacked image pickup device), which is impossible with a conventional solid-state imaging device (for example, see Japanese Patent Application Laid-Open No. 2011-138927). In addition, there is an advantage that false color does not occur by not requiring a demosaicing treatment. In addition, in the following description, an imaging element provided with a photoelectric conversion portion provided on or above a semiconductor substrate is referred to as " first type imaging element " for convenience, and a photoelectric conversion portion constituting the first type imaging element, For convenience, the " first type photoelectric conversion unit ", and the imaging element provided in the semiconductor substrate, for convenience, is referred to as " second type imaging element ", and the photoelectric conversion unit constituting the second type imaging element, for convenience, Sometimes referred to as "second type photoelectric conversion unit".

Fig. 60 shows a structural example of a conventional stacked imaging device (stacked solid-state imaging device). In the example shown in FIG. 60, in the semiconductor substrate 370, a third photoelectric conversion unit that is a second type of photoelectric conversion unit constituting the third imaging device 330 and the second imaging device 320 that are second type imaging devices. The conversion unit 331 and the second photoelectric conversion unit 321 are stacked and formed. In addition, a first photoelectric conversion unit 311 that is a first type photoelectric conversion unit is disposed above the semiconductor substrate 370 (specifically, above the second imaging element 320). Here, the first photoelectric conversion unit 311 includes a first electrode 311, a photoelectric conversion layer 315 made of an organic material, and a second electrode 311, and is a first type of imaging device. The imaging element 310 is configured. In the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331, for example, blue and red light, respectively, are photoelectrically converted by differences in absorption coefficients. In addition, in the first photoelectric conversion unit 311, for example, green light is photoelectrically converted.

After the charges generated by the photoelectric conversion in the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331 are accumulated once in the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331 , Respectively, the second floating diffusion layer (FD ₂ ) and the third floating diffusion layer (FD ₃ ) by the vertical transistor (showing the gate portion 322) and the transfer transistor (showing the gate portion 332) ), And output to an external read circuit (not shown). These transistors and floating diffusion layers FD ₂ and FD ₃ are also formed on the semiconductor substrate 370.

The charge generated by the photoelectric conversion in the first photoelectric conversion unit 311 is accumulated in the first floating diffusion layer FD ₁ formed on the semiconductor substrate 370 through the contact hole portion 361 and the wiring layer 362. In addition, the first photoelectric conversion unit 311 is also connected to the gate portion 318 of the amplifying transistor that converts the amount of charge into a voltage through the contact hole portion 361 and the wiring layer 362. Then, the first floating diffusion layer FD ₁ constitutes a part of the reset transistor (showing the gate portion 317). Further, reference numeral 371 is an element isolation region, reference numeral 372 is an oxide film formed on the surface of the semiconductor substrate 370, reference numerals 376 and 381 are interlayer insulating layers, reference numeral 383 is a protective layer, and reference numeral 390 is It is an on-chip micro lens.

Patent Document 1: Special Patent 2011-138927

By the way, after the electric charges generated by the photoelectric conversion in the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331 are accumulated once in the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331 , It is transmitted to the second floating diffusion layer (FD ₂ ) and the third floating diffusion layer (FD ₃ ). Therefore, the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331 can be completely depleted. However, the charge generated by the photoelectric conversion in the first photoelectric conversion unit 311 directly accumulates in the first floating diffusion layer FD ₁ . Therefore, it is difficult to completely deplete the first photoelectric conversion unit 311. And as a result of the above, kTC noise becomes large, random noise deteriorates, and image quality deteriorates. In addition, there is a strong demand for transferring the charges generated by the photoelectric conversion in the first photoelectric conversion unit 311 more easily and reliably. Furthermore, there is also a strong demand for the configuration, simplification of structure, and miniaturization in a pixel region in which a plurality of imaging elements are arranged.

Therefore, the first object of the present disclosure is an imaging element in which a photoelectric conversion section is disposed above or above a semiconductor substrate, and it is possible to suppress the deterioration of image quality, and furthermore, the charge generated by photoelectric conversion can be further easily performed. Moreover, it is providing the solid-state imaging device provided with the imaging element of the structure and structure which makes it possible to transmit reliably, the laminated imaging element comprised of these imaging elements, these imaging elements, or the laminated imaging element. In addition, a second object of the present disclosure is an imaging element in which a photoelectric conversion section is disposed above or above a semiconductor substrate, which has a plurality of imaging elements capable of suppressing deterioration of imaging quality, and in addition, a plurality of imaging elements are arranged. It is to provide a solid-state imaging device capable of simplifying and miniaturizing the structure and structure in a pixel region.

The imaging elements according to the first aspect to the sixth aspect of the present disclosure for achieving the above-described first object,

The first electrode, the photoelectric conversion layer and the second electrode is provided with a photoelectric conversion unit made of a stack,

The photoelectric conversion unit is further provided with an electrode for electric charge accumulation, which is disposed apart from the first electrode and is disposed to face the photoelectric conversion layer through an insulating layer.

The photoelectric conversion section is composed of N (however, N≥2) photoelectric conversion section segments,

The photoelectric conversion layer is composed of N photoelectric conversion layer segments,

The insulating layer is composed of N insulating layer segments,

In the imaging elements according to the first to third aspects of the present disclosure, the electrode for charge accumulation is composed of N electrode segments for charge accumulation,

In the imaging elements according to the fourth to fifth aspects of the present disclosure, the electrodes for accumulating charges are composed of N electrode segments for accumulating charges, which are disposed apart from each other,

The n-th (however, n = 1, 2, 3 ... N) photoelectric conversion section segments are the n-th charge accumulation electrode segment, the n-th insulating layer segment, and the n-th photoelectric conversion layer segment. Is composed,

The larger the value of n is, the larger the segment of the photoelectric conversion part is, which is located away from the first electrode.

In the imaging device according to the first aspect of the present disclosure, the thickness of the insulating layer segment gradually changes from the first photoelectric conversion section segment to the Nth photoelectric conversion section segment.

In addition, in the imaging device according to the second aspect of the present disclosure, the thickness of the photoelectric conversion layer segment gradually changes from the first photoelectric conversion section segment to the Nth photoelectric conversion section segment.

In addition, in the imaging element according to the third aspect of the present disclosure, adjacent

In the photoelectric conversion section segment, the materials constituting the insulating layer segment are different.

In addition, in the imaging element according to the fourth aspect of the present disclosure, the materials constituting the electrode segments for charge accumulation are different in the adjacent photoelectric conversion section segments.

In addition, in the imaging element according to the fifth aspect of the present disclosure, the area of the electrode segment for charge accumulation gradually decreases from the first photoelectric conversion section segment to the Nth photoelectric conversion section segment. In addition, the area may be continuously small or may be small in the shape of a staircase.

A sixth aspect of the present disclosure for achieving the above first object,

The first electrode, the photoelectric conversion layer and the second electrode is provided with a photoelectric conversion unit made of a stack,

The photoelectric conversion unit is further provided with an electrode for electric charge accumulation, which is disposed apart from the first electrode and is disposed to face the photoelectric conversion layer through an insulating layer.

When the stacking direction of the electrode for accumulating charge, the insulating layer and the photoelectric conversion layer is set to the Z direction, and the direction from the first electrode to the X direction, the stacking of the charge accumulating electrode, the insulating layer and the photoelectric conversion layer in the YZ virtual plane is stacked. The cross-sectional area of the laminated portion at the time of cutting the portion varies depending on the distance from the first electrode. Further, the change in the cross-sectional area may be a continuous change or a step-like change.

The stacked-type imaging element of the present disclosure for achieving the above-mentioned first object has at least one imaging element according to the first to sixth aspects of the present disclosure.

A solid-state imaging device according to a first aspect of the present disclosure for achieving the above-described second object,

The first electrode, the photoelectric conversion layer and the second electrode is provided with a photoelectric conversion unit made of a stack,

The photoelectric conversion section further has a plurality of imaging elements provided with electrodes for charge accumulation, which are disposed spaced apart from the first electrode and are arranged to face the photoelectric conversion layer through an insulating layer,

The imaging element block is composed of a plurality of imaging elements,

The first electrode is shared by a plurality of imaging elements constituting the imaging element block.

The solid-state imaging device according to the second aspect of the present disclosure for achieving the second object described above has a plurality of imaging elements according to the first to seventh aspects of the present disclosure,

The imaging element block is composed of a plurality of imaging elements,

The first electrode is shared by a plurality of imaging elements constituting the imaging element block.

The solid-state imaging device according to the third aspect of the present disclosure for achieving the above-described first object is provided with a plurality of imaging elements according to the first to sixth aspects of the present disclosure. In addition, the solid-state imaging device according to the fourth aspect of the present disclosure for achieving the above-described first object includes a plurality of stacked-type imaging devices of the present disclosure.

In addition, the solid-state imaging device of the present disclosure,

A first imaging element,

A second imaging element,

A first transfer transistor, a first reset transistor, and a first selection transistor electrically connected to the second imaging element;

A third imaging element,

A second transfer transistor, a second reset transistor, and a second selection transistor electrically connected to the third imaging element,

Has a pixel with on-chip micro-lens,

The first imaging element includes a first electrode, a third electrode, and a second electrode opposite to the first and third electrodes,

The pixel,

A third electrode control line connected to the third electrode,

Connected to each of the first transfer transistor, the first reset transistor, the first select transistor, the second transfer transistor, the second reset transistor, and the second select transistor, and the third electrode It is also provided with a plurality of control lines, different from the control lines,

In addition, the pixel,

The distance between the center of the on-chip micro-lens provided in the pixel and any one of the plurality of control lines provided in the pixel is provided in the center of the on-chip micro-lens provided in the pixel and the pixel. Is smaller than the distance between the third electrode control lines. In this way, by arranging the third electrode control line in a region as far as possible from the center of the on-chip / micro-lens, the second imaging element and the second imaging element by the third electrode control line are produced, compared to the solid-state imaging device without this structure. 3 Inhibition of the incidence of light into the imaging element does not occur, and the sensitivity of the solid-state imaging device can be increased.

In addition, in the solid-state imaging device of the present disclosure,

The pixel,

A first imaging element,

A second imaging element,

A third imaging element,

With on-chip micro-lens,

The distance (d4) between the center of the first electrode inscribed circle and the center of the on-chip / micro-lens, or the distance (d5) between the center of the floating diffusion region inscribed and the center of the on-chip / micro-lens, and the center of the electrode inscribed for charge accumulation The distance (d1) between the on-chip micro-lens center, the distance (d2) between the second imaging element inscribed circle center and the on-chip micro-lens center, and the third imaging element inscribed circle center and the on-chip micro-lens The distance d3 between the centers is small. Thus, by arranging the floating diffusion region or the first electrode as far as possible from the on-chip, micro-lens center, the area of the second imaging element and the third imaging element is larger than that of the solid-state imaging device without this structure. It is possible to increase the sensitivity of the solid-state imaging device.

In addition, the solid-state imaging device of the present disclosure,

A first imaging element,

A first floating diffusion region electrically connected to the first imaging element,

A second imaging element,

A second floating diffusion region electrically connected to the second imaging element,

A third imaging element,

A third floating diffusion region electrically connected to the third imaging element,

Has a pixel with on-chip micro-lens,

The first imaging element includes a first electrode, a third electrode, and a second electrode opposite to the first and third electrodes,

Any of the centers of each of the first to third floating diffusion layers,

Outside the inscribed circle of the third electrode, or

Outside the outline of the third electrode, or

It is arranged outside the circumscribed circle of the third electrode. In this way, by placing the floating diffusion region as far as possible from the center of the on-chip / micro-lens L, the third electrode, the second imaging element, and the third imaging element are compared to the solid-state imaging device without this structure. The area of can be increased, and the sensitivity of the solid-state imaging device can be increased.

In addition, the solid-state imaging device of the present disclosure,

A first imaging element,

A second imaging element,

A first transfer transistor, a first reset transistor, and a first selection transistor electrically connected to the second imaging element;

A third imaging element,

A second transfer transistor, a second reset transistor, and a second selection transistor electrically connected to the third imaging element,

Has a pixel with on-chip micro-lens,

The first imaging element includes a first electrode, a third electrode, and a second electrode opposite to the first and third electrodes,

The channel length that becomes the minimum in the first and second transfer transistors, the first and second reset transistors, and the first and second selection transistors is smaller than the minimum distance between the third electrode and the first electrode. short. As described above, by arranging the floating diffusion region as far as possible from the center of the on-chip / micro-lens, the area of the third electrode, the second imaging element, and the third imaging element is higher than that of the solid-state imaging device without this structure. It can be enlarged, and the sensitivity of the solid-state imaging device can be increased.

In addition, the solid-state imaging device of the present disclosure,

Within the pixel,

A first imaging element,

A second imaging element,

A third imaging element,

With on-chip micro-lens,

The first imaging element,

A first electrode, a third electrode, and a second electrode opposite to the first and third electrodes are provided.

The area of the third electrode is larger than that of the third imaging element. Thus, by making the area of the third electrode larger than the area of the third imaging element, the sensitivity to green light can be made higher than that of the solid-state imaging device without this structure. Moreover, it is preferable that the area of the third electrode is smaller than that of the second imaging element.

An imaging device according to the first to sixth aspects of the present disclosure, an imaging device of the present disclosure constituting the stacked imaging device of the present disclosure, and a solid-state imaging device according to the first to fourth aspects of the present disclosure. In the imaging device of the present disclosure, the photoelectric conversion unit is irradiated with light because an electrode for electric charge accumulation is disposed spaced apart from the first electrode and disposed opposite to the photoelectric conversion layer through the insulating layer. , When photoelectric conversion is performed in the photoelectric conversion unit, charges of the photoelectric conversion layer may be accumulated. Therefore, at the start of exposure, it becomes possible to completely deplete the charge accumulation portion and erase the charge. As a result, it is possible to suppress the occurrence of a phenomenon that kTC noise becomes large, random noise deteriorates, and image quality deteriorates. In addition, in the imaging elements according to the first to sixth aspects of the present disclosure, the multilayered imaging elements of the present disclosure to which these imaging elements are applied, or the solid-state imaging devices according to the first to fourth aspects of the present disclosure , The thickness of the insulating layer segment is defined, or the thickness of the photoelectric conversion layer segment is defined, or the materials constituting the insulating layer segment are different, or the materials constituting the electrode segment for charge accumulation are different, , Or In addition, since the area of the electrode segment for accumulating charge is defined, or, in addition, the cross-sectional area of the stacked portion is defined, a kind of charge transfer gradient is formed, so that the charge generated by photoelectric conversion can be easily and , Surely, it becomes possible to transfer to the first electrode. And, as a result, generation of an afterimage or generation of a transfer residue can be prevented. Furthermore, in the solid-state imaging device according to the first aspect to the second aspect of the present disclosure, since the first electrodes are shared by a plurality of imaging elements constituting the imaging element block, a pixel region in which a plurality of imaging elements are arranged It is possible to simplify and refine the structure and structure in. In addition, the effects described in the present specification are merely examples and are not limited, and may have additional effects.

1 is a schematic partial cross-sectional view of the imaging device of Example 1 and a stacked imaging device.
FIG. 2 is a schematic partial cross-sectional view of an enlarged portion of a charge accumulation electrode, a photoelectric conversion layer, and a second electrode stacked in the imaging device of Example 1. FIG.
3 is an equivalent circuit diagram of the imaging device of Example 1 and a stacked imaging device.
4 is an equivalent circuit diagram of the imaging device of Example 1 and a stacked imaging device.
5 is a schematic layout view of a transistor constituting a first electrode constituting the imaging element of Example 1, an electrode for charge accumulation, and a control unit.
Fig. 6 is a diagram schematically showing the state of potential at each site during operation of the imaging device of Example 1;
7 is a schematic arrangement diagram of a first electrode and an electrode for charge accumulation constituting the imaging element of Example 1. FIG.
8 is a schematic perspective perspective view of a first electrode, a charge storage electrode, a second electrode, and a contact hole portion constituting the imaging device of Example 1. FIG.
9 is a conceptual diagram of the solid-state imaging device of Example 1. FIG.
10 is an equivalent circuit diagram of a modification example of the imaging element of Example 1 and a stacked image pickup element.
FIG. 11 is a schematic layout view of a transistor constituting a first electrode, a charge storage electrode, and a control unit constituting a modification of the imaging device of Example 1 shown in FIG. 10;
Fig. 12 is a schematic partial cross-sectional view of an enlarged portion of a charge accumulation electrode, a photoelectric conversion layer, and a second electrode stacked in the imaging device of Example 2;
13 is a schematic partial cross-sectional view of the imaging device of Example 3 and a stacked imaging device.
14 is a schematic partial cross-sectional view of the imaging device of Example 4 and Example 5 and a stacked imaging device.
15A and 15B are schematic plan views of an electrode segment for charge accumulation in Example 5;
16A and 16B are schematic plan views of electrode segments for charge accumulation in Example 5. FIG.
17 is an equivalent circuit diagram of the imaging device of Example 5 and a stacked imaging device.
18 is an equivalent circuit diagram of the imaging device of Example 5 and a stacked imaging device.
19 is a schematic layout view of a transistor constituting a first electrode constituting the imaging element of Example 5, an electrode for charge accumulation, and a control unit.
Fig. 20 is a diagram schematically showing the state of potential at each site during operation of the imaging element of Example 5;
Fig. 21 is a diagram schematically showing the state of dislocations at each site during another operation (transmission) of the imaging device of Example 5;
22 is a schematic layout view of a first electrode and a charge storage electrode constituting a modification of the imaging element of Example 5. FIG.
23 is a schematic partial cross-sectional view of the imaging device of Example 6 and Example 5 and a stacked imaging device.
24A and 24B are schematic plan views of an electrode segment for charge accumulation in Example 6;
25 is a schematic plan view of a first electrode and an electrode segment for charge accumulation in the solid-state imaging device of Example 7. FIG.
26 is a schematic plan view of the first electrode and the electrode segment for charge accumulation in the first modification of the solid-state imaging device of Example 7. FIG.
27 is a schematic plan view of a first electrode and an electrode segment for charge accumulation in a second modification of the solid-state imaging device of Example 7. FIG.
28 is a schematic plan view of a first electrode and an electrode segment for charge accumulation in a third modification of the solid-state imaging device of Example 7. FIG.
29 is a schematic plan view of a first electrode and an electrode segment for charge accumulation in a fourth modification of the solid-state imaging device of Example 7. FIG.
30 is a schematic plan view of the first electrode and the electrode segment for charge accumulation in the fifth modification of the solid-state imaging device of Example 7. FIG.
31 is a schematic plan view of a first electrode and an electrode segment for charge accumulation in a sixth modification of the solid-state imaging device of Example 7. FIG.
32 is a schematic plan view of a first electrode and an electrode segment for charge accumulation in a seventh modification of the solid-state imaging device of Example 7. FIG.
33 is a schematic plan view of the first electrode and the electrode segment for charge accumulation in the eighth modification of the solid-state imaging device of Example 7. FIG.
34 is a schematic plan view of the first electrode and the electrode segment for charge accumulation in the ninth modification of the solid-state imaging device of Example 7. FIG.
35A, 35B, and 35C are charts showing read driving examples in the imaging element block of Example 7. FIG.
36 is a schematic plan view of a first electrode and an electrode segment for charge accumulation in the solid-state imaging device of Example 8. FIG.
37 is a schematic plan view of a first electrode and an electrode segment for charge accumulation in a modification of the solid-state imaging device of Example 8. FIG.
38 is a schematic plan view of a first electrode and an electrode segment for charge accumulation in a modification of the solid-state imaging device of Example 8. FIG.
39 is a schematic plan view of a first electrode and an electrode segment for charge accumulation in a modification of the solid-state imaging device of Example 8. FIG.
40 is a schematic partial cross-sectional view of the imaging device of Example 9 and a stacked imaging device.
41 is a schematic partial cross-sectional view of the imaging device of Example 10 and a stacked imaging device.
42 is a schematic partial cross-sectional view of a modification example of the imaging element of Example 10 and a stacked image pickup element.
43 is a schematic partial cross-sectional view of another modification of the imaging element of Example 10;
44 is a schematic partial cross-sectional view of still another modification of the imaging element of Example 10;
45 is a schematic partial cross-sectional view of a part of the imaging device of Example 11 and a stacked imaging device.
46 is a schematic layout view of a first electrode, a charge accumulation electrode, and a charge discharge electrode constituting the imaging element of Example 11. FIG.
Fig. 47 is a schematic perspective perspective view of a first electrode, a charge accumulation electrode, a charge discharge electrode, a second electrode, and a contact hole portion constituting the imaging element of Example 11.
48 is a schematic partial cross-sectional view of another modification example of the image pickup device of Example 1 and a stacked image pickup device.
49 is a schematic partial cross-sectional view of still another modification example of the imaging device of Example 1 and a stacked imaging device.
50A, 50B, and 50C are schematic partial cross-sectional views, in which the imaging element of Example 1, a portion of the first electrode of another modification of the stacked imaging element, and the like are enlarged.
51 is a schematic partial cross-sectional view of an enlarged portion of a portion of a charge discharge electrode of another example of the imaging device of Example 11, another example of a stacked imaging device, and the like.
52 is a schematic partial cross-sectional view of still another modification of the imaging element of Example 1 and a stacked imaging element.
53 is a schematic partial cross-sectional view of still another modification example of the imaging device of Example 1 and a stacked imaging device.
54 is a schematic partial cross-sectional view of still another modification example of the imaging device of Example 1 and a stacked imaging device.
55 is a schematic partial cross-sectional view of still another modification example of the imaging device of Example 1 and a stacked imaging device.
56 is a schematic partial cross-sectional view of still another modification example of the imaging device of Example 1 and a stacked imaging device.
FIG. 57 is a schematic partial cross-sectional view of an enlarged portion of a charge accumulation electrode, a photoelectric conversion layer, and a second electrode in a modification of the imaging device of Example 1. FIG.
FIG. 58 is a schematic partial cross-sectional view of an enlarged portion of a charge accumulation electrode, a photoelectric conversion layer, and a second electrode in a modification of the imaging device of Example 2. FIG.
59 is a conceptual diagram of an example in which an electronic device (camera) is used for a solid-state imaging device composed of the imaging device and the multilayer imaging device of the present disclosure.
Fig. 60 is a conceptual diagram of a conventional stacked imaging device (stacked solid-state imaging device).
61 is a schematic partial cross-sectional view of the stacked image pickup device of Example 12;
Fig. 62 is an equivalent circuit diagram of a four-pixel stacked image pickup device in Example 12.
63 is a view showing a planar structure of a part of a pixel array provided in the solid-state imaging device of Example 12;
FIG. 64 is a view showing the position of each transistor provided with one repeating unit while showing the outline of one repeating unit in the same drawing as that of FIG. 63 as a phantom line.
FIG. 65 is a diagram showing how the repeating units described in FIG. 64 are repeatedly arranged in both the row direction and the column direction of the pixel array 111 in the same view as in FIG. 63.
FIG. 66 is a view similar to FIG. 64, in which the planar shape of the photodiode provided in the third imaging element is additionally described with a dashed line.
FIG. 67 is a view showing the charges of the four photodiodes provided in the pixels at the positions shown in FIG. 63 using the transistor included in the repeating unit shown in FIG. 65 by the dashed line.
FIG. 68 is a view similar to FIG. 64, in which the planar shape of the electrode for charge accumulation of the photoelectric conversion unit provided in the first imaging element is additionally described with a grid line.
FIG. 69 is a diagram showing the charges of the four photoelectric conversion units provided in the pixel at the position shown in FIG. 63 using the transistor included in the repeating unit shown in FIG. 65 by the dashed line.
FIG. 70 is a view in which the planar shape of the photodiode provided in the second imaging element is further described in the same diagram as in FIG.
FIG. 71 is a view showing the charges of the four photodiodes provided in the pixels at the positions shown in FIG. 63 using the transistor included in the repeating unit shown in FIG. 65 by the dashed line.
FIG. 72 is a diagram showing the arrangement of a control signal line VAO for connecting a charge accumulation electrode provided in each pixel at a position of the pixel as shown in FIG. 63 and driving the charge accumulation electrode.
Fig. 73 is a diagram illustrating an example in which two sets of control signal lines (VOA) in an area enclosed by a thin line dashed line are arranged only with a wiring layer on the first floor and a connection structure therefor.
FIG. 74 is a view showing a part of wiring connected to each element shown in FIG. 64 using wiring provided in the stacked image pickup device at the position of the pixel as shown in FIG. 63 in order to realize the configuration shown in FIG. 62;
FIG. 75 is a view showing a part of wiring connected to each element shown in FIG. 64 using wiring provided in the stacked image pickup device at the position of the pixel as shown in FIG. 63 in order to realize the configuration shown in FIG. 62;
FIG. 76 is a view showing a part of wiring connected to each element shown in FIG. 64 using wiring provided in the stacked image pickup device at the position of the pixel as shown in FIG. 63 in order to realize the structure shown in FIG. 62;
77 is a diagram showing an outline of the configuration of a solid-state imaging device in Example 12;
78 is a diagram showing an outline of the configuration of a solid-state imaging device of Example 12;
79 is a diagram showing an outline of the configuration of a solid-state imaging device of Example 12;
80 is a diagram showing an outline of the configuration of a solid-state imaging device of Example 12;
FIG. 81 shows the control wiring necessary for driving the four-pixel stacked image pickup device sharing the control unit among the control wirings shown in solid lines in FIG. 75 and also in FIG. 75 with the solid line solid lines. , The rest of the control wiring is indicated by dotted lines.
FIG. 82 is a line between the center of the on-chip micro-lens described in FIG. 72 and the first imaging element described in the drawing, and wiring (VOA) for driving the electrode for charge accumulation provided in the drawing. The distance (d1) in the drawing was added (加 筆, 書 き 加 え).
83 shows the center of the on-chip micro-lens described in FIG. 68, and the largest circle inscribed in the electrode for charge accumulation provided in the first imaging element described in the figure. The distance (d2) between them is drawn in the drawing.
FIG. 84 shows the distance between the center of the on-chip micro-lens described in the figure and the largest circle inscribed in the photodiode provided in the second imaging element described in the figure. The distance d3 is drawn in the drawing.
FIG. 85 shows the distance between the center of the on-chip micro-lens described in FIG. 66 and the maximum circle inscribed to the photodiode provided in the third imaging element described in the figure. The distance d4 is drawn in the drawing.
FIG. 86 shows the distance between the center of the on-chip micro-lens described in FIG. 68 and the largest circle inscribed to the first electrode provided in the first imaging element described in the figure. The distance (d2) of the chart was drawn in the drawing.
Fig. 87 recounts Fig. 68, and further deletes the first electrode and the electrode for charge accumulation described in the figure, while the center of the largest circle inscribed to the through electrode described in the figure, and on-chip micro The center of the lens is refilled, and the distance d3 between the center of the largest circle inscribed to the through electrode and the center of the on-chip micro-lens is drawn in the drawing.
FIG. 88 is a diagram in which FIG. 68 is removed and codes other than the first electrode and the first floating diffusion layer provided in the first imaging element are deleted.
FIG. 89 is a view of FIG. 70, in which codes other than the second floating diffusion layer provided in the second imaging element are deleted.
FIG. 90 is a diagram in which FIG. 66 is removed and codes other than the third floating diffusion layer 3 provided in the third imaging element are deleted.
FIG. 91 shows the charge accumulation electrode provided in the first imaging element, and the through electrode, the first floating diffusion layer, the second floating diffusion layer, and the third floating diffusion layer shown in FIGS. Drawing showing positional relationship.
FIG. 92 shows the minimum distance d7 between the first electrode 11 and the electrode for charge accumulation while removing the edge line showing the repeating arrangement unit of the transistors constituting the control unit in FIG. 68; A compelling thing.
FIG. 93 shows the line in FIG. 64 and removes a border line showing repeating arrangement units of transistors constituting the control unit.
FIG. 94 is a view similar to FIG. 62 about the structure of a single pixel.
FIG. 95 is a view similar to FIG. 66 about the structure of a single pixel.
96 is a view similar to that of FIG. 70, regarding the structure of a single pixel.
FIG. 97 is a view similar to FIG. 68 about the structure of a single pixel.
FIG. 98 is a view similar to FIG. 74 with respect to a single pixel structure.
FIG. 99 is a view similar to FIG. 75 about the structure of a single pixel.
100 is a view similar to FIG. 76 about the single pixel structure.
FIG. 101 is a view similar to FIG. 82 about a single pixel structure.
FIG. 102 is a view similar to FIG. 85 about the structure of a single pixel.
FIG. 103 is a view similar to FIG. 84 about the structure of a single pixel.
FIG. 104 is a view similar to FIG. 83 about the structure of a single pixel.
105 is a view similar to FIG. 91 with respect to a single pixel structure.
FIG. 106 is a view similar to FIG. 92 about the structure of a single pixel.
FIG. 107 is a view similar to FIG. 93 about the structure of a single pixel.

Hereinafter, the present disclosure will be described based on examples with reference to the drawings, but the present disclosure is not limited to the examples, and various numerical values and materials in the examples are examples. In addition, description is performed in the following procedure.

1. Imaging element according to first to sixth aspects of the present disclosure, stacked-type imaging element of the present disclosure, and solid-state imaging device according to first to fourth aspects of the present disclosure, general description

2. Example 1 (Image pickup element according to the first aspect of the present disclosure and the sixth aspect of the present disclosure, a stacked-type imaging device of the present disclosure, and a solid-state imaging device according to the fourth aspect of the present disclosure)

3. Example 2 (Image pickup device according to second aspect of the present disclosure and sixth aspect of the present disclosure)

4. Example 3 (Image pickup element according to the third aspect of the present disclosure)

5. Example 4 (Image pickup element according to the fourth aspect of the present disclosure)

6. Example 5 (imaging element according to the fifth aspect of the present disclosure)

7. Example 6 (imaging element according to the sixth aspect of the present disclosure)

8. Example 7 (Solid-state imaging device according to first to second aspects of the present disclosure)

9. Example 8 (Variation of Example 7)

10. Example 9 (Variation of Examples 1 to 6)

11.Example 10 (modifications of Examples 1 to 6 and 9)

12. Example 11 (Variation of Examples 1 to 6 and Examples 9 to 10)

13.Example 12

14.Other

<< Image pickup element according to the first to sixth aspects of the present disclosure, stacked image pickup device of the present disclosure, and solid-state imaging device according to the first to fourth aspects of the present disclosure, overall description >>

In the solid-state imaging device according to the first aspect to the second aspect of the present disclosure, an electrode for transmission control may be provided between a plurality of imaging elements constituting the imaging element block. The transfer control electrode may be formed on the first electrode side at the same level as the first electrode or the charge storage electrode, or may be formed at a different level. Alternatively, the electrode for transmission control may be formed on the second electrode side at the same level as the second electrode, or may be formed at a different level. Furthermore, in the solid-state imaging device according to the first aspect to the second aspect of the present disclosure including this preferred aspect, one on-chip micro-lens is provided above one imaging element. Alternatively, the imaging element block may be composed of two imaging elements, and one on-chip micro-lens may be provided above the imaging element block.

In the solid-state imaging device according to the first to second aspects of the present disclosure, one floating diffusion layer is provided for a plurality of imaging elements. Here, the plurality of imaging elements provided for one floating diffusion layer may be composed of a plurality of first type imaging elements described later, and at least one first type imaging element and one or two or more imaging elements described below. It may be composed of two types of imaging elements. Then, by appropriately controlling the timing of the charge transfer period, it becomes possible for a plurality of imaging elements to share one floating diffusion layer. The plurality of imaging elements are operated in conjunction, and are connected as a imaging element block to a driving circuit which will be described later. That is, a plurality of imaging elements constituting the imaging element block are connected to one driving circuit. However, control of the electrode for charge accumulation is performed for each imaging element. Further, it is possible for a plurality of imaging elements to share one contact hole portion. In the arrangement relationship between the first electrodes shared by the plurality of imaging elements and the charge accumulation electrodes of each imaging element, the first electrode may be arranged adjacent to the charge accumulation electrodes of each imaging element. Alternatively, the first electrode may be disposed adjacent to the charge storage electrodes of a part of the plurality of imaging elements, and may not be disposed adjacent to the remaining charge accumulation electrodes of the plurality of imaging elements. , The movement of charges from the rest of the plurality of imaging elements to the first electrode is a movement via a part of the plurality of imaging elements. The distance between the charge accumulation electrode constituting the imaging element and the charge accumulation electrode constituting the imaging element (for convenience, referred to as "distance A") is the first electrode in the imaging element adjacent to the first electrode. A longer than the distance between the electrodes for charge accumulation (for convenience, referred to as &quot; distance B &quot;) is preferable because it ensures the movement of electric charges from each imaging element to the first electrode. In addition, it is preferable that the value of the distance A is increased as the imaging element positioned away from the first electrode.

In the imaging elements according to the first to fifth aspects of the present disclosure, the larger the value of n is, the larger the segment of the photoelectric conversion section is, which is located away from the first electrode. Judging by the criteria. In addition, in the imaging element according to the sixth aspect of the present disclosure, the direction away from the first electrode is set to the X direction, and "X direction" is defined as follows. That is, the pixel region in which a plurality of imaging elements or stacked imaging elements are arranged is composed of pixels arranged in a two-dimensional array, that is, regularly arranged in the X direction and the Y direction. When the planar shape of the pixel is a rectangle, the direction in which the side closest to the first electrode extends is the Y direction, and the direction orthogonal to the Y direction is the X direction. Alternatively, when the planar shape of the pixel is an arbitrary shape, the overall direction including the line segment or curve closest to the first electrode is the Y direction, and the direction orthogonal to the Y direction is the X direction.

It is preferable that the second electrode located on the light incident side is common to a plurality of imaging elements. That is, the second electrode can be a so-called beta electrode. The photoelectric conversion layer may be common to a plurality of imaging elements, that is, one photoelectric conversion layer may be formed from a plurality of imaging elements, or may be provided for each imaging element.

In the imaging elements according to the first to second aspects of the present disclosure, the N photoelectric conversion layer segments are continuously provided, the N insulating layer segments are continuously provided, and the N electric charge accumulation electrode segments are also continuous. Is provided. In the imaging elements according to the third to fifth aspects of the present disclosure, N photoelectric conversion layer segments are provided continuously. In addition, in the imaging elements according to the fourth and fifth aspects of the present disclosure, N insulating layer segments are continuously provided, while in the imaging elements according to the third aspect of the present disclosure, N insulating layer segments Is provided corresponding to each of the photoelectric conversion section segments. Furthermore, in the imaging device according to the fourth to fifth aspects of the present disclosure, and in some cases, in the imaging device according to the third aspect of the present disclosure, the electrode segments for accumulating N charges are photoelectrically converted. It is provided corresponding to each of the sub-segments. Then, in the imaging elements according to the first to sixth aspects of the present disclosure, the same potential is applied to all of the electrode segments for charge accumulation. Alternatively, in the imaging elements according to the fourth to fifth aspects of the present disclosure, and in some cases, in the imaging elements according to the third aspect of the present disclosure, to each of the N charge accumulation electrode segments, Other potentials may be applied.

Imaging element according to first aspect to sixth aspect of the present disclosure, or imaging element according to first aspect to sixth aspect constituting the multilayered image pickup element of the present disclosure, and the present invention including the above-described preferred aspect Imaging elements (hereinafter, referred to collectively as imaging elements) constituting the solid-state imaging device according to the first to second aspects of the disclosure and the solid-state imaging device according to the third to fourth aspects of the present disclosure, (Referred to as "the imaging device of the present disclosure"),

It also has a semiconductor substrate,

The photoelectric conversion unit can be formed in a form disposed above the semiconductor substrate. Moreover, the 1st electrode, the electrode for charge accumulation, and the 2nd electrode are connected to the drive circuit mentioned later.

Furthermore, in the imaging element of the present disclosure including various preferred embodiments described above, the first electrode can be formed in a form in which the inside of the opening provided in the insulating layer is extended and connected to the photoelectric conversion layer. Alternatively, the photoelectric conversion layer may extend in the opening provided in the insulating layer and be connected to the first electrode. In this case,

The edge of the top surface of the first electrode is ^{covered with} an insulating layer,

The first electrode is exposed on the bottom surface of the opening,

When the surface of the insulating layer in contact with the top surface of the first electrode is the first surface, and the surface of the insulating layer in contact with the portion of the photoelectric conversion layer facing the charge storage electrode is the second surface, the side surface of the opening is the first surface It can be in a form having an inclination extending toward the second surface, and furthermore, a side surface of the opening having an inclination extending from the first surface toward the second surface may be formed on the side of the electrode for charge accumulation. You can. In addition, it includes a form in which another layer is formed between the photoelectric conversion layer and the first electrode (for example, a form in which a material layer suitable for charge accumulation is formed between the photoelectric conversion layer and the first electrode).

Furthermore, in the imaging device of the present disclosure including various preferred embodiments described above,

It is provided on the semiconductor substrate, and is also provided with a control unit having a driving circuit,

The first electrode and the electrode for charge accumulation are connected to a driving circuit,

In the charge accumulation period, the potential V ₁₁ is applied to the first electrode from the driving circuit, the potential V ₁₂ is applied to the electrode for charge accumulation, and charge is accumulated in the photoelectric conversion layer,

In the charge transfer period, the potential V ₂₁ is applied to the first electrode from the driving circuit, the potential V ₂₂ is applied to the charge accumulation electrode, and the charge accumulated in the photoelectric conversion layer passes through the first electrode. It can be configured to be read by the control unit. However, when the potential of the first electrode is higher than the potential of the second electrode,

V ₁₂ ≥V ₁₁ , and also V ₂₂ <V ₂₁

And, when the potential of the first electrode is lower than the potential of the second electrode,

V ₁₂ ≤V ₁₁ , and also V ₂₂ > V ₂₁

to be.

Hereinafter, a description will be given of the case where the potential of the first electrode is higher than the potential of the second electrode. When the potential of the first electrode is lower than the potential of the second electrode, the height of the potential may be reversed.

In the imaging device according to the first aspect of the present disclosure, the thickness of the insulating layer segment gradually changes from the first photoelectric conversion section segment to the Nth photoelectric conversion section segment. The thickness may be gradually increased or may be thin, whereby a kind of charge transfer gradient is formed.

When the charge to be accumulated is made of electrons, a structure in which the thickness of the insulating layer segment is gradually and thickly adopted may be adopted. When the charge to be accumulated is used as the hole, a structure in which the thickness of the insulating layer segment is gradually and thinned is adopted. It is good to hire. And in these cases, in the state of | V ₁₂ | ≥ | V ₁₁ | in the charge accumulation period, the n-th photoelectric conversion section segment is more than the (n + 1) -th photoelectric conversion section segment. , A large amount of charge can be accumulated, and a strong electric field is applied, so that the flow of charge from the first photoelectric conversion segment to the first electrode can be reliably prevented. In the charge transfer period, when | V ₂₂ | <| V ₂₁ |, the flow of charge from the first photoelectric conversion segment to the first electrode, the (n + 1) -th photoelectric conversion unit The flow of electric charge from the segment to the n-th photoelectric conversion section segment can be ensured.

In the imaging device according to the second aspect of the present disclosure, the thickness of the photoelectric conversion layer segment gradually changes from the first photoelectric conversion section segment to the Nth photoelectric conversion section segment. The thickness of the segment may be gradually increased or may be thin, thereby forming a kind of charge transfer gradient.

When the charge to be accumulated is made of electrons, a configuration in which the thickness of the photoelectric conversion layer segment is gradually increased may be adopted. When the charge to be accumulated is used as the hole, the thickness of the photoelectric conversion layer segment is gradually and thinned. It is good to adopt a structure. And, when the thickness of the photoelectric conversion layer segment is gradually, thick, when the state of V ₁₂ ≥ V ₁₁ in the charge accumulation period, and further, when the thickness of the photoelectric conversion layer segment is gradually, thin, in the charge accumulation period When V ₁₂ ≤V ₁₁ , the n-th photoelectric conversion section segment is applied with a stronger electric field than the (n + 1) -th photoelectric conversion section segment, from the first photoelectric conversion section segment. The flow of charge to the first electrode can be reliably prevented. Then, in the charge transfer period, when the thickness of the photoelectric conversion layer segment is gradually and thick, when V ₂₂ <V ₂₁ , and further, when the thickness of the photoelectric conversion layer segment is gradually, thin, V ₂₂ > In the state of V ₂₁ , the flow of charge from the first photoelectric conversion segment to the first electrode, the charge of the charge from the (n + 1) th photoelectric conversion segment to the nth photoelectric conversion segment The flow can be ensured.

In the imaging device according to the third aspect of the present disclosure, in the adjacent photoelectric conversion section segments, the materials constituting the insulating layer segment are different, thereby forming a kind of charge transfer gradient, the first photoelectric conversion section segment It is preferable that the value of the relative dielectric constant of the material constituting the insulating layer segment gradually decreases from to the Nth photoelectric conversion section. And, by adopting such a configuration, in the state of charge accumulation, in the state of V ₁₂ ≥ V ₁₁ , the charge of the n-th photoelectric conversion section segment is greater than the (n + 1) -th photoelectric conversion section segment. Can accumulate. In the charge transfer period, when V ₂₂ <V ₂₁ , the flow of charge from the first photoelectric conversion unit segment to the first electrode, the nth from the (n + 1) th photoelectric conversion unit segment The flow of charge to the first photoelectric conversion section segment can be securely ensured.

In the imaging device according to the fourth aspect of the present disclosure, in the adjacent photoelectric conversion section, the materials constituting the electrode segment for charge accumulation are different, thereby forming a kind of charge transfer gradient. The first photoelectric conversion It is preferable that the value of the work function of the material constituting the insulating layer segment gradually increases from the sub-segment to the N-th photoelectric conversion section. And by adopting such a structure, a potential gradient favorable for signal charge transfer can be formed without depending on the positive and negative voltages.

In the imaging device according to the fifth aspect of the present disclosure, the area of the electrode segment for charge accumulation is gradually smaller from the first photoelectric conversion section to the Nth photoelectric conversion section. , Since a kind of charge transfer gradient is formed, in the charge accumulation period, when V ₁₂ ≥ V ₁₁ , the n-th photoelectric conversion section segment is more than the (n + 1) -th photoelectric conversion section segment. A lot of charge can accumulate. In the charge transfer period, when V ₂₂ <V ₂₁ , the flow of charge from the first photoelectric conversion unit segment to the first electrode, the nth from the (n + 1) th photoelectric conversion unit segment The flow of charge to the first photoelectric conversion section segment can be securely ensured.

In the imaging device according to the sixth aspect of the present disclosure, the cross-sectional area of the laminated portion varies depending on the distance from the first electrode, whereby a kind of charge transfer gradient is formed. Specifically, if a structure in which the thickness of the cross-section of the stacked portion is made constant and the width of the cross-section of the stacked portion becomes smaller from the first electrode is adopted, as described in the imaging device according to the fifth aspect of the present disclosure, In the charge accumulation period, when the state of V ₁₂ ≥ V ₁₁ is reached, more charges can be accumulated in a region closer to the first electrode than in a distant region. Therefore, in the charge transfer period, when V ₂₂ <V ₂₁ , the flow of charge from the region close to the first electrode to the first electrode and the flow of electric charge from the distant region to the close region can be reliably secured. have. On the other hand, if the width of the cross-section of the laminated portion is made constant and the structure of gradually increasing the thickness of the cross-section of the laminated portion, specifically, the thickness of the insulating layer segment, the imaging according to the first aspect of the present disclosure is adopted. As described in the device, in the state of charge accumulation, in the state of V ₁₂ ≥ V ₁₁ , the area closer to the first electrode can accumulate more electric charges than the distant area, and a strong electric field is applied. The flow of charge from the region close to one electrode to the first electrode can be reliably prevented. In the charge transfer period, when V ₂₂ <V ₂₁ , the flow of charge from the region close to the first electrode to the first electrode and the flow of electric charge from the distant region to the close region can be reliably secured. have. In addition, if a structure in which the thickness of the photoelectric conversion layer segment is gradually and thickly adopted is adopted, as in the imaging device according to the second aspect of the present disclosure, in the state of charge accumulation, in the state of V ₁₂ ≥ V ₁₁ , A region closer to the first electrode is applied with a stronger electric field than the distant region, so that the flow of charge from the region close to the first electrode to the first electrode can be reliably prevented. In the charge transfer period, when V ₂₂ <V ₂₁ , the flow of charge from the region close to the first electrode to the first electrode and the flow of electric charge from the distant region to the close region can be reliably secured. have.

In addition, in the imaging elements according to the fourth to fifth aspects of the present disclosure, and in some cases, the imaging elements according to the third aspect of the present disclosure, different potentials are provided for each of the N charge accumulation electrode segments. If you add

When the potential of the first electrode is higher than the potential of the second electrode, in the charge transfer period, the potential applied to the electrode segment for charge accumulation (the first photoelectric conversion section segment) located closest to the first electrode is: Higher than the potential applied to the electrode segment for accumulating charge (the Nth photoelectric conversion section segment) located at the farthest point from the first electrode,

When the potential of the first electrode is lower than the potential of the second electrode, in the charge transfer period, the potential applied to the electrode segment for charge accumulation (the first photoelectric conversion section segment) located closest to the first electrode is: It can be set to a form lower than the potential applied to the electrode segment for accumulating charge (the Nth photoelectric conversion section segment) located at the farthest point from the first electrode.

Furthermore, in the imaging device of the present disclosure including various preferred forms and configurations described above, the photoelectric conversion layer is also connected, and further includes a first electrode and a charge discharging electrode disposed apart from the electrode for charge accumulation. It can be done in the form. In addition, the imaging element etc. of this indication of this form for convenience are called "the imaging element etc. of this indication provided with the charge discharge electrode" for convenience. In addition, in the imaging device of the present disclosure including a charge discharge electrode, the charge discharge electrode can be arranged so as to surround the first electrode and the charge accumulation electrode (that is, in a frame shape). The charge discharge electrode can be shared (commonized) by a plurality of imaging elements. And, in this case,

The photoelectric conversion layer extends in the second opening provided in the insulating layer, and is connected to the charge discharge electrode,

The edge of the top surface of the charge discharge electrode is ^{covered with} an insulating layer,

A charge discharge electrode is exposed on the bottom surface of the second opening,

When the surface of the insulating layer in contact with the top surface of the charge discharge electrode is the third surface, and the surface of the insulating layer in contact with the portion of the photoelectric conversion layer facing the electrode for charge accumulation is the second surface, the side surface of the second opening is: It can be made into the shape which has the inclination widening toward the 2nd surface from 3 sides.

Furthermore, in the image pickup device of the present disclosure provided with a charge discharge electrode,

It is provided on the semiconductor substrate, and is also provided with a control unit having a driving circuit,

The first electrode, the charge accumulation electrode, and the charge discharge electrode are connected to a driving circuit,

In the charge accumulation period, from the driving circuit, is applied to the potential (V ₁₁₎ to the first electrode, the charge is applied to the potential (V ₁₂₎ to the accumulation electrode and the charge drain is applied to the potential (V ₁₄₎ to the electrode, the photoelectric Electric charges accumulate in the conversion layer,

In the charge transfer period, from the driving circuit, the applied electric potential (V ₂₁₎ to the first electrode, and applying a potential (V ₂₂₎ to the charge accumulation electrode, and applying a potential (V ₂₄₎ to the charge drain electrode, the photoelectric It can be configured such that charges accumulated in the conversion layer are read to the control unit through the first electrode. However, when the potential of the first electrode is higher than the potential of the second electrode,

V ₁₄ > V ₁₁ , and also V ₂₄ <V ₂₁

And, when the potential of the first electrode is lower than the potential of the second electrode,

V ₁₄ <V ₁₁ , and also V ₂₄ > V ₂₁

to be.

In the imaging device of the present disclosure, including various preferred forms and configurations described above,

At least the floating diffusion layer and the amplifying transistor constituting the control unit are provided on the semiconductor substrate,

The first electrode can be configured to be connected to the floating diffusion layer and the gate portion of the amplifying transistor. And, in this case, furthermore,

The semiconductor substrate is further provided with a reset transistor and a selection transistor constituting the control unit,

The floating diffusion layer is connected to one of the source / drain regions of the reset transistor,

The source / drain region of one of the amplifying transistors is connected to one source / drain region of the selection transistor, and the other source / drain region of the selection transistor is connected to a signal line.

Furthermore, in the image pickup device of the present disclosure including various preferred forms and configurations described above, the size of the electrode for charge accumulation can be made larger than the first electrode. When the area of the electrode for charge accumulation is S ₁ ′ and the area of the first electrode is S ₁ , it is not limited,

4≤S ₁ '/ S ₁

It is preferable to satisfy.

Furthermore, in the imaging device of the present disclosure including various preferred forms and configurations described above, light can be incident from the second electrode side and a light-shielding layer is formed on the light incident side near the second electrode. have. Alternatively, light may be incident from the second electrode side, and light may not be incident on the first electrode. In this case, as a light incident side near the second electrode, a light blocking layer is provided above the first electrode. Can be of a structure that is formed, or

On-chip micro lenses are provided above the charge accumulation electrode and the second electrode,

The light incident on the on-chip micro-lens can be configured to be condensed on an electrode for charge accumulation. Here, the light shielding layer may be disposed above the surface of the second electrode on the light incident side, or may be disposed on the surface of the second electrode on the light incident side. In some cases, a light shielding layer may be formed on the second electrode. As a material constituting the light-shielding layer, chromium (Cr), copper (Cu), aluminum (Al), tungsten (W), and a resin that does not pass light (for example, polyimide resin) can be exemplified.

As an imaging element of the present disclosure, specifically, to a blue color provided with a photoelectric conversion layer (for convenience, referred to as "the first type of blue photoelectric conversion layer") that absorbs blue light (light of 425 nm to 495 nm). Sensitive imaging device (for convenience, referred to as &quot; first type of blue imaging device &quot;), photoelectric conversion layer that absorbs green light (light from 495 nm to 570 nm) (for convenience, "first type of green photoelectricity" An imaging element having a sensitivity to green, which is called a "conversion layer" (for convenience, referred to as "the first type of green imaging element"), a photoelectric conversion that absorbs red light (lights from 620 nm to 750 nm) And an imaging element having a sensitivity to red with a layer (for convenience, referred to as "the first type of red photoelectric conversion layer") (for convenience, referred to as "the first type of red imaging element"). In addition, as a conventional imaging element that does not include an electrode for accumulating charge, an imaging element having sensitivity to blue is referred to as &quot; a second type of imaging element for blue &quot; for convenience, and an imaging element having sensitivity to green is used for convenience. , A &quot; second type of green imaging element &quot;, and for convenience, an imaging element having a sensitivity to red is called &quot; second type of red imaging element &quot;, and a photoelectric constituting a second type of blue imaging element For convenience, the conversion layer is referred to as "the second type of blue photoelectric conversion layer", and for convenience, the photoelectric conversion layer constituting the second type of green imaging device is referred to as "the second type of green photoelectric conversion layer", For convenience, the photoelectric conversion layer constituting the second type of red imaging device is referred to as &quot; second type red photoelectric conversion layer &quot;.

The multilayered imaging element of the present disclosure has at least one imaging element (photoelectric conversion element) of the present disclosure, specifically, for example,

[A] The first type of blue photoelectric conversion part, the first type of green photoelectric conversion part and the first type of red photoelectric conversion part are stacked in the vertical direction,

The structure and structure of each of the control units of the first type of blue imaging element, the first type of green imaging element, and the first type of red imaging element are provided on the semiconductor substrate

[B] The photoelectric conversion unit for blue of the first type and the photoelectric conversion unit for green of the first type are stacked in the vertical direction,

A photoelectric conversion section for red of the second type is disposed below the first type photoelectric conversion section of the two layers,

The structure and structure of each of the control units of the first type blue imaging element, the first type green imaging element, and the second type red imaging element are provided on the semiconductor substrate.

[C] Below the first type of green photoelectric conversion unit, a second type of blue photoelectric conversion unit and a second type of red photoelectric conversion unit are arranged,

The structure and structure of each of the control units of the first type green imaging element, the second type blue imaging element, and the second type red imaging element are provided on the semiconductor substrate.

[D] Below the first type blue photoelectric conversion section, the second type green photoelectric conversion section and the second type red photoelectric conversion section are arranged,

Each of the control units of the first type of blue imaging element, the second type of green imaging element, and the second type of red imaging element is configured and structure provided on the semiconductor substrate.

Can be lifted. In addition, the order of arrangement of these imaging elements in the vertical direction of the photoelectric conversion part is the order of the blue photoelectric conversion part, the green photoelectric conversion part, the red photoelectric conversion part from the light incident direction, or the green photoelectric from the light incident direction. It is preferable that it is the order of a conversion part, a blue photoelectric conversion part, and a red photoelectric conversion part. This is because light of a shorter wavelength is absorbed more efficiently from the incident surface side. Since red is the longest wavelength among the three colors, it is preferable to position the red photoelectric conversion section in the lowermost layer from the light incident surface. One pixel is constituted by the stacked structure of these imaging elements. Further, a first type of infrared photoelectric conversion unit may be provided. Here, the photoelectric conversion layer of the first type infrared photoelectric conversion unit is made of, for example, an organic material, is the lowermost layer of the stacked structure of the first type imaging element, and is disposed above the second type imaging element. desirable. Alternatively, a photoelectric conversion unit for infrared rays of the second type may be provided below the first type photoelectric conversion unit.

In the first type of imaging element, for example, a first electrode is formed on an interlayer insulating layer provided on a semiconductor substrate. The imaging element formed on the semiconductor substrate may be of a backside irradiation type or a surface irradiation type.

When the photoelectric conversion layer is made of an organic material, the photoelectric conversion layer,

(1) It consists of a p-type organic semiconductor.

(2) It consists of an n-type organic semiconductor.

(3) It consists of the laminated structure of p-type organic semiconductor layer / n-type organic semiconductor layer. It consists of a stacked structure of a p-type organic semiconductor layer / p-type organic semiconductor and an n-type organic semiconductor mixed layer (bulk heterostructure) / n-type organic semiconductor layer. It consists of a laminated structure of a mixed layer (bulk heterostructure) of a p-type organic semiconductor layer / p-type organic semiconductor and an n-type organic semiconductor. It consists of a laminated structure of a mixed layer (bulk heterostructure) of an n-type organic semiconductor layer / p-type organic semiconductor and an n-type organic semiconductor.

(4) It is composed of a mixture of a p-type organic semiconductor and an n-type organic semiconductor (bulk heterostructure).

It can be any one of the 4 aspects of. However, the stacking order may be configured in an arbitrary replacement.

As a p-type organic semiconductor, a naphthalene derivative, anthracene derivative, phenanthrene derivative, pyrene derivative, perylene derivative, tetracene derivative, pentacene derivative, quinacridone derivative, thiophene derivative, thienothiophene derivative, benzothiophene derivative, Coordinator of benzothienobenzothiophene derivatives, triallylamine derivatives, carbazole derivatives, perylene derivatives, picene derivatives, chrysene derivatives, fluoranthene derivatives, phthalocyanine derivatives, subphthalocyanine derivatives, subporphyrazine derivatives, heterocyclic compounds Metal complexes, polythiophene derivatives, polybenzothiadiazole derivatives, polyfluorene derivatives, and the like. As an n-type organic semiconductor, fullerene and fullerene derivatives <e.g., fullerenes (higher fullerenes) such as C60, C70, C74, nested fullerenes, etc.) or fullerene derivatives (e.g. fullerene fluoride, PCBM fullerene compounds, fullerenes) Sieve)>, an organic semiconductor having a larger (deeper) HOMO and LUMO than a p-type organic semiconductor, and a transparent inorganic metal oxide. As an n-type organic semiconductor, specifically, a heterocyclic compound containing a nitrogen atom, an oxygen atom, and a sulfur atom, such as a pyridine derivative, a pyrazine derivative, a pyrimidine derivative, a triazine derivative, a quinoline derivative, a quinoxaline derivative, Isoquinoline derivative, acridine derivative, phenazine derivative, phenanthroline derivative, tetrazole derivative, pyrazole derivative, imidazole derivative, thiazole derivative, oxazole derivative, imidazole derivative, benzoimidazole derivative, benzotriazole Derivatives, benzoxazole derivatives, benzoxazole derivatives, carbazole derivatives, benzofuran derivatives, dibenzofuran derivatives, subporpyrazine derivatives, polyphenylenevinylene derivatives, polybenzothiadiazole derivatives, polyfluorene derivatives, etc. And organic molecules, organometallic complexes, and subphthalocyanine derivatives on a part of the molecular skeleton. Examples of the group contained in the fullerene derivative include a halogen atom; Straight-chain, branched or cyclic alkyl groups or phenyl groups; A group having a straight-chain or condensed aromatic compound; A group having a halide; Partial fluoroalkyl group; Perfluoroalkyl group; Silylalkyl group; Silylalkoxy groups; Arylsilyl group; Arylsulfanyl group; Alkyl sulfanyl groups; Arylsulfonyl group; Alkyl sulfonyl groups; Aryl sulfide group; Alkyl sulfide groups; Amino group; Alkyl amino groups; Arylamino group; Hydroxy group; Alkoxy group; Acylamino group; Acyloxy group; Carbonyl group; Carboxy group; Carboxamide groups; Carboalkoxy group; Acyl group; Sulfonyl group; Cyano group; Nitro group; A group having a chalcogenide; Phosphine group; Phosphonic group; And derivatives thereof. The thickness of the photoelectric conversion layer (sometimes referred to as "organic photoelectric conversion layer") made of an organic material is not limited, but is, for example, 1 × 10 ^-8 m to 5 × 10 ^-7 m, preferably 2.5 × 10 ^-8 m to 3 × 10 ^-7 m, more preferably 2.5 × 10 ^-8 m to 2 × 10 ^-7 m, still more preferably 1 × 10 ^-7 m to 1.8 × 10 ^-7 m Can be illustrated. In addition, organic semiconductors are often classified into p-type and n-type, and p-type means easy to transport holes, n-type means easy to transport electrons, and heat excitation like inorganic semiconductor (熱 勵It is not limited to the interpretation that it has holes or electrons as the majority carrier of iv).

Alternatively, as a material constituting an organic photoelectric conversion layer that photoelectrically converts light of a green wavelength, for example, rhodamine-based pigments, merocyanine pigments, quinacridone derivatives, subphthalocyanine pigments (subphthalocyanine derivatives), etc. Examples of the material constituting the organic photoelectric conversion layer that photoelectrically converts blue light include, for example, coumarin acid pigments, tris-8-hydroxyquinolialuminum (Alq3), and merocyanine pigments. Examples of the material constituting the organic photoelectric conversion layer for photoelectric conversion of red light include phthalocyanine-based pigments and subphthalocyanine-based pigments (subphthalocyanine derivatives).

Or, as an inorganic material constituting the photoelectric conversion layer, crystalline silicon, amorphous silicon, microcrystalline silicon, crystalline selenium, amorphous selenium, and a calcopyrite-based compound CIGS (CuInGaSe), CIS (CuInSe ₂ ), CuInS ₂ , CuAlS ₂ , CuAlSe ₂ , CuGaS ₂ , CuGaSe ₂ , AgAlS ₂ , AgAlSe ₂ , AgInS ₂ , AgInSe ₂ , or also a group III-V compound GaAs, InP, AlGaAs, InGaP, AlGaInP, InGaAsP, furthermore, CdSe, And compound semiconductors such as CdS, In2Se ₃ , In2S ₃ , Bi2Se ₃ , Bi ₂ S ₃ , ZnSe, ZnS, PbSe, and PbS. In addition, it is also possible to use quantum dots made of these materials for the photoelectric conversion layer.

Alternatively, the photoelectric conversion layer can be a stacked structure of a lower layer semiconductor layer and an upper layer photoelectric conversion layer. By providing the lower layer semiconductor layer in this way, recombination at the time of charge accumulation can be prevented, the transfer efficiency of the charge accumulated in the photoelectric conversion layer to the first electrode can be increased, and generation of dark current can be suppressed. The material constituting the upper layer photoelectric conversion layer may be appropriately selected from various materials constituting the photoelectric conversion layer described above. On the other hand, as a material constituting the lower layer semiconductor layer, a material having a large band gap energy value (for example, a band gap energy value of 3.0 eV or more) and a material having a higher mobility than the material constituting the photoelectric conversion layer. It is preferred to use. Specifically, oxide semiconductor materials, such as IGZO; Transition metal die chalcogenide; Silicon carbide; Diamond ; Graphene; Carbon nanotubes; And organic semiconductor materials such as condensed polycyclic hydrocarbon compounds and condensed heterocyclic compounds. Alternatively, as the material constituting the lower layer semiconductor layer, if the charge to be accumulated is electrons, a material having an ionization potential greater than that of the material constituting the photoelectric conversion layer may be mentioned, and the charge to be accumulated is a hole In this case, a material having an electron affinity smaller than the electron affinity of the material constituting the photoelectric conversion layer may be mentioned. Alternatively, the impurity concentration in the material constituting the lower semiconductor layer is preferably 1 × 10 ¹⁸ cm ^-3 or less. The lower layer semiconductor layer may have a single layer structure or a multilayer structure. Further, the material constituting the lower semiconductor layer located above the electrode for charge accumulation may be different from the material constituting the lower semiconductor layer located above the first electrode.

The solid-state imaging device according to the first to fourth aspects of the present disclosure can constitute a single-plate color solid-state imaging device.

In the solid-state imaging device according to the second or fourth aspect of the present disclosure having a stacked imaging device, unlike a solid-state imaging device equipped with a Bayer array of imaging devices (i.e., blue, green, using a color filter), Rather than performing spectroscopy in red), since an imaging element having sensitivity to light of a plurality of wavelengths is stacked to form a single pixel in the direction of incidence of light within the same pixel, the sensitivity is improved and pixels per unit volume Density can be improved. In addition, since the organic material has a high absorption coefficient, the film thickness of the organic photoelectric conversion layer can be made thinner compared to the conventional Si-based photoelectric conversion layer, and the light leakage from adjacent pixels and the limitation of the incident angle of light are alleviated. Furthermore, in the conventional Si-based imaging element, a false color occurs because an interpolation process is performed between pixels of three colors to produce a color signal, but the second aspect or the fourth aspect of the present disclosure provided with the multilayered imaging element In the solid-state imaging device concerned, the occurrence of false color is suppressed. Since the organic photoelectric conversion layer itself also functions as a color filter, color separation is possible without providing a color filter.

On the other hand, in the solid-state imaging device according to the first aspect, the second aspect, or the third aspect of the present disclosure, by using a color filter, the demand for blue, green, and red spectral characteristics can be alleviated, and , Has high mass productivity. An array of imaging elements in the solid-state imaging device according to the first aspect, the second aspect, or the third aspect of the present disclosure, in addition to the Bayer arrangement, an interline arrangement, a G-stripe RB checkered arrangement, a G-stripe RB full check Pattern arrangement, checkered complementary color arrangement, stripe arrangement, inclined stripe arrangement, primary color difference arrangement, field color difference sequence, frame color difference sequence, MOS type arrangement, improved MOS type arrangement, frame interleaved arrangement, field interleaved arrangement. Here, one pixel (or sub-pixel) is constituted by one imaging element.

A pixel region in which a plurality of the imaging elements of the present disclosure or the stacked imaging elements of the present disclosure are arranged is composed of pixels that are regularly arranged in a two-dimensional array shape. The pixel region is generally composed of an effective pixel region that receives light and amplifies the signal charge generated by photoelectric conversion and reads it into a driving circuit, and a black reference pixel region for outputting optical black as a reference for the black level. It is done. The black reference pixel area is usually arranged on the outer peripheral portion of the effective pixel area.

In the imaging device of the present disclosure including various preferred forms and configurations described above, light is irradiated, photoelectric conversion occurs in the photoelectric conversion layer, and holes (holes) and electrons are carrier separated. In addition, an electrode from which holes are taken out is an anode, and an electrode from which electrons are taken out is a cathode. There are also forms in which the first electrode constitutes the anode, and the second electrode constitutes the cathode, and conversely, the first electrode constitutes the cathode and the second electrode constitutes the anode.

In the case of forming a stacked-type imaging element, the first electrode, the electrode for charge accumulation, the electrode for transfer control, the charge discharge electrode, and the second electrode can be configured with a transparent conductive material. In addition, the first electrode, the electrode for charge accumulation, the electrode for transfer control, and the charge discharge electrode are collectively called "first electrode, etc.". Alternatively, when the imaging device of the present disclosure is disposed in a plane such as, for example, a Bayer arrangement, the second electrode may be made of a transparent conductive material, and the first electrode or the like may be made of a metal material. , In this case, specifically, the second electrode located on the light incident side is made of a transparent conductive material, and the first electrode or the like is, for example, Al-Nd (alloy of aluminum and neodymium) or ASC (aluminum, Alloy of samarium and copper). In addition, an electrode made of a transparent conductive material may be referred to as a "transparent electrode". Here, it is preferable that the band gap energy of the transparent conductive material is 2.5 eV or more, preferably 3.1 eV or more. As a transparent conductive material constituting the transparent electrode, there may be mentioned conductive metal oxides, specifically, indium oxide, indium-tin oxide (ITO, Indium Tin Oxide, Sn-doped In ₂ O ₃ , crystalline ITO and Amorphous ITO), indium-zinc oxide (IZO) with indium added as a dopant to zinc oxide, indium-gallium oxide (IGO) with indium added as a dopant to gallium oxide, and as a dopant to zinc oxide Indium-gallium-zinc oxide (IGZO, In-GaZnO ₄ ) with indium and gallium added, indium-tin-zinc oxide (ITZO) with indium and tin as a dopant to zinc oxide, IFO (In ₂ O of F-doped) ₃ ), tin oxide (SnO ₂ ), ATO (SnO _{2 in} Sb dope), FTO (SnO _{2 in} F dope), zinc oxide (including ZnO doped with other elements), and aluminum added as a dopant to zinc oxide One aluminum-zinc oxide (AZO), gallium-zinc oxide (GZO) with gallium added as a dopant to zinc oxide, acid Examples of titanium oxide (TiO ₂ ), niobium-titanium oxide (TNO) in which niobium is added as a dopant to titanium oxide, antimony oxide, spinel oxide, and oxide having a YbFe ₂ O ₄ structure can be exemplified. Alternatively, a transparent electrode using gallium oxide, titanium oxide, niobium oxide, nickel oxide or the like as a mother layer may be mentioned. As the thickness of the transparent electrode, 2 x 10 ^-8 m to 2 x 10 ^-7 m, preferably 3 x 10 ^-8 m to 1 x 10 ^-7 m can be mentioned. When transparency is required for the first electrode, from the viewpoint of simplifying the manufacturing process, it is preferable that the charge discharge electrode is also made of a transparent conductive material.

Alternatively, when transparency is unnecessary, it is preferable to use a conductive material having a high work function (for example, φ = 4.5eV to 5.5eV) as a conductive material constituting an anode having a function as an electrode for extracting holes. Specifically, gold (Au), silver (Ag), chromium (Cr), nickel (Ni), palladium (Pd), platinum (Pt), iron (Fe), iridium (Ir), germanium (Ge) , Osmium (Os), rhenium (Re), and tellurium (Te). On the other hand, as a conductive material constituting a cathode having a function as an electrode for taking out electrons, it is preferable to be composed of a conductive material having a low work function (for example, phi = 3.5 eV to 4.5 eV), specifically, Alkali metals (eg Li, Na, K, etc.) and fluorides or oxides thereof, and alkaline earth metals (eg, Mg, Ca, etc.) and fluorides or oxides thereof, aluminum (Al), zinc (Zn), tin (Sn) ), Thallium (Tl), sodium-potassium alloy, aluminum-lithium alloy, magnesium-silver alloy, indium, Italy? Rare earth metals, such as these, or these alloys are mentioned. Or, as a material constituting the anode or cathode, platinum (Pt), gold (Au), palladium (Pd), chromium (Cr), nickel (Ni), aluminum (Al), silver (Ag), tantalum (Ta) ), Tungsten (W), copper (Cu), titanium (Ti), indium (In), tin (Sn), iron (Fe), metals such as cobalt (Co), molybdenum (Mo), or metals thereof Conductives such as alloys containing elements, conductive particles made of these metals, conductive particles of alloys containing these metals, polysilicon containing impurities, carbon-based materials, oxide semiconductors, carbon nanotubes, graphene, etc. Materials can be mentioned, and it can also be set as the laminated structure of the layer containing these elements. Furthermore, an organic material (conductive polymer) such as poly (3,4-ethylenedioxythiophene) / polystyrenesulfonic acid [PEDOT / PSS] may be used as a material constituting the positive electrode or the negative electrode. Further, these conductive materials may be mixed with a binder (polymer) to cure the paste or ink to be used as an electrode.

As a method of forming a first electrode or the like or a second electrode (anode or cathode), it is possible to use a dry method or a wet method. Examples of the dry method include physical vapor deposition (PVD) and chemical vapor deposition (CVD). As a film deposition method using the principle of PVD method, vacuum deposition method using resistance heating or high-frequency heating, EB (electron beam) deposition method, various sputtering methods (magnetron sputtering method, RF-DC combined bias sputtering method, ECR sputtering method, opposite target Sputtering method, high frequency sputtering method), ion plating method, laser ablation method, molecular beam epitaxy method, laser transfer method. Further, examples of the CVD method include plasma CVD, thermal CVD, organometallic (MO) CVD, and optical CVD. On the other hand, as the wet method, methods such as electrolytic plating, electroless plating, spin coating, inkjet, spray coating, stamping, micro contact printing, flexography, offset printing, gravure printing, dip, etc. Can be lifted. Examples of the patterning method include chemical etching such as shadow mask, laser transfer, and photolithography, and physical etching using ultraviolet light or laser. As a planarization technique for the first electrode or the second electrode, a laser planarization method, a reflow method, a chemical mechanical polishing (CMP) method, or the like can be used.

As a material constituting the insulating layer, a silicon oxide-based material; Silicon nitride (SiN _Y ); Inorganic insulating materials exemplified by metal oxide high dielectric insulating materials such as aluminum oxide (Al ₂ O ₃ ), as well as polymethyl methacrylate (PMMA); Polyvinylphenol (PVP); Polyvinyl alcohol (PVA); Polyimide; Polycarbonate (PC); Polyethylene terephthalate (PET); Polystyrene; Silanol derivatives such as N-2 (aminoethyl) 3-aminopropyl trimethoxysilane (AEAPTMS), 3-mercaptopropyl trimethoxysilane (MPTMS), octadecyl trichlorosilane (OTS) (silane coupling agent) ; Novolac type phenol resin; Fluorine resin; And organic insulating materials (organic polymers) exemplified by straight chain hydrocarbons having a functional group capable of binding to a control electrode at one end such as octadecanethioldodecyl isocyanate, and combinations thereof. In addition, as the silicon oxide-based material, silicon oxide (SiO _X ), BPSG, PSG, BSG, AsSG, PbSG, silicon oxynitride (SiON), SOG (spin-on-glass), low dielectric constant material (e.g., polyaryl ether) , Cycloperfluorocarbon polymer and benzocyclobutene, cyclic fluorine resin, polytetrafluoroethylene, aryl fluoride ether, polyimide fluoride, amorphous carbon, organic SOG). Materials constituting various interlayer insulating layers and insulating films may also be appropriately selected from these materials.

The structure and structure of the floating diffusion layer, the amplifying transistor, the reset transistor and the selection transistor constituting the control unit can be the same as the structure and structure of the conventional floating diffusion layer, the amplifying transistor, the reset transistor and the selection transistor. The driving circuit can also be of a well-known configuration and structure.

The first electrode is connected to the floating diffusion layer and the gate portion of the amplifying transistor, but a contact hole portion may be formed to connect the first electrode and the floating diffusion layer and the gate portion of the amplifying transistor. As a material constituting the contact hole, polysilicon doped with impurities, high melting point metals such as tungsten, Ti, Pt, Pd, Cu, TiW, TiN, TiNW, WSi ₂ and MoSi ₂ , metal silicides, and materials thereof The lamination structure (for example, Ti / TiN / W) of the layer which consists of can be illustrated.

A first carrier blocking layer may be provided between the organic photoelectric conversion layer and the first electrode, or a second carrier blocking layer may be provided between the organic photoelectric conversion layer and the second electrode. Further, a first charge injection layer may be provided between the first carrier blocking layer and the first electrode, or a second charge injection layer may be provided between the second carrier blocking layer and the second electrode. For example, as a material constituting the electron injection layer, for example, alkali metals such as lithium (Li), sodium (Na), and potassium (K) and fluorides and oxides thereof, magnesium (Mg), and calcium (Ca) And alkaline earth metals and fluorides and oxides thereof.

The dry film forming method and the wet film forming method are mentioned as a film forming method of various organic layers. As a dry film forming method, resistance heating or high frequency heating, vacuum deposition method using electron beam heating, flash deposition method, plasma deposition method, EB deposition method, various sputtering methods (2-pole sputtering method, direct current sputtering method, direct current magnetron sputtering method, high frequency sputtering method, Magnetron sputtering method, RF-DC combined bias sputtering method, ECR sputtering method, counter target sputtering method, high frequency sputtering method, ion beam sputtering method), DC (Direct Current) method, RF method, next pole method, activation reaction method, electric field Various ion plating methods, such as a vapor deposition method, a high frequency ion plating method, a reactive ion plating method, a laser ablation method, a molecular beam epitaxy method, a laser transfer method, and the molecular beam epitaxy method (MBE method) are mentioned. Further, examples of the CVD method include plasma CVD, thermal CVD, MOCVD, and optical CVD. On the other hand, as a wet method, specifically, a spin coat method; Immersion method; Cast method; Micro contact printing method; Drop cast method; Various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexography; Stamp method; Spray method; Air doctor coater method, blade coater method, rod coater method, knife coater method, squeeze coater method, reverse roll coater method, transfer roll coater method, gravure coater method, kiss coater method, cast coater method, spray coater method, slit orifice coater method Various coating methods, such as a method and a calendar coater method, can be illustrated. In addition, in the coating method, non-polar or low-polarity organic solvents such as toluene, chloroform, hexane and ethanol can be exemplified as the solvent. Examples of the patterning method include chemical etching such as shadow mask, laser transfer, and photolithography, and physical etching using ultraviolet light or laser. As a planarization technique for various organic layers, a laser planarization method, a reflow method, or the like can be used.

On the imaging element or solid-state imaging device, as described above, an on-chip, micro-lens, or light-shielding layer may be provided as needed, and a driving circuit and wiring for driving the imaging element are provided. If necessary, a shutter for controlling the incidence of light to the imaging element may be provided, or an optical cut filter may be provided according to the purpose of the solid-state imaging device.

For example, when a solid-state imaging device is stacked with a read integrated circuit (ROIC), the connecting portions are in contact with a drive substrate formed with a connecting portion made of a reading integrated circuit and copper (Cu), and an imaging element having a connecting portion. By overlapping so as to connect the connecting parts, it can be laminated, and the connecting parts can also be joined using a solder bump or the like.

Example 1

Example 1 relates to the imaging device according to the first aspect of the present disclosure and the sixth aspect of the present disclosure, the stacked imaging device of the present disclosure, and the solid-state imaging device according to the fourth aspect of the present disclosure.

1 is a schematic partial cross-sectional view of the imaging device of Example 1 and a stacked-type imaging device, and FIG. 2 is a schematic partial cross-sectional view of an enlarged portion of a charge accumulation electrode, a photoelectric conversion layer, and a second electrode. Fig. 3 and Fig. 4 show equivalent circuit diagrams of the image pickup device of Example 1 and the stacked image pickup device, and the model of the first electrode and charge accumulation electrode and the control part of the image pickup device of Example 1 Fig. 5 is a schematic arrangement diagram, and Fig. 6 schematically shows the state of the electric potential at each site during operation of the imaging device of Example 1. 7 is a schematic arrangement diagram of the first electrode constituting the imaging element of Example 1 and the electrode for charge accumulation, and the first electrode constituting the imaging element of Example 1, the electrode for charge accumulation, and the second. 8 is a schematic perspective perspective view of the electrode and contact hole portions, and a conceptual diagram of the solid-state imaging device of Example 1 is illustrated in FIG. 9. 3 and 4, for simplification of the drawing, the thickness of the insulating layer segment is shown as a constant thickness.

The imaging element of Example 1 (for example, the green imaging element described later) or the imaging elements of Examples 2 to 6 and Examples 9 to 11 described later, the first electrode 11 , The photoelectric conversion layer 15 and the second electrode 16 are provided with a photoelectric conversion portion made of a stack, the photoelectric conversion portion is further disposed apart from the first electrode 11, and further, the insulating layer 82 It is provided with an electrode 12 for charge accumulation disposed opposite to the photoelectric conversion layer 15 through.

In addition, the stacked-type imaging element of Example 1 has at least one imaging element of Examples 1-6, and the imaging element of Example 1 in Examples 1-6.

Furthermore, the solid-state imaging device of Example 1 is provided with a plurality of the multilayer imaging elements of Example 1.

Here, in the imaging element of Example 1 or the imaging elements of Examples 2 to 6 and Examples 9 to 11 described later,

The photoelectric conversion section is composed of N (however, N≥2) photoelectric conversion section segments (specifically, in each embodiment, three photoelectric conversion section segments 10 ₁ , 10 ₂ , 10 ₃ ),

The photoelectric conversion layer 15 is composed of N photoelectric conversion layer segments (specifically, in each embodiment, three photoelectric conversion layer segments 15 ₁ , 15 ₂ , 15 ₃ ),

The insulating layer 82 is composed of N insulating layer segments (specifically, in each embodiment, three insulating layer segments 82 ₁ , 82 ₂ , 82 ₃ ),

In Examples 1 to 3, the electrode 12 for charge accumulation is composed of N electrode segments for charge accumulation (specifically, in each embodiment, three electrode segments 12 ₁ , 12 ₂ , 12 for charge accumulation) ₃ )),

In Examples 4 to 5, in some cases, in Example 3, the electrodes 12 for charge accumulation were arranged spaced apart from each other, and N electrode segments for charge accumulation (specifically, in each embodiment) , Consisting of three electrode segments for charge accumulation (12 ₁ , 12 ₂ , 12 ₃ ),

The n-th (however, n = 1, 2, 3 ... N) photoelectric conversion section segment 10 _n includes the n-th charge accumulation electrode segment 12 _n and the n-th insulating layer segment 82 _n ) and the n-th photoelectric conversion layer segment 15 _n ,

The larger the value of n is, the larger the segment of the photoelectric conversion part is, which is located away from the first electrode 11.

Alternatively, the imaging element of Example 1 or the imaging elements of Example 2 and Example 5 described later,

A first electrode 11, a photoelectric conversion layer 15 and a second electrode 16 are provided with a photoelectric conversion unit made of a stack,

The photoelectric conversion section is further provided with an electrode 12 for charge accumulation, which is disposed apart from the first electrode 11 and is disposed to face the photoelectric conversion layer 15 through the insulating layer 82,

When the stacking direction of the electrode 12 for charge accumulation, the insulating layer 82, and the photoelectric conversion layer 15 is set in the Z direction and the direction falling from the first electrode 11 in the X direction, YZ is used to accumulate charge in the virtual plane. The cross-sectional area of the stacked portion when cutting the stacked portion where the electrode 12, the insulating layer 82, and the photoelectric conversion layer 15 are stacked changes depending on the distance from the first electrode.

In addition, in the imaging device of Example 1, the thickness of the insulating layer segment gradually changes from the _first photoelectric conversion section segment 10 ₁ to the Nth photoelectric conversion section segment 10 _N. . Specifically, the thickness of the insulating layer segment is gradually increased. Alternatively, in the imaging device of Example 1, the width of the cross section of the laminated portion is constant, and the thickness of the cross section of the laminated portion, specifically, the thickness of the insulating layer segment depends on the distance from the first electrode 11. Therefore, it gradually becomes thicker. In addition, the thickness of the insulating layer segment is thick in the shape of a step. The thickness of the insulating layer segment 82 _{n in} the n-th photoelectric conversion section segment 10 _n was made constant. When the thickness of the insulating layer segment 82 _{n in} the n-th photoelectric conversion section segment 10 _n is “1”, the (n + 1) -th photoelectric conversion section segment 10 _{(n + 1)} As the thickness of the insulating layer segment 82 _{(n + 1) in} ), 2 to 10 may be exemplified, but is not limited to such a value. In Example 1, the thickness of the insulating layer segments 82 ₁ , 82 ₂ , 82 ₃ is gradually increased by gradually reducing the thickness of the electrode segments 12 ₁ , 12 ₂ , 12 _{3 for} charge accumulation. The thickness of the photoelectric conversion layer segments 15 ₁ , 15 ₂ , 15 ₃ is constant.

Further, in the imaging elements of Example 1 or Examples 2 to 6 and Examples 9 to 11 described later, a semiconductor substrate (more specifically, a silicon semiconductor layer 70) is also provided, and photoelectric The conversion unit is disposed above the semiconductor substrate 70. In addition, a control unit provided on the semiconductor substrate 70 and having a driving circuit to which the first electrodes 11 are connected is also provided. Here, the light incident surface of the semiconductor substrate 70 is upward, and the opposite side of the semiconductor substrate 70 is downward. A wiring layer 62 made of a plurality of wirings is provided below the semiconductor substrate 70. Further, the semiconductor substrate 70 is provided with at least a floating diffusion layer (FD ₁ ) and an amplifying transistor (TR1 _amp ) constituting a control unit, and the first electrode 11 includes a floating diffusion layer (FD ₁ ) and an amplifying transistor (TR1). _amp ). The semiconductor substrate 70 is further provided with a reset transistor TR1 _rst and a selection transistor TR1 _sel constituting a control unit. In addition, the floating diffusion layer FD ₁ is connected to one source / drain region of the reset transistor TR1 _rst , and one source / drain region of the amplification transistor TR1 _amp is the selection transistor TR1 _sel . One of the source / drain regions is connected to, and the other of the source / drain regions of the selection transistor TR1 _sel is connected to the signal line VSL ₁ . These amplifying transistors TR1 _amp , reset transistor TR1 _rst , and selection transistor TR1 _sel constitute a driving circuit.

Specifically, the imaging device of Example 1 and the stacked imaging device have a sensitivity to green with a first type of green photoelectric conversion layer that absorbs green light as a back-illumination imaging device and a stacked imaging device. The green type imaging element of Embodiment 1 of the first type (hereinafter referred to as "the first imaging element"), the second type having a sensitivity to blue with a blue photoelectric conversion layer of the second type absorbing blue light Conventional blue imaging element (hereinafter referred to as &quot; second imaging element &quot;), a second type of conventional red for sensitivity to red with a second type of red photoelectric conversion layer that absorbs red light It has a structure in which three imaging elements of an imaging element (hereinafter referred to as "third imaging element") are stacked. Here, the red imaging element (third imaging element) and the blue imaging element (second imaging element) are provided in the semiconductor substrate 70, and the second imaging element is on the light incident side than the third imaging element. Located. Moreover, the green imaging element (first imaging element) is provided above the blue imaging element (second imaging element). One pixel is constituted by the stacked structure of the first imaging element, the second imaging element, and the third imaging element. No color filter is provided.

In the first imaging element, on the interlayer insulating layer 81, the first electrode 11 and the charge storage electrode 12 are spaced apart. The interlayer insulating layer 81 and the electrode 12 for charge accumulation are covered with the insulating layer 82. The photoelectric conversion layer 15 is formed on the insulating layer 82, and the second electrode 16 is formed on the photoelectric conversion layer 15. A protective layer 83 is formed on the entire surface including the second electrode 16, and an on-chip micro lens 90 is provided on the protective layer 83. The first electrode 11, the electrode 12 for charge accumulation, and the second electrode 16 are made of, for example, a transparent electrode made of ITO (work function: about 4.4 eV). The photoelectric conversion layer 15 is composed of a layer containing a well-known organic photoelectric conversion material (e.g., rhodamine-based pigment, merocyanine pigment, quinacridone-based organic material) having sensitivity to green. . Further, the photoelectric conversion layer 15 may further include a material layer suitable for charge accumulation. That is, a material layer suitable for charge accumulation may be formed between the photoelectric conversion layer 15 and the first electrode 11 (for example, in the connecting portion 67). The interlayer insulating layer 81, the insulating layer 82, and the protective layer 83 are made of a known insulating material (for example, SiO ₂ or SiN). The photoelectric conversion layer 15 and the first electrode 11 are connected by a connecting portion 67 provided on the insulating layer 82. The photoelectric conversion layer 15 is extended in the connection portion 67. That is, the photoelectric conversion layer 15 extends inside the opening 84 provided in the insulating layer 82 and is connected to the first electrode 11.

The charge accumulation electrode 12 is connected to a driving circuit. Specifically, the charge accumulation electrode 12 is a vertical driving circuit (which constitutes a driving circuit) through a connection hole 66, a pad portion 64, and a wiring V _OA provided in the interlayer insulating layer 81. 112).

The size of the electrode 12 for charge accumulation is larger than that of the first electrode 11. When the area of the charge accumulation electrode 12 is S ₁ ′, and the area of the first electrode 11 is S ₁ , it is not limited,

4≤S ₁ '/ S ₁

It is preferable to satisfy, and in Example 1, although not limited, for example,

S ₁ '/ S ₁ = 8

Was made. In addition, in Example 1 or Examples 2 to 4 described later, the sizes of the three photoelectric conversion section segments 10 ₁ , 10 ₂ , and 10 ₃ were set to the same size, and the planar shape was also the same.

An element isolation region 71 is formed on the side of the first surface (outer surface) 70A of the semiconductor substrate 70, and an oxide film 72 is formed on the first surface 70A of the semiconductor substrate 70. . Furthermore, a reset transistor TR1 _rst , an amplifying transistor TR1 _amp and a selection transistor TR1 _sel constituting a control unit of the first imaging element are provided on the first surface side of the semiconductor substrate 70, and further, The first floating diffusion layer FD ₁ is provided.

The reset transistor TR1 _rst includes a gate portion 51, a channel formation region 51A, and source / drain regions 51B and 51C. The gate portion 51 of the reset transistor (TR1 _rst) a reset line (RST ₁₎ is connected to the reset transistor source / drain region (51C) of one of (TR1 _rst) includes a first floating diffusion (FD ₁ ), And the other source / drain region 51B is connected to the power supply V _DD .

The first electrode 11 includes a contact hole 65 formed in the interlayer insulating layer 81, a contact hole portion 61 formed on the pad portion 63, the semiconductor substrate 70 and the interlayer insulating layer 76, and interlayer insulation The source / drain region 51C (first floating diffusion layer FD ₁ ) of one of the reset transistors TR1 _rst is connected to the wiring layer 62 formed in the layer 76.

The amplifying transistor TR1 _amp is composed of a gate portion 52, a channel formation region 52A, and source / drain regions 52B and 52C. The gate portion 52 is connected to the source / drain region 51C (first floating diffusion layer FD ₁ ) of the first electrode 11 and one of the reset transistors TR1 _rst through the wiring layer 62. have. In addition, one source / drain region 52B shares the region with the other source / drain region 51B constituting the reset transistor TR1 _rst , and is connected to the power supply V _DD .

The selection transistor TR1 _sel is composed of a gate portion 53, a channel formation region 53A, and source / drain regions 53B and 53C. The gate portion 53 is connected to the selection line SEL ₁ . In addition, one source / drain region 53B shares the region with the other source / drain region 52C constituting the amplifying transistor TR1 _amp , and the other source / drain region 53C includes: It is connected to a signal line (data output line) (VSL ₁ ) 117.

The second imaging element includes an n-type semiconductor region 41 provided on the semiconductor substrate 70 as a photoelectric conversion layer. The gate portion 45 of the transfer transistor TR2 _trs made of a vertical transistor extends to the n-type semiconductor region 41 and is also connected to the transfer gate line TG ₂ . In addition, the second floating diffusion layer FD ₂ is provided in the region 45C of the semiconductor substrate 70 near the gate portion 45 of the transfer transistor TR2 _trs . The charge accumulated in the n-type semiconductor region 41 is read into the second floating diffusion layer FD ₂ through the transmission channel formed along the gate portion 45.

In the second imaging element, the reset transistor TR2 _rst , the amplifying transistor TR2 _amp and the selection transistor TR2 _sel constituting the control unit of the second imaging element are further provided on the first surface side of the semiconductor substrate 70. It is prepared.

The reset transistor TR2 _rst includes a gate portion, a channel formation region, and a source / drain region. The gate portion of the reset transistor TR2 _rst is connected to the reset line RST ₂ , and one source / drain region of the reset transistor TR2 _rst is connected to the power source V _DD , and the other source / drain region Silver also serves as the second floating diffusion layer (FD ₂ ).

The amplifying transistor TR2 _amp is composed of a gate portion, a channel formation region, and a source / drain region. The gate portion is connected to the other source / drain region (second floating diffusion layer FD ₂ ) of the reset transistor TR2 _rst . Further, one source / drain region shares the region with one of the source / drain regions constituting the reset transistor TR2 _rst , and is connected to the power supply V _DD .

The selection transistor TR2 _sel includes a gate portion, a channel formation region, and a source / drain region. The gate portion is connected to the selection line SEL ₂ . In addition, one source / drain region shares the region with the other source / drain region constituting the amplifying transistor TR2 _amp , and the other source / drain region is a signal line (data output line) (VSL ₂ ).

The third imaging element includes an n-type semiconductor region 43 provided on the semiconductor substrate 70 as a photoelectric conversion layer. The gate portion 46 of the transfer transistor TR3 _trs is connected to the transfer gate line TG ₃ . Further, a third floating diffusion layer FD ₃ is provided in the region 46C of the semiconductor substrate 70 near the gate portion 46 of the transfer transistor TR3 _trs . The charge accumulated in the n-type semiconductor region 43 is read into the third floating diffusion layer FD ₃ through the transmission channel 46A formed along the gate portion 46.

In the third imaging element, a reset transistor (TR3 _rst ), an amplifying transistor (TR3 _amp ), and a selection transistor (TR3 _sel ) constituting the control unit of the third imaging element are further provided on the first surface side of the semiconductor substrate (70). It is prepared.

The reset transistor TR3 _rst includes a gate portion, a channel formation region, and a source / drain region. The gate portion of the reset transistor TR3 _rst is connected to the reset line RST ₃ , and one source / drain region of the reset transistor TR3 _rst is connected to the power supply V _DD , and the other source / drain region Silver also serves as the third floating diffusion layer (FD ₃ ).

The amplifying transistor TR3 _amp includes a gate portion, a channel formation region, and a source / drain region. The gate portion is connected to the other source / drain region (third floating diffusion layer FD ₃ ) of the reset transistor TR3 _rst . Further, one source / drain region shares the region with one of the source / drain regions constituting the reset transistor TR3 _rst , and is connected to the power supply V _DD .

The selection transistor TR3 _sel includes a gate portion, a channel formation region, and a source / drain region. The gate portion is connected to the selection line SEL ₃ . In addition, one source / drain region shares the region with the other source / drain region constituting the amplifying transistor TR3 _amp , and the other source / drain region is a signal line (data output line) (VSL ₃ ).

The reset lines (RST ₁ , RST ₂ , RST ₃ ), the selection lines (SEL ₁ , SEL ₂ , SEL ₃ ), and the transmission gate lines (TG ₂ , TG ₃ ) are connected to the vertical driving circuit 112 constituting the driving circuit. The signal lines (data output lines) VSL ₁ , VSL ₂ , and VSL ₃ are connected to the column signal processing circuit 113 constituting the driving circuit.

A p ⁺ layer 44 is provided between the n-type semiconductor region 43 and the surface 70A of the semiconductor substrate 70 to suppress dark current generation. Between the n-type semiconductor region 41 and the n-type semiconductor region 43, a p ⁺ layer 42 is formed, and further, a part of the side surface of the n-type semiconductor region 43 is a p ⁺ layer 42 ). On the side of the back surface 70B of the semiconductor substrate 70, a p ⁺ layer 73 is formed, and from the p ⁺ layer 73, the contact hole portion 61 inside the semiconductor substrate 70 is to be formed. , HfO ₂ film 74 and insulating film 75 are formed. In the interlayer insulating layer 76, wiring is formed over a plurality of layers, but illustration is omitted.

The HfO ₂ film 74 is a film having a negative fixed charge, and by providing such a film, generation of dark current can be suppressed. In addition, instead of HfO ₂ film, aluminum oxide (Al ₂ O ₃ ) film, zirconium oxide (ZrO ₂ ) film, tantalum oxide (Ta ₂ O ₅ ) film, titanium oxide (TiO ₂ ) film, lanthanum oxide (La ₂ O) ₃ ) film, preseodymium oxide (Pr ₂ O ₃ ) film, cerium oxide (CeO ₂ ) film, neodymium oxide (Nd ₂ O ₃ ) film, promethium oxide (Pm ₂ O ₃ ) film, samarium oxide (Sm ₂ O ₃ ) film, europium oxide (Eu ₂ O ₃ ) film, gadolinium oxide ((Gd ₂ O ₃ ) film, terbium oxide (Tb ₂ O ₃ ) film, dysprosium oxide (Dy ₂ O ₃ ) film, holmium oxide (HO ₂ O ₃ ) film, thulium oxide (Tm ₂ O ₃ ) film, ytterbium oxide (Yb ₂ O ₃ ) film, ruthenium oxide (Lu ₂ O ₃ ) film, yttrium oxide (Y ₂ O ₃ ) film, hafnium nitride film, An aluminum nitride film, a hafnium oxynitride film, or an aluminum oxynitride film may be used, and examples of the film forming method include a CVD method, a PVD method, and an ALD method.

The operation of the imaging element (first imaging element) of Example 1 will be described below with reference to FIG. 6. Here, the potential of the first electrode 11 was made higher than the potential of the second electrode. That is, for example, the first electrode 11 is set to a positive potential, the second electrode is set to a negative potential, and photoelectric conversion is performed in the photoelectric conversion layer 15, and electrons are read into the floating diffusion layer. The same applies to other examples. In the form in which the first electrode 11 is set to a negative potential, the second electrode is set to a positive potential, and the holes generated based on the photoelectric conversion in the photoelectric conversion layer 15 are read into the floating diffusion layer, described below. It is good to reverse the height of the potential.

The reference numerals used in Figs. 6 and 20 and 21 in Example 5 to be described later are as follows.

Potential at the point PA of the region of the photoelectric conversion layer 15 opposite to the electrode 12 for charge accumulation and PA, or photoelectricity opposite to the electrode segment 12 _{3 for} charge accumulation Potential at the point PA of the region of the conversion layer 15

The potential at the point PB of the region of the photoelectric conversion layer 15 opposite to the region located between the electrode 12 for charge accumulation and the first electrode 11, or, Further, the potential at the point PB of the region of the photoelectric conversion layer 15 that faces the electrode segment 12 _{2 for} charge accumulation.

PC ······· Potential at the point PC of the region of the photoelectric conversion layer 15 facing the first electrode 11, or photoelectric conversion opposite the electrode segment 12 _{1 for} charge accumulation Dislocation at the point (PC) of the region of the layer 15

Electric potential at the point PD of the region of the photoelectric conversion layer 15 opposite to the region located between the electrode segment 1 2 _{3 for} charge accumulation and the first electrode 11

FD ..... potential in the first floating diffusion layer (FD ₁ )

Potential at the electrode 12 for charge accumulation in VOA ...

V _OA 1... In the first electrode segment 12 _{1 for} charge accumulation electric potential

VOA2 ... in the second electrode segment 12 _{2 for} charge accumulation electric potential

VOA3 ... in the third electrode segment 12 _{3 for} charge accumulation electric potential

Potential at the gate portion 51 of the reset transistor TR1 _rst

VDD ······ Electric potential

VSL_1 ... signal line (data output line) (VSL ₁ )

TR1_ _rst ... reset transistor (TR1 _rst )

TR1_ _amp ... amplification transistor (TR1 _amp )

TR1_ _sel ... selective transistor (TR1 _sel )

In the charge accumulation period, from the driving circuit, is applied to the potential (V ₁₁₎ to the first electrode 11 is applied with the potential (V ₁₂₎ to the charge accumulation electrode 12. The photoelectric conversion occurs in the photoelectric conversion layer 15 by the light incident on the photoelectric conversion layer 15. Holes generated by photoelectric conversion are sent from the second electrode 16 to the driving circuit through the wiring V _OU . On the other hand, since the potential of the first electrode 11 is set higher than that of the second electrode 16, that is, for example, a positive potential is applied to the first electrode 11, and the second electrode 16 is applied. Since it is said that a negative potential is applied, V ₁₂ ≥ V ₁₁ , preferably V ₁₂ > V ₁₁ . Thereby, the electrons generated by the photoelectric conversion are attracted to the electrode 12 for charge accumulation and stay in the region of the photoelectric conversion layer 15 facing the electrode 12 for charge accumulation. That is, electric charges are accumulated in the photoelectric conversion layer 15. Since V ₁₂ > V ₁₁ , electrons generated inside the photoelectric conversion layer 15 do not move toward the first electrode 11. With the passage of time of the photoelectric conversion, the potential in the region of the photoelectric conversion layer 15 facing the charge storage electrode 12 becomes a more negative value.

In the imaging device of Example 1, since the thickness of the insulating layer segment is gradually increased, when the state of V ₁₂ ≥ V ₁₁ in the charge accumulation period, the nth photoelectric conversion section segment ( 10 _n ) can accumulate more electric charges than the (n + 1) -th photoelectric conversion section segment 10 _{(n + 1)} , and a strong electric field is applied to the first photoelectric conversion section The flow of charge from the segment 10 ₁ to the first electrode 11 can be reliably prevented.

In the later stage of the charge accumulation period, a reset operation is performed. Accordingly, the potential of the first floating diffusion layer FD ₁ is reset, and the potential of the first floating diffusion layer FD ₁ becomes the potential V _DD of the power source.

After completion of the reset operation, the charge is read. That is, in the charge transfer period, from the driving circuit, is applied to the potential (V ₂₁₎ to the first electrode 11 is applied with the potential (V ₂₂₎ to the charge accumulation electrode 12. Here, let V ₂₂ <V ₂₁ . Thereby, the electrons remaining in the region of the photoelectric conversion layer 15 facing the charge storage electrode 12 are read into the first electrode 11 and, further, the first floating diffusion layer FD ₁ . That is, the charge accumulated in the photoelectric conversion layer 15 is read to the control unit.

More specifically, in the charge transfer period, when V ₂₂ <V ₂₁ , the flow of charge from the first photoelectric converter segment 10 ₁ to the first electrode 11, n (1 + 1) ) The flow of electric charge from the segment (10 _{(n + 1)} ) of the nth photoelectric conversion section to the nth photoelectric conversion section segment (10 _n ) can be reliably ensured.

Thus, a series of operations such as charge accumulation, reset operation, and charge transfer are completed.

The operations of the amplifying transistor TR1 _amp and the selection transistor TR1 _sel after the electrons are read into the first floating diffusion layer FD ₁ are the same as those of the conventional transistors. In addition, the series of operations of charge accumulation, reset operation and charge transfer of the second imaging element and the third imaging element are the same as those of the conventional series of operations of charge accumulation, reset operation and charge transfer. In addition, the reset noise of the first floating diffusion layer FD ₁ can be removed by correlated double sampling (CDS) processing as in the prior art.

As described above, in the imaging elements of Example 1 or Examples 1 to 6 and Examples 9 to 11 described later, they are disposed apart from the first electrode and photoelectrically converted through an insulating layer. Since an electrode for charge accumulation disposed opposite to the layer is provided, light is irradiated to the photoelectric conversion unit, and when photoelectric conversion is performed in the photoelectric conversion unit, a kind of capacitor is formed by the photoelectric conversion layer, the insulating layer, and the electrode for charge accumulation. Formed, it is possible to accumulate charge in the photoelectric conversion layer. Therefore, at the start of exposure, it becomes possible to completely deplete the charge accumulation portion and erase the charge. As a result, it is possible to suppress the occurrence of a phenomenon that kTC noise becomes large, random noise deteriorates, and image quality deteriorates. Moreover, since all the pixels can be reset all at once, the so-called global shutter function can be realized.

Furthermore, in the imaging device of Example 1, the thickness of the insulating layer segment gradually changes from the first photoelectric conversion section segment to the Nth photoelectric conversion section segment, or further, the YZ virtual plane. Therefore, since the cross-sectional area of the laminated portion when cutting the laminated portion in which the electrode for charge accumulation, the insulating layer and the photoelectric conversion layer is laminated, changes depending on the distance from the first electrode, a kind of charge transfer gradient is formed, and the photoelectric It becomes possible to more easily and reliably transfer the electric charge generated by the conversion.

9 is a conceptual diagram of the solid-state imaging device of Example 1. The solid-state imaging device 100 of the first embodiment includes an imaging area 111 in which the stacked imaging elements 101 are arranged in a two-dimensional array, and a vertical driving circuit 112 and a column as the driving circuit (peripheral circuit) thereof. It consists of a signal processing circuit 113, a horizontal driving circuit 114, an output circuit 115, a driving control circuit 116, and the like. Further, these circuits can be constituted by well-known circuits, and can be constructed using other circuit configurations (for example, various types of circuits used in conventional CCD type solid-state imaging devices or CMOS type solid-state imaging devices). Needless to say, you can. In addition, in FIG. 9, the reference numeral "101" in the stacked image pickup device 101 is set to only one line.

The drive control circuit 116 is a reference for the operation of the vertical drive circuit 112, the column signal processing circuit 113, and the horizontal drive circuit 114 based on the vertical synchronization signal, horizontal synchronization signal, and master clock. Generate a clock signal or control signal. Then, the generated clock signal or control signal is input to the vertical driving circuit 112, the column signal processing circuit 113, and the horizontal driving circuit 114.

The vertical drive circuit 112 is configured by, for example, a shift register, and selectively scans each stacked imaging element 101 of the imaging area 111 in the vertical direction sequentially in units of rows. In addition, the pixel signal (image signal) based on the current (signal) generated in response to the amount of light received by each of the stacked imaging elements 101 is a column signal processing circuit 113 through signal lines (data output lines) 117 and VSL. ).

The column signal processing circuit 113 is, for example, arranged for each column of the stacked imaging element 101, and a black reference pixel (not shown) for an image signal output from the stacked imaging element 101 for one row for each imaging element. However, noise removal and signal amplification signal processing are performed by a signal from the effective pixel region). At the output end of the column signal processing circuit 113, a horizontal selection switch (not shown) is provided connected between the horizontal signal lines 118.

The horizontal drive circuit 114 is constituted by, for example, a shift register, sequentially selects each of the column signal processing circuits 113 by sequentially outputting horizontal scanning pulses, and the column signal processing circuit 113 The signal from each of is output to the horizontal signal line 118.

The output circuit 115 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 113 through the horizontal signal line 118 and outputs them.

Fig. 10 shows an equivalent circuit diagram of a modification example of the imaging element of Example 1 and a stacked-type imaging element, and of the first electrode constituting the modification example of the imaging element of Example 1, the electrode for charge accumulation, and the transistors constituting the control unit. 11, instead of connecting the other source / drain region 51B of the reset transistor TR1 _rst to the power source V _DD , the ground may be grounded.

The imaging element of Example 1 and a laminated-type imaging element can be manufactured with the following method, for example. That is, first, an SOI substrate is prepared. Then, a first silicon layer is formed on the surface of the SOI substrate by epitaxial growth, and a p ⁺ layer 73 and an n-type semiconductor region 41 are formed on the first silicon layer. Subsequently, a second silicon layer is formed on the first silicon layer by epitaxial growth, and in the second silicon layer, the device isolation region 71, the oxide film 72, the p ⁺ layer 42, and the n-type The semiconductor regions 43 and p ⁺ layers 44 are formed. Further, after forming various transistors and the like constituting the control unit of the imaging element on the second silicon layer, and further forming the wiring layer 62, the interlayer insulating layer 76, and various wirings thereon, the interlayer insulating layer 76 ) And the supporting substrate (not shown) are bonded. Thereafter, the SOI substrate is removed to expose the first silicon layer. Further, the surface of the second silicon layer corresponds to the surface 70A of the semiconductor substrate 70, and the surface of the first silicon layer corresponds to the back surface 70B of the semiconductor substrate 70. In addition, the first silicon layer and the second silicon layer are collectively expressed as a semiconductor substrate 70. Subsequently, an opening for forming the contact hole portion 61 is formed on the side of the back surface 70B of the semiconductor substrate 70, and an HfO ₂ film 74, an insulating film 75, and a contact hole portion 61 are formed. Further, the pad portions 63 and 64, the interlayer insulating layer 81, the connection holes 65 and 66, the first electrode 11, the charge accumulation electrode 12, and the insulating layer 82 are formed. Next, the connecting portion 67 is opened to form the photoelectric conversion layer 15, the second electrode 16, the protective layer 83, and the on-chip micro-lens 90. By the above, the imaging element of Example 1 and the laminated-type imaging element can be obtained.

In the imaging element of Example 1, in forming the first electrode 11, the electrode 12 for charge accumulation, and the insulating layer 82, first, the electrode 12 for charge accumulation on the interlayer insulating layer 81 ₃ ) forming a conductive material layer for forming, and patterning the conductive material layer to form a conductive material layer in an area to form the photoelectric conversion segment (10 ₁ , 10 ₂ , 10 ₃ ) and the first electrode 11 By remaining, a part of the first electrode 11 and an electrode 12 _{3 for} charge accumulation can be obtained. Next, over the entire surface, forming an insulating layer for forming the insulating layer segment (82 _3), and by patterning the insulating layer by performing a planarizing process, it is possible to obtain the insulating layer segment (82 _3). Next, a conductive material layer for forming an electrode 12 _{2 for} charge accumulation is formed on the entire surface, and the conductive material layer is patterned, so that the photoelectric conversion section segments 10 ₁ and 10 ₂ and the first electrode 11 are formed. By leaving the conductive material layer in the region where is to be formed, a portion of the first electrode 11 and the electrode 12 _{2 for} charge accumulation can be obtained. Next, by forming the insulating layer for forming the insulating layer segment (82 ₂₎ on the front, and patterning the insulating layer, and performing a planarization process, it is possible to obtain the insulating layer segment (82 _2). Next, a conductive material layer for forming an electrode 12 _{1 for} charge accumulation is formed on the entire surface, and the conductive material layer is patterned to form the photoelectric conversion section segment 10 ₁ and the first electrode 11. By leaving a conductive material layer in the region to be obtained, the first electrode 11 and the electrode 12 _{1 for} charge accumulation can be obtained. Next, by forming the insulating layer on the front, and performing a planarization process, it is possible to obtain an insulating layer segments (82 ₁₎ (insulation layer 82). Then, the photoelectric conversion layer 15 is formed on the insulating layer 82. In this way, the photoelectric conversion section segments 10 ₁ , 10 ₂ , 10 ₃ can be obtained.

Example 2

The imaging element of Example 2 is related with the imaging element which concerns on 2nd aspect and 6th aspect of this indication. As shown in FIG. 12, a schematic partial cross-sectional view of an enlarged portion of a charge accumulation electrode, a photoelectric conversion layer, and a second electrode is stacked, in the imaging device of Example 2, the first photoelectric conversion section segment 10 ₁₎ from the thickness of the photoelectric conversion layer segments over a period of the N-th photoelectric conversion section segment (10 _N) for, gradually, it is changing. Alternatively, in the imaging device of Example 2, the width of the cross-section of the stacked portion is constant, and the thickness of the cross-section of the stacked portion, specifically, the thickness of the photoelectric conversion layer segment, is a distance from the first electrode 11. Gradually, thicken depending on it. More specifically, the thickness of the photoelectric conversion layer segment is gradually increasing. In addition, the thickness of the photoelectric conversion layer segment is thick in the shape of a step. The thickness of the photoelectric conversion layer segment 15 _{n in} the n-th photoelectric conversion section segment 10 _n was made constant. When the thickness of the photoelectric conversion layer segment 15 _{n in} the n-th photoelectric conversion unit segment 10 _n is "1", the (n + 1) -th photoelectric conversion unit segment 10 _{(n + 1)} ), The thickness of the photoelectric conversion layer segment 15 (n + 1) may be exemplified 2 to 10, but is not limited to such a value. In Example 2, the thickness of the photoelectric conversion layer segments 15 ₁ , 15 ₂ , 15 ₃ is gradually increased by gradually reducing the thickness of the electrode segments 12 ₁ , 12 ₂ , 12 _{3 for} charge accumulation. The thickness of the insulating layer segments 82 ₁ , 82 ₂ , 82 ₃ is constant.

In the imaging device of Example 2, since the thickness of the photoelectric conversion layer segment gradually and thickens, in the state of charge accumulation, when the state of V ₁₂ ≥ V ₁₁ is reached, the nth photoelectric conversion section segment 10 _n In this case, an electric field stronger than that of the (n + 1) -th photoelectric conversion section segment 10 _{(n + 1)} is applied to the first electrode 11 from the first photo-electric conversion section segment 10 ₁ . It is possible to reliably prevent the flow of electric charge. In the charge transfer period, when V ₂₂ <V ₂₁ , the flow of electric charge from the first photoelectric converter segment 10 ₁ to the first electrode 11, the (n + 1) th The flow of charge from the photoelectric conversion section segment 10 _{(n + 1)} to the n-th photoelectric conversion section segment 10 _n can be reliably ensured.

In this way, in the imaging device of Example 2, the thickness of the photoelectric conversion layer segment gradually changes from the first photoelectric conversion section segment to the Nth photoelectric conversion section segment, or further, YZ. Since the cross-sectional area of the laminated portion when cutting the laminated portion in which the electrode for electrical charge accumulation and the insulating layer and the photoelectric conversion layer are stacked in a virtual plane varies depending on the distance from the first electrode, a kind of charge transfer gradient is formed. , It is possible to more easily and reliably transfer electric charges generated by photoelectric conversion.

In the imaging element of Example 2, in the formation of the first electrode 11, the electrode 12 for charge accumulation, the insulating layer 82 and the photoelectric conversion layer 15, first, on the interlayer insulating layer 81 , Forming a conductive material layer for forming the charge accumulation electrode 123, and patterning the conductive material layer to form the photoelectric conversion section segments 10 ₁ , 10 ₂ , 10 ₃ and the first electrode 11 By leaving a conductive material layer in the region to be divided, a part of the first electrode 11 and an electrode 12 _{3 for} charge accumulation can be obtained. Subsequently, a conductive material layer for forming an electrode 12 _{2 for} charge accumulation is formed on the front surface, and the conductive material layer is patterned to form the photoelectric conversion section segments 10 ₁ , 10 ₂ and the first electrode 11. By leaving the conductive material layer in the region to be formed, a part of the first electrode 11 and an electrode 12 _{2 for} charge accumulation can be obtained. Subsequently, a conductive material layer for forming a charge accumulation electrode 12 ₁ is formed on the front surface, and the conductive material layer is patterned to form the photoelectric conversion part segment 10 ₁ and the first electrode 11. By leaving the conductive material layer in the region, the first electrode 11 and the electrode 12 _{1 for} charge accumulation can be obtained. Next, an insulating layer 82 is conformally formed on the entire surface. Then, a photoelectric conversion layer 15 is formed on the insulating layer 82, and a planarization process is performed on the photoelectric conversion layer 15. In this way, the photoelectric conversion section segments 10 ₁ , 10 ₂ , 10 ₃ can be obtained.

Example 3

Example 3 relates to an imaging element according to a third aspect of the present disclosure. 13 is a schematic sectional view of a part of the imaging device of Example 3 and a stacked imaging device. In the imaging device of Example 3, the materials constituting the insulating layer segment in the adjacent photoelectric conversion section segments are different. Here, from the first photoelectric conversion section segment 10 ₁ to the Nth photoelectric conversion section segment 10 _N , the value of the relative dielectric constant of the material constituting the insulating layer segment is gradually reduced. In the imaging device of Example 3, the same potential may be applied to all of the N charge accumulation electrode segments, or a different potential may be applied to each of the N charge accumulation electrode segments. In the case of the latter, as described in Example 4, the electrode segments 12 ₁ , 12 ₂ , 12 ₃ for electric charge accumulation arranged spaced apart from each other, through the pad portions 64 ₁ , 64 ₂ , 64 ₃ , It is sufficient to connect to the vertical drive circuit 112 constituting the drive circuit.

Then, by adopting such a configuration, a kind of charge transfer gradient is formed, and in the state of V ₁₂ ≥ V ₁₁ in the charge accumulation period, the n-th photoelectric conversion section segment is the (n + 1) More charges can be accumulated than the first photoelectric conversion section. In the charge transfer period, when V ₂₂ <V ₂₁ , the flow of charge from the first photoelectric conversion unit segment to the first electrode, the nth from the (n + 1) th photoelectric conversion unit segment The flow of charge to the first photoelectric conversion section segment can be securely ensured.

Example 4

Example 4 relates to an imaging device according to a fourth aspect of the present disclosure. 14 is a schematic sectional view of a part of the imaging device of Example 4 and a stacked imaging device. In the imaging device of Example 4, the materials constituting the electrode segments for charge accumulation differ in adjacent photoelectric conversion section segments. Here, the value of the work function of the material constituting the insulating layer segment is gradually increased from the _first photoelectric conversion section segment 10 ₁ to the Nth photoelectric conversion section segment 10 _N. In the imaging device of Example 4, the same potential may be applied to all of the N charge accumulation electrode segments, or a different potential may be applied to each of the N charge accumulation electrode segments. In the latter case, the electrode segments 12 ₁ , 12 ₂ , 12 _{3 for} charge accumulation are connected to the vertical drive circuit 112 constituting the drive circuit through the pad portions 64 ₁ , 64 ₂ , 64 ₃ . have.

Example 5

The imaging element of Example 5 is related with the imaging element which concerns on the imaging element concerning 5th aspect of this indication. 15A, 15B, 16A, and 16B are schematic plan views of the electrode segments for charge accumulation in Example 5. FIG. 17 and 18 show equivalent circuit diagrams of the imaging device of Example 5 and the stacked imaging device. 19 is shown in FIG. 19, and the state of electric potential at each site during operation of the imaging device of Example 5 is schematically shown in FIGS. Some of the schematic cross-sectional views of the imaging device of Example 5 and the stacked imaging device are the same as those shown in FIG. 14 or FIG. 23. In the imaging device of Example 5, the area of the electrode segment for charge accumulation is gradually smaller from the _first photoelectric conversion section segment 10 ₁ to the Nth photoelectric conversion section segment 10 _N. . In the imaging device of Example 5, the same potential may be applied to all of the N charge accumulation electrode segments, or a different potential may be applied to each of the N charge accumulation electrode segments. In the latter case, as described in Example 4, the electrode segments 12 ₁ , 12 ₂ , _{1 2 3} for electric charge accumulation arranged spaced apart from each other are driven through the pad portions 64 ₁ , 64 ₂ , 64 ₃ . It is sufficient to connect to the vertical drive circuit 112 constituting the circuit.

In Example 5, the electrode 12 for charge accumulation consists of a plurality of electrode segments 12 ₁ , 12 ₂ , 12 ₃ for charge accumulation. The number of the electrode segments for charge accumulation may be 2 or more, and is set to "3" in Example 5. In addition, in the imaging element and the stacked-type imaging element of Example 5, since the potential of the first electrode 11 is higher than that of the second electrode 16, that is, for example, the positive potential of the first electrode 11 Since is applied and a negative potential is applied to the second electrode 16, in the charge transfer period, the potential applied to the electrode segment 12 ₁ for charge accumulation located closest to the first electrode 11 is It is higher than the electric potential applied to the electrode segment 1 2 ₃ for charge accumulation located at the farthest point from the first electrode 11. As described above, by providing a potential gradient to the electrode 12 for charge accumulation, electrons remaining in the region of the photoelectric conversion layer 15 facing the electrode 12 for charge accumulation, the first electrode 11, furthermore , It is more reliably read by the first floating diffusion layer (FD ₁ ). That is, the charge accumulated in the photoelectric conversion layer 15 is read to the control unit.

In the example shown in Fig. 20, in the charge transfer period, by setting the potential of the electrode segment 1 2 _{3 for} charge accumulation <the potential of the electrode segment 12 _{2 for} charge accumulation <the potential of the electrode segment 12 _{1 for} charge accumulation , The electrons staying in the region of the photoelectric conversion layer 15 are read out as the first floating diffusion layer FD _{1 at the same} time. On the other hand, in the example shown in FIG. 21, in the charge transfer period, the potential of the electrode segment 12 _{3 for} charge accumulation, the potential of the electrode segment 12 _{2 for} charge accumulation, and the potential of the electrode segment 12 _{1 for} charge accumulation By gradually changing (i.e., by changing in a stepped or inclined shape), the electrons that have remained in the region of the photoelectric conversion layer 15 facing the electrode segment 12 ₃ for charge accumulation, the electrode segment 12 for charge accumulation ₂ ) to the region of the photoelectric conversion layer 15 facing, and subsequently, the electrode segment for charge accumulation electrode segment 12 ₂ and the electrons that remained in the region of the photoelectric conversion layer 15 facing, electrode segment for charge accumulation (12 ₁₎ and moved to the area of the opposite one photoelectric conversion layer 15 and subsequently, the electron which remains in the area of the charge accumulation electrode segments (12 ₁₎ and opposite the photoelectric conversion layer 15, the first floating It is reliably read by the diffusion layer (FD ₁ ).

As shown in FIG. 22, a schematic layout diagram of a first electrode constituting a modification of the imaging element of Example 5, an electrode for charge accumulation, and a transistor constituting a control unit is shown as the other source of the reset transistor TR1 _rst . The drain region 51B may be grounded instead of being connected to the power supply V _DD .

Also in the imaging element of Example 5, by adopting such a structure, a kind of charge transfer gradient is formed. That is, since the area of the electrode segment for charge accumulation is gradually smaller from the _first photoelectric conversion section segment 10 ₁ to the Nth photoelectric conversion section segment 10 _N , in the charge accumulation period , V ₁₂ ≥V ₁₁ , more charges can be accumulated in the n-th photoelectric conversion unit segment than in the (n + 1) -th photoelectric conversion unit segment. In the charge transfer period, when V ₂₂ <V ₂₁ , the flow of charge from the first photoelectric conversion unit segment to the first electrode, the nth from the (n + 1) th photoelectric conversion unit segment The flow of charge to the first photoelectric conversion section segment can be securely ensured.

Example 6

Example 6 relates to an imaging element according to a sixth aspect of the present disclosure. 23 is a schematic sectional view of a part of the imaging device of Example 6 and a stacked imaging device. Also, a schematic plan view of the electrode segment for charge accumulation in Example 6 is shown in FIGS. 24A and 24B. The imaging element of Example 6 is provided with a photoelectric conversion part in which the first electrode 11, the photoelectric conversion layer 15 and the second electrode 16 are stacked, and the photoelectric conversion part further comprises a first electrode 11 ), And is provided with an electrode 12 for charge accumulation disposed opposite to the photoelectric conversion layer 15 through the insulating layer 82. Then, when the stacking direction of the electrode 12 for charge accumulation, the insulating layer 82, and the photoelectric conversion layer 15 is set in the Z direction and the direction away from the first electrode 11 is set in the X direction, the electric charge is charged to the YZ virtual plane. The cross-sectional area of the laminated portion when cutting the laminated portion in which the accumulation electrode 12, the insulating layer 82, and the photoelectric conversion layer 15 are stacked changes depending on the distance from the first electrode 11.

Specifically, in the imaging device of Example 6, the thickness of the cross-section of the laminated portion is constant, and the width of the cross-section of the laminated portion becomes narrower as it falls from the first electrode 11. In addition, the width may be continuously narrowed (see FIG. 24A) or may be narrowed in a step shape (see FIG. 24B).

As described above, in the imaging device of Example 5, the cross-sectional area of the laminated portion when the laminated portion in which the electrode 12 for charge accumulation, the insulating layer 82 and the photoelectric conversion layer 15 is cut in the YZ virtual plane, is cut. , Since it varies depending on the distance from the first electrode, a kind of charge transfer gradient is formed, and it becomes possible to transfer the charges generated by photoelectric conversion more easily and reliably.

Example 7

Example 7 relates to a solid-state imaging device according to the first aspect and the second aspect of the present disclosure.

The solid-state imaging device of Example 7,

A first electrode 11 ', a photoelectric conversion layer 15 and a second electrode 16 are provided with a photoelectric conversion unit made of a stack,

The photoelectric conversion unit is further provided with an electrode 12 'for charge accumulation, which is disposed spaced apart from the first electrode 11' and is disposed to face the photoelectric conversion layer 15 through the insulating layer 82. It has a plurality of imaging elements,

The imaging element block is composed of a plurality of imaging elements,

The first electrodes 11 'in a plurality of imaging elements constituting the imaging element block are shared.

Alternatively, the solid-state imaging device of Example 7 includes a plurality of imaging elements described in Examples 1 to 6.

In Example 7, one floating diffusion layer is provided for a plurality of imaging elements. Then, by appropriately controlling the timing of the charge transfer period, it becomes possible for a plurality of imaging elements to share one floating diffusion layer. And in this case, it is possible for a plurality of imaging elements to share one contact hole portion.

In addition, the solid-state imaging device of Example 7 is substantially in Examples 1 to 6, except that the first electrode 11 'in the plurality of imaging elements constituting the imaging element block is shared. It has the same structure and structure as the described solid-state imaging device.

The arrangement state of the first electrode 11 'and the charge storage electrode 12' in the solid-state imaging device of Example 7 is schematically shown in FIGS. 25 (Example 7) and FIG. 26 (First Example of Example 7). Modifications), 27 (the second modification of Example 7), 28 (the third modification of Example 7), and 29 (the fourth modification of Example 7). 25, 26, 29, and 30 show 16 imaging elements, and FIGS. 27 and 28 show 12 imaging elements. And the imaging element block is comprised by two imaging elements. The imaging element block is shown surrounded by a dotted line. The subscripts attached to the first electrode 11 'and the charge storage electrode 12' are for distinguishing the first electrode 11 'and the charge storage electrode 12'. The same is true in the following description. In addition, one on-chip micro-lens (not shown in FIGS. 25 to 34) is provided above one imaging element. Then, in one imaging element block, the first electrode 11 'is sandwiched, and two electrodes 12' for charge accumulation are disposed (see FIGS. 25 and 26). Alternatively, one first electrode 11 'is disposed to face two parallel electrodes 12' for charge accumulation (see FIGS. 29 and 30). That is, the first electrode is arranged adjacent to the electrode for charge accumulation of each imaging element. Alternatively, the first electrodes are disposed adjacent to the charge accumulation electrodes of a part of the plurality of imaging elements, and are not disposed adjacent to the remaining charge accumulation electrodes of the plurality of imaging elements (FIGS. 27 and 28). In this case, in this case, the movement of the electric charge from the rest of the plurality of imaging elements to the first electrode is a movement via a part of the plurality of imaging elements. The distance (A) between the charge accumulation electrode constituting the imaging element and the charge accumulation electrode constituting the imaging element is the distance (B) between the first electrode and the charge accumulation electrode in the imaging element adjacent to the first electrode. Longer than) is preferable because the transfer of electric charges from each imaging element to the first electrode is ensured. In addition, it is preferable that the value of the distance A is increased as the imaging element positioned away from the first electrode. In addition, in the example shown in FIGS. 26, 28, and 30, the transfer control electrode 13 'is provided between the plurality of imaging elements constituting the imaging element block. By disposing the transfer control electrode 13 ', the movement of charges in the imaging element block by sandwiching the transfer control electrode 13' can be reliably suppressed. In addition,, V _12> V ₁₃ (for example, _12- V _2> V ₁₃₎ may be in when the potential applied to the transfer control electrode (13 ') to V _13.

The transfer control electrode 13 'may be formed on the first electrode side at the same level as the first electrode 11' or the charge storage electrode 12 ', and may be at a different level (specifically, the first electrode). (11 ') or a level lower than the charge storage electrode 12'. In the former case, since the distance between the transfer control electrode 13 'and the photoelectric conversion layer can be shortened, it is easy to control the potential. On the other hand, in the latter case, the distance between the transfer control electrode 13 'and the charge storage electrode 12' can be shortened, which is advantageous for miniaturization.

Hereinafter, the first electrode (11 _'2) and two two charge accumulation electrode (12, operation of the image pickup element block is configured by _21, 12, _22).

In the charge accumulation period, from the driving circuit, a first electrode (11 _'2), the potential (V _a) to be applied, charge accumulation electrode (12', the potential (V _A) to _21, 12, ₂₂₎ is applied. The photoelectric conversion occurs in the photoelectric conversion layer 15 by the light incident on the photoelectric conversion layer 15. Holes generated by photoelectric conversion are sent from the second electrode 16 to the driving circuit through the wiring V _OU . On the other hand, since the potential of the first electrode 11 ' ₂ is made higher than the potential of the second electrode 16, that is, for example, a positive potential is applied to the first electrode 11' ₂ and the second electrode Since it is said that negative potential is applied to (16), V _A ≥V _a , preferably V _A > V _a . This is a result, electrons generated by photoelectric conversion, charge accumulation electrode (12, _21, 12, ₂₂₎ is pulled, the charge accumulation electrode (12, _21, 12, ₂₂₎ and opposing a photoelectric conversion layer ( 15). That is, electric charges are accumulated in the photoelectric conversion layer 15. Since V _A ≥ V _a , electrons generated inside the photoelectric conversion layer 15 do not move toward the first electrode 11 ′ ₂ . With the passage of time of the photoelectric conversion, the potential in the region of the photoelectric conversion layer 15 facing the electrodes 12 _'21 and 12' _{22 for} charge accumulation becomes a more negative value.

In the later stage of the charge accumulation period, a reset operation is performed. Thereby, the potential of the first floating diffusion layer is reset, and the potential of the first floating diffusion layer becomes the potential V _DD of the power source.

After completion of the reset operation, the charge is read. That is, in the charge transfer period, the potential V _b is applied to the first electrode 11 ′ ₂ from the driving circuit, and the potential V _{21 -B} is applied to the electrode 12 ′ _{21 for} charge accumulation, The potential V _{22 -B} is applied to the charge accumulation electrode 12 ′ ₂₂ . Here, let V _{21 -B} <V _b <V _22-B . Thus, the charge accumulation electrode (12, ₂₁₎ and the electrons, the first electrode (11, which remains in the area of the opposite one photoelectric conversion layer 15 _'2), and further, a 1 is read by the floating diffusion layer. In other words, the charges accumulated in the area of the photoelectric conversion layer 15 opposite to the charge accumulation electrode (12, ₂₁₎ is read to the control unit. When the reading is completed, it is assumed that V _22-B ≤ V _21-B <V _b . In the examples shown in Figs. 29 and 30, V _22-B < V _b &lt; V _21-B may be used. Thus, the charge accumulation electrode (12, ₂₂₎ and the electrons, the first electrode (11, which remains in the area of the opposite one photoelectric conversion layer 15 _'2), and further, a 1 is read by the floating diffusion layer. In Figure 27, the example shown in Figure 28, the charge accumulation electrode (12, ₂₂₎ and the electron which remains in the area of the opposite one photoelectric conversion layer 15, the charge accumulation electrode (12, ₂₂₎ are adjacent and via the first electrode (11, _3), the floating diffusion layer 1 it may be read out. In this way, the charges accumulated in the area of the photoelectric conversion layer 15 opposite to the charge accumulation electrode (12, _22), be read to the control unit. Further, if the charge accumulation electrode (12, ₂₁₎ to read out the electric charges accumulated in the area of the photoelectric conversion layer 15 opposite to the control is completed, it may be reset to the potential of the first floating diffusion layer.

35A shows a read driving example in the imaging element block of Example 7,

[Step-A]

Auto zero signal input to comparator

[Step-B]

Reset operation of one shared floating diffusion layer

[Step-C]

Charge accumulation electrode (12, _21), a P-phase reading of the image sensor and the first corresponding to the

Transfer of charge to the electrode 11 ' ₂

[Step-D]

The charge of the charge transfer to the accumulation electrode (12, ₂₁₎ the read-state imaging element D, and the first electrode (11 in response to _"2)

[Step-E]

Reset operation of one shared floating diffusion layer

[Step-F]

Auto zero signal input to comparator

[Step-G]

The charge of the charge transfer to the accumulation electrode (12, ₂₂₎ the image pickup device P phase readout and the first electrode (11 in response to _"2)

[Step-H]

The charge of the charge transfer to the accumulation electrode (12, ₂₂₎ the read-state imaging element D, and the first electrode (11 in response to _"2)

Of the flow, it reads a signal from the two imaging elements corresponding to the charge accumulation electrode (12, ₂₁₎ and _the charge accumulation electrode (12, _22). Any two of the basis of the sampling (CDS) processing, the difference between the D and the reading of the P-phase reading at Step -C] and [Step -D], corresponding to the charge accumulation electrode (12, ₂₁₎ a signal from the image sensor, the signal from the image sensing element corresponding to step -G] P-phase readout and step -H] the difference between the D-phase reading, charge accumulation electrode (12, ₂₂₎ in at to be.

Note that the operation of [Step-E] may be omitted (see Fig. 35B). Further, the operation of [Step-F] may be omitted, and in this case, [Step-G] may be omitted further (see FIG. 35C), and P-phase reading and [Step] of [Step-C] may be omitted. the difference between the D-phase reading at -D], and the signals from the image sensing element corresponding to the charge accumulation electrode (12, _21), in step -D] D phase readout and in step -H] the difference between the D-phase reading, and the signal from the image sensing element corresponding to the charge accumulation electrode (12, _22).

The arrangement state of the first electrode 11 'and the charge accumulation electrode 12' is schematically shown in Figs. 31 (6th modification example of Example 7) and Fig. 32 (7th modification example of Example 7). In the modification example described above, an imaging element block is composed of four imaging elements. The operation of these solid-state imaging devices can be substantially the same as those of the solid-state imaging devices shown in FIGS. 25 to 30.

In the eighth modification example and the ninth modification example schematically showing the arrangement state of the first electrode 11 'and the charge accumulation electrode 12', the imaging element block is composed of 16 imaging elements. It is composed. 33 and as shown in FIG. 34, the charge accumulation electrode (12, ₁₁₎ and the charge accumulation electrode (12 'applied ₁₂₎ between the charge accumulation electrode (12, ₁₂₎ and the charge accumulation of the electrode (12 in between the _"13) and between the charge accumulation electrode (12, ₁₃₎ and the charge accumulation electrode (12, _14), the transfer control electrode _{(13'A 1, 13'A 2, 13'A} 3) This is excreted. As it is shown in Figure 34, the charge accumulation electrode (12, _21, 12, _31, 13, ₄₁₎ and the charge accumulation electrode (12, _22, 12, _32, 13, ₄₂₎ between the charge accumulating electrode (12, _22, 12, _32, 13, ₄₂₎ and the charge accumulation electrode (12, _23, 12, _33, 13, ₄₃₎ between the charge accumulation electrode (12, _23, 12, ₃₃ , in between the 13, ₄₃₎ and the charge accumulation electrode (12, _24, 12, _34, 13, ₄₄₎ it is provided with a transfer control electrode _{(13'B 1, 13'B 2, 13'B} 3) . Furthermore, an electrode 13'C for transmission control is provided between the imaging element block and the imaging element block. And in these solid-state imaging devices, by controlling the 16 charge accumulation electrodes 12 ', the charge accumulated in the photoelectric conversion layer 15 can be read from the first electrode 11'.

[Step-10]

Specifically, first, "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the (first electrode ₁₁ (charge accumulation electrode 11, 12), reads from). Next, the area of the photoelectric conversion layer 15 opposite to "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(12, charge accumulation electrode (12 charge accumulation electrode 12), ₁₁₎ It reads from the 1st electrode 11 'via. Opposite to the next, charge accumulation electrode (12, _13), the charge accumulated in the region of the photoelectric conversion layer 15, the charge accumulation electrode (12 opposed to the _'12) and a charge accumulation electrode (12, ₁₁₎ It reads from the 1st electrode 11 'via the region of the photoelectric conversion layer 15.

[Step-20]

After that, moves to an area of the photoelectric conversion layer 15 opposite to "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(21, charge accumulation electrode (12 charge accumulation electrode 12), ₁₁₎ Order. Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(22, charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _12). Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(23, charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _13). Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(24-charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _14).

[Step-21]

Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(31, charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _21). Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(32-charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _22). Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(33, charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _23). Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(34, charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _24).

[Step-22]

Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to ₍₄₁ charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _31). Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(42-charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _32). Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to ₍₄₃ charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _33). Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to ₍₄₄ charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _34).

[Step-30]

And, by executing again the Step -10], the photoelectric charge accumulation electrode opposed to the "electric charge, charge accumulation electrode (12 accumulated in the area of the photoelectric conversion layer 15 opposite to the _{(21 22)} 12) ' opposite to the "electric charge, and a charge accumulation electrode (12 accumulated in the area of the photoelectric conversion layer 15 opposite to _{(23, 24)} the charges, charge accumulation electrode 12)" stored in the area of the conversion layer 15 The charge accumulated in the region of the photoelectric conversion layer 15 can be read via the first electrode 11 '.

[Step-40]

After that, moves to an area of the photoelectric conversion layer 15 opposite to "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(21, charge accumulation electrode (12 charge accumulation electrode 12), ₁₁₎ Order. Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(22, charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _12). Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(23, charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _13). Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(24-charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _14).

[Step-41]

It is moved to the area of the photoelectric conversion layer 15 opposite to "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the ₍₃ 1 charge accumulation electrode (12 charge accumulation electrode 12), _21). Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(32-charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _22). Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(33, charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _23). Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(34, charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _24).

[Step-50]

And, by executing again the Step -10], charge accumulation electrode opposite to the "electric charge, charge accumulation electrode (12 accumulated in the area of the photoelectric conversion layer 15 opposite to the _{(31 32)} 12) ' in 'the electric charge, and a charge accumulation electrode (12 accumulated in the area of the photoelectric conversion layer 15 opposite to _{(33, 34)} the charges, charge accumulation electrode 12) "stored in the area of the photoelectric conversion layer 15 The charge accumulated in the region of the opposing photoelectric conversion layer 15 can be read via the first electrode 11 '.

[Step-60]

After that, moves to an area of the photoelectric conversion layer 15 opposite to "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(21, charge accumulation electrode (12 charge accumulation electrode 12), ₁₁₎ Order. Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(22, charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _12). Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(23, charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _13). Moves "the charge accumulated in the region of the photoelectric conversion layer 15 opposite to the _(24-charge accumulation electrode (charge accumulation electrode 12, 12), the area of the photoelectric conversion layer 15 opposed to _14).

[Step-70]

And, by executing again the Step -10], the photoelectric charge accumulation electrode opposed to the "electric charge, charge accumulation electrode (12 accumulated in the area of the photoelectric conversion layer 15 opposite to the _{(41 42)} 12) ' opposite to the "electric charge, and a charge accumulation electrode (12 accumulated in the area of the photoelectric conversion layer 15 opposite to the _{(43 44)} the charges, charge accumulation electrode 12)" stored in the area of the conversion layer 15 The charge accumulated in the region of the photoelectric conversion layer 15 can be read via the first electrode 11 '.

In the solid-state imaging device of Example 7, since the first electrodes are shared by a plurality of imaging elements constituting the imaging element block, it is possible to simplify and refine the structure and structure in a pixel region where a plurality of imaging elements are arranged. Further, the plurality of imaging elements provided for one floating diffusion layer may be composed of a plurality of first type imaging elements, and at least one first type imaging element and one or more second type imaging elements. It may be composed of.

Example 8

Example 8 is a modification of Example 7. In the solid-state imaging device of Example 8 shown schematically in the arrangement state of the first electrode 11 'and the electrode 12' for charge accumulation, two imaging elements are provided. The imaging device block is constructed. Then, one on-chip micro-lens 90 is provided above the imaging element block. In addition, in the example shown in FIGS. 37 and 39, the transfer control electrode 13 'is provided between a plurality of imaging elements constituting the imaging element block.

For example, the photoelectric conversion layer corresponding to the electrodes 12 _'11 , 12' ₂₁ , 12 _'31 and 12' ₄₁ for charge accumulation constituting the imaging element block is high in the incident light from above the drawing and the right slope. It has sensitivity. In addition, the photoelectric conversion layer corresponding to the electrodes 12 _'12 , 12' ₂₂ , 12 _'32 and 12' ₄₂ for charge accumulation constituting the imaging element block has high sensitivity to incident light from above the drawing and the left slope. Have Thus, for example, it becomes possible by combining an imaging device with the "imaging device and the charge accumulation electrode (12 having a _{(11 12)} charge accumulation electrode 12), the upper surface (像面) obtaining the phase difference signal. Further, when adding the signals from the image sensing device having a "signal and the charge accumulation electrode (12 from the image pickup element having a _{(11, 12)} charge accumulation electrode 12) ', by a combination of the imaging element, one image pick-up of the Device can be configured. In the example shown in Figure 36, there is arranged a first electrode (11'1) between the charge accumulation electrode (12, ₁₁₎ and the charge accumulation electrode (12, _12), the example shown in Figure 38 and Thus, by placing a first electrode (11 _'1) opposite to the juxtaposition of two charge accumulation electrode (12, _11, 12, _12), it is possible to improve the sensitivity of incidentally.

Example 9

Example 9 is a modification of Examples 1-6. The imaging element of Example 9 showing a partial cross-sectional view schematically in FIG. 40, and a stacked image pickup element are surface-illumination image pickup elements and stacked image pickup elements, each having a first type of green photoelectric conversion layer that absorbs green light. Sensitivity to blue with a green type imaging element (first imaging element) of Examples 1 to 6 having a sensitivity to green, and a second type of blue photoelectric conversion layer that absorbs blue light. A second type of conventional imaging device for red color having a second type of conventional red imaging device having a second type of red photoelectric conversion layer that absorbs red light. It has a structure in which three imaging elements of (third imaging element) are stacked. Here, the red imaging element (third imaging element) and the blue imaging element (second imaging element) are provided in the semiconductor substrate 70, and the second imaging element is on the light incident side than the third imaging element. Located. Moreover, the green imaging element (first imaging element) is provided above the blue imaging element (second imaging element).

In addition, in FIGS. 40, 41, 42, 43, 44, 45, 48, 49, 51, 52, 53, 54, 55, and 56, the drawings are simplified. , The illustration of the photoelectric conversion section segment is omitted, and shown as the electrode 12 for charge accumulation, the insulating layer 82, and the photoelectric conversion layer 15.

On the surface 70A side of the semiconductor substrate 70, as in Example 1, various transistors constituting the control unit are provided. These transistors can have substantially the same structure and structure as the transistors described in Example 1. In addition, the semiconductor substrate 70 is provided with a second imaging element and a third imaging element. These imaging elements also have substantially the same configuration and structure as the second imaging element and the third imaging element described in Example 1. can do.

On the surface 70A of the semiconductor substrate 70, interlayer insulating layers 77 and 78 are formed, and photoelectricity constituting the imaging elements of Examples 1 to 6 in the amount of the interlayer insulating layers 78 A conversion unit (first electrode 11, photoelectric conversion layer 15 and second electrode 16), an electrode 12 for charge accumulation, and the like are provided.

In this way, the structure and structure of the image pickup device of Example 9 and the stacked image pickup device, except for the surface irradiation type, can be the same as the configuration and structure of the image pickup device of Examples 1 to 6 and the stacked image pickup device. Therefore, detailed description is omitted.

Example 10

Example 10 is a modification of Examples 1 to 9.

The imaging element of Example 10 and a stacked image pickup element showing a schematic partial sectional view in FIG. 41 are a back-illumination image pickup element and a stacked image pickup element, and are the first image pickup elements of Examples 1 to 6 of the first type. , And a structure in which two imaging elements of the second imaging element of the second type are stacked. In addition, the modified example of the imaging element of Example 10 and a laminated | stacked imaging element which show some sectional drawing schematically in FIG. 42 are surface irradiation-type imaging element and a laminated | stacked imaging element, and are the 1st type of Examples 1-6. It has a structure in which two imaging elements of the first imaging element and the second imaging element of the second type are stacked. Here, the first imaging element absorbs primary color light, and the second imaging element absorbs complementary color light. Alternatively, the first imaging element absorbs white light, and the second imaging element absorbs infrared light.

A modified example of the imaging element of Example 10 showing a schematic partial cross-sectional view in FIG. 43 is a back-illumination imaging element, and is composed of the first imaging elements of Examples 1 to 6 of the first type. In addition, a modification example of the imaging element of Example 10 showing a schematic cross-sectional view in FIG. 44 is a surface irradiation type imaging element, and is composed of the first imaging elements of Examples 1 to 6 of the first type. have. Here, the first imaging element is composed of three types of imaging elements: an imaging element that absorbs red light, an imaging element that absorbs green light, and an imaging element that absorbs blue light. Furthermore, a solid-state imaging device according to the third aspect of the present disclosure is configured from a plurality of these imaging elements. As an arrangement of a plurality of these imaging elements, a Bayer arrangement is exemplified. Color filters for performing spectroscopy of blue, green, and red are provided on the light incident side of each imaging element, if necessary.

In addition, instead of providing one of the imaging elements of Examples 1 to 6 of the first type, two or more of them are stacked (i.e., two photoelectric conversion units are stacked, and two imaging elements are stacked on a semiconductor substrate). It is also possible to use a form in which a control unit is provided, or three or in a stacking mode (i.e., three photoelectric conversion units are stacked and a control unit for three imaging elements is provided on a semiconductor substrate). An example of a laminated structure of the first type of imaging element and the second type of imaging element is exemplified in the following table.

Example 11

Example 11 is a modification of Examples 1 to 10, and relates to the imaging device of the present disclosure provided with a discharge electrode. 45 is a schematic partial cross-sectional view of a part of the imaging device of Example 11 and a part of a stacked-type imaging device, and a schematic arrangement diagram of the first electrode, charge accumulation electrode, and charge discharge electrode constituting the imaging device of Example 11 is shown. 46 is a schematic perspective perspective view of a first electrode, a charge accumulation electrode, a charge discharge electrode, a second electrode, and a contact hole portion constituting the imaging element of Example 11, shown in FIG.

In the imaging device of Example 11 and the stacked imaging device, the charge discharge electrode is connected to the photoelectric conversion layer 15 through the connecting portion 69 and is spaced apart from the first electrode 11 and the charge storage electrode 12. (14) is also provided. Here, the charge discharge electrode 14 is disposed to surround the first electrode 11 and the charge storage electrode 12 (that is, in a frame shape). The charge discharge electrode 14 is connected to a pixel driving circuit constituting the driving circuit. In the connecting portion 69, a photoelectric conversion layer 15 is extended. That is, the photoelectric conversion layer 15 extends in the second opening 85 provided in the insulating layer 82 and is connected to the charge discharge electrode 14. The charge discharge electrode 14 is shared (common) with a plurality of imaging elements.

Exemplary cases of the 11, in the charge accumulation period, from the driving circuit, is applied to the potential (V ₁₁₎ to the first electrode 11, it is applied to the potential (V ₁₂₎ to the charge accumulation electrode 12, a charge-discharge electrode The potential V ₁₄ is applied to the ₁₄ and charge is accumulated in the photoelectric conversion layer 15. The photoelectric conversion occurs in the photoelectric conversion layer 15 by the light incident on the photoelectric conversion layer 15. Holes generated by photoelectric conversion are sent from the second electrode 16 to the driving circuit through the wiring V _OU . On the other hand, since the potential of the first electrode 11 is set higher than that of the second electrode 16, that is, for example, a positive potential is applied to the first electrode 11, and the second electrode 16 is applied. Since negative potential is applied, V ₁₄ > V ₁₁ (eg, V ₁₂ > V ₁₄ > V ₁₁ ). Thereby, the electrons generated by the photoelectric conversion are attracted to the electrode 12 for charge accumulation, stopped in the region of the photoelectric conversion layer 15 facing the electrode 12 for charge accumulation, and the first electrode 11 It can be surely prevented from moving toward). However, electrons (so-called overflowed electrons) that are not sufficiently attracted by the charge storage electrode 12 or that are not all accumulated in the photoelectric conversion layer 15 pass through the charge discharge electrode 14. Thus, it is sent to the driving circuit.

In the later stage of the charge accumulation period, a reset operation is performed. Accordingly, the potential of the first floating diffusion layer FD ₁ is reset, and the potential of the first floating diffusion layer FD ₁ becomes the potential V _DD of the power source.

After completion of the reset operation, the charge is read. That is, in the charge transfer period, from the driving circuit, the electric potential to the first electrode 11, the potential (V ₂₁₎ is, charge accumulation electrode 12 is applied to the (V ₂₂₎ is applied, charge-discharge electrode 14, The potential V ₂₄ is applied to. Here, let V ₂₄ <V ₂₁ (for example, V ₂₄ <V ₂₂ <V ₂₁ ). As a result, electrons remaining in the region of the photoelectric conversion layer 15 facing the charge storage electrode 12 are reliably read by the first electrode 11 and, further, the first floating diffusion layer FD ₁ . . That is, the charge accumulated in the photoelectric conversion layer 15 is read to the control unit.

Thus, a series of operations such as charge accumulation, reset operation, and charge transfer are completed.

The operations of the amplifying transistor TR1 _amp and the selection transistor TR1 _sel after the electrons are read into the first floating diffusion layer FD ₁ are the same as those of the conventional transistors. In addition, for example, the series of operations of charge accumulation, reset operation and charge transfer of the second imaging element and the third imaging element are the same as those of the conventional series of operations of charge accumulation, reset operation and charge transfer.

In Example 11, the so-called overflowed electrons are sent to the driving circuit via the charge discharge electrode 14, so that leakage of adjacent pixels into the charge accumulation portion can be suppressed and occurrence of blooming can be suppressed. And thereby, the imaging performance of the imaging element can be improved.

Example 12

As another embodiment of the present disclosure, Example 12 will be described using FIGS. 61 to 96.

In the first embodiment described with reference to FIGS. 1 to 56 and the modification example and the solid-state imaging device 100 serving as a modification thereof, as shown in FIG. 9, the stacked imaging device 101 is a repeating unit, It is provided with the imaging region 111 which is arranged and arranged in a two-dimensional array. Then, with respect to the stacked image pickup device 101 serving as a repeating unit, (1) equivalent circuits of the first to third imaging devices 102 to 104 provided in the stacked image pickup device 101 are shown in FIG. (2) The entire equivalent circuit of the stacked image pickup devices 101 provided with the first to third image pickup devices 102 to 104 is shown in FIG. 4, and (3) included in the stacked image pickup devices 101. The layout of the transistor on the first surface of the semiconductor substrate 70 is shown in Fig. 5, and (4) cross-sectional views of the stacked image pickup device 101 are shown in Figs.

The solid-state imaging device 100 disclosed as Example 12 differs from Example 1 in the structure on the equivalent circuit, the cross-sectional structure, and the planar structure. Each of these differences will be described.

<Sectional structure>

61 is a diagram showing a cross-sectional structure of a stacked imaging element 101 provided in the solid-state imaging device 100 of Example 12.

The cross-sectional structure of the stacked image pickup device 101 of Example 12 described in FIG. 61 has the same basic configuration as the stacked image pickup device 101 serving as a modification of Example 1 shown in FIG. 56. That is, one stacked image pickup element 101 (in other words, one stacked image pickup element 101),

(1) One on-chip micro lens 90,

(2) As the photoelectric conversion unit constituting the first imaging element 102, the first electrode 11, the electrode 12 for charge accumulation, the insulating layer 82, the semiconductor layer 15B, and the photoelectric conversion layer ( 15A) and one photoelectric conversion unit 17 including the second electrode 16,

(3) one PD 2 constituting the second imaging element 103,

(4) One PD 3 constituting the third imaging element 104 is

It is provided by lamination.

However, as the description on the drawing, the cross-sectional structure of the stacked image pickup device 101 of Example 12 shown in FIG. 61 is the cross-sectional structure of the stacked image pickup device 101 serving as a modification of Example 1 shown in FIG. 56, The following points differ.

(1) In the stacked image pickup device 101 shown in Fig. 56, the second electrode 16, the photoelectric conversion layer 15B, and the semiconductor layer 15A have an outer edge in the left and right directions of the drawing. On the other hand, in the stacked-type imaging element 101 serving as Example 12, the second electrode 16, the photoelectric conversion layer 15B, and the semiconductor layer 15A have a plurality of stacked-type imaging elements 101 (in other words, multiple pixels) It is extended over the stacked-layer imaging device 101 of the minute. More preferably, it extends over the entire imaging area (in other words, the pixel array area 111) provided in the solid-state imaging device 100. In the stacked image pickup device 101 shown in Fig. 61, the second electrode 16, the photoelectric conversion layer 15B, and the semiconductor layer 15A have no outer edges in the left and right directions in the drawing. However, the second electrode 16, the photoelectric conversion layer 15B, the semiconductor layer 15A, or the photoelectric conversion layer 15 are extended over the multi-pixel stacked imaging element 101, and the cell configuration is: It is also applicable to all the examples of the present disclosure and variations thereof. For this reason, the difference in the above-described configuration for these films is that of the stacked-type imaging element 101 of Example 12 shown in FIG. 61 and of the stacked-type imaging element 101 which becomes a modification of Example 1 shown in FIG. , It is not an essential difference.

(2) In the stacked-type imaging element 101 shown in Fig. 56, the electrode 12 for charge accumulation includes a connection hole 66, a pad portion 64, and a metal wiring layer that is the same layer as the pad portion 64. It is configured to be driven between the charge accumulation electrode 12 and the contact hole portion 61 and is driven through the drive wiring VAO of the charge accumulation electrode shown in FIG. 8 extending across a plurality of pixels. On the other hand, the stacked-type imaging element 101 which becomes Example 12 is among the interlayer insulating layers 81 between one surface 70B and the photoelectric conversion section 17 located on the incident side of the light of the semiconductor substrate 70. , A wiring layer of a conductor that can be used for a signal wiring or a supply line of a specific voltage and a connection structure therein are provided in two sets and stacked in the stacking direction of the stacked image pickup device 101. However, the structure provided with the above-mentioned two sets of wiring layers and the connection structure therefor is applicable also to all the embodiments of this disclosure and its modification. For this reason, the difference in the above structures related to these wirings and connection structures is the stacked image pickup device 101 of Example 12 shown in FIG. 61 and a stacked image pickup device serving as a modification of Example 1 shown in FIG. 56 ( 101), it is not an essential difference.

(3) In the stacked-type imaging element 101 shown in Fig. 56, the semiconductor substrate 70 is disposed on the side opposite to the incident light, and placed below one surface 70A (the direction opposite to the incident surface of the light). In the interlayer insulating layer 76, the wiring layer 62 is described as a wiring layer in the drawing. On the other hand, the stacked-type imaging element 101 used as Example 12 includes at least three or more wiring layers in the interlayer insulating layer 76. In Fig. 61, three layers of wiring layers 62A to 62C in the interlayer insulating layer 76 and connection structures therein are described. However, the structure provided with the said multiple layer wiring layer and the connection structure to it is applicable also to all the Example of this indication and its modification. For this reason, the difference in the above-described configuration regarding the wiring and the connection structure is the stacked-type imaging device 101 of Example 12 shown in FIG. 61 and a stacked-type imaging device 101 serving as a modification of Example 1 shown in FIG. ), Not an essential difference.

(4) In the stacked-type imaging element 101 shown in Fig. 1, the photoelectric conversion section is provided with N photoelectric conversion section segments, whereby it is arranged between the electrode 12 for charge accumulation and the photoelectric conversion layer 15. The insulating layer 82 and the electrode 12 for charge accumulation are configured such that their film thickness varies depending on the distance from the first electrode. On the other hand, the stacked-type imaging element 101 which becomes Example 12 may be provided with the said N photoelectric conversion part segment, without the photoelectric conversion part segment, the insulating layer 82 and the electrode for charge accumulation ( The film thickness of 12) may be a constant film thickness without depending on the distance from the first electrode.

<Equivalent circuit>

FIG. 62 shows equivalent circuits of four stacked imaging elements 101 provided in the solid-state imaging device 100 of Example 12, in other words, four pixels.

In the stacked image pickup device 101 of Example 1 described in FIGS. 3 and 4, one pixel is provided with one of the first to third imaging elements 102 to 104,

(1) The first imaging element 102 includes a first electrode 11, an electrode 12 for charge accumulation, an insulating layer 82, a photoelectric conversion layer 15, and a second electrode 16. A photoelectric conversion unit 17, a reset transistor TR1 _rst , which is a pixel transistor constituting the first imaging element 102, an amplification transistor TR1 _amp and a selection transistor TR1 _sel , and each photoelectric A first floating diffusion layer (FD1) connected to the conversion unit 17 is provided,

(2) The second imaging element 103 includes a photodiode PD2 including an n-type semiconductor region 41 and a transfer transistor TR2 _{trs which} is a pixel transistor constituting the second imaging element 103. And a reset transistor TR2 _rst , an amplifying transistor TR2 _amp , a selection transistor TR2 _sel , and a second floating diffusion layer FD2 connected to the transfer transistor TR2 _trs . ,

(3) The third imaging element 104 includes a photodiode PD3 including an n-type semiconductor region 43 and a transfer transistor TR3 _{trs which} is a pixel transistor constituting the third imaging element 104. And a reset transistor TR3 _rst , an amplifying transistor TR3 _amp , a selection transistor TR3 _sel , and a third floating diffusion layer FD3 connected to the transfer transistor TR3 _trs . have.

In contrast, in the stacked image pickup device 101 of Example 12 shown in FIG. 62, a plurality of first to third image pickup devices 102 to 104 provided in the stacked image pickup device 101 for a plurality of pixels, It has a structure in which the pixel transistor, which is an element constituting the imaging element, and the floating diffusion layer are shared.

Referring to Fig. 62, a specific configuration of the stacked image pickup device 101 of Example 12 will be described.

The four-pixel stacked imaging element 101 shown in FIG. 62 includes four first imaging elements 102, four second imaging elements 103, and four third imaging elements 104. ).

Each of the four first imaging elements 102 includes four photoelectric conversion units 17, one in total. The four photoelectric conversion units 17 are connected to one first floating diffusion layer FD1.

One reset transistor TR1 _rst and a power supply line Vdd are connected to the first floating diffusion layer FD1 in series. Separately, each of the amplifying transistor TR1 _amp and the selection transistor TR1 _sel and the signal line (data output line) VSL ₁ are connected in series to the first floating diffusion layer FD1.

Each of the four charge accumulation electrodes 12 provided in the four photoelectric conversion units 17, the reset transistor TR1 _rst , the amplifying transistor TR1 _amp and the selection transistor TR1 _sel , respectively, the A set of control units (first control units) that are responsible for the read operation and reset operation of the four first imaging elements 102 are configured.

The four first imaging elements 102 provided in the four-pixel stacked imaging element 101 shown in FIG. 62, except for the electrode 12 for charge accumulation, are a set of the above-described control unit (first control unit) ). When the electric charges generated in the photoelectric conversion units 17 provided in the four first imaging elements 102 are read, time-divided and sequentially read processing is performed using the first control unit.

Each of the four second imaging elements 103 provided in the four-pixel stacked imaging element 101 shown in FIG. 62 includes one and four photodiodes PD2 in total. The four photodiodes PD2 are connected to one second floating diffusion layer FD2 through four transfer transistors TR2 _trs .

The four third imaging elements 104 provided in the four-pixel stacked imaging element 101 shown in Fig. 62 include one and four photodiodes PD3 in total. The four photodiodes PD3 are also connected to the third floating diffusion layer FD2 through four transfer transistors TR3 _trs .

One reset transistor TR2 _rst and a power supply line Vdd are connected to the second floating diffusion layer FD2 in series. Separately, one of the amplifying transistor TR2 _amp and the selection transistor TR2 _sel and a signal line (data output line) VSL2 are connected in series to the second floating diffusion layer FD2.

The four transfer transistors TR2 _trs , the four transfer transistors TR3 _trs , the reset transistor TR2 _rst , the amplification transistor TR2 _amp , and the selection transistor TR2 _sel , each of the four A pair of control units (second control unit), which are in charge of the read operation and the reset operation, of the two second imaging elements 103 and the four third imaging elements 104 are constituted.

The four second imaging elements 103 and four third imaging elements 104 provided in the four-pixel stacked imaging element 101 shown in FIG. 62 include transfer transistors TR2 _trs and transfer transistors. Except for (TR3 _trs ), it is configured to share the above-described set 1 control section (second control section). When reading charges generated by the photodiode PD2 provided in the four second imaging elements 103 and the photodiode PD3 provided in the four third imaging elements 104, the second A time-divided and read-out process is performed using the control unit.

As described above, in Example 12 described in FIG. 62, the four-pixel stacked imaging element 101 excludes the electrode 12 for charge accumulation, the transfer transistor TR2 _trs , and the transfer transistor TR3 _trs , It has a configuration in which the first set of control units and the second set of control groups are shared between the four-layer stacked imaging elements 101. More specifically, one set of the first control unit is constituted by each of the reset transistor TR1 _rst , the amplifying transistor TR1 _amp and the selection transistor TR1 _sel , and the reset transistor TR2 _rst and amplified. Each of the transistor TR2 _amp and the selection transistor TR2 _sel constitutes a set of second control units, and the first set of control units and the second set of control units are stacked for four pixels. ).

In Example 12 of the present disclosure, on the equivalent circuit shown in Fig. 62, the four-pixel stacked imaging element 101 is used as one repeating unit and arranged in a plurality of two-dimensional shapes, thereby providing the solid-state imaging device 100. The provided pixel array 111 is formed.

In Example 12 of the present disclosure, the first control unit of the first set and the second control group of the first set are shared between the four-layer stacked imaging elements 101. For this reason, as in Example 1 described in Figs. 3 and 4, compared to the configuration in which the single-pixel stacked image pickup device 101 has a control unit independently of each other, the configuration in Example 12 is the transistor required. There are few, and as a result, the action effect of being easy to achieve high integration of the stacked-type imaging element 101 and the solid-state imaging device 100 using the same occurs.

<Plane structure>

63 is a diagram showing a partial planar structure of the pixel array 111 provided in the solid-state imaging device 100 of Example 12. Fig. 63 shows a planar structure of a total of 16 pixels in a stacked image pickup device 101, each of four pixels in the row direction and the column direction.

More specifically, in Figure 63,

(1) A pixel transistor provided in the first to third imaging elements 102 to 104 of the stacked imaging element 101, wherein the active region of the transistor formed on one surface 70A of the semiconductor substrate 70 is formed. With a solid line,

(2) A pixel transistor provided in the first to third imaging elements 102 to 104 of the stacked imaging element 101, wherein the gate electrode of the transistor formed on one surface 70A of the semiconductor substrate 70 is provided. With a solid line,

(3) The on-chip micro-lens 90 provided in the stacked-type imaging element 101 is a two-dot chain line of thin lines,

(4) The line that becomes the outer edge of a pixel for one pixel of the stacked image pickup device 101, that is, the pixel boundary line is a dashed line of thin lines,

(5) The positions (coordinates) of the pixels in the row direction and the column direction of each pixel in the pixel array are in the form of (X, Y),

Is displayed.

As described above, in Example 12 of the present disclosure, the four-pixel stacked imaging element 101 is used as one repeating unit on the equivalent circuit shown in FIG. 62, and a plurality of two-dimensional shapes are arranged to form a solid. The pixel array 111 provided in the imaging device 100 is formed.

FIG. 64 is a view showing the position of each transistor provided with one repeating unit, while the outline of one repeating unit is indicated by a solid line in the same drawing as in FIG. 63.

FIG. 65 is a diagram showing how the repeating units described in FIG. 64 are repeatedly arranged in both the row direction and the column direction of the pixel array 111 in the same view as in FIG. 63.

FIG. 66 is a view in which the planar shape of the photodiode PD3 provided in the third imaging element is additionally described in the same diagram as in FIG. Since the multilayer imaging element 101 for 16 pixels is described in Fig. 66, the photodiode PD3 provided therein is also described for 16 pixels.

In addition, FIG. 66 is a transistor included in one repeating unit described by a Tae-seon, an operation for reading charge generated in the photodiode PD3 provided in the third imaging device, and a second floating diffusion layer provided in the repeating unit ( Eight transistors used for the operation of resetting FD2, that is, four transfer transistors TR3 _trs , one reset transistor TR2 _rst , an amplification transistor TR2 _amp , and a selection transistor TR2 _sel , respectively. Also shown.

In addition, FIG. 66 shows four photodiodes PD3 for the purpose of performing a read operation of charges by connecting to a transistor included in one repeating unit described by a dashed line among the 16-pixel photodiodes PD3 described in the figure. ) Is shown by attaching a net.

As can be seen with reference to Figs. 63, 64, and 66, in Example 12, the transistors included in one repeating unit shown in Figs. The charges of the four photodiodes PD3 provided in the pixels at positions (1, 1), (1, 2), (2, 1), and (2, 2) are read.

FIG. 67 is a diagram showing the charges of the four photodiodes PD3 provided in the pixels at the positions shown in FIG. 63 using the transistor included in the repeating unit shown in FIG. 65 using the repeating unit. .

As described with reference to FIG. 66, the four photodiodes PD3 to be subjected to the read operation using the transistor included in the repeating unit described by the dashed line described in the figure are ( A total of 2 pixels in the row direction of the pixel array 111 and 2 pixels in the column direction, located in 1, 1), (1, 2), (2, 1), (2, 2) It was a two-pixel photodiode (PD3).

In FIG. 67, (1, 1)-(2, 2) is described as a repeating unit at the same position as the repeating unit shown in FIG. 66, and (1, 1) using a transistor provided in the repeating unit, It has been described that the charge of the photodiode PD3 for 2 x 2 pixels located at (1, 2), (2, 1), and (2, 2) is read. In addition, in Fig. 67, it has been described in which repeating unit the charge of the photodiode PD3 provided in the pixel is read. In each repeating unit provided in the pixel array 111 shown in FIG. 67, (2n + 1, 2n + 1), (2n + 1, 2n + 2), (2n + 2, 2n + 1), (2n) +2, 2n + 2), (where n = 0, 1, 2, ...), the charge of the photodiode PD3 for 2x2 pixels is read.

FIG. 68 is a view in which the planar shape of the electrode 12 for charge accumulation of the photoelectric conversion unit 17 provided in the first imaging element is further described in the same diagram as in FIG. In Fig. 68, since the stacked imaging element 101 for 16 pixels is described, the electrode 12 for charge accumulation provided therein is also described for 16 pixels.

Here, in the multilayer imaging element 101 of Example 12, as described with reference to FIG. 62, the four-pixel stacked imaging element 101 serving as a repeating unit is provided with four first imaging elements 102. In addition, the four photoelectric conversion units 17 provided in the four first imaging elements 102 are connected to one first floating diffusion layer FD1. In more detail, the four photoelectric conversion units 17 do not each include a first electrode 11 and an electrode 12 for charge accumulation, and the four photoelectric conversion units 17 are provided. Each of the first electrode 11 for charge accumulation is provided, while for the first electrode 11, the four photoelectric conversion units 17 share one first electrode 11. have. As shown in FIG. 61, the shared first electrode 11 is a through electrode (TSV, Through Silicon Via) (TSV) penetrating through a silicon substrate through two stacked wiring layers and a connection structure therein. 61), and further connected to the wiring layer 62 formed below one surface 70A of the semiconductor substrate 70 through the through electrode 61, and through this, the semiconductor substrate 70 It is connected to one first floating diffusion layer (FD1) 51C formed on one surface 70A of. In FIG. 68, one first electrode 11 and one through electrode 61 shared by the four photoelectric conversion units 17 are also described.

In addition, FIG. 68 is a transistor included in one repeating unit described by a dashed line, which reads the charge generated in the photoelectric conversion unit 17 provided in the first imaging element and the first floating diffusion layer provided in the repeating unit. The positions of the four transistors used for the operation of resetting (FD1), that is, each of the reset transistor TR1 _rst , the amplifying transistor TR1 _amp and the selection transistor TR1 _sel , are also shown.

In addition, FIG. 66 shows four photoelectric conversion targets that are connected to transistors included in one repeating unit described by the dashed line among the electrodes 12 for charge accumulation of 16 pixels described in the figure, and perform an operation for reading electric charges. The electrode 12 for electric charge accumulation provided in the part 17 is shown by netting.

As can be seen with reference to Figs. 63, 64, and 68, in Example 12, the transistors included in one repeating unit shown in Figs. Electric charges are read from the four photoelectric conversion units 17 provided in the pixels at positions (1, 2), (1, 3), (2, 2), and (2, 3).

FIG. 69 is a diagram showing the charges of the four photoelectric conversion units 17 provided in the pixels at the positions shown in FIG. 63 using the transistor included in the repeating unit shown in FIG. 65 using the repeating unit. to be.

As described with reference to Fig. 68, the four photoelectric conversion units 17, which are subjected to the read operation using the transistor included in the repeating unit described by the dashed line described in the figure, at the coordinates shown in Fig. 63, A total of 2 × 2 pixels in the row direction and 2 pixels in the column direction of the pixel array 111, located at (1, 2), (1, 3), (2, 2), (2, 3) It was the photoelectric conversion part 17 of two pixels.

In FIG. 69, (1, 2)-(2, 3) is described as a repeating unit at the same position as the repeating unit shown in FIG. 68, and (1, 2) using transistors provided in this repeating unit, It has been described that the charges of the photoelectric conversion section 17 of 2x2 pixels located at (1, 3), (2, 2), and (2, 3) are read. In addition, in FIG. 69, it is described in which repeating unit the charge of the photoelectric conversion unit 17 provided in the pixel is read. In each repeating unit provided in the pixel array 111 shown in FIG. 69, (2n + 1, 2n + 2), (2n + 1, 2n + 3), (2n + 2, 2n + 2), (2n) +2, 2n + 3), (where n = 0, 1, 2, ...), the charge of the photoelectric conversion section 17 of 2x2 pixels is read.

FIG. 70 is a view in which the planar shape of the photodiode PD2 provided in the second imaging element is further described in the same diagram as in FIG. Since the multilayer imaging element 101 for 16 pixels is described in FIG. 70, the photodiode PD2 provided therein is also described for 16 pixels.

In addition, FIG. 70 is a transistor included in one repeating unit described by a Tae-seon, an operation of reading charge generated in the photodiode PD2 provided in the second imaging element, and a second floating diffusion layer provided in the repeating unit ( Eight transistors used for the operation of resetting FD2), that is, four transfer transistors TR2 _trs and one reset transistor TR2 _rst , amplification transistor TR2 _amp and selection transistor TR2 _sel , respectively. Also shown.

In addition, in the photodiode PD2 for 16 pixels described in the figure, four photodiodes PD2 which are connected to transistors included in one repeating unit described by the dashed line and are subjected to an operation for reading electric charges. ) Is shown by netting.

As can be seen with reference to Figs. 63, 64, and 70, in Example 12, the transistors included in one repeating unit shown in Figures 64 and 70 as a dashed line are described in Fig. 63, The charges of the four photodiodes PD2 provided in the pixels at positions (2, 2), (2, 3), (3, 2), and (3, 3) are read.

FIG. 71 is a diagram showing the charges of the four photodiodes PD2 provided in the pixels at the positions shown in FIG. 63 using the transistor included in the repeating unit shown in FIG. 65 using the repeating unit. .

As described with reference to FIG. 70, the four photodiodes PD2 that are subjected to the read operation using the transistor included in the repeating unit described by the dashed line described in the figure are ( 2, 2), (2, 3), (3, 2), located in (3, 3), the total of 2 pixels in the row direction of the pixel array 111 and 2 pixels in the column direction It was a photodiode for a pixel (PD2).

In FIG. 71, (2, 2)-(3, 3) is described as a repeating unit at the same position as the repeating unit shown in FIG. 70, and a transistor provided in the repeating unit is used as ((2, 2). It was described that the charges of the photodiode PD2 for 2 x 2 pixels located at (2, 3), (3, 2), and (3, 3) were read. It is described in which unit the charge of the photodiode PD2 provided in the pixel is read in. In each repeating unit provided in the pixel array 111 shown in Fig. 71, (2n + 2, 2n + 2) , (2n + 2, 2n + 3), (2n + 3, 2n + 2), (2n + 3, 2n + 3), 2 × 2 pixels (where n = 0, 1, 2,…) The charge of the minute photodiode PD2 is read.

As described with reference to the cross-sectional view illustrated in FIG. 61, in the solid-state imaging device 100 of Example 12, the one-pixel stacked imaging device 101 has the on-chip micro-lens 90 and the first to the first. Three imaging elements 102 to 104 are provided by stacking each one. Further, as described with reference to the equivalent circuit shown in Fig. 62, in the solid-state imaging device 100 of Example 12, the four-pixel stacked imaging element 101 has a first set of control units and a second set of sets. It is configured to share the control unit of. Then, on the equivalent circuit shown in Fig. 62, the four-pixel stacked imaging element 101 is used as one repeating unit and arranged in a plurality of two-dimensional shapes, thereby providing the pixel array 111 provided in the solid-state imaging device 100. ).

However, as can be seen by comparing FIGS. 66, 68, and 70, and also comparing FIGS. 67, 69, and 71, in the solid-state imaging device 100 of Example 12, the one repeat unit The four photoelectric conversion units 17, four photodiodes PD2, and four photodiodes PD3, which are targets to be read by the first set of first control units and the second set of second control units provided in the , It does not necessarily have a structure commonly included in the same four stacked imaging elements 101. For example, when describing one repetition unit commonly described in FIGS. 66, 68, and 70, a set of first control units and a set of second control units provided in the repetition unit are objects to be read. The photodiode PD3 to be provided is provided in the pixels located at (1, 1), (1, 2), (2, 1), and (2, 2), and the first control unit of the first set and one set of The photoelectric conversion unit 17 to be read by the second control unit is provided in pixels located at (1, 2), (1, 3), (2, 2), (2, 3), The photodiodes PD2 to be read by the first control unit of the first set and the second control group of the first set are (2, 2), (2, 3), (3, 2), (3, 3) It is provided in the pixel located at.

The operational effects caused by using such a special configuration will be described below. In order to reduce the number of transistors used to read the charges of the plurality of photodiodes PD3 and to achieve high integration of the stacked image pickup device 101 and the solid-state imaging device 100 using the same, a plurality of control units used for the readings are provided. When attempting to share between the four photodiodes PD3, as shown in FIG. 66, four transfer transistors TR3 _trs each connected to the four photodiodes PD3 are placed close to each other, and placed therein. It is preferable that the third floating diffusion layer (FD3) to be connected is shared. Similarly, in order to reduce the number of transistors used to read the charges of the photoelectric conversion section 17 and the photodiode PD2, as shown in Fig. 68, between the four photoelectric conversion sections 17, one agent It is preferable to have a configuration in which one electrode 11 is shared, and four transfer transistors TR2 _trs each connected to four photodiodes PD2 are disposed close to each other and connected to them. It is preferable that the floating diffusion layer (FD2) is shared.

However, one third floating diffusion layer FD3 is shared among the four photodiodes PD3, one first electrode 11 is shared among the four photoelectric conversion units 17, and four One second floating diffusion layer FD2 is shared between the photodiodes PD2, and the four photodiodes PD3, four photoelectric converters 17, and four photodiodes PD2 are shared. , In order to have a configuration common to the same four stacked imaging elements 101, the first third floating diffusion layer FD3, the first first electrode 11, and the second floating diffusion layer FD2 ) Needs to be placed in almost the same place. If the third floating diffusion layer FD3, the first electrode 11, and the second floating diffusion layer FD2 are to be disposed in substantially the same place, the four stacked imaging elements 101 may be used to secure a place therefor. It is necessary to arrange them separately and to dye the place. In this way, it becomes obstructive to highly integrate the stacked-type imaging element 101 and further to highly integrate the solid-state imaging device 100.

In Example 12 of the present disclosure, the third floating diffusion layer (FD3), the first electrode 11 and the second floating diffusion layer (FD2), which are the targets of the sharing, are almost the same in order to exclude factors that hinder the high integration. Intentionally avoiding the arrangement placed in the place, and disposing the third floating diffusion layer (FD3), the first electrode 11, and the second floating diffusion layer (FD2), which are the targets of the sharing, in a space separated by one pixel each It is configured. More specifically, the first electrode 11 and the second floating diffusion layer FD2 are separated from the third floating diffusion layer FD3 by one pixel in the column direction in the pixel array 111. In addition, the second floating diffusion layer FD2 is disposed at a position separated by one pixel from the third floating diffusion layer FD3 and the first electrode 11 in the row direction of the pixel array 111. . By using this configuration, compared with the solid-state imaging device that does not have this configuration, the effect of being easy to achieve high integration of the solid-state imaging device 100 is produced.

FIG. 72 shows the arrangement of the control signal line V _OA for connecting the charge accumulation electrodes 12 provided in each pixel at the position of the pixel as shown in FIG. 63 and driving the charge accumulation electrodes 12. It is a figure shown. More specifically, in Fig. 72, the center line of the control signal line VAO arranged with a width is shown by a solid line and a dotted line.

As described with reference to FIG. 61, in Example 12, in the interlayer insulating layer 81 between one side 70B of the semiconductor substrate 70 and the photoelectric conversion section 17, a signal line or a supply line of a specific voltage A wiring layer of a conductor that can be used as a material and a connection structure therein are provided in two sets and stacked in the stacking direction of the stacked imaging element 101. In FIG. 72, two sets of control signal lines V _OA described by solid and solid dashed lines are two-layer wiring layers arranged between one surface 70B of the semiconductor substrate 70 and the photoelectric conversion unit 17. In the middle, it is arrange | positioned using each one layer. For this reason, the two sets of control signal lines V _OA described by solid and solid dashed lines in FIG. 72 can be arranged to overlap the center line on the pixel boundary line indicated by the dashed line in FIG. 72. However, in FIG. 72, in order to easily understand that two sets of control signal lines V _OA having different layers are disposed at the pixel boundary line, the two sets of control signal lines V _OA described by solid and solid dashed lines are slightly shown. It is described in a separate manner.

In addition, the two sets of control signal lines V _OA described by solid and solid dashed lines in FIG. 72 can be arranged by using only the wiring layer on the first floor and the connection structure therefor as long as they are arranged apart. In FIG. 73, FIG. 73 shows an example in which two sets of control signal lines (VOA) in an area enclosed by a thin line dashed line are arranged only by a wiring layer on the first floor and a connection structure therein.

FIG. 74 is a part of wiring connected to each element shown in FIG. 64 using wiring provided in the stacked image pickup device 101 at the position of the pixel as shown in FIG. 63 in order to realize the configuration shown in FIG. 62. It is a diagram described.

Fig. 74 is, more specifically, the wiring layer 62A serving as the wiring layer of the first layer closest to one surface 70A of the semiconductor substrate 70 among the plurality of wiring layers 62A to 62C described in Fig. 61. This is a diagram showing the arrangement, and the center line of the wiring layer 62A arranged with a width is shown by a solid line. In addition, the center point of the connection structure between the wiring layer 62A and each transistor or through electrode 61 formed on the surface of the surface 70A is illustrated by a black dot.

To realize the configuration shown in FIGS. 75 and 62, a part of the wiring connected to each element shown in FIG. 64 using the wiring provided in the stacked image pickup device 101 at the position of the pixel as shown in FIG. It is a diagram described.

75 is more specifically, among the plurality of wiring layers 62A to 62C described in FIG. 61, a wiring layer that counts from one surface 70A of the semiconductor substrate 70 to become a wiring layer of the second layer. The arrangement of (62B) is drawn and illustrated in FIG. 74, and the center line of the wiring layer 62B disposed with a width is shown by a solid line. In addition, the center point of the connection structure between the wiring layer 62B and each transistor formed on the surface of the surface 70A is illustrated by a black dot.

In order to realize the configuration shown in FIGS. 76 and 62, a part of the wiring connected to each element shown in FIG. 64 using the wiring provided in the stacked image pickup device 101 at the position of the pixel as shown in FIG. It is a diagram described.

76 is more specifically, among the plurality of wiring layers 62A to 62C described in FIG. 61, the wiring layer 62C that counts from one surface 70A of the semiconductor substrate 70 to become the third wiring layer. This is a diagram showing the arrangement, and the center line of the wiring layer 62C disposed with a width is shown by a solid line. In addition, the center point of the connection structure between the wiring layer 62C and each transistor formed on the surface of the surface 70A is illustrated by a black dot. In addition, in FIG. 76, the center line of the wiring layer 62B shown in FIG. 75 and the center point of the connection structure therein are also described.

77 to 80 are diagrams showing an outline of the configuration of the solid-state imaging device 100 of Example 12.

The solid-state imaging device 100 described in FIGS. 77 to 80 has the same basic configuration as the solid-state imaging device 100 of Example 1 shown in FIG. 9. That is, the body imaging device 100,

(1) A pixel array (in other words, an imaging area 111) in which a plurality of stacked imaging elements 101 are arranged in a two-dimensional array shape,

(2) As a circuit for driving a pixel provided in the pixel array 111, a driving control circuit 116, a vertical driving circuit 112, a horizontal driving circuit 114,

(3) From a circuit for driving a pixel, a pixel driving signal line 119 for sending a signal for driving a pixel to each pixel,

(4) a data output line 117 (VSL) for sending a read signal from each pixel to the column signal processing circuit 113,

(5) A column signal processing circuit 113 and an output circuit 115 for processing and outputting a read signal from pixels provided in the pixel array 111 are output.

Be equipped.

77 to 80, the pixel drive signal line 119 described by a solid line extends across a plurality of pixels in the row direction of the pixel array 111, and the data output line 117 described by a dotted line shows a pixel array ( 111) is extended over a plurality of pixels in the column direction. The pixel driving signal line 119 is a plurality of signal lines for transmitting a signal driving a pixel. Pixel drive signal line 119, described in FIG. 62, the control signal (V _OA), the transfer transistor of the signal line (TTR2, TTR3) connected to the gate electrode of (TR2 _rst, TR3 _trs), reset transistor (TR1 _rst, TR2 _It includes signal lines TTRST1, TTRST2, TTRST3 connected to the gate electrodes of _rst , TR3 _rst , and signal lines TTRSEL1, TTRSEL2, TTRSEL3 connected to the gate electrodes of the selection transistors TR1 _sel , TR2 _sel , TR3 _sel . 78 to 80, the pixel drive signal line 119 is branched from the pixel drive signal line 119 and connected to each of the stacked image pickup elements 101 constituting each pixel in the pixel array 111. The branch line is indicated by a solid line. Similarly, a branch line of the data connection line 117, one of which is connected to each of the stacked imaging elements 101 and the other of which is connected to the data output line 117, is indicated by a dotted line. The branch line of the pixel driving signal line 119 and the branch line of the data connection line 117 are the photoelectric conversion unit 17, the photodiode PD2, and the first and second control units described with reference to FIG. The wiring connected to the photodiode PD3 is shown. In addition, as described with reference to FIG. 62, the stacked image pickup device 101 provided in the solid-state imaging device 100 of Example 12 includes a first and second control unit, and a stacked image pickup device 101 for four pixels ). However, in Figs. 78 to 80, description of these control units is given for simplicity.

77 to 80, there are a plurality of pixel drive signal lines 119 connected to each control unit from the circuit driving the pixels, but for simplicity, these are collectively referred to as bus notation. One set of pixel driving signal lines 119 marked on the bus is arranged one set per two pixels in the row direction of the pixel array 111. Similarly, in FIGS. 77 to 80, since there are a plurality of data output lines 117 connected to the column signal processing circuit 113 from each control unit shared among the four-pixel stacked imaging elements 101, These were collectively designated as buses. One set of data output lines 117 marked on the bus is arranged one set per two pixels in the column direction of the pixel array 111. In addition, in FIGS. 77 to 80, the positions (coordinates) of the pixels in the row direction and the column direction of each pixel in the pixel array are displayed in the format (X, Y).

As shown with reference to FIGS. 66 and 67, FIG. 78 uses (1, 1), (1, 2), (2, 1) using the control unit provided in the repeating unit shown in solid line in FIG. ), The situation in which the charges of the four photodiodes PD3 provided in the pixels at positions (2, 2) are read are shown in the schematic diagram of the configuration of the solid-state imaging device 100. . More specifically, a driving signal is sent to the control unit using the pixel driving signal line 119-1 shown in FIG. 78, and (1, 1), (1, 2), (2, 1), (2, 2) A situation is shown in which the charges of the four photodiodes PD3 provided in the pixels at the positions of are read and the read signals are sent to the column signal processing circuit 113 via the data output lines VSL ₁ 17-1. .

79, (1, 2), (1, 3), (2, 2) using the control unit provided in the repeating unit shown by the solid line in FIG. 68 as described with reference to FIGS. 68 and 69; ), The situation in which the charges of the four photoelectric conversion units 17 provided in the pixels at positions (2, 3) are read are shown on the schematic diagram of the configuration of the solid-state imaging device 100. More specifically, a driving signal is sent to the control unit using the pixel driving signal line 119-1 shown in FIG. 79, and (1, 2), (1, 3), (2, 2), (2, 3) Shows the situation of reading the charges of the four photoelectric conversion units 17 provided in the pixels at the positions of and sending the read signals to the column signal processing circuit 113 through the data output line VSL ₁ 17-1. Doing.

80, as described with reference to FIGS. 70 and 71, (2, 2), (2, 3), (3, 2) using the control unit provided in the repeating unit shown by the solid line in FIG. ), The situation in which the charges of the four photodiodes PD2 provided in the pixels at positions (3, 3) are read are shown on the schematic diagram of the configuration of the solid-state imaging device 100. More specifically, a driving signal is sent to the control unit using the pixel driving signal line 119-1 shown in FIG. 80, and (2, 2), (2, 3), (3, 2), (3, 3) The situation of reading the charges of the four photodiodes PD2 provided in the pixel at the position of and sending the read signal to the column signal processing circuit 113 via the data output line VSL ₁ 17-1. .

<The relationship between the first imaging element and the second and third imaging elements>

For example, the solid-state imaging device 100 of the present disclosure, as described in the cross-sectional structure with reference to FIG. 61, and the plane structure with reference to FIGS. 68 and 66 and 70, and FIGS. 72 and 75, The structure is significantly different between the first imaging element and the second and third imaging elements. The stacked-type imaging element 101 of the present disclosure has a unique configuration for stacking the first and second and third imaging elements, which have significantly different structures.

Fig. 81 shows only the control wiring necessary to drive the four-pixel stacked image pickup device 101 sharing the control unit among the control wirings shown in Fig. 75 and also indicated by the solid line in the drawing. It remains as a solid line, and the rest of the control wiring is described as a dotted line. In addition, in FIG. 81, the center of the on-chip micro-lens 90 described in the figure is also described.

The second and third imaging elements provided in the stacked-type imaging element 101 of the present disclosure form photodiodes PD2 and PD3 that are photoelectric conversion means provided in the imaging element in the semiconductor substrate 70, and , A so-called back-illumination type imaging element in which transistors and driving wirings for driving the elements are disposed on surfaces of the two surfaces of the semiconductor substrate 70 opposite to the incident surface of light to the photodiode It is made. Since the driving wiring is disposed on the opposite side to the incident surface of the light, even if the wiring is disposed in any region in the pixel, this prevents the light from entering the photodiodes PD2 and PD3 provided in the second and third imaging elements. There is nothing to do. For this reason, in the stacked-type imaging element 101 of the present disclosure, it is possible to arrange a number of control wirings for driving the second and third imaging elements over the entire pixel area, as shown in FIG. 81. . (In addition, in FIG. 81, since the control wiring is superimposed on the pixel boundary line, it is difficult to recognize the pixel boundary line. For the position of the pixel boundary line, see FIG. 63.)

FIG. 82 drives FIG. 72, further driving the center of the on-chip micro-lens 90 described in the figure, and the charge accumulation electrode 12 provided in the first imaging element described in the figure. The distance d1 between the wirings V _OA is to be drawn in the drawing. As described with reference to FIG. 72, in the solid-state imaging device 100 of the present disclosure, the wiring VAO driving the charge accumulation electrode 12 provided in the first imaging element is one fine line in FIG. 82. It can be arranged on a pixel boundary line described by a chain line. For this reason, for example, when the center of the on-chip micro-lens 90 is arranged at the center of the pixel, the center of the on-chip micro-lens 90 and the drive wiring (VOA) of the electrode 12 for charge accumulation The distance d1 between) is the distance from the center of the pixel to the border of the pixel.

The first imaging element provided in the stacked-type imaging element 101 of the present disclosure also includes the photoelectric conversion means among the two surfaces of the photoelectric conversion means (that is, the photoelectric conversion section 17) provided in the imaging element. It is a so-called back-illumination imaging element in which a transistor driving the element and a driving wiring are arranged on a surface opposite to the incident surface of the light.

However, the stacked imaging element 101 of the present disclosure has a structure in which the first imaging element and the second and third imaging elements are stacked. For this reason, if the wiring VOA for driving the charge accumulation electrode 12 provided in the first imaging element as shown in FIG. 82 is inadvertently disposed, this is the agent placed below the first imaging element. It becomes a hindrance to the incidence of light to the 2nd and 3rd imaging elements.

For this reason, in the stacked imaging element 101 of the present disclosure, the second wiring in which the wiring VAO for driving the charge storage electrode 12 provided in the first imaging element is disposed below the first imaging element is provided. And the wiring V _OA as far as possible from the center of the pixel, in other words, arranged as close as possible to the pixel boundary so as not to obstruct the incident of light to the third imaging element. More preferably, as described with reference to FIG. 72, the center line of the wiring VAO is arranged on the pixel boundary line. In other words, the distance d1 between the center of the on-chip micro-lens 90 described in FIG. 82 and the driving wiring VAO of the electrode 12 for charge accumulation is the driving wiring shown in FIG. 81. It is larger than the distance between the drive wiring other than (VOA) and the center of the on-chip micro-lens 90.

For example, one, four transfer transistor (TR2 _trs) four drive wires (TG2-1 to TG2-4) and on-chip micro-lenses, which drives the image pickup device which is provided on the second substrate in FIG. 81 ( 90) away, and the four transfer transistor (TR3 _trs), the four drive the drive wires (TG3-1 to TG3-4) and on-chip micro-lenses, provided in the image pickup device of the third between the center of the ( The distance (d1) between the center of the on-chip micro-lens (90) shown in Fig. 82 and the drive wiring (VOA) of the charge accumulation electrode (12) is increased. have. As a result, an action effect is generated that the incidence of light into the second and third imaging elements is not hindered, as compared with a solid-state imaging device without this configuration.

FIG. 83 shows the center of the on-chip micro-lens 90 described in the drawing, and also the charge accumulation electrode 12 provided in the first imaging element described in the drawing. The distance (d2) between the centers of the largest circles in contact is drawn in the drawing.

Here, "the center of the largest circle inscribed in the target figure" means the center of the circle inscribed in these four sides when the shape of the figure is, for example, a square. On the other hand, when the shape of the figure is, for example, a rectangle, the circle inscribed on these three sides becomes the maximum, but the place where the maximum circle can be arranged is not one point, but becomes a line segment shape. Thus, if the place where the "maximum circle inscribed in the target figure" can be placed is not limited to one point, the center of the place where the place can be placed is "maximum inscribed in the target figure." The position of the center of the circle ”. For example, when the target figure is a rectangle, the center point of the line segment that can arrange the circle inscribed on the three sides of the rectangle is "the position of the center of the largest circle inscribed in the target figure" Determined by.

FIG. 84 is the maximum inscribed in FIG. 70 and further inscribed in the center of the on-chip micro-lens 90 described in the figure and the photodiode PD2 provided in the second imaging element described in the figure. The distance (d3) between the centers of the circles is plotted in the drawing.

FIG. 85 is the maximum inscribed in FIG. 66, and further inscribes the center of the on-chip micro-lens 90 described in the figure and the photodiode PD3 provided in the third imaging element described in the figure. The distance (d4) between the centers of the circles is plotted in the drawing.

FIG. 86 is to measure FIG. 68, and to inscribe the center of the on-chip micro-lens 90 described in the figure and the first electrode 11 provided in the first imaging element described in the figure. The distance (d2) between the centers of the largest circles is drawn in the drawing.

FIG. 87 shows the largest circle inscribed in FIG. 68, and further deletes the first electrode 11 and the charge storage electrode 12 described in the drawing, while inscribed in the through electrode 61 described in the drawing. Between the center of the on-chip micro-lens 90 and the center of the largest circle inscribed into the through-electrode 61, and between the center of the on-chip micro-lens 90 The distance d3 of is drawn in the drawing.

The stacked imaging element 101 of the present disclosure has a structure in which a first imaging element and a second and third imaging element are stacked. On the other hand, the through electrode 61 shown in FIG. 87 is an electrode formed through the silicon substrate 70 as shown in FIG. 61. For this reason, it is necessary to arrange the photodiodes PD2 and PD3 provided in the second and third imaging elements of the stacked imaging element 101 to avoid the through electrode 61. For this reason, if the through-electrodes 61 shown in Fig. 87 are disposed inadvertently, the photodiodes PD2 and PD3 provided in the second and third imaging elements need to be avoided and placed. The areas where the diodes PD2 and PD3 receive light become small.

For this reason, the stacked-type imaging element 101 of this disclosure is a through electrode 61 and an electrode connected to the through electrode, which is the first electrode (which is a factor determining the place where the through electrode 61 is disposed). 11), the through-electrode 61 and the first electrode 11 so as not to interfere with the arrangement of the photodiodes PD2 and PD3 provided in the second and third imaging elements disposed below the first imaging element ) As far as possible from the center of the pixel.

More preferably, as described in FIGS. 83 to 87,

(1) The distance d2 between the center of the inscribed circle of the electrode 12 for charge accumulation and the center of the on-chip micro-lens 90, and

(2) the distance (d3) between the center of the inscribed circle of the photodiode PD2 and the center of the on-chip micro-lens 90,

(3) than the distance (d4) between the center of the inscribed circle of the photodiode PD3 and the center of the on-chip micro-lens 90,

(4) The distance d6 between the through electrode 61 and the center of the on-chip micro-lens 90, and

(5) The distance d5 between the center of the inscribed circle of the first electrode 11 and the center of the on-chip micro-lens 90 is,

I am enlarging it. Thereby, the effect of the arrangement | positioning of the photodiode PD2 and PD3 is not disturbed compared with the solid-state imaging device which does not have this structure is produced.

FIG. 88 is a diagram in which FIG. 68 is removed and codes other than the through electrode 61 and the first floating diffusion layer FD1 provided in the first imaging element are deleted.

FIG. 89 is a diagram in which FIG. 70 is removed and codes other than the second floating diffusion layer FD2 provided in the second imaging element are deleted.

FIG. 90 is a diagram in which FIG. 66 is removed and codes other than the third floating diffusion layer FD3 provided in the third imaging element are deleted.

FIG. 91 shows the measurements shown in FIG. 68, the charge accumulation electrode 12 provided in the first imaging element, the through electrodes 61 shown in FIGS. 88 to 91, the first floating diffusion layer FD1, and the second It is a figure which shows the positional relationship of the floating diffusion layer FD2 and the 3rd floating diffusion layer FD3.

The stacked imaging element 101 of the present disclosure has a structure in which a first imaging element and a second and third imaging element are stacked. On the other hand, the charge accumulation electrode 12 provided in the first imaging element, the photodiode PD2 provided in the second imaging element, and the photodiode PD3 provided in the third imaging element are shown in FIGS. It is necessary to arrange the penetration electrode 61 shown in FIG. 91, the 2nd floating diffusion layer FD2, and the 3rd floating diffusion layer FD3. For this reason, if the latter (that is, the through electrode 61, the second floating diffusion layer FD2, and the third floating diffusion layer FD3) is disposed inadvertently, the former (ie, the electrode 12 for charge accumulation and the photodiode PD2) And the photodiode PD3) need to be disposed avoiding the latter, so that the area where the former receives light becomes small.

For this reason, in the stacked-type imaging element 101 of the present disclosure, the latter (that is, the through electrode 61, the second floating diffusion layer FD2, and the third floating diffusion layer FD3) described above is the former (that is, the charge axis). In order not to obstruct the arrangement of the application electrode 12, the photodiode PD2 and the photodiode PD3, the latter is as far as possible from the center of the pixel, in other words, as close as possible to the pixel boundary. Doing.

More preferably, as described in FIG. 91,

(1) the center of the largest circle inscribed to the through electrode 61,

(2) As the electrode connected to the through electrode, the center of the largest circle inscribed to the through electrode of the first electrode 11, which is a factor determining the place where the through electrode 61 is to be placed, because of that,

(3) the center of the largest circle inscribed in the second floating diffusion layer (FD2),

(4) the center of the largest circle inscribed in the third floating diffusion layer (FD3),

It is arranged outside the center of the largest circle inscribed in the charge storage electrode 12 provided in the first imaging device.

More preferably, the above (1) to (4) are arranged outside the outline of the charge storage electrode 12 provided in the first imaging device.

More preferably, (1) to (4) are arranged outside the circumscribed circle of the electrode 12 for charge accumulation provided in the first imaging device.

Alternatively, the above (1) to (4) are arranged outside the largest circle inscribed to the photodiode PD3 provided in the third imaging device.

Alternatively, the above (1) to (4) are arranged outside the outline of the photodiode PD3 provided in the third imaging device.

Alternatively, the above (1) to (4) are arranged outside the largest circle inscribed to the photodiode PD2 provided in the third imaging device.

Alternatively, the above (1) to (4) are arranged outside the outline of the photodiode PD2 provided in the third imaging device.

FIG. 92 shows the minimum distance between the first electrode 11 and the electrode 12 for charge accumulation while removing the border lines showing the repeating arrangement units of the transistors constituting the control unit in FIG. d7).

FIG. 93 removes the border lines showing the repeating arrangement units of the transistors constituting FIG. 64 and forming the control unit.

As described with reference to FIG. 6, in the photoelectric conversion unit 17 provided in the first imaging element of the embodiment of the present disclosure, photoelectric conversion is performed by applying a first voltage for charge accumulation to an electrode for charge accumulation. By accumulating the charge generated in the layer 17 in the lower semiconductor layer 15A, and applying a second voltage for charge transfer (in other words, for reading charge) to the charge storage electrode, the lower semiconductor layer ( The charge accumulated in 15A) is transferred to the first electrode 11 for reading. In this case, the lower semiconductor layer 15A, the charge accumulation electrode 12, and the first electrode 11 function similarly to each of the MOS transistors and the channel and gate electrodes and the drain electrode. However, the MOS transistor has a different conductivity type between the source and drain regions and the channel region (for example, in the case of NMOS, the source and drain regions are N-type, and the channel region is P-type). A potential barrier is created in between. When the transistor is turned off by this potential barrier, the movement of the carrier from the source region to the drain region (in other words, leakage current) is suppressed. In contrast, in the case of the photoelectric conversion unit 17 provided in the first imaging element, there is no potential barrier such as the channel region and the drain region in the lower semiconductor layer 15A. For this reason, in order to suppress the leak current in the photoelectric conversion section 17 provided in the first imaging element, between the charge accumulation electrode 12 for accumulating electric charges and the first electrode 11 as a transfer destination of electric charges It is preferable to distance the distance to some extent. For example, it is preferable to increase the distance between the charge accumulation electrode 12 for accumulating charge and the first electrode 11 serving as a transfer destination of charge, larger than the minimum gate length in a typical MOS transistor. Alternatively, the distance between the charge accumulation electrode 12 for accumulating electric charge and the first electrode 11 serving as a transfer destination of the electric charge is placed on one surface 70A of the semiconductor substrate 70 of the stacked imaging element 101. It is preferable to make it larger than the minimum L (length) provided in the formed MOS transistor. By providing such a structure, as compared with the solid-state imaging device 100 without such a structure, from the area disposed above the charge storage electrode 12 as an area included in the lower semiconductor layer 15A, As a region included in the lower semiconductor layer 15A, the action effect of reducing the leakage current flowing to the region disposed above the first electrode 11 can be produced.

<Modified Example 12>

Each relationship described with reference to FIGS. 81 to 93 is not only a solid-state imaging device 100 having a pixel sharing structure as described in FIGS. 62 to 80, but also a so-called single pixel without a pixel sharing structure ( (Iii) The solid-state imaging device 100 in which the structured stacked imaging elements 101 are arranged in a pixel array shape is also established.

Regarding the single-pixel structure, a view like FIG. 62 is shown in FIG. 94, a view like FIG. 66 is shown in FIG. 95, a view like FIG. 70 is shown in FIG. 96, a view like FIG. 68 is shown in FIG. 97, and a view like FIG. Figure 98, Figure 75, Figure 99, Figure 76, Figure 100, Figure 82, Figure 101, Figure 85, Figure 102, Figure 84, and Figure 84 FIG. 103 is shown in FIG. 103, FIG. 83 is shown in FIG. 104, FIG. 91 is shown in FIG. 105, FIG. 92 is shown in FIG. 106, and FIG. 93 is shown in FIG. 107.

Each relationship described with reference to Figs. 81 to 93 is also established in the solid-state imaging device 100 in which the so-called single pixel structure of the stacked imaging elements 101 described in Figs. 94 to 107 are arranged in a pixel array shape. . The aspect in which the above relationship is established also in Figs. 94 to 107 is the same as that described with reference to Figs. 81 to 93, so that explanation will be repeated again.

As described above, the present disclosure has been described based on preferred embodiments, but the present disclosure is not limited to these embodiments. The structure and configuration of the imaging element, stacked imaging element, and solid-state imaging device described in the examples, manufacturing conditions, manufacturing methods, and materials used are examples, and can be appropriately changed. The imaging element of Example 1, the imaging element of Example 2, the imaging element of Example 3, the imaging element of Example 4, and the imaging element of Example 5 can be arbitrarily combined, and the imaging element of Example 1 and the Example The imaging element of 2, the imaging element of Example 3, the imaging element of Example 4, and the imaging element of Example 6 can be arbitrarily combined.

In some cases, floating diffusion layers (FD ₁ , FD ₂ , FD ₃ , 51C, 45C, 46C) may be shared.

In Fig. 48, for example, as shown in the modified example of the imaging element and the laminated imaging element described in Example 1, the first electrode 11 extends inside the opening 84A provided in the insulating layer 82. Alternatively, it may be configured to be connected to the photoelectric conversion layer 15.

Or, as shown in Fig. 49, for example, a modified example of the imaging element and the stacked imaging element described in Example 1, and a partial cross-sectional view schematically showing an enlarged portion of the first electrode and the like in Fig. 50A. , The edge portion of the top surface of the first electrode 11 is ^{covered with} an insulating layer 82, the first electrode 11 is exposed on the bottom surface of the opening 84B, and the insulating layer contacts the top surface of the first electrode 11 The surface of the layer 82 is the first surface 82a, and the surface of the insulating layer 82 in contact with the portion of the photoelectric conversion layer 15 facing the charge storage electrode 12 is the second surface 82b. At this time, the side surface of the opening 84B has an inclination extending from the first surface 82a toward the second surface 82b. As described above, by inclining the side surface of the opening 84B, the movement of electric charges from the photoelectric conversion layer 15 to the first electrode 11 becomes smoother. In the example shown in Fig. 50A, the side surface of the opening portion 84B is rotationally symmetrical with respect to the axis of the opening portion 84B, but as shown in Fig. 50B, the second side surface from the first surface 82a. The opening portion 84C may be provided so that the side surface of the opening portion 84C having an inclination extending toward the 82b is located on the electrode 12 side for charge accumulation. As a result, it is difficult to move the electric charge from the portion of the photoelectric conversion layer 15 on the opposite side to the charge storage electrode 12 through the opening 84C. Further, the side surface of the opening portion 84B has an inclination extending from the first surface 82a to the second surface 82b, but the edge portion of the side surface of the opening portion 84B in the second surface 82b is also shown in FIG. As shown in 50A, it may be located outside the edge of the first electrode 11, or may be located inside the edge of the first electrode 11, as shown in FIG. 50C. By adopting the former configuration, the transfer of electric charges is further facilitated, and by adopting the latter configuration, the shape variation at the time of formation of the opening can be reduced.

These openings 84B and 84C are inclined to the side of the opening of the etching mask by reflowing an etching mask made of a resist material formed when the opening is formed in the insulating layer based on the etching method, and this etching is performed. It can be formed by etching the insulating layer 82 using a dragon mask.

Alternatively, with respect to the charge discharge electrode 14 described in Example 11, as shown in FIG. 51, the photoelectric conversion layer 15 is extended in the second opening 85A provided in the insulating layer 82. , Connected to the charge discharge electrode 14, the edge of the top surface of the charge discharge electrode 14 is ^{covered with} an insulating layer 82, and the charge discharge electrode 14 is exposed on the bottom surface of the second opening 85A And the insulating layer 82 that contacts the top surface of the charge discharge electrode 14 and the portion of the photoelectric conversion layer 15 that faces the third surface 82c and the electrode 12 for charge accumulation ( When the surface of 82) is used as the second surface 82b, the side surface of the second opening 85A may be in a form having a slope extending from the third surface 82c toward the second surface 82b. .

In addition, as shown in Fig. 52, for example, a modified example of the imaging element and the laminated imaging element described in Example 1, light enters from the side of the second electrode 16, and the second electrode 16 It can be set as the structure in which the light shielding layer 92 is formed in the light incident side. In addition, various wiring provided on the light incident side than the photoelectric conversion layer can function as a light shielding layer.

In the example shown in Fig. 52, the light shielding layer 92 is formed above the second electrode 16, that is, on the light incident side than the second electrode 16, and the first electrode 11 Although the light-shielding layer 92 is formed above (), as shown in FIG. 53, it may be disposed on the surface of the light incident side of the second electrode 16. In addition, in some cases, as illustrated in FIG. 54, the light blocking layer 92 may be formed on the second electrode 16.

Alternatively, the light may be incident from the second electrode 16 side, and light may not be incident on the first electrode 11. Specifically, as illustrated in FIG. 52, as a light incident side near the second electrode 16, a light shielding layer 92 is formed above the first electrode 11. Alternatively, as shown in Fig. 55, on-chip micro-lenses 90 are provided above the electrodes 12 and the second electrodes 16 for charge accumulation, and on-chip micro-lenses 90 are provided. The light incident on the light may be condensed on the electrode 12 for charge accumulation, and the first electrode 11 may not be reached. Alternatively, the light incident on the on-chip micro-lens 90 may be of a structure that does not reach the first electrode 11.

By adopting these structures and structures, or further, the light-blocking layer 92 is provided so that light enters only a portion of the photoelectric conversion layer 15 positioned above the charge storage electrode 12, or is also turned on. By designing the chip micro-lens 90, the portion of the photoelectric conversion layer 15 positioned above the first electrode 11 does not contribute to photoelectric conversion, so that all pixels are reset more reliably at once. It is possible to realize the global shutter function more easily. That is, in the driving method of the solid-state imaging device provided with a plurality of imaging elements having these structures and structures,

In all the imaging elements, while simultaneously accumulating charge in the photoelectric conversion layer 15, the charge from the first electrode 11 is discharged out of the system, and thereafter,

In all imaging elements, the charges accumulated in the photoelectric conversion layer 15 are transferred to the first electrode 11 at the same time, and after the transfer is completed, the charges sequentially transferred to the first electrode 11 in each imaging element To read,

Each process is repeated.

In the driving method of such a solid-state imaging device, each imaging element has a structure in which light incident from the second electrode side does not enter the first electrode, and in all imaging elements, while simultaneously accumulating charges in the photoelectric conversion layer, , Since the charge from the first electrode is discharged out of the system, it is possible to reliably reset the first electrode simultaneously in all the imaging elements. Then, in all the imaging elements, the charges accumulated in the photoelectric conversion layer are transferred to the first electrode all at once, and after the transfer is completed, the charges transferred to the first electrodes in each imaging element are sequentially read. Therefore, the so-called global shutter function can be easily realized.

The photoelectric conversion layer is not limited to a single layer configuration. For example, as shown in Fig. 56, a modified example of the imaging element and the laminated imaging element described in Example 1, the photoelectric conversion layer 15, for example, a lower semiconductor layer 15A made of IGZO, It is also possible to form a stacked structure of the upper layer photoelectric conversion layer 15B made of a material constituting the photoelectric conversion layer 15 described in Example 1. By providing the lower semiconductor layer 15A in this way, recombination at the time of charge accumulation can be prevented, and the transfer efficiency of the charge accumulated in the photoelectric conversion layer 15 to the first electrode 11 can be increased, The generation of dark current can be suppressed.

In Example 1 illustrated in FIGS. 1 and ₂ , the thickness of the insulating layer segments 82 ₁ , 82 ₂ , 82 ₃ is gradually reduced by gradually reducing the thickness of the electrode segments 12 ₁ , 12 ₂ , 12 _{3 for} charge accumulation. Is gradually thickening. On the other hand, exemplary cases, charge accumulation electrode segment as the charge accumulation electrode, a photoelectric conversion layer, and a schematic partial sectional view of a second electrode is enlarged to the stacked portion of the modification of the first shown in Fig. 57 (12 ₁ , 12 ₂ , 12 ₃ ), and the thickness of the insulating layer segments 82 ₁ , 82 ₂ , 82 ₃ may be gradually increased. In addition, the thickness of the photoelectric conversion layer segments 15 ₁ , 15 ₂ , 15 ₃ is constant.

Further, in Example 2 illustrated in FIG. 12, the thickness of the photoelectric conversion layer segments 15 ₁ , 15 ₂ , 15 ₃ is gradually reduced by gradually decreasing the thickness of the electrode segments 12 ₁ , 12 ₂ , 12 _{3 for} charge accumulation. Is gradually thickening. On the other hand, exemplary cases, charge accumulation electrode segment as the charge accumulation electrode, a photoelectric conversion layer, and a schematic partial sectional view of a second electrode is enlarged to the laminated portion in the second modification of the shown in Figure 58 (12 ₁ , 12, _2, a constant thickness of 12, _3), an insulating layer segments (82 _1, 82 _2, 82 ₃₎ the thickness of, by gradually reducing the thickness of the photoelectric conversion layer segments (15 _1, 15 _2, 15 ₃₎ May be gradually thickened.

It goes without saying that the various modifications described above can also be applied to other embodiments.

In the embodiment, the electron is used as the signal charge, and the conductivity type of the photoelectric conversion layer formed on the semiconductor substrate is n-type, but it can also be applied to a solid-state imaging device in which holes are used as the signal charge. In this case, each semiconductor region may be composed of a semiconductor region of the opposite conductivity type, and the conductivity type of the photoelectric conversion layer formed on the semiconductor substrate may be p-type.

Further, in the embodiment, the case where the unit pixels for detecting the signal charge in response to the amount of incident light as a physical amount is applied to a CMOS type solid-state imaging device, which is arranged in a matrix form as an example, is limited to application to a CMOS-type solid-state imaging device. It can also be applied to CCD type solid-state imaging devices. In the latter case, the signal charge is transferred in the vertical direction by the vertical transfer register of the CCD type structure, is transferred in the horizontal direction by the horizontal transfer register, and amplified to output a pixel signal (image signal). In addition, it is not limited to the whole column type solid-state imaging device in which a pixel is formed in a two-dimensional matrix and a column signal processing circuit is arranged for each pixel column. Furthermore, the selection transistor may be omitted in some cases.

Furthermore, the imaging element of the present disclosure and the stacked-type imaging element do not limit the application to a solid-state imaging device that detects the distribution of the incident light amount of visible light and image it as an image, and the amount of incident light such as infrared rays, X-rays, or particles. It is also applicable to a solid-state imaging device that images the distribution of. In addition, it is applicable to all solid-state imaging devices (physical quantity distribution detection devices) such as fingerprint detection sensors that detect distribution of other physical quantities, such as pressure and capacitance, and image them as images.

Furthermore, it is not limited to a solid-state imaging device in which each unit pixel of the imaging area is sequentially scanned row by row to read a pixel signal from each unit pixel. It is also applicable to an X-Y address type solid-state imaging device in which an arbitrary pixel is selected in units of pixels and a pixel signal is read in units of pixels from the selected pixels. The solid-state imaging device may be in the form of a single chip, or may be in the form of a module having an imaging function packaged by integrating the imaging area and the driving circuit or optical system.

Moreover, it is not limited to application to a solid-state imaging device, and is applicable also to an imaging device. Here, the imaging device refers to a camera system such as a digital still camera or a video camera, or an electronic device having an imaging function such as a mobile phone. In some cases, a module form mounted on an electronic device, that is, a camera module is used as an imaging device.

An example in which the solid-state imaging device 201 composed of the imaging element of the present disclosure and the stacked-type imaging element is used in the electronic device (camera) 200 is shown as a conceptual diagram in FIG. 59. The electronic device 200 includes a solid-state imaging device 201, an optical lens 210, a shutter device 211, a driving circuit 212, and a signal processing circuit 213. The optical lens 210 forms the image light (incident light) from the subject on the imaging surface of the solid-state imaging device 201. As a result, signal charges are accumulated in the solid-state imaging device 201 for a period of time. The shutter device 211 controls the light irradiation period and the light blocking period to the solid-state imaging device 201. The driving circuit 212 supplies driving signals for controlling the transfer operation of the solid-state imaging device 201 and the shutter operation of the shutter device 211. The signal transmission of the solid-state imaging device 201 is performed by a drive signal (timing signal) supplied from the drive circuit 212. The signal processing circuit 213 performs various signal processing. The video signal subjected to signal processing is stored in a storage medium such as a memory or output to a monitor. In such an electronic device 200, it is possible to achieve miniaturization of the pixel size and improvement of transmission efficiency in the solid-state imaging device 201, so that the electronic device 200 with improved pixel characteristics can be obtained. The electronic device 200 to which the solid-state imaging device 201 can be applied is not limited to a camera, and can be applied to an imaging device such as a camera module for a mobile device such as a digital still camera or a mobile phone.

Moreover, this disclosure can also take the following structures.

[A01] << Image pickup element: First aspect≫

The first electrode, the photoelectric conversion layer and the second electrode is provided with a photoelectric conversion unit made of a stack,

The photoelectric conversion unit is further provided with an electrode for electric charge accumulation, which is disposed apart from the first electrode and is disposed to face the photoelectric conversion layer through an insulating layer.

The photoelectric conversion section is composed of N (however, N≥2) photoelectric conversion section segments,

The photoelectric conversion layer is composed of N photoelectric conversion layer segments,

The insulating layer is composed of N insulating layer segments,

The electrode for charge accumulation is composed of N electrode segments for charge accumulation,

The n-th (however, n = 1, 2, 3 ... N) photoelectric conversion section segments are the n-th charge accumulation electrode segment, the n-th insulating layer segment, and the n-th photoelectric conversion layer segment. Is composed,

The segment of the photoelectric conversion section having a larger value of n is located away from the first electrode,

The imaging element whose thickness of the insulating layer segment gradually changes from the 1st photoelectric conversion section segment to the Nth photoelectric conversion section segment.

[A02] << Image pickup element: Second aspect >>

The first electrode, the photoelectric conversion layer and the second electrode is provided with a photoelectric conversion unit made of a stack,

The photoelectric conversion unit is further provided with an electrode for electric charge accumulation, which is disposed apart from the first electrode and is disposed to face the photoelectric conversion layer through an insulating layer.

The photoelectric conversion section is composed of N (however, N≥2) photoelectric conversion section segments,

The photoelectric conversion layer is composed of N photoelectric conversion layer segments,

The insulating layer is composed of N insulating layer segments,

The electrode for charge accumulation is composed of N electrode segments for charge accumulation,

The n-th (however, n = 1, 2, 3 ... N) photoelectric conversion section segments are the n-th charge accumulation electrode segment, the n-th insulating layer segment, and the n-th photoelectric conversion layer segment. Is composed,

The segment of the photoelectric conversion section having a larger value of n is located away from the first electrode,

An imaging element in which the thickness of the photoelectric conversion layer segment gradually changes from the first photoelectric conversion section segment to the Nth photoelectric conversion section segment.

[A03] << Image pickup element: Third aspect≫

The first electrode, the photoelectric conversion layer and the second electrode is provided with a photoelectric conversion unit made of a stack,

The photoelectric conversion unit is further provided with an electrode for electric charge accumulation, which is disposed apart from the first electrode and is disposed to face the photoelectric conversion layer through an insulating layer.

The photoelectric conversion section is composed of N (however, N≥2) photoelectric conversion section segments,

The photoelectric conversion layer is composed of N photoelectric conversion layer segments,

The insulating layer is composed of N insulating layer segments,

The electrode for charge accumulation is composed of N electrode segments for charge accumulation,

The n-th (however, n = 1, 2, 3 ... N) photoelectric conversion section segments are the n-th charge accumulation electrode segment, the n-th insulating layer segment, and the n-th photoelectric conversion layer segment. Is composed,

The segment of the photoelectric conversion section having a larger value of n is located away from the first electrode,

An imaging element having different materials constituting the insulating layer segment in adjacent photoelectric conversion section segments.

[A04] << Image pickup device: Fourth aspect≫

The first electrode, the photoelectric conversion layer and the second electrode is provided with a photoelectric conversion unit made of a stack,

The photoelectric conversion unit is further provided with an electrode for electric charge accumulation, which is disposed apart from the first electrode and is disposed to face the photoelectric conversion layer through an insulating layer.

The photoelectric conversion section is composed of N (however, N≥2) photoelectric conversion section segments,

The photoelectric conversion layer is composed of N photoelectric conversion layer segments,

The insulating layer is composed of N insulating layer segments,

The electrode for charge accumulation is composed of N electrode segments for charge accumulation, spaced apart from each other,

The n-th (however, n = 1, 2, 3 ... N) photoelectric conversion section segments are the n-th charge accumulation electrode segment, the n-th insulating layer segment, and the n-th photoelectric conversion layer segment. Is composed,

The segment of the photoelectric conversion section having a larger value of n is located away from the first electrode,

An imaging element having different materials constituting the electrode segment for charge accumulation in adjacent photoelectric conversion section segments.

[A05] << Image pickup device: 5th aspect >>

The first electrode, the photoelectric conversion layer and the second electrode is provided with a photoelectric conversion unit made of a stack,

The photoelectric conversion unit is further provided with an electrode for electric charge accumulation, which is disposed apart from the first electrode and is disposed to face the photoelectric conversion layer through an insulating layer.

The photoelectric conversion section is composed of N (however, N≥2) photoelectric conversion section segments,

The photoelectric conversion layer is composed of N photoelectric conversion layer segments,

The insulating layer is composed of N insulating layer segments,

The electrode for charge accumulation is composed of N electrode segments for charge accumulation, spaced apart from each other,

The n-th (however, n = 1, 2, 3 ... N) photoelectric conversion section segments are the n-th charge accumulation electrode segment, the n-th insulating layer segment, and the n-th photoelectric conversion layer segment. Is composed,

The segment of the photoelectric conversion section having a larger value of n is located away from the first electrode,

An imaging element in which the area of the electrode segment for charge accumulation is gradually reduced from the first photoelectric conversion section segment to the Nth photoelectric conversion section segment.

[A06] << Image pickup device: Sixth aspect≫

The first electrode, the photoelectric conversion layer and the second electrode is provided with a photoelectric conversion unit made of a stack,

The photoelectric conversion unit is further provided with an electrode for electric charge accumulation, which is disposed apart from the first electrode and is disposed to face the photoelectric conversion layer through an insulating layer.

When the stacking direction of the electrode for accumulating charge, the insulating layer and the photoelectric conversion layer is set to the Z direction, and the direction from the first electrode to the X direction, the stacking of the charge accumulating electrode, the insulating layer and the photoelectric conversion layer in the YZ virtual plane is stacked. An imaging element in which the cross-sectional area of the laminated portion when the portion is cut is changed depending on the distance from the first electrode.

[B01] also has a semiconductor substrate,

The photoelectric conversion unit is the imaging element according to any one of [A01] to [A06], which is disposed above the semiconductor substrate.

[B02] The imaging element according to any one of [A01] to [B01], in which the first electrode extends in the opening provided in the insulating layer and is connected to the photoelectric conversion layer.

[B03] The imaging element according to any one of [A01] to [B01], in which the photoelectric conversion layer extends through an opening provided in the insulating layer and is connected to the first electrode.

[B04] The edge of the top surface of the first electrode is ^{covered with} an insulating layer,

The first electrode is exposed on the bottom surface of the opening,

When the surface of the insulating layer in contact with the top surface of the first electrode is the first surface, and the surface of the insulating layer in contact with the portion of the photoelectric conversion layer facing the charge storage electrode is the second surface, the side surface of the opening is the first surface The imaging element according to [B03], which has an inclination widening toward the second surface.

[B05] The imaging element according to [B04], wherein a side surface of an opening having an inclination extending from the first surface to the second surface is located on the electrode side for charge accumulation.

[B06] << control of electric potential of first electrode and electrode for charge accumulation≫

It is provided on the semiconductor substrate, and is also provided with a control unit having a driving circuit,

The first electrode and the electrode for charge accumulation are connected to a driving circuit,

In the charge accumulation period, the potential V ₁₁ is applied to the first electrode from the driving circuit, the potential V ₁₂ is applied to the electrode for charge accumulation, and charge is accumulated in the photoelectric conversion layer,

In the charge transfer period, the potential V ₂₁ is applied to the first electrode from the driving circuit, the potential V ₂₂ is applied to the charge accumulation electrode, and the charge accumulated in the photoelectric conversion layer passes through the first electrode. The imaging element according to any one of [A01] to [B05], which is read by the control unit.

However, when the potential of the first electrode is higher than that of the second electrode,

V ₁₂ ≥V ₁₁ , and also V ₂₂ <V ₂₁

And when the potential of the first electrode is lower than that of the second electrode,

V ₁₂ ≤V ₁₁ , and also V ₂₂ > V ₂₁

to be.

[B07] << charge discharge electrode >>

The imaging element according to any one of [A01] to [B06], further connected to the photoelectric conversion layer and further comprising a first electrode and a charge discharge electrode disposed apart from the electrode for charge accumulation.

[B08] The imaging device according to [B07], wherein the charge discharge electrode is disposed to surround the first electrode and the charge accumulation electrode.

[B09] The photoelectric conversion layer is extended in the second opening provided in the insulating layer, and is connected to the charge discharge electrode,

The edge of the top surface of the charge discharge electrode is ^{covered with} an insulating layer,

A charge discharge electrode is exposed on the bottom surface of the second opening,

When the surface of the insulating layer in contact with the top surface of the charge discharge electrode is the third surface, and the surface of the insulating layer in contact with the portion of the photoelectric conversion layer facing the electrode for charge accumulation is the second surface, the side surface of the second opening is: The imaging element according to [B07] or [B08], which has an inclination extending from the 3rd surface toward the 2nd surface.

[B10] << control of electric potentials of the first electrode, the electrode for accumulating electric charges, and the electrode for discharging electric charges≫

It is provided on the semiconductor substrate, and is also provided with a control unit having a driving circuit,

The first electrode, the charge accumulation electrode, and the charge discharge electrode are connected to a driving circuit,

In the charge accumulation period, from the driving circuit, is applied to the potential (V ₁₁₎ to the first electrode, the charge is applied to the potential (V ₁₂₎ to the accumulation electrode and the charge drain is applied to the potential (V ₁₄₎ to the electrode, the photoelectric Electric charges accumulate in the conversion layer,

In the charge transfer period, from the driving circuit, the applied electric potential (V ₂₁₎ to the first electrode, and applying a potential (V ₂₂₎ to the charge accumulation electrode, and applying a potential (V ₂₄₎ to the charge drain electrode, the photoelectric The imaging element according to any one of [B07] to [B09], in which charge accumulated in the conversion layer is read to the control unit through the first electrode.

However, when the potential of the first electrode is higher than that of the second electrode,

V ₁₄ > V ₁₁ , and also V ₂₄ <V ₂₁

And when the potential of the first electrode is lower than that of the second electrode,

V ₁₄ <V ₁₁ , and also V ₂₄ > V ₂₁

to be.

[B11] When the potential of the first electrode is higher than that of the second electrode, in the charge transfer period, the potential applied to the electrode segment for charge accumulation located closest to the first electrode is located farthest from the first electrode Higher than the potential applied to the electrode segment for charge accumulation,

When the potential of the first electrode is lower than that of the second electrode, in the charge transfer period, the potential applied to the electrode segment for charge accumulation located closest to the first electrode is for charge accumulation located farthest from the first electrode The imaging element according to any one of [A01] to [B10], which is lower than the potential applied to the electrode segment.

[B12] At least a floating diffusion layer and an amplifying transistor constituting the control unit are provided on the semiconductor substrate,

The imaging element according to any one of [A01] to [B11], wherein the first electrode is connected to the floating diffusion layer and the gate portion of the amplifying transistor.

[B13] The semiconductor substrate is further provided with a reset transistor and a selection transistor constituting a control unit,

The floating diffusion layer is connected to one of the source / drain regions of the reset transistor,

The imaging element according to [B12], wherein one source / drain region of the amplification transistor is connected to one source / drain region of the selection transistor, and the other source / drain region of the selection transistor is connected to a signal line.

[B14] The imaging element according to any one of [A01] to [B13], wherein the size of the electrode for charge accumulation is larger than the first electrode.

[B15] The imaging element according to any one of [A01] to [B14], in which light enters from the second electrode side and a light-shielding layer is formed on the light incident side near the second electrode.

[B16] The imaging element according to any one of [A01] to [B14], in which light enters from the second electrode side and no light enters the first electrode.

[B17] The imaging element according to [B16], in which a light-shielding layer is formed above the first electrode as the light incident side near the second electrode.

[B18] On-chip micro lenses are provided above the charge accumulation electrode and the second electrode,

The imaging element according to [B16], wherein light incident on the on-chip micro-lens is condensed on an electrode for charge accumulation.

[C01] «Laminated image pickup device»

A stacked-type imaging element having at least one imaging element according to any one of [A01] to [B18].

[D01] << solid-state imaging device: first aspect >>

The first electrode, the photoelectric conversion layer and the second electrode is provided with a photoelectric conversion unit made of a stack,

The photoelectric conversion section further has a plurality of imaging elements provided with electrodes for charge accumulation, which are disposed spaced apart from the first electrode and are arranged to face the photoelectric conversion layer through an insulating layer,

The imaging element block is composed of a plurality of imaging elements,

A solid-state imaging device in which a first electrode is shared by a plurality of imaging elements constituting an imaging element block.

[D02] << solid-state imaging device: 2nd aspect >>

A plurality of imaging elements according to any one of [A01] to [B17] are provided,

The imaging element block is composed of a plurality of imaging elements,

A solid-state imaging device in which a first electrode is shared by a plurality of imaging elements constituting an imaging element block.

[D03] The solid-state imaging device according to [D01] or [D02], in which a transfer control electrode is provided between a plurality of imaging elements constituting the imaging element block.

[D04] The solid-state imaging device according to any one of [D01] to [D03], wherein one on-chip micro-lens is provided above one imaging element.

[D05] An imaging element block is composed of two imaging elements,

The solid-state imaging device according to any one of [D01] to [D04], wherein one on-chip, micro-lens is provided above the imaging element block.

[D06] The solid-state imaging device according to any one of [D01] to [D05], wherein one floating diffusion layer is provided for a plurality of imaging elements.

[D07] The solid-state imaging device according to any one of [D01] to [D06], wherein the first electrode is disposed adjacent to the charge storage electrode of each imaging element.

[D08] [D01] to [D07], in which the first electrodes are disposed adjacent to the electrodes for accumulating charges of a part of the plurality of imaging elements, and not disposed adjacent to the remaining electrodes for accumulating charges of the plurality of imaging elements The solid-state imaging device according to any one of the preceding.

[D09] The distance between the charge accumulation electrode constituting the imaging element and the charge accumulation electrode constituting the imaging element is longer than the distance between the first electrode and the charge accumulation electrode in the imaging element adjacent to the first electrode [ D08].

[E01] << solid-state imaging device: third aspect≫

A solid-state imaging device comprising a plurality of imaging elements according to any one of [A01] to [A06].

[E02] << solid-state imaging device: the fourth aspect≫

A solid-state imaging device provided with a plurality of the multilayer imaging elements described in [C01].

[F01] «How to drive a solid-state imaging device»

The first electrode, the photoelectric conversion layer and the second electrode is provided with a photoelectric conversion unit made of a stack,

The photoelectric conversion unit is further provided with an electrode for electric charge accumulation, which is disposed apart from the first electrode and is disposed to face the photoelectric conversion layer through an insulating layer.

As a driving method of a solid-state imaging device comprising a plurality of imaging elements having a structure in which light enters from the second electrode side and no light enters the first electrode,

In all the imaging elements, while simultaneously accumulating electric charges in the photoelectric conversion layer, the electric charges from the first electrode are discharged out of the system, and thereafter,

In all the imaging elements, the charges accumulated in the photoelectric conversion layer are simultaneously transferred to the first electrode, and after the transfer is completed, the charges transferred to the first electrode in each imaging element are sequentially read.

The driving method of the solid-state imaging device which repeats each process.

10 ₁ , 10 ₂ , 10 ₃ : Segment of photoelectric conversion part
11, 11 ': first electrode
12, 12 ': charge accumulation electrode
12 ₁ , 12 ₂ , _{1 2 3} : Electrode segment for charge accumulation
13 ': Transmission control electrode
14: charge discharge
15: photoelectric conversion layer
15 ₁ , 15 ₂ , 15 ₃ : Photoelectric conversion layer segment
16: second electrode
41: n-type semiconductor region constituting the second imaging element
43: n-type semiconductor region constituting the third imaging element
42, 44, 73: p ⁺ layer
FD ₁ , FD ₂ , FD ₃ , 45C, 46C: floating diffusion layer
TR1 _amp : amplifying transistor
TR1 _rst : Reset transistor
TR1 _sel : Selection transistor
51: gate portion of reset transistor (TR1 _rst )
51A: Channel formation region of reset transistor TR1 _rst
51B, 51C: Source / drain area of reset transistor (TR1 _rst )
52: gate portion of the amplifying transistor (TR1 _amp )
52A: Channel formation region of amplification transistor (TR1 _amp )
52B, 52C: Source / drain region of amplifying transistor (TR1 _amp )
53: gate portion of the selection transistor TR1 _sel
53A: Channel formation region of selection transistor TR1 _sel
53B, 53C: source / drain regions of the selection transistor TR1 _sel
TR2 _trs : transfer transistor
45: gate portion of the transfer transistor
TR2 _rst : Reset transistor
TR2 _amp : amplifying transistor
TR2 _sel : Selection transistor
TR3 _trs : transfer transistor
46: gate portion of the transfer transistor
TR3 _rst : Reset transistor
TR3 _amp : amplification transistor
TR3 _sel : Selection transistor
V _DD : Power
RST ₁ , RST ₂ , RST ₃ : Reset wire
SEL ₁ , SEL ₂ , SEL ₃ : Selection line
117, VSL ₁ , VSL ₂ , VSL ₃ : Signal line
TG ₂ , TG ₃ : Transmission gate line
V _OA , V _OT , V _OU : Wiring
61: contact hole
62: wiring layer
63, 64, 68A: Pad section
65, 68B: connection hole
66, 67, 69: connection
70: semiconductor substrate
70A: first surface of semiconductor substrate (outer surface)
70B: second side of semiconductor substrate (back side)
71: device isolation region
72: oxide film
74: HfO ₂ membrane
75: insulating film
76: interlayer insulating layer
77, 78, 81: interlayer insulating layer
82: insulating layer
82 ₁ , 82 ₂ , 82 ₃ : Insulation layer segment
82a: first side of insulating layer
82b: second side of insulating layer
82c: third side of insulating layer
83: protective layer
84, 84A, 84B, 84C: opening
85, 85A: second opening
90: on-chip micro-lens
91: various imaging device components positioned below the interlayer insulating layer
92: light-shielding layer
100: solid-state imaging device
101: stacked image pickup device
111: imaging area
112: vertical drive circuit
113: column signal processing circuit
114: horizontal driving circuit
115: output circuit
116: drive control circuit
118: horizontal signal line
200: electronic device (camera)
201: solid-state imaging device
210: optical lens
211: shutter device
212: driving circuit
213: signal processing circuit

Claims (6)

A first imaging element,
A second imaging element,
A first transfer transistor, a first reset transistor, and a first selection transistor electrically connected to the second imaging element;
A third imaging element,
A second transfer transistor, a second reset transistor, and a second selection transistor electrically connected to the third imaging element,
Has a pixel with on-chip micro-lens,
The first imaging element includes a first electrode, a third electrode, and a second electrode opposite to the first and third electrodes,
The pixel,
A third electrode control line connected to the third electrode,
Connected to each of the first transfer transistor, the first reset transistor, the first select transistor, the second transfer transistor, the second reset transistor, and the second select transistor, and the third electrode It is also provided with a plurality of control lines, different from the control lines,
In addition, the pixel,
The distance between the center of the on-chip micro-lens provided in the pixel and any one of the plurality of control lines provided in the pixel is provided in the center of the on-chip micro-lens provided in the pixel and the pixel. And a distance between the third electrode control lines. The pixel,
A first imaging element,
A second imaging element,
A third imaging element,
With on-chip micro-lens,
The distance (d4) between the center of the first electrode inscribed circle and the center of the on-chip / micro-lens, or the distance (d5) between the center of the floating diffusion region inscribed and the center of the on-chip / micro-lens, and the center of the electrode inscribed for charge accumulation The distance (d1) between the on-chip micro-lens center, the distance (d2) between the second imaging element inscribed circle center and the on-chip micro-lens center, and the third imaging element inscribed circle center and the on-chip micro-lens A solid-state imaging device characterized in that the distance between the centers (d3) is small. A first imaging element,
A first floating diffusion region electrically connected to the first imaging element,
A second imaging element,
A second floating diffusion region electrically connected to the second imaging element,
A third imaging element,
A third floating diffusion region electrically connected to the third imaging element,
Has a pixel with on-chip micro-lens,
The first imaging element includes a first electrode, a third electrode, and a second electrode opposite to the first and third electrodes,
Any one of the centers of the first to third floating diffusion layers is disposed outside the inscribed circle of the third electrode, outside the outline of the third electrode, or outside the outside circle of the third electrode. A solid-state imaging device characterized by being present. A first imaging element,
A second imaging element,
A first transfer transistor, a first reset transistor, and a first selection transistor electrically connected to the second imaging element;
A third imaging element,
A second transfer transistor, a second reset transistor, and a second selection transistor electrically connected to the third imaging element,
Has a pixel with on-chip micro-lens,
The first imaging element includes a first electrode, a third electrode, and a second electrode opposite to the first and third electrodes,
The channel length that becomes the minimum in the first and second transfer transistors, the first and second reset transistors, and the first and second selection transistors is smaller than the minimum distance between the third electrode and the first electrode. A solid-state imaging device characterized by being short. Within the pixel,
A first imaging element,
A second imaging element,
A third imaging element,
With on-chip micro-lens,
The first imaging element,
A first electrode, a third electrode, and a second electrode opposite to the first and third electrodes are provided.
The area of the third electrode is larger than that of the third imaging element. The method of claim 5,
The area of the third electrode is smaller than that of the second imaging element.

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