KR20200036586A - Display panel module and display using the same - Google Patents

Abstract

The present invention relates to a display panel module and a display device using the same. The display panel module of the present invention comprises: a display panel including a pixel array, a first bezel outside the upper side of the pixel array, a second bezel outside the left side of the pixel array, a third bezel outside the lower side of the pixel array, a fourth bezel outside the right side of the pixel array, a data driving part driving data lines of the pixel array, and a gate driving part driving gate lines of the pixel array; and a bezel cover covering at least two bezels among the bezels of the display panel. Therefore, power required for driving the display panel is smoothly applied to the display panel.

Description

Display panel module and display device using the same {DISPLAY PANEL MODULE AND DISPLAY USING THE SAME}

The present invention relates to a display panel module including a bezel cover electrically connected to a bezel of a display panel and a display device using the same.

The flat panel display includes a liquid crystal display (LCD), an electroluminescence display, a field emission display (FED), and a plasma display panel (PDP).

The electroluminescent display device is roughly classified into an inorganic light emitting display device and an organic light emitting display device according to the material of the light emitting layer. The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light by itself, and has a high response speed, high luminous efficiency, brightness and viewing angle. There are advantages. Since the organic light emitting diode display can express black gradation in full black, it is possible to reproduce an image at a level superior to that of contrast ratio and color reproduction.

Each of the pixels of the organic light emitting display device includes an OLED, which is a light emitting element, and a driving element that drives the OLED by supplying a current to the OLED according to the gate-source voltage Vgs. The OLED includes an anode and a cathode, and an organic compound layer formed between the electrodes. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer (Electron Injection layer, EIL). When a current flows through the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emission layer (EML) to form excitons, and as a result, the emission layer (EML) can emit visible light. have.

Recently, an organic light emitting display device has been applied in various fields. The display panel of the organic light emitting display device has a structure in which a TFT (Thin Film Transistor) and an OLED are formed on a glass substrate or a plastic substrate. Since the plastic substrate is flexible, it is suitable for various types of release displays or flexible displays.

The following display device attaches a flexible circuit board such as an FPCB (Flexible Printed Circuit Board) to the board of the display panel, connects the flexible circuit board to a printed circuit board (PCB), and displays the power and signals required to drive the display panel. Supplied to. However, since the size of the flexible circuit board is small, the pads of the flexible circuit board are disposed at high density, so the pads are small, the pitch between the pads is small, and the number of pads is limited. Pads adhered to the pads of the flexible circuit board on the substrate of the display panel are also disposed at a high density. Due to this, the display panel has a large resistance on the power and signal transmission path, and there are various problems such as signal distortion.

Accordingly, the present invention provides a display panel module and a display device using the same, which can smoothly supply a video signal and power required for driving the display panel to the display panel.

The display panel module of the present invention includes a pixel array in which data lines and gate lines intersect and pixels are disposed, a first bezel outside the pixel array, a second bezel outside the left side of the pixel array, and a third bezel outside the bottom side of the pixel array. A display panel including a fourth bezel outside the right side of the pixel array, a data driver driving the data lines, and a gate driver driving the gate lines; And a bezel cover covering at least two bezels among the bezels of the display panel.

Internal pads are disposed on the bezels of the display panel covered by the bezel cover.

The bezel cover is electrically connected to the bezels of the display panel including external pads in contact with the internal pads.

The display device of the present invention includes a pixel array in which data lines and gate lines are crossed and pixels are disposed, a first bezel outside the pixel array, a second bezel outside the left side of the pixel array, and a third bezel outside the bottom side of the pixel array, A display panel including a fourth bezel outside the right side of the pixel array, a data driver driving the data lines, and a gate driver driving the gate lines; A timing controller that supplies an image signal from a host system to the data driver and controls the operation timing of the data driver and the gate driver; And a bezel cover that receives an image signal from the timing controller and covers at least two of the bezels of the display panel.

The present invention arranges inner pads on the bezels of the display panel and forms outer pads contacting the inner pads on cover members covering the bezels of the display panel. The inner pads can be made large by utilizing the wide surface of the bezel of the display panel, and the spacing (or pitch) between neighboring inner pads can be increased. Accordingly, the present invention can smoothly supply the image signal and power required for driving the display panel to the display panel.

The present invention reduces the phenomenon of voltage delay when power or gate timing signals are transmitted to both sides of the pixel array and the gate driver through the pads disposed in the central portion of the internal pad portion through the wiring of the display panel. You can. In addition, the present invention can reduce the power variation according to the position of the pixel array by supplying each of the pixel driving power to the display panel 100 in parallel through a plurality of pads.

Furthermore, the present invention provides the pixel driving voltage on the pixel array by arranging the power supply pads on the side-by-side bezels with the pixel array interposed so that the current of the pixel driving voltage and the low potential power supply voltage commonly supplied to the pixels are in the same direction. The difference in voltage difference between and the low potential voltage can be reduced.

1 is a block diagram showing a display device according to an exemplary embodiment of the present invention.
2 and 3 are circuit diagrams showing examples of pixel circuits applicable to the present invention.
4 is a plan view illustrating cover members separated from a display panel in a display panel module according to an exemplary embodiment of the present invention.
5 is a plan view illustrating an example in which cover members are assembled to four sides of a display panel in a display panel module according to an exemplary embodiment of the present invention.
6 is a cross-sectional view of the display panel module taken along line “I-I” in FIG. 5.
7 and 8 are views showing an example of a method of assembling the display panel and the cover members.
9 is a view showing another example of a method of assembling the display panel and the cover members.
10 is a plan view showing a display panel module according to another exemplary embodiment of the present invention.
11 to 13 are views showing a method of connecting a display panel module and a host system according to an embodiment of the present invention.
14 is a diagram showing an example in which a PCB on which a drive IC and a power supply circuit are mounted is connected to a display panel.
FIG. 15 is a view showing ELVDD current and ELVSS current in the display panel module shown in FIG. 14.
FIG. 16 is a view showing a voltage difference between ELVDD and ELVSS according to the pixel array position of the display panel in the display panel module shown in FIG. 14.
17 is a view showing ELVDD current and ELVSS current in the display panel module of the present invention.
18 is a view showing a voltage difference between ELVDD and ELVSS according to the pixel array position of the display panel in the display panel module shown in FIG. 17.

Advantages and features of the present invention, and methods for achieving them will be clarified with reference to embodiments described below in detail together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present invention to be complete, and those skilled in the art to which the present invention pertains. It is provided to fully inform the scope of the invention, and the invention is only defined by the scope of the claims.

Since the shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present invention are exemplary, the present invention is not limited to the details shown in the drawings. Throughout the specification, the same reference numerals refer to substantially the same components. In addition, in the description of the present invention, when it is determined that detailed descriptions of related known technologies may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted.

When "equipped", "includes", "haves", "consists of" and the like referred to herein are used, other parts may be added unless '~ only' is used. When a component is expressed in singular, it may be interpreted in plural unless otherwise specified.

In analyzing the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, when the positional relationship between the two components is described as' on the top ',' on the top ',' on the bottom ',' on the side ',' One or more other components may be interposed between those components for which no 'direct' or 'direct' is used.

The first, second, etc. may be used to classify the components, but the functions or structures of these components are not limited by the ordinal number or the name of the component before the component.

"Case" may be interpreted as synonymous with "cover."

The following embodiments may be partially or totally combined or combined with each other, and technically various interlocking and driving are possible. Each of the embodiments may be implemented independently of each other or may be implemented together in an association relationship.

In the electroluminescent display device of the present invention, a pixel circuit and a gate driver may be disposed on a plastic substrate of the display panel. The pixel circuit and gate driver include a plurality of transistors. Each of the transistors may include one or more of an n-channel transistor (NMOS) and a p-channel transistor (PMOS). Transistors are three-electrode devices, including gates, sources, and drains. The source is an electrode that supplies a carrier to the transistor. In the transistor, carriers begin to flow from the source. The drain is an electrode from which a carrier is driven out of the transistor. In the transistor, the carrier flows from source to drain. In the case of an n-channel transistor, since the carrier is electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In n-channel transistors, the direction of current flows from drain to source. In the case of the p-channel transistor (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In the p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain may be changed according to the applied voltage. Therefore, the invention is not limited due to the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal output from the gate driver swings between a gate on voltage and a gate off voltage. The gate-on voltage is set to a voltage higher than the transistor's threshold voltage, and the gate-off voltage is set to a voltage lower than the transistor's threshold voltage. The transistor is turned on in response to the gate on voltage, while it is turned off in response to the gate off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL). In the case of a p-channel transistor, the gate-on voltage may be a gate low voltage (VGL) and the gate-off voltage may be a gate high voltage (VGH).

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, the organic light emitting display device in which the pixel array is disposed on the plastic substrate is mainly described, but is not limited thereto. For example, the present invention may be applied to any display device using a glass substrate or a plastic-based display panel.

1 to 6, a display device according to an exemplary embodiment of the present invention includes a display panel 100 and a display panel driving circuit for writing data to pixels 101 of the display panel 100. .

The display panel 100 includes a pixel array displaying an input image on a screen. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 103, and pixels arranged in a matrix form.

Each of the pixels may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color realization. Each of the pixels may further include a white sub-pixel. Each of the sub pixels 101 includes a pixel circuit. Hereinafter, the pixel may be interpreted as synonymous with sub-pixel.

The pixel circuit includes a light emitting element, a driving element, one or more switch elements, and a capacitor, as in the example of FIGS. 2 and 3. The driving element and the switching element can be implemented by a thin film transistor (TFT). It should be noted that the pixel circuit is not limited to FIGS. 2 and 3. For example, FIGS. 2 and 3 may illustrate a pixel circuit implemented based on a p-channel TFT, but the pixel circuit may also be implemented as a known n-channel TFT based pixel circuit. The pixel circuit is connected to the data line 102 and the gate line 103.

The display panel 100 includes first power lines 1041 and 43 for supplying the pixel driving voltage ELVDD to the sub-pixels 101 as shown in FIGS. 2 and 3, and a reference for initializing the pixel circuit. Power lines such as a second power line 1042 for supplying the voltage Vref to the sub-pixels 101 and an ELVSS line for supplying the low-potential power voltage ELVSS to the pixels may be further included. The power lines are connected to a power circuit (not shown).

The power circuit generates power required for driving the display panel driving circuit and the display panel 100 using a DC-DC converter, a charge pump, a regulator, or the like. The power circuit may generate pixel power such as ELVDD, ELVSS, Vini, and Vref, drive power of the display panel driving circuit, gate power such as VGH and VGL, and gamma reference voltage by adjusting the input voltage from the host system.

Touch sensors may be disposed on the display panel 100. The touch input may be sensed using separate touch sensors or may be sensed through pixels. The touch sensors may be implemented as in-cell type or in-cell type touch sensors disposed on a screen of a display panel or embedded in a pixel array in an on-cell type or an add-on type. You can.

The pixel array on the display panel 100 may be disposed on a plastic substrate. The manufacturing method of the display panel 100 is a process of manufacturing a plastic substrate by filming the PI solution by coating a thin coating of a poly-imide (PI) solution on a carrier glass and curing it in an oven. LLO that sequentially forms the pixel array and seals the pixel array to protect the OLED from moisture and oxygen. Encapsulation, laser is irradiated under the glass substrate to peel the plastic substrate from the glass substrate. (Laser Lift Off) process, and the process of sequentially bonding the touch screen, polarizer, and cover window to the pixel array, display panel driving circuit mounting process, inspection process, and a series of manufacturing processes such as aging. It is produced through.

The display panel driving circuit includes a data driving unit 110 and a gate driving unit 120. The display panel driving circuit may further include a demultiplexer 112 disposed between the data driving unit 110 and the data lines 102.

The display panel driving circuit writes input image data to pixels of the display panel 100 under the control of a timing controller (TCON) 130. The display panel driving circuit may further include a touch sensor driver for driving touch sensors. The touch sensor driver is omitted in FIG. 1. In a mobile device, the display panel driving circuit, the timing controller 130 and the power supply circuit may be integrated in one integrated circuit.

The display panel driving circuit may operate in a low-speed driving mode. The low-speed driving mode may be set to analyze the input image and reduce power consumption of the display device when the input image does not change as many as a preset number of frames. In other words, in the low-speed driving mode, when a still image is input for a predetermined time or more, the refresh rate of pixels may be lowered to control the data writing cycle of pixels for a long time to reduce power consumption. The low-speed driving mode is not limited when a still image is input. For example, the display panel driving circuit may operate in a low-speed driving mode when the display device operates in a standby mode or when a user command or input image is not input to the display panel driving circuit for a predetermined time or longer.

The data driver 110 receives the gamma reference voltage from the power supply circuit and divides the gamma reference voltage to generate a gamma compensation voltage for each gradation. The data driver 110 converts pixel data (digital data) of the input image received from the timing controller 130 into a gamma compensation voltage every frame period to generate a voltage of a data signal (hereinafter referred to as “data voltage”). do. The data driver 110 outputs the data voltage through the output buffer in each of the channels.

The demultiplexer 112 is disposed between the data driver 110 and the data lines 102 using a plurality of switch elements to distribute the data voltage output from the data driver 110 to the data lines 102. Since one channel in the data driver 110 is sequentially connected to a plurality of data lines through the demultiplexer 112, the number of channels of the data driver 110 may be reduced due to the demultiplexer 112. The demultiplexer 112 may be disposed on the substrate of the display panel 100 or may be integrated in one integrated circuit (IC) together with the data driver 110.

The gate driver 120 may be disposed on a bezel area BZ on the display panel 100 together with a TFT array of pixel arrays. The gate driver 120 outputs the gate signal to the gate lines 103 under the control of the timing controller 130. The gate driver 120 may sequentially supply the signals to the gate lines 103 by shifting the gate signal using a shift register. The gate signal includes a scan signal (SCAN1, SCAN2) for selecting pixels of a line on which data is to be written, and a light emission control signal (hereinafter referred to as “EM signal”) that defines the light emission time of the pixels charged with the data voltage. can do.

The gate driver 120 may include a first gate driver 121 and a second gate driver 122. The first gate driver 121 outputs the scan signals SCAN1 and SCAN2, and sequentially shifts the scan signals SCAN1 and SCAN2 according to the shift clock. The second gate driver 122 outputs the EM signal EM and sequentially shifts the EM signal EM according to the shift clock. In the case of a model without a bezel, switch elements constituting the first and second gate drivers 121 and 122 may be distributedly disposed in the pixel array.

The timing controller 130 receives digital video data DATA of an input image from a host system (not shown) and a timing signal synchronized therewith. The timing signal may include a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a clock (CLK), and a data enable signal (DE). One period of the horizontal synchronization signal Hsync and the data enable signal DE is one horizontal period 1H. The pulse of the data enable signal DE is synchronized with the pixel data of one pixel line to be displayed on the pixels of the active area AA. Since the frame period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted.

The host system may be any one of a TV (Television) system, a set top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device. In the case of a mobile Gigagawa wearable device, the timing controller 130 and the data driver 110 may be integrated in one drive IC.

The timing controller 130 controls the operation timing of the display panel driving units 110, 112, and 120 by multiplying the input frame frequency by i times to a frame frequency of input frame frequency x i (i is a positive integer greater than 0) Hz. You can. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) method and 50 Hz in the PAL (Phase-Alternating Line) method. The timing controller 130 may lower the frame frequency to a frequency between 1 Hz and 30 Hz in order to lower the refresh rate of pixels in the low speed driving mode.

The timing controller 130 controls the data timing control signal for controlling the operation timing of the data driver 110 and the operation timing of the demultiplexer 112 based on the timing signals Vsync, Hsync, and DE received from the host system. For generating a switch control signal, the gate timing control signal for controlling the operation timing of the gate driver 120.

The gate timing control signal includes a start pulse (VST), a shift clock (Gate Shift Clock, GCLK), and the like. The start pulse is generated once at the beginning of the frame period for every frame period and is input to the gate driver 120. The gate start pulse VST controls the start timing of the gate driver 120 every frame period. The shift clock CLK controls shift timing of the gate signal output from the gate driver 120.

The voltage level of the gate timing control signal output from the timing controller 130 may be converted into a gate-on voltage and a gate-off voltage through a level shifter (not shown) and supplied to the gate driver 120. The level shifter converts the low level voltage of the gate timing control signal to the gate low voltage VGL, and the high level voltage of the gate timing control signal to the gate high voltage VGH. .

2 and 3 are circuit diagrams showing examples of pixel circuits applicable to the present invention. The pixel circuits illustrated in FIGS. 2 and 3 are examples in which an internal compensation circuit is applied that senses a threshold voltage Vth of a driving element in real time and compensates for a data voltage Vdata by the threshold voltage Vth. The internal compensation circuit is built in each pixel circuit, and samples the threshold voltage of the driving element that varies according to the electrical characteristics of the driving element in each of the pixel circuits, thereby real-time compensating the data voltage by the threshold voltage of the driving element.

Referring to FIG. 2, an example of a pixel circuit includes a light emitting element EL, a plurality of TFTs T1 to T5, DT, a capacitor Cst, and the like. The TFTs T1 to T5 and DT may be implemented as a p-channel TFT (PMOS), but is not limited thereto.

The light emitting element EL may be implemented as an OLED. The OLED includes an organic compound layer formed between the anode and the cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the OLED is connected to the fourth and fifth switch TFTs T4 and T5 through the fourth node n4. The cathode of the OLED is connected to the ELVSS line to which the low potential power voltage (ELVSS) is applied. The driving TFT (DT) drives the OLED by supplying current to the OLED. The OLED emits light with a current amount controlled by the driving TFT DT according to the data voltage Vdata. The current path of the OLED is switched by the fourth switch TFT (T4).

The capacitor Cst is connected between the first node n1 and the second node n2. The first node n1 is connected to the second electrode of the first switch TFT T1, the first electrode of the third switch TFT T3, and the first electrode of the capacitor Cst. The second node n2 is connected to the second electrode of the capacitor Cst, the gate of the driving element DT, and the first electrode of the second switch TFT T2. The data voltage Vdata compensated by the threshold voltage Vth of the driving TFT DT sampled in the capacitor Cst is charged. Therefore, since the data voltage Vdata in each of the sub-pixels is compensated by the threshold voltage Vth of the driving TFT DT, the characteristic deviation of the driving TFT in the sub-pixels can be compensated and driven with a uniform driving characteristic. .

The first switch TFT T1 is a switch element that is turned on in response to the gate-on voltage of the first scan signal SCAN1 to supply the data voltage Vdata to the first node n1. The first switch TFT (T1) includes a gate connected to the first gate line 1031, a first electrode connected to the data line 102, and a second electrode connected to the first node n1.

The second switch TFT T2 is turned on in response to the gate-on voltage of the second scan signal SCAN2 to connect the gate of the driving TFT DT and the second electrode to diode the driving TFT DT. Let it work. The second switch TFT (T2) includes a gate connected to the second gate line 1032, a first electrode connected to the second node n2, and a second electrode connected to the third node n3.

The third switch TFT T3 supplies the predetermined reference voltage Vref to the first node n1 in response to the EM signal EM to initialize the first node n1 to the reference voltage Vref. The third switch TFT (T3) includes a gate connected to the third gate line 1033, a first electrode connected to the first node n1, and a second electrode connected to the second power line 1042. The EM signal EM defines the light emission time of the light emitting element EL. When the EM signal EM is the gate-on voltage VGL, the current path of the light-emitting element EL is connected to turn on the light-emitting element EL so that the light-emitting element EL can emit light.

The fourth switch TFT T4 switches the current path of the light emitting element EL in response to the EM signal EM. The gate of the fourth switch TFT (T4) is connected to the third gate line 1033. The first electrode of the fourth switch TFT T4 is connected to the third node n3, and the second electrode of the fourth switch TFT T4 is connected to the fourth node n4.

The fifth switch TFT T5 initializes the voltage of the fourth node n4 connected to the anode of the light emitting element EL to the reference voltage Vref in response to the second scan signal SCAN2. The fifth switch TFT (T5) includes a gate connected to the second gate line 1032, a first electrode connected to the second power line 1042, and a second electrode connected to the fourth node n4. The reference voltage Vref is supplied to the pixels through the second power line 1042.

The driving TFT DT is a driving element that adjusts the current flowing through the light emitting element EL according to the gate-source voltage Vgs. The driving TFT DT includes a gate connected to the second node n2, a first electrode connected to the first power line 1041, and a second electrode connected to the third node n3. The pixel driving voltage ELVDD is supplied to the pixels through the first power line 1041.

Referring to FIG. 3, the pixel circuit includes a light emitting element EL, a plurality of TFTs T11 to T16, DT, and a capacitor Cst. The TFTs T11 to T16 and DT may be implemented as a p-channel TFT (PMOS), but is not limited thereto.

The capacitor Cst is connected between the first node n1 and the second node n2. The pixel driving voltage ELVDD is supplied to the pixel circuit through the first power line 1041. The first node n1 is connected to the first power line 1041 to which the pixel driving voltage ELVDD is applied, the first electrode of the third switch TFT T13, and the first electrode of the capacitor Cst. The second node n2 is connected to the second electrode of the capacitor Cst, the gate of the driving element DT, the first electrode of the fifth switch TFT T15, and the first electrode of the first switch TFT T11. do.

The first switch TFT T11 connects the gate of the driving TFT DT and the second electrode in response to the Nth (N is a positive integer) scan signal SCAN (N). The first switch TFT T11 includes a gate connected to the first gate line 1031, a first electrode connected to the gate of the driving TFT DT, and a second electrode connected to the second electrode of the driving TFT DT. . The N-th scan signal SCAN (N) is applied to the pixel circuit through the first gate line 1031.

The second switch TFT T12 applies the data voltage Vdata to the first electrode of the driving TFT DT in response to the Nth scan signal SCAN (N). The second switch TFT T12 includes a gate connected to the first gate line 1031, a first electrode connected to the first electrode of the driving TFT DT, and a second electrode connected to the data line 102.

The third switch TFT T13 applies the pixel driving voltage ELVDD to the first electrode of the driving TFT DT in response to the gate-on voltage of the EM signal EM1. The third switch TFT T13 includes a gate connected to the third gate line 1033, a first electrode connected to the first power line 1041 through a first node n1, and a first electrode of the driving TFT DT And a second electrode connected to the first electrode of the second switch element T12. The EM signal EM1 is applied to the pixel circuit through the third gate line 1033.

The fourth switch TFT T14 connects the second electrode of the driving TFT DT to the anode of the light emitting element EL in response to the gate-on voltage of the EM signal EM1 to drive the TFT (DT) and the light emitting element EL ). The gate of the fourth switch TFT T14 is connected to the third gate line 1033. The first electrode of the fourth switch TFT (T14) is connected to the second electrode of the driving TFT (DT) and the second electrode of the first switch TFT (T11), and the second electrode of the fourth switch TFT (T14) emits light. It is connected to the anode of the element EL.

The fifth switch TFT T15 connects the second node n2 to the second power line 1042 in response to the N-1 scan signal SCAN (N-1). The reference voltage Vini is applied to the pixel circuit through the second power line 1042. The fifth switch TFT T15 includes a gate connected to the second gate line 1032, a first electrode connected to the second node n2, and a second electrode connected to the second power line 1042.

The sixth switch TFT T16 connects the second power line 1042 to the anode of the light emitting element EL in response to the Nth scan signal SCAN (N). The sixth switch TFT T16 includes a gate connected to the first gate line 1031, a first electrode connected to the second power line 1042, and a second electrode connected to the anode of the light emitting element EL.

The driving TFT DT adjusts the current flowing through the light emitting element EL according to the gate-source voltage Vgs. The driving TFT DT includes a gate connected to the second node n2, a first electrode connected to the first electrode of the second switch TFT T12 and a second electrode of the third switch TFT T13, and a first switch TFT And a second electrode connected to the second electrode of (T11) and the first electrode of the fourth TFT (T14).

ELVDD, ELVSS, and Vini may be DC voltages of ELVDD = 7V to 8V, ELVSS = 0V, and Vini = 1V, but are not limited thereto. Vdata may be a voltage between 0V and 5V output from the data driver 110, but is not limited thereto.

4 is a plan view illustrating cover members separated from a display panel in a display panel module according to an exemplary embodiment of the present invention. 5 is a plan view illustrating an example in which covers are assembled on four sides of a display panel in a display panel module according to an exemplary embodiment of the present invention. 6 is a cross-sectional view of the display panel module taken along line “I-I” in FIG. 5.

4 to 6, the display panel module 1000 of the present invention includes a display panel 100 and a bezel cover of a display panel covering at least two or more of the bezels of the display panel 100 .

The display panel 100 includes a pixel array constituting a screen and bezels outside the pixel array. The bezels are the first bezel in the minor axis direction (y) (or the left side), the second bezel in the major axis direction (x) (or the lower side), the third bezel in the minor axis direction (y) (right side), and the major axis direction ( x) includes a fourth bezel (or upper side).

The bezel cover covers at least two bezels of the bezels of the display panel and is electrically connected to the bezels to supply a video signal to the drive IC 200 on the display panel, and a pixel driving power source and a gate driving unit necessary for driving pixels. 120) to supply power and gate timing signals necessary for driving. The bezel cover may include two or more cover members that individually cover different bezels on the display panel.

The inner pads are disposed on the bezels of the display panel 100 covered by the bezel cover. The internal pads are connected to at least one of the wirings of the pixel array, the drive IC on which the data driver is mounted, and the input terminals of the gate driver. The wirings of the pixel array include data lines, gate lines, and power lines. The bezel cover is electrically connected to the bezels of the display panel 100 including external pads in contact with inner pads disposed on the bezel of the display panel 100.

In the following embodiments, the bezel cover includes a first cover member covering the first bezel, a second cover member covering the second bezel, a third cover member covering the third bezel, and a fourth cover member covering the fourth bezel. Including but not limited to.

The display panel 100 may have a pixel array and a touch screen formed on a plastic substrate. The drive IC 200 may be mounted on at least one of the four sides of the display panel 100. In the example of FIG. 4, the drive IC 200 illustrates an example disposed on the first bezel of the display panel 100, but is not limited thereto. The drive IC 200 may be mounted on a plastic substrate in the same manner as the process of mounting the drive IC on a base film of a conventional chip on film (COF). In the example of FIG. 4, the drive IC 200 includes a data driver 110.

The inner pads are dispersedly disposed on edges of at least two sides among the four sides of the display panel 100. The inner pads formed on the display panel 100 are in contact with the outer pads formed on the cover members. The inner pads are electrically connected to the outer pads to receive an image signal input from the outside through at least one of the cover members 300, 310, 320, and 330, a pixel driving power source, and a signal required for driving the gate driver 120. Supplied. The inner pads are connected to wirings connected to the pixel circuit shown in FIGS. 2 and 3. Some of the internal pads may be connected to input wirings of the gate driver 120 to supply a start signal VST, a shift clock GCLK, and the like to the gate driver 120.

At least one of the cover members 300, 310, 320, and 330 may include an external host system, a timing controller 130, and external pads connected to a power circuit. At least one of the cover members 300, 310, 320, and 330 may include circuits such as a power supply circuit and an interface circuit.

The first cover member 310 is made of a structure that covers the top surface of the first bezel of the display panel 100. As illustrated in FIG. 6, the first cover member 310 may be manufactured to have a structure surrounding a side surface and a bottom surface together with an upper surface in a first bezel of the display panel 100. The first cover member 310 may include a data transmission unit 312, a data reception unit 314, and a first power supply unit 316. The data receiving unit 314 supplies the input image signal received from the external host system or timing controller 130 to the data transmission unit 312. The input video signal includes pixel data and timing signals. The data transmission unit 312 transmits an image signal to the drive IC 200 according to a communication protocol transmitted to the drive IC 200. The first power supply unit 316 includes pads for receiving power from a power circuit such as a gamma reference voltage, analog and digital power, and transferring the power to the drive IC 200. The first power supply unit 316 may include a power circuit or be connected to an external power circuit. The first cover member 310 includes external pads to connect the circuits of the first cover member 310 to the display panel 100.

First and second inner pad portions 12 and 14 are disposed on the top surface of the first bezel of the display panel 100. The first and second internal pad parts 12 and 14 may be spaced apart from the first bezel of the display panel with the drive IC 200 interposed therebetween. The first inner pad unit 12 includes pads that are electrically connected to the pads of the first power supply unit 316 through external pads to transfer power from the first power supply unit 316 to the drive IC 200. do. The pads of the first internal pad portion 12 are connected to power input pins of the drive IC. The second internal pad unit 14 includes pads that are electrically connected to pads of the data transmission unit 312 through external pads to supply an input image signal and a timing signal to the drive IC 200. The pads of the second internal pad portion 12 are connected to input pins of the drive IC 200. When the first cover member 310 is connected to the first bezel of the display panel 100, the pads of the inner pad portions 12 and 14 are electrically connected to the outer pads of the first cover member 310.

The internal pad portions 312 and 314 on both sides of the drive IC 200 are symmetrically distributed based on the drive IC 200 to receive input image signals and power. This pad arrangement is suitable for impedance matching and reducing the left and right deviation of the power supply.

The second cover member 320 is made of a structure that covers the top surface of the second bezel of the display panel 100. The second cover member 320 may be manufactured to have a structure surrounding a side surface and a bottom surface together with an upper surface in a first bezel of the display panel 100. The second cover member 320 includes a second power supply unit 322 and a gate timing signal supply unit 334. The second power supply unit 322 includes external pads that supply power to the display panel 100 such as driving power of a pixel, for example, ELVDD, ELVSS, Vini, and Vref. The gate timing signal supply unit 334 includes external pads that supply the gate timing signal necessary for driving the gate driver 120, for example, a start pulse (VST), a shift clock (GCLK), etc., to the display panel 100. . In order to connect the circuits formed on the second cover member 320 to the display panel, the first cover member 320 includes external pads 311 and 331 as shown in FIG. 6.

The inner pad portion 16 is disposed on the upper surface of the second bezel of the display panel 100. The inner pad unit 16 includes pads connected to power lines that supply pixel driving power to pixels, and pads connected to input wirings of the gate driving unit 120. When the second cover member 320 is connected to the second bezel of the display panel 100, the pads of the inner pad portion 16 are electrically connected to the outer pads of the second cover member 320. Pixel driving power may be supplied to the pixels through the pads of the internal pad unit 16, and a gate timing signal required for driving the gate driving unit 120 may be transmitted to the gate driving unit 120.

When the power or gate timing signal is transmitted to the pixel array and the gate driver 120 through the pads disposed in the central portion of the inner pad unit 16, the pixel power and the gate timing signal are transmitted to both sides through wiring of the display panel 100. Delay of the voltage in the long axis direction (y) can be reduced in 1/2 order. The pads of the inner pad portion 16 may be disposed on the display panel 100 by utilizing the entire second bezel in the long axis direction. Since the size and pitch of each of the pads of the inner pad portion 16 can be formed wide, the pad contact resistance is small, so that the signal and power can be stably supplied to the display panel 100. In addition, each pixel driving power can be supplied to the display panel 100 in parallel through a plurality of pads to reduce power variation depending on the pixel array position.

The third cover member 330 is made of a structure that covers the top surface of the third bezel of the display panel 100. The third cover member 330 may be manufactured to have a structure surrounding a side surface and a bottom surface together with an upper surface in a third bezel of the display panel 100. The third cover member 330 includes a third power supply unit 332. The third power supply unit 332 supplies power to the display panel 100 such as driving power of a pixel, for example, ELVDD, ELVSS, Vini, and Vref. The third cover member 330 includes external pads for connecting the circuit to the display panel 100.

The inner pad portion 18 is disposed on the upper surface of the third bezel of the display panel 100. The inner pad portion 18 may include pads connected to external pads of the third cover member 330 and connected to power lines that supply pixel driving power to pixels. Pixel driving power may be supplied to the pixels through the pads of the internal pad unit 16. When the third cover member 330 is connected to the third bezel of the display panel 100, the pads of the inner pad portion 18 are electrically connected to the outer pads of the third cover member 330.

The pads on which the inner pad portion 18 is disposed may be disposed on the display panel 100 by utilizing the entire second bezel. Accordingly, power variation depending on the position of the pixel array can be reduced by supplying each of the pixel driving powers to the display panel 100 in parallel through a plurality of pads.

Of the four bezels of the display panel 100, pixel driving power may be supplied through two or more pads to provide uniform pixel driving power throughout the pixel array, as well as ELVDD and ELVSS as in the examples of FIGS. 17 and 18. The current flows in one direction to reduce the difference between ELVDD and ELVSS depending on the pixel array position.

The fourth cover member 300 is made of a structure that covers the top surface of the fourth bezel of the display panel 100. The fourth cover member 300 may be manufactured to have a structure surrounding a side surface and a bottom surface together with an upper surface in a fourth bezel of the display panel 100. The fourth cover member 300 may be connected to the cover window 302. The fourth cover member 300 couples the cover window on the display panel 100. The fourth cover member 300 may include only the cover window 302 without a circuit or may further include a circuit.

The plastic substrate of the display panel 100 may be deformed at a high temperature. In the bonding process using anisotropic conductive film (ACF) performed in a high temperature environment, the display panel 100 may be exposed to high temperatures. 7 and 8 show methods of connecting the cover bezels to the display panel 100 in the same way as the cable and connector connection method that does not require a high temperature environment.

The cover members 300, 310, 320, and 330 may be manufactured in the form of a connector having a slot so that an edge of the display panel 100 can be inserted as shown in FIG. 6. When the edge of the display panel 100 is inserted into a slot of the first to third cover members 310, 320, and 330 of the connector structure as shown in FIG. 7, these cover members 310, 320, and 330 are inserted. The display panel 100 can be easily connected. When the cover members 310, 320, and 330 are connected to the display panel 100, the outer pads of the cover members 310, 320, and 330 and the inner pads of the display panel 100 contact to cover the cover members. The display panel 100 is electrically connected. When the fourth cover member 300 is assembled to the display panel 100 as shown in FIG. 8, the cover window 302 covers the display panel 100. Simultaneously with the assembly of the fourth cover member 300, the cover window 302 is assembled to the display panel 100, thereby simplifying the cover assembly process of the display panel module.

Referring to FIG. 9, the cover members 400, 410, 420, and 430 may be manufactured in a structure in which the upper surface is openable. The upper surfaces of the cover members 400, 410, 420, and 430 are opened to secure an assembly space of the display panel. Subsequently, the display panel 100 in the assembly space between the cover members 400, 410, 420, 430 such that the pads of the display panel 100 and the pads of the cover members 400, 410, 420, 430 face each other. ). Subsequently, if the top surfaces of the cover members 400, 410, 420, 430 cover the four bezels of the display panel 100, the cover members 400, 410, 420, 430 can be simply fastened to the display panel 100. have. When the cover members 400, 410, 420, 430 are connected to the display panel 100, the outer pads of the cover members 400, 410, 420, 430 and the inner pads of the display panel 100 are in contact, The cover members and the display panel 100 may be electrically connected.

The screen of the display panel module can be produced in various forms. For example, the screen may be produced as a landscape in which the long axis direction is parallel to the horizontal direction, a portrait in which the long axis direction is parallel to the vertical direction, and a release screen such as an automobile dashboard or a clock.

10 is a plan view showing a display panel module according to another exemplary embodiment of the present invention. The example of FIG. 10 illustrates a mobile terminal having a portrait screen.

Referring to FIG. 10, the display panel module 1000 of the present invention includes the display panel 100 and cover members 300, 310, 320 fastened to edges of at least two sides of four sides of the display panel 100, 330).

In the display panel 100, the four bezels outside the pixel array are the first bezel (or left side) in the minor axis direction (x), the second bezel (or lower side) in the major axis direction (y), and the third bezel in the minor axis direction (x). It includes a bezel (right side) and a fourth bezel (or upper side) in the long axis direction (y).

The display panel 100 may have a pixel array and a touch screen formed on a plastic substrate. In this embodiment, internal pads may be dispersedly disposed on the first bezel, the second bezel, and the fourth bezel of the display panel 100.

The first bezel of the display panel 100 includes internal pads that receive image signals and power from a drive IC, a host system, or a timing controller 130 and wires connected to the internal pads. Impedance matching is facilitated by using symmetrically arranged pads with the drive IC interposed therebetween, and the left and right deviations of power sources can be reduced.

The first cover member 310 is made of a structure that covers the top surface of the first bezel of the display panel 100. The first cover member 310 may be manufactured to have a structure surrounding a side surface and a bottom surface together with an upper surface in a first bezel of the display panel 100. The first cover member 310 may include circuits such as a data transmission unit, a data reception unit, and a power supply unit. Also, the first cover member 310 may include external pads connected to internal pads formed on the first bezel of the display panel 100.

In the display panel 100, the second and fourth bezels in the long axis direction are side by side with the pixel array interposed therebetween. In the display panel 100, the second and fourth bezels in the long axis direction supply wirings and internal pads for transmitting a gate timing signal for controlling the gate driver 120, and pixel driving power sources such as ELVDD and ELVSS. For wiring and internal pads. Because the second and fourth bezels are long, the size of the inner pads dispersed in these bezels can be increased and the pitch between the inner pads is formed wide.

The second cover member 320 is made of a structure that covers the top surface of the second bezel of the display panel 100. The second cover member 320 may be manufactured to have a structure surrounding a side surface and a bottom surface together with an upper surface in a second bezel of the display panel 100. The fourth cover member 300 is made of a structure that covers the top surface of the third bezel of the display panel 100. The fourth cover member 300 may be manufactured to have a structure surrounding a side surface and a bottom surface together with an upper surface in a fourth bezel of the display panel 100. Each of the second and fourth cover members 320 and 300 may include a circuit such as a power supply unit for supplying pixel driving power to the pixel array, and external pads connected to the circuit.

The third cover member 330 fastened to the third bezel of the display panel 100 may be integrated with the cover window without internal pads. Circuits and pads may be formed on the third bezel and the third cover member 330 of the display panel 100 as necessary.

The cover members 300, 310, 320, and 330 may be connected to the bezels of the display panel 100 by the connection method described in the above-described embodiment.

The display panel 100 may be connected to an external system in the same manner as in FIGS. 11 to 13. In the example of FIGS. 12 and 13, the fourth bezel member 300 includes a power supply unit 304 and a gate timing signal supply unit 306.

11, the timing controller 130 may be mounted on the display panel 100 together with the drive IC 200. In this case, the timing controller 130 of the display panel module 1000 is connected to the host system 500 through wiring.

11, the drive IC 200 of the display panel module 1000 may be connected to an external timing controller 130 through wiring. The timing controller 130 is mounted on a separate control board as shown in FIG. 12, and a graphic processing circuit of the host system 500 is connected to the control board.

The timing controller 130 may be integrated in one IC package or mounted on one circuit board together with the graphics processing circuit of the host system 530 as shown in FIG. 13. In this case, the host system 530 is connected to the drive IC 200 on the display panel 100 through the cover member 310.

The gate timing signal from the timing controller 130 is supplied to the gate driver 120 through a level shifter. The level shifter may be disposed on the first bezel of the display panel 100.

According to the present invention, since the internal pads are distributed by widely using the bezels of the display panel, the contact resistance between the pads is small and the pitch between the pads is sufficiently wide to prevent short circuits between neighboring pads.

On the other hand, when the drive IC 200 and the power circuit 210 are mounted on the PCB as shown in FIG. 14 and the PCB is connected to the display panel 100 by FPCB, the power V generated on the PCB ) Is supplied to the display panel 100 through the resistance R1 between the PCB and the FPCB and the resistance R2 between the FPCB and the display panel 100. Due to the size limitation of the FPCB, the pad size is small, and the contact resistance between the pads is large, resulting in a voltage drop and a short pitch between pads may occur due to the narrow pitch between the pads. In addition, when ELVDD and ELVSS are supplied to the display panel through the power supply circuit 210 on the PCB as shown in FIG. 15, the direction of the current from ELVDD and the current flowing to ELVSS is reversed as shown in FIGS. 15 and 16. The voltage difference (ΔV) between ELVDD and ELVSS increases at the upper pixel position (L1) and the lower pixel position (Ln) of the EVDD display panel close to the PCB due to the voltage drop. This causes a difference in the amount of current flowing through the OLED according to the position on the pixel array, and a luminance difference can be seen on the upper and lower sides of the display panel.

As shown in FIG. 17, in the display panel module 1000 of the present invention, ELVDD is supplied to a pixel array in one of two opposing bezels with a pixel array interposed therebetween, and ELVSS is supplied in the other. In this case, the direction of the current flowing from ELVDD to the pixel array (ELVDD current) and the current flowing from the pixel array to ELVSS (ELVSS) are the same. As a result, even if a voltage drop between ELVDD and ELVSS occurs in the pixel array, the voltage difference (ΔV) deviation between ELVDD and ELVSS is reduced at any position of the pixel array as shown in FIG. 18.

Through the above description, those skilled in the art will appreciate that various changes and modifications are possible without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be determined by the scope of the claims.

12, 14, 16, 18: inner pad portion 102: data line
1031 ~ 1033, 103: gate line 1041, 1042: power line
100: display panel 101, 101A, 101B: sub-pixel (pixel circuit)
110: data driving unit 112: demultiplexer
120: gate driver 130: timing controller
300, 310, 320, 330: cover member 311, 331: outer pad
500, 530: host system

Claims (9)

A pixel array in which data lines and gate lines are intersected and pixels are disposed, a first bezel outside the upper side of the pixel array, a second bezel outside the left side of the pixel array, a third bezel outside the lower side of the pixel array, and a product outside the right side of the pixel array. A display panel including a 4 bezel, a data driver driving the data lines, and a gate driver driving the gate lines; And
And a bezel cover covering at least two bezels among the bezels of the display panel,
Internal pads are disposed on the bezels of the display panel covered by the bezel cover,
The bezel cover is a display panel module that is electrically connected to the bezels of the display panel including external pads in contact with the inner pads. According to claim 1,
The bezel cover includes two or more cover members that individually cover different bezels on the display panel,
A drive IC in which a data driver is integrated is disposed in one of the bezels,
A data receiving unit that receives a signal from the outside, a data transmission unit that transmits the image signal to the drive IC, and a power supply unit that supplies a gamma reference voltage to the drive IC. Display panel module including. According to claim 1,
The bezel cover,
A first cover member covering the first bezel;
A second cover member covering the second bezel;
A third cover member covering the third bezel; And
A display panel module including a fourth cover member covering the fourth bezel. The method of claim 3,
At least one bezel of the cover member,
External pads supplying a gate timing control signal for controlling the gate driver; And
And external pads for supplying pixel driving power to the pixel array.
The bezel of the display panel is a display panel module including the inner pads in contact with the outer pads. The method of claim 3,
The cover members have a structure surrounding a top surface, a side surface, and a bottom surface of the bezel of the display panel. The method of claim 3,
A display panel module further comprising a cover window connected to any one of the bezel covers to cover the display panel. The method of claim 3,
The pixel driving power source,
A high potential pixel driving voltage (ELVDD) and a low potential power supply voltage (ELVSS) commonly supplied to all pixels of the pixel array,
Internal pads for supplying the high-potential pixel driving voltage to the pixel array are disposed on one of two bezels spaced apart and parallel with the pixel array among the bezels, and the other one of the two bezels. A display panel module in which internal pads for supplying the low potential power voltage to the pixel array are disposed. The method of claim 7,
A current flowing in the high potential pixel driving voltage on the pixel array,
A display panel module having the same direction of current flowing through the low potential power voltage on the pixel array. A pixel array in which data lines and gate lines are intersected and pixels are disposed, a first bezel outside the upper side of the pixel array, a second bezel outside the left side of the pixel array, a third bezel outside the lower side of the pixel array, and a product outside the right side of the pixel array. A display panel including a 4 bezel, a data driver driving the data lines, and a gate driver driving the gate lines;
A timing controller that supplies an image signal from a host system to the data driver and controls the operation timing of the data driver and the gate driver; And
And a bezel cover for receiving an image signal from the timing controller and covering at least two of the bezels of the display panel,
Internal pads are disposed on the bezels of the display panel covered by the bezel cover,
The bezel cover is a display device electrically connected to the bezels of the display panel including external pads in contact with the internal pads.

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