KR20200036566A - Data Driver and Display Device having the Same - Google Patents

Abstract

A display device capable of reducing the overall size of a data driving unit of the present invention comprises: a display panel on which two or more pixel lines made of a plurality of pixels are disposed; and a data driving unit receiving image data and generating a data voltage and applying the data voltage to the pixels. The pixel lines include a first pixel group and a second pixel group. A first latch unit of the data driving unit latches image data written to the first pixel group for a first period and latches image data written to the second pixel group for a second period. A second latch unit of the data driving unit latches the image data written to the first pixel group for the second period.

Description

Data driver and display device including the same

The present invention relates to a data driver and a display device including the same.

Flat panel displays include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), and organic light emitting diode devices (OLEDs). ). In the flat panel display device, data lines and gate lines are orthogonal to each other, and an area where data lines and gate lines are orthogonal is defined as one pixel. A plurality of pixels are formed in a matrix form in the panel.

In order to drive each pixel, the data driver generates a data voltage based on image data input from the outside and supplies it to data lines. The data driver includes a latch unit that latches input image data in units of pixel lines. Since the latch unit latches input image data in units of pixel lines, it must hold a latch corresponding to the number of pixels belonging to one pixel line. Recently, as the resolution increases, the number of pixels belonging to the pixel line increases, and the size of the latch portion increases. In order to reduce the size and manufacturing cost of the data driving unit, a method of reducing the size of the latch unit is being sought.

The present invention is to provide a data driving unit and a display device including the same, which can reduce size and manufacturing cost.

The present invention includes a display panel in which two or more pixel lines are arranged, and a data driver that receives image data, generates a data voltage, and applies a data voltage to the pixels. The pixel line includes a first pixel group and a second pixel group. The first latch unit of the data driving unit latches image data written in the first pixel group during the first period, and latches image data written in the second pixel group during the second period. The second latch unit of the data driver latches image data written to the first pixel group during the second period.

The present invention can reduce the overall size of the data driver using a latch unit that latches image data written in one pixel line in groups.

In the present invention, since the speed at which image data is transmitted is maintained, the size of the data driver can be reduced without changing the driving frequency.

1 is a view showing an organic light emitting display device of the present invention.
2 is a view showing a pixel.
3 is a view showing a data driver according to the first embodiment.
4 is a diagram illustrating a division between pixel groups according to a first embodiment.
5 is a diagram showing the timing of latching image data according to the first embodiment.
6 to 11 are views showing the operation of the data driver according to the first embodiment.
12 is a view showing a data driver according to a second embodiment.
13 is a diagram illustrating division between pixel groups according to a second embodiment.
14 is a diagram showing the timing of latching image data according to a second embodiment.
15 to 22 are views showing operations of the data driver according to the second embodiment.
23 is a diagram showing a data driver according to a third embodiment.
24 is a diagram illustrating timing of latching image data according to a third embodiment.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Throughout the specification, the same reference numbers refer to substantially the same components. In the following description, when it is determined that the detailed description of the known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. In describing various embodiments, the same components are representatively described at the outset and may be omitted in other embodiments.

1 is a block diagram schematically showing an organic light emitting display device.

Referring to FIG. 1, the organic light emitting display device according to the present invention is for driving a display panel 100 on which pixels P are formed, a timing controller 200, and gate lines GL1 to GLm (where m is a natural number). A data driver 400 is provided to drive the gate driver 300 and the data lines DL1 to DLn (n is a natural number that is an even number or a multiple of 3).

The display panel 100 includes a display area AA in which pixels P are arranged to display an image, and a non-display area NAA that does not display an image. The display area AA may be referred to as a pixel array, and the non-display area NAA may be referred to as a bezel surrounding the display area AA.

In the display area AA of the display panel 100, a plurality of data lines DL1 to DLn and a plurality of gate lines GL1 to GLm cross each other, and pixels P are arranged in a matrix form for each of the crossing areas. do. Each pixel line HL1 to HLm includes pixels arranged in the same row. Hereinafter, in the present specification, the X direction shown in FIG. 1 will be referred to as a row direction and a Y direction as a column direction. When the number of pixels P arranged in the display area AA is mХn, the display area AA includes m pixel lines.

The pixels P arranged in the first pixel line HL1 are connected to the first gate line GL1, and the pixels P arranged in the nth pixel line HLm are connected to the m gate line GLm. do. The gate lines GL1 to GLm may include a plurality of lines providing respective gate signals. Also, in a double rate driving (DRD) method, two gate lines may be arranged to drive pixels in one pixel line.

The transistors constituting the pixels P may be implemented as an oxide transistor including an oxide semiconductor layer. The oxide transistor is advantageous for the large area of the display panel 100 in consideration of electron mobility, process variation, and the like. However, the present invention is not limited to this, and the semiconductor layer of the transistor may be formed of amorphous silicon or polysilicon.

The timing controller 200 operates timing of the data driver 400 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. Generates a data control signal for controlling and a clock signal MCLK for controlling the operation timing of the gate driver 300.

In addition, the timing controller 200 rearranges the image data DATA input from the host 20 according to the resolution of the display panel 100 and supplies it to the data driver 400. In particular, the timing controller 200 transmits the image data DATA received in pixel line units to the data driver 400 in group units. The pixel line may include two or more groups. For example, when one pixel line includes the first and second pixel groups, the timing controller 200 transmits image data written to the first pixel group for a period of (1/2) H, followed by (1 / 2) During the H period, image data written in the second pixel group may be transmitted. Specific embodiments thereof will be described later.

The gate driver 300 may generate gate signals based on the clock signal MCLK. The gate driver 300 may be directly formed on a non-display area of the display panel 100 according to a gate-driver in panel (GIP) method.

The data driver 400 converts the image data DATA input from the timing controller 200 into an analog data voltage based on the data control signal DDC. A specific embodiment of the data driver 400 will be described later.

2 is a diagram showing an example of a pixel.

Referring to FIG. 2, the pixel P according to an embodiment includes a driving transistor DT, a storage capacitor Cst, a first transistor T1 and a second transistor T2. FIG. 2 illustrates an embodiment in which the gate line GL shown in FIG. 1 includes a scan line SCL and a sense line SEL.

The driving transistor DT controls the driving current flowing through the organic light emitting diode OLED according to the voltage difference Vgs between the gate and the source. The driving transistor DT includes a gate electrode connected to the first node N1, a drain electrode connected to the input terminal of the high potential driving voltage EVDD, and a source electrode connected to the second node N2. The storage capacitor Cst is connected between the first node N1 and the second node N2. The first transistor T1 includes a gate electrode connected to the input terminal of the scan signal SCAN, a drain electrode connected to the data line DL, and a source electrode connected to the first node N1. The second transistor T2 includes a gate electrode connected to the input terminal of the sense signal SENSE, a drain electrode connected to the second node N2, and a source electrode connected to the reference voltage line REFL. The organic light emitting diode OLED includes an anode connected to the second node N2, a cathode connected to the input terminal of the low potential driving voltage EVSS, and an organic compound layer positioned between the anode and the cathode.

The pixel illustrated in FIG. 2 shows a circuit applied to an external compensation method that acquires the voltage of the second node N2 as a sensing voltage and compensates driving characteristics based on the obtained sensing voltage. The pixel according to the present invention is not limited to the embodiment shown in FIG. 2. For example, the pixel may be composed of a pixel applied to an internal compensation method that automatically compensates inside the pixel so that the current flowing through the organic light emitting diode is not affected by the threshold voltage of the driving transistor.

3 is a view showing a data driver according to a first embodiment of the present invention.

Referring to FIG. 3, the data driving unit 400 according to the first embodiment includes a first latch unit 411, a second latch unit 412, a digital-to-analog conversion unit 420, a switch unit 425, and an output unit 430.

The first latch unit 411 samples and latches the image data DATA from the timing controller 200 and simultaneously outputs the latched data. The first latch unit 411 includes first to k (natural numbers satisfying 2k = n) latches L1_1 to L1_ [K], and first to kth latches L1_1 to L1_ [K] ) Each latches one pixel of image data.

The second latch unit 412 latches data provided from the first latch 411 and simultaneously outputs the latched data. The second latch unit 412 includes first to k-th latches L2_1 to L2_ [k], and each of the first to k-th latches L2_1 to L2_ [K] is image data of one pixel. Latch.

The digital-to-analog converter 420 converts the image data provided from the second latch unit 412 into an analog data voltage. The digital-to-analog converter 420 includes first to n-th digital analog converters (hereinafter referred to as DACs) (DAC1 to DAC [n]), and first to n-th digital-to-analog converters (DAC1 to DAC [ n]) Each converts one image data among image data written in n pixels arranged in one pixel line into an image data voltage.

The switch unit 425 selectively connects the digital analog conversion unit 420 and the output buffers of the buffer unit 430. The odd-numbered switches SW1, SW3, SW5 respond to the first SOE (SOE1), and the odd-numbered DACs DAC1, DAC3, DAC5, DAC [n-1] and output buffers BUF1-BUF [k] ) On a one-to-one basis. For example, the first switch SW1 connects the first DAC DAC1 and the first output buffer BUF1 in response to the first SOE (SOE1). The superior switches (SW2, SW4, SW6) respond to the second SOE (SOE2), and select the superior DAC (DAC2, DAC4, DAC6, DAC [n]) and output buffers (BUF1 ~ BUF [n]). Connect one to one. For example, the second switch SW2 connects the second DAC DAC2 and the first output buffer BUF1 in response to the second SOE (SOE2).

The buffer unit 430 provides an analog-type data voltage output from the digital-to-analog converter 420 to the data lines DL. To this end, the buffer unit 430 uses the low potential voltage (GND) and the voltage received through the high potential input terminal as the driving voltage to output the first to kth output buffers (BUF1 to BUF [k]). It includes.

The multiplexer 430 distributes the data voltages output from the first to kth output buffers BUF1 to BUF [k] in time division to n data lines DL. To this end, the multiplexer 430 includes first to n-th mux switches M1 to M [n]. The odd-numbered mux switches M1, M3, and M5 respond to the first control signal MUX1, and the first to k-th output buffers BUF1 to BUF [k] and the odd-numbered data lines DL1, DL3, DL5) is connected one-to-one. For example, the first MUX switch M1 connects the first output buffer BUF1 and the first data line DL1 in response to the first control signal MUX1. The superior th mux switches M2, M4, and M6 respond to the second control signal MUX2, and the first to k th output buffers BUF1 to BUF [k] and the superior th data lines DL2, DL4, DL6) is connected one-to-one. For example, the second MUX switch M2 connects the first output buffer BUF1 and the second data line DL2 in response to the second control signal MUX2.

Although the multiplexer 430 is illustrated in FIG. 3 as being disposed on the display panel 100, the position of the multiplexer 430 is not limited thereto.

Looking at the operation of the data driver according to the first embodiment is as follows.

4 is a diagram schematically illustrating a pixel group according to the first embodiment. 4 shows image data written in pixels arranged in the n-th column in the m-th pixel line as D [m, n].

Referring to FIG. 4, a pixel group according to the first embodiment includes a first pixel group and a first pixel group. The first pixel group includes pixels arranged in odd-numbered pixels in each pixel line, that is, (2k-1) (natural number satisfying 2k = n) -th column. The second pixel group includes superior pixels in each pixel line, that is, pixels arranged in a 2k-th column.

Accordingly, image data written in the first pixel group of the first pixel line may be represented by D [1,2k-1], and image data written in the second pixel group of the first pixel line may be D [1, 2k]. Similarly, image data written in the first pixel group of the mth pixel line may be represented by D [m, 2k-1], and image data written in the second pixel group of the mth pixel line may be D [m, 2k].

5 is a diagram showing timing of image data and driving signals transmitted from a timing controller to a data driver.

4 and 5, the timing controller 200 transmits image data to be written to a pixel group in units of (1/2) H.

During the first period t1, the timing controller 200 transmits image data written to the first pixel group of the first pixel line HL1.

During the second period t2, the timing controller 200 transmits image data written to the second pixel group of the first pixel line HL1.

The first period t1 and the second period t2 correspond to a (1/2) H period, respectively. As a result, the timing controller 200 transmits the image data DATA to be written to one pixel line during the 1H period to the data driver 400. That is, the speed at which the timing controller 200 transmits image data DATA is the same as in the prior art.

During the third period t3, the timing controller 200 transmits image data written to the first pixel group of the second pixel line HL2.

Hereinafter, the operation of the data driver in the first period t1 to the third period t3 is as follows.

6 is a view showing image data received by the data driver in the first period, and FIG. 7 is a view for explaining the operation of the data driver in the first period. 8 is a view showing image data received by the data driver in the second period, and FIG. 9 is a view for explaining the operation of the data driver in the second period. FIG. 10 is a diagram illustrating image data received by the data driver in a third period, and FIG. 11 is a diagram illustrating an operation of the data driver in a third period. 7, 9, and 11 show a part of the data driver.

6 and 7, in the first period t1, the data driver 400 receives image data written in the first pixel group of the first pixel line.

The first latch unit 411 latches image data written in the first pixel group of the first pixel line. For example, the first latch L1_1 of the first latch unit 411 latches “D [1,1]”. The second latch L1_2 of the first latch unit 411 latches “D [1,3]”, and the third latch L1_3 of the first latch unit 411 is “D [1,5]” Latch.

The second latch unit 412 latches the image data transmitted at the previous timing and transmits it to the digital analog converter 420.

8 and 9, in the second period t2, the data driver 400 receives image data written in the second pixel group of the first pixel line HL1.

The first latch unit 411 latches image data written in the second pixel group of the first pixel line. For example, the first latch L1_1 of the first latch unit 411 latches “D [1,2]”. The second latch L1_2 of the first latch unit 411 latches “D [1,4]”, and the third latch L1_3 of the first latch unit 411 is “D [1,6]” Latch.

The second latch unit 412 latches image data written to the first pixel group of the first pixel line received from the first latch unit 411, and simultaneously outputs the latched image data.

In the second period t2, the first SOE (SOE1) becomes a turn-on voltage, and the odd-numbered switches make the odd-numbered DACs and the first to k-th output buffers BUF1 to BUF [k] one-to-one. Connect. For example, the first switch SW1 connects the first DAC DAC1 and the first output buffer BUF1 in response to the first SOE (SOE1).

The first control signal MUX1 becomes a turn-on voltage, and the odd-numbered mux switches M1, M3, and M5 are first to k-th output buffers BUF1 to BUF [k] and odd-numbered data lines. Connect (DL1, DL3, DL5) one-to-one. For example, the first MUX switch M1 connects the first output buffer BUF1 and the first data line DL1 in response to the first control signal MUX1.

As a result, during the second period t2, the first pixel group of the first pixel line HL1 is provided with a data voltage.

10 and 11, in the third period t3, the data driver 400 receives image data written in the first pixel group of the second pixel line HL2.

The first latch unit 411 latches image data written in the first pixel group of the second pixel line HL2. For example, the first latch L1_1 of the first latch unit 411 latches “D [2,1]”. The second latch L1_2 of the first latch unit 411 latches “D [2,3]”, and the third latch L1_3 of the first latch unit 411 is “D [2,5]” Latch.

In the third period t3, the second latch unit 412 latches the image data written in the second pixel group of the first pixel line HL1 received from the first latch unit 411 and latches the image. Output data simultaneously.

In the third period (t3), the second SOE (SOE2) becomes a turn-on voltage, and the even-numbered switches make the even-th DACs and the first to k-th output buffers (BUF1 to BUF [k]) one-to-one. Connect. For example, the second switch SW2 connects the second DAC DAC2 and the first output buffer BUF1 in response to the second SOE (SOE2).

Further, the second control signal MUX2 becomes a turn-on voltage, and the even-numbered mux switches connect the first to k-th output buffers BUF1 to BUF [k] and the even-numbered data lines one-to-one. For example, the second MUX switch M2 connects the first output buffer BUF1 and the second data line DL2 in response to the second control signal MUX2.

As a result, during the third period t3, the second pixel group of the first pixel line HL1 is provided with a data voltage.

As described above, the data driver 400 of the first embodiment transmits image data written in n pixels in time division using a first latch unit consisting of (1/2) n first latches corresponding to n pixels. Receive. In addition, the number of second latch units 412 for receiving image data from the first latch unit 411 also corresponds to (1/2) n pieces. That is, the data driving unit of the first embodiment can reduce the number of latches to 1/2 level in comparison with the prior art.

12 is a view showing a data driver according to a second embodiment of the present invention.

Referring to FIG. 12, the data driver 400 according to the second embodiment includes a first latch unit 411, a second latch unit 412, a digital-to-analog conversion unit 420, a switch unit 425, and an output unit ( 430).

The first latch unit 411 samples and latches the image data DATA from the timing controller 200 and simultaneously outputs the latched data. The first latch unit 411 includes first to k (natural numbers satisfying 3k = n) latches L1_1 to L1_ [k], and first to kth latches L1_1 to L1_ [k] ) Each latches one pixel of image data.

The second latch unit 412 latches data provided from the first latch 411 and simultaneously outputs the latched data. The second latch unit 412 includes first to k-th latches L2_1 to L2_ [k], and each of the first to k-th latches L2_1 to L2_ [k] is image data of one pixel. Latch.

The digital-to-analog converter 420 converts the image data DATA provided from the second latch unit 412 into an analog data voltage. The digital-to-analog converter 420 includes first to n-th digital-to-analog converters (DAC1 to DAC [n]), and each of the first to n-th digital-to-analog converters (DAC1 to DAC [n]) has one pixel line. Among the image data written in the n pixels arranged in, one image data is converted into an image data voltage.

The switch unit 425 selectively connects the digital analog conversion unit 420 and the output buffers of the buffer unit 430. The (3k-2) th switches connect the (3k-2) th DAC and the output buffers one-to-one in response to the first SOE (SOE1). For example, the first switch SW1 connects the first DAC DAC1 and the first output buffer BUF1 in response to the first SOE (SOE1). The (3k-1) th switches connect the (3k-1) th DAC and the output buffers one-to-one in response to the second SOE (SOE2). For example, the second switch SW2 connects the second DAC DAC2 and the first output buffer BUF1 in response to the second SOE (SOE2). The 3k-th switches connect the 3k-th DAC and the output buffers one-to-one in response to the third SOE (SOE3). For example, the third switch SW3 connects the third DAC DAC3 and the first output buffer BUF1 in response to the third SOE (SOE3).

The buffer unit 430 provides an analog-type data voltage output from the digital-to-analog converter 420 to the data lines DL. To this end, the buffer unit 430 uses the low potential voltage (GND) and the voltage received through the high potential input terminal as the driving voltage to output the first to kth output buffers (BUF1 to BUF [k]). It includes.

The multiplexer 430 distributes the data voltages output from the first to k-th output buffers BUF1 to BUF [k] in time division to n data lines. To this end, the multiplexer 430 includes first to n-th mux switches M1 to M [n]. The (3k-2) th mux switch connects the first to k th output buffers BUF1 to BUF [k] and the (3k-2) th data lines in a one-to-one response to the first control signal MUX1. . For example, the first MUX switch M1 connects the first output buffer BUF1 and the first data line DL1 in response to the first control signal MUX1. The (3k-1) th mux switch connects the first to k th output buffers BUF1 to BUF [k] and the (3k-1) th data lines in a one-to-one response to the second control signal MUX2. . For example, the second MUX switch M2 connects the first output buffer BUF1 and the second data line DL2 in response to the second control signal MUX2. In response to the third control signal SOE3, the 3k th mux switch connects the first to k th output buffers BUF1 to BUF [k] and the 3k th data lines one-to-one. For example, the second MUX switch M2 connects the first output buffer BUF1 and the third data line DL3 in response to the third control signal SOE3.

Looking at the operation of the data driver according to the second embodiment is as follows.

13 is a diagram schematically illustrating a pixel group according to a second embodiment. 13 shows image data written in pixels arranged in the n-th column in the m-th pixel line as D [m, n].

Referring to FIG. 13, the pixel group according to the first embodiment includes first to third pixel groups. The first pixel group includes pixels arranged in the (3k-2) -th column of each pixel line (k is a natural number satisfying 3k = n). The second pixel group includes pixels arranged in the (3k-1) th column in each pixel line, and the third pixel group includes pixels arranged in the 3k th column in each pixel line.

Accordingly, image data written in the first pixel group of the first pixel line may be represented by D [1,3k-2], and image data written in the second pixel group of the first pixel line may be D [1, 3k-1], and image data written in the third pixel group of the first pixel line may be displayed as D [1,3k].

14 is a diagram showing timing of image data and driving signals transmitted from a timing controller to a data driver.

13 and 14, the timing controller 200 transmits image data to be written to a pixel group in units of (1/3) H.

During the first period t1, the timing controller 200 transmits image data written to the first pixel group of the first pixel line.

During the second period t2, the timing controller 200 transmits image data written to the second pixel group of the first pixel line, and during the third period t3, the timing controller 200 receives the first pixel line The image data written in the third pixel group is transmitted.

The first period t1, the second period t2, and the third period t3 correspond to a (1/3) H period, respectively. As a result, the timing controller 200 transmits the image data DATA to be written to one pixel line during the 1H period to the data driver 400.

Subsequently, during the fourth period t4, the timing controller 200 transmits image data written to the first pixel group of the second pixel line HL2.

 Hereinafter, the operation of the data driver in the first period t1 to the fourth period t4 will be described.

15 is a view showing image data received by the data driver in the first period, and FIG. 16 is a view for explaining the operation of the data driver in the first period. FIG. 17 is a view showing image data received by the data driver in the second period, and FIG. 18 is a view for explaining operation of the data driver in the second period. 19 is a diagram showing image data received by the data driver in the third period, and FIG. 20 is a diagram for explaining the operation of the data driver in the third period. 21 is a diagram illustrating image data received by the data driver in a fourth period, and FIG. 22 is a diagram illustrating an operation of the data driver in a fourth period.

15 and 16, in the first period t1, the data driver 400 receives image data written in a first pixel group of a first pixel line.

The first latch unit 411 latches image data written in the first pixel group of the first pixel line. For example, the first latch L1_1 of the first latch unit 411 latches “D [1,1]”, and the second latch L1_2 of the first latch unit 411 is “D [1,4]. ] ”.

The second latch unit 412 latches the image data transmitted at the previous timing and transmits it to the digital analog converter 420.

17 and 18, in the second period t2, the data driver 400 receives image data written in the second pixel group of the first pixel line.

The first latch unit 411 latches image data written in the second pixel group of the first pixel line. For example, the first latch L1_1 of the first latch unit 411 latches “D [1,2]”. The second latch L1_2 of the first latch unit 411 latches “D [1,5]”.

The second latch unit 412 latches image data written to the first pixel group of the first pixel line received from the first latch unit 411, and simultaneously outputs the latched image data.

In the second period t2, the first SOE (SOE1) becomes a turn-on voltage, the (3k-2) th switches are the (3k-2) th DACs and the first to k th output buffers (BUF1 ~ BUF [k]) in a one-to-one connection. For example, the first switch SW1 connects the first DAC DAC1 and the first output buffer BUF1 in response to the first SOE (SOE1).

The first control signal MUX1 becomes a turn-on voltage, and the (3k-2) th mux switches include the first to k th output buffers BUF1 to BUF [k] and the (3k-2) th data lines. Connect one-to-one. For example, the first MUX switch M1 connects the first output buffer BUF1 and the first data line DL1 in response to the first control signal MUX1.

As a result, during the second period t2, the first pixel group of the first pixel line is provided with a data voltage.

19 and 20, in the third period t3, the data driver 400 receives image data written in a third pixel group of the first pixel line.

The first latch unit 411 latches image data written in the third pixel group of the first pixel line. For example, the first latch L1_1 of the first latch unit 411 latches “D [1,3]”, and the second latch L1_2 of the first latch unit 411 is “D [1,6]. ] ”.

In the third period t3, the second latch unit 412 latches image data written in the second pixel group of the first pixel line received from the first latch unit 411, and simultaneously latches the image data. Output.

In the third period t3, the second SOE (SOE2) becomes a turn-on voltage, the (3k-1) th switches are the (3k-1) th DACs and the first to k th output buffers (BUF1 ~ BUF [k]) in a one-to-one connection. For example, the second switch SW2 connects the second DAC DAC2 and the first output buffer BUF1 in response to the second SOE (SOE2).

In addition, the second control signal MUX2 becomes a turn-on voltage, and the (3k-1) th mux switches are the first to k th output buffers BUF1 to BUF [k] and (3k-1) th data. Connect the lines one-to-one. For example, the second MUX switch M2 connects the first output buffer BUF1 and the second data line DL2 in response to the second control signal MUX2.

As a result, during the third period t3, the second pixel group of the first pixel line is provided with a data voltage.

21 and 22, in the fourth period t4, the data driver 400 receives image data written in a first pixel group of a second pixel line.

The first latch unit 411 latches image data written in the first pixel group of the second pixel line. For example, the first latch L1_1 of the first latch unit 411 latches “D [2,1]”, and the second latch L1_2 of the first latch unit 411 is “D [2,4]. ] ”.

In the fourth period t4, the second latch unit 412 latches the image data written in the third pixel group of the first pixel line transmitted from the first latch unit 411, and simultaneously latches the image data. Output.

In the fourth period (t4), the third SOE (SOE3) becomes a turn-on voltage, and the 3k th switches switch the 3k th DACs and the first to k th output buffers (BUF1 to BUF [k]) one-to-one. Connect. For example, the third switch SW3 connects the third DAC DAC3 and the first output buffer BUF1 in response to the third SOE (SOE3).

In addition, the third control signal SOE3 becomes a turn-on voltage, and the 3k th mux switches connect the first to k th output buffers BUF1 to BUF [k] and the 3k th data lines one-to-one. For example, the third MUX switch M3 connects the first output buffer BUF1 and the third data line DL3 in response to the third control signal SOE3.

As a result, during the fourth period t4, the second pixel group of the first pixel line is provided with a data voltage.

As described above, the data driver 400 of the second embodiment uses a first latch unit 411 made of first latches corresponding to (1/3) n pieces of image data written in n pixels. And receive it in time division. In addition, the number of second latch units 412 for receiving image data from the first latch unit 411 also corresponds to (1/3) n pieces. That is, the data driving unit of the second embodiment can reduce the number of latches to a level of 1/3 compared to the prior art.

FIG. 23 is a view showing a modification of the first embodiment, and FIG. 24 is a view showing timing of drive signals applied to the data driver and the display panel shown in FIG. 23.

The data driving unit 400 shown in FIG. 23 is the same as the first latch unit 411, the second latch unit 412, the digital-to-analog conversion unit 420, the switch unit 425, and the output as in the first embodiment described above. Includes part 430. Accordingly, the method of transmitting image data to the data driver 400 shown in FIG. 23 and the method of outputting the data voltage by the output unit 430 of the data driver 400 using the method are substantially the same as the first embodiment described above. Is the same.

In the embodiment illustrated in FIG. 23, pixels of the display panel 100 are distributed with a data division time division by a DRD method.

In the display panel 100 illustrated in FIG. 23, a pair of adjacent pixels share a data line. Further, odd-numbered pixels P1, P3, P5, and P [n-1] are connected to the first gate line GL1, and even-numbered pixels P2, P4, P6, and P [n-1]. Is connected to the second gate line GL2.

The first gate line GL1 receives the first gate pulse Gout1 synchronized with the first SOE (SOE1). That is, odd-numbered pixels connected to the first gate line GL1 are provided with data voltages output from the first to k-th output buffers BUF1 to BUF [k] in the second period t2.

The second gate line GL2 is applied with a second gate pulse Gout2 synchronized with the second SOE (SOE2). That is, even-numbered pixels connected to the second gate line GL2 are provided with data voltages output from the first to k-th output buffers BUF1 to BUF [k] in the third period t3.

Since the latches of the data driver according to the embodiment shown in FIG. 23 correspond to half the number of pixels of the pixel line, as in the first embodiment, the size of the latches can be reduced.

Through the above description, those skilled in the art will be able to variously change and modify without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the scope of the claims.

10: host 100: display panel
200: timing controller 300: gate driving circuit
400: data driving circuit 411: first latch unit
412: second latch unit 420: digital analog conversion unit
430: output

Claims (13)

A display panel in which two or more pixel lines of a plurality of pixels are disposed; And
And a data driver that receives image data, generates a data voltage, and applies the data voltage to the pixels.
The pixel line includes a first pixel group and a second pixel group,
The data driving unit
A first latch unit for latching image data written in a first pixel group during a first period and latching image data written in the second pixel group during a second period; And
And a second latch unit latching image data written to the first pixel group during the second period. According to claim 1,
Further comprising a timing controller for providing the image data from the outside to the data driver,
The timing controller
During the first period, image data written in the first pixel group is transmitted to the data driver,
During the second period, a display device that transmits image data written to the second pixel group to the data driver. According to claim 1,
The data driving unit
A digital-to-analog conversion unit converting the image data output from the second latch unit into the data voltage; And
Further comprising a buffer for providing the data voltage converted by the digital-to-analog converter to the pixels,
The buffer unit
A display device that outputs the data voltage provided to the first pixel group during the second period and outputs the data voltage provided to the second pixel group during the third period. The method of claim 3,
The digital analog conversion unit
A first DAC that converts image data written in the first pixel group to the data voltage during the second period; And
And a second DAC that converts image data written in the second pixel group to the data voltage during the third period. The method of claim 4,
The buffer unit includes a first buffer receiving the data voltage output from the first DAC and the second DAC,
The data driving unit
A first switch for connecting the first DAC with the first buffer during the second period; And
And a second switch connecting the second DAC to the first buffer during the third period. The method of claim 5,
The first buffer is a display device that provides the data voltage in time division to a first pixel of the first pixel group and a second pixel of the second pixel group. The method of claim 6,
The data line includes a first data line connected to the first pixel and a second data line connected to the second pixel,
The display panel
A first mux switch connecting the first buffer and the first data line during the second period; And
And a second mux switch connecting the second buffer and the second data line during the third period. The method of claim 6,
The data line includes a first data line connected to the first and second pixels,
The gate line
A first gate line connected to the first pixel and receiving a gate signal having a turn-on voltage during the second period;
And a second gate line connected to the second pixel and receiving a gate signal having a turn-on voltage during the third period. According to claim 1,
The pixel line includes n (where n is an even natural number) pixels,
The first pixel group includes (2k-1) (natural numbers satisfying 2k = n) th pixels,
The second pixel group includes 2k-th pixels,
The first latch part and the second latch part each include k latches. The method of claim 9,
Further comprising a timing controller for providing the image data from the outside to the data driver,
The timing controller
During the first period, image data written to the first pixel group is transmitted to the data driver,
During the second period, image data written to the second pixel group is transmitted to the data driver,
A display device in which the sum of the first period and the second period is 1H. According to claim 1,
The pixel line including n (n is a natural number that is a multiple of 3) pixels further includes a third pixel group,
The first pixel group includes (3k-2) th (the natural number satisfying 3k = n) th pixels,
The second pixel group includes (3k-1) th pixels,
The third pixel group includes 3k th pixels,
The first latch part and the second latch part each include k latches. The method of claim 11,
Further comprising a timing controller for providing the image data from the outside to the data driver,
The timing controller
During the first period, image data written to the first pixel group is transmitted to the data driver,
During the second period, image data written to the second pixel group is transmitted to the data driver,
During the third period following the second period, image data written to the third pixel group is transmitted to the data driver,
A display device in which the sum of the first to third periods is 1H. During the first period, image data written to a first pixel group among pixels connected to a first gate line is latched, and image data written to a second pixel group among pixels connected to the first gate line during a second period A first latch unit for latching;
A second latch unit latching image data written to the first pixel group during the second period;
A first DAC for converting the image data written in the first pixel group into a data voltage in the second period following the first period; And
And a second DAC converting the image data written in the second pixel group into a data voltage in a third period following the second period.

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