KR20200027146A - Voltage regulator and open load diagnosis method thereof - Google Patents

Abstract

According to the present invention, a voltage regulator comprises: a comparator comparing a reference voltage and a feedback voltage of a feedback pin; a transistor outputting an output voltage to an output pin in response to the output of the comparator; a first shunt resistor having one end thereof connected to the output pin; a second shunt resistor connected between the other end of the first shunt resistor and a ground terminal; and a voltage monitor performing a short circuit diagnosis or an open load diagnosis by monitoring the feedback voltage of the feedback pin connected to the other end of the first shunt resistor.

Description

Voltage regulator and its open-load diagnostic method {VOLTAGE REGULATOR AND OPEN LOAD DIAGNOSIS METHOD THEREOF}

The present invention relates to a voltage regulator and its open load diagnostic method.

The power supply precision control device is a key component of the power generator in the vehicle and is a device designed to maintain a constant output voltage even when the input voltage and output load change. This performs the core function of maintaining a precise and constant change in the voltage of the generator terminal due to the change in the load speed in the vehicle, charging the electricity used in the car to the battery to start the car when it is not generating electricity or to start the radio. Use it as a power source, and also adjust the irregular fluctuations of the voltage to supply a constant voltage to the load (electric components) so that efficient distribution of power is achieved.

Patent: 10-1651367, Registration date: August 19, 2016 Title: Programmable vehicle regulator Japanese Registered Patent: JP 4925171, Registration Date: February 17, 2012, Title: Semiconductor integrated circuit and method for diagnosis thereof.

An object of the present invention is to provide a voltage regulator that performs real-time open-load diagnosis and a method for diagnosing the open-load.

A voltage regulator according to an exemplary embodiment of the present invention includes a comparator comparing a reference voltage and a feedback voltage of a feedback pin; A transistor outputting an output voltage to an output pin in response to the output of the comparator; A first shunt resistor having one end connected to the output pin; A second shunt resistor connected between the other end of the first shunt resistor and a ground terminal; And a voltage monitor performing a short circuit diagnosis or an open load diagnosis by monitoring the feedback voltage of the feedback pin connected to the other end of the first shunt resistor, and providing a diagnostic current to the feedback pin during the open load diagnosis. It is characterized by.

In an embodiment, the diagnostic current is characterized in that the rate of change of the output voltage is determined to be equal to or less than a predetermined value.

In an embodiment, a first PMOS transistor connected between a power supply terminal and the feedback pin and having a gate terminal connected to a first node; A second PMOS transistor connected between the power supply terminal and the first node, and having a gate terminal connected to the first node; A third PMOS transistor connected between the power terminal and the first node and having a gate terminal receiving a pull-up off signal; And a first diagnostic current source connected to the first node.

In an embodiment, a first NMOS transistor connected between the feedback pin and the ground terminal and having a gate terminal connected to a second node; A second NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to the second node; A third NMOS transistor connected between the second node and the ground terminal and having a gate terminal receiving a pull-down signal; And a second diagnostic current source connected to the second node.

In an embodiment, a first PMOS transistor connected between a power supply terminal and the feedback pin and having a gate terminal connected to a first node; A second PMOS transistor connected between the power supply terminal and the first node, and having a gate terminal connected to the first node; A third PMOS transistor connected between the power terminal and the first node and having a gate terminal receiving a pull-up off signal; A fourth PMOS transistor connected between the power supply terminal and the second node and having a gate terminal connected to the third node; A fifth PMOS transistor connected between the power supply terminal and the third node and having a gate terminal connected to the third node; A first NMOS transistor connected between the feedback pin and the ground terminal and having a gate terminal connected to the second node; A second NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to the second node; A third NMOS transistor connected between the second node and the ground terminal and having a gate terminal receiving a pull-down signal; A fourth NMOS transistor connected between the first node and the ground terminal and having a gate terminal connected to a fourth node; A fifth NMOS transistor connected between the third node and the ground terminal and having a gate terminal connected to the fourth node; A sixth NMOS transistor connected between the fourth node and the ground terminal, and having a gate terminal connected to the fourth node; And a current source connected between the power terminal and the fourth node.

In an embodiment, at least one of the first and second shunt resistors is characterized by being a variable resistor.

In an embodiment, the diagnostic current may include: a first diagnostic current provided from the power supply terminal to the feedback pin; And a second diagnostic current that falls from the feedback pin to the ground terminal.

In an embodiment, a first transistor connected to the output pin and turned on when the second diagnostic current falls to the ground terminal; And a first variable shunt resistor connected between the drain terminal of the first transistor and the feedback pin.

In an embodiment, a second transistor connected to the ground terminal and turned on when the first diagnostic current is provided to the feedback pin; And a first variable shunt resistor connected between the drain terminal of the second transistor and the feedback pin.

In an embodiment, a first PMOS transistor connected between a power supply terminal and the feedback pin and having a gate terminal connected to a first node; A second PMOS transistor connected between the power supply terminal and the first node, and having a gate terminal connected to the first node; A third PMOS transistor connected between the power supply terminal and the first node and having a gate terminal connected to a pull-up off stage; A fourth PMOS transistor connected between the power supply terminal and the second node and having a gate terminal connected to the third node; A fifth PMOS transistor connected between the power supply terminal and the third node and having a gate terminal connected to the third node; A first NMOS transistor connected between the feedback pin and the ground terminal and having a gate terminal connected to the second node; A second NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to the second node; A third NMOS transistor connected between the second node and the ground terminal, and having a gate terminal connected to a pull-down off terminal; A fourth NMOS transistor connected between the first node and the ground terminal and having a gate terminal connected to a fourth node; A fifth NMOS transistor connected between the third node and the ground terminal and having a gate terminal connected to the fourth node; A sixth NMOS transistor connected between the fourth node and the ground terminal, and having a gate terminal connected to the fourth node; A current source connected between the power terminal and the fourth node; A first transistor connected to the output pin and having a gate terminal connected to the pull-down off stage; A second transistor connected to the ground terminal and having a gate terminal connected to the pull-up off terminal; A first variable shunt resistor connected between the drain terminal of the first transistor and the feedback pin; And a second variable shunt resistor connected between the feedback pin and the drain terminal of the second transistor.

In an embodiment, one diagnostic pin for canceling the diagnostic current may be further included.

In an embodiment, the first PMOS transistor is connected between the power supply terminal and the diagnostic pin and has a gate terminal connected to a first node; A second PMOS transistor connected between the power supply terminal and the first node, and having a gate terminal connected to the first node; A third PMOS transistor connected between the power supply terminal and the first node, and having a gate terminal connected to a fifth node connected to the feedback pin; A fourth PMOS transistor connected between the power terminal and the sixth node, and having a gate terminal connected to the third node; A fifth PMOS transistor connected between the power supply terminal and the third node and having a gate terminal connected to the third node; A sixth PMOS transistor connected between the power supply terminal and the feedback pin and having a gate terminal connected to the fifth node; A seventh PMOS transistor connected between the power terminal and the fifth node, and having a gate terminal connected to the fifth node; An eighth PMOS transistor connected between the power supply terminal and the fifth node and having a gate terminal receiving a pull-up off signal; A first NMOS transistor connected between the diagnostic pin and the ground terminal and having a gate terminal connected to a second node; A second NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to the second node; A third NMOS transistor connected between the first node and the ground terminal, and having a gate terminal connected to the sixth node; A fourth NMOS transistor connected between the fifth node and the ground terminal, and having a gate terminal connected to a fourth node; A fifth NMOS transistor connected between the third node and the ground terminal and having a gate terminal connected to the fourth node; A sixth NMOS transistor connected between the fourth node and the ground terminal, and having a gate terminal connected to the fourth node; A seventh NMOS transistor connected between the feedback pin and the ground terminal and having a gate terminal connected to the sixth node; An eighth NMOS transistor connected between the sixth node and the ground terminal and having a gate terminal connected to the sixth node; A ninth NMOS transistor connected between the sixth node and the ground terminal and having a gate terminal receiving a pull-down signal; And a current source connected between the power terminal and the fourth node.

In an embodiment, the diagnostic current includes a first diagnostic current of a pull-up type and a second diagnostic current of a pull-down type, and a resistance value of the first shunt resistor so that the second diagnostic current always flows during the open load diagnosis. It is characterized by being determined.

In an embodiment, a gate driver for controlling on / off of the transistor using the output of the comparator may be further included.

A method of diagnosing an open load of a voltage regulator according to an embodiment of the present invention includes: diagnosing an open load in an off state; And real-time diagnosis of an open load in an on state, wherein the real-time diagnosis comprises: providing a diagnostic current to a feedback pin; And canceling the diagnostic current.

In an embodiment, the step of canceling the diagnostic current may include the step of canceling the diagnostic current through variable control of a shunt resistor connected between the output pin and the ground terminal.

In an embodiment, the step of canceling the diagnostic current may include providing a current that cancels the diagnostic current using a diagnostic pin.

In an embodiment, the value of the shunt resistor connected between the output pin and the feedback pin is determined so that the diagnostic current always flows.

In an embodiment, providing the diagnostic current may further include providing a first diagnostic current from the power supply terminal to the feedback pin.

In an embodiment, the step of providing the diagnostic current may further include the step of releasing the second diagnostic current from the feedback pin to the ground terminal.

The voltage regulator according to an embodiment of the present invention and its open-load diagnostic method can implement real-time open-load diagnostics by implementing various methods to generate a current that cancels the diagnostic current during diagnosis.

In addition, the voltage regulator according to an embodiment of the present invention and its open load diagnostic method can be implemented with a simple configuration such as an external resistor and a diagnostic current source to diagnose an open load inexpensively and efficiently.

The accompanying drawings are provided to help understanding of the present embodiment, and provide embodiments with a detailed description. However, the technical features of the present embodiment are not limited to specific drawings, and the features disclosed in each drawing may be combined with each other to form a new embodiment.
1 is a view showing a typical linear regulator.
2 is a view showing a typical switching regulator.
3 is a view showing that an SCG or SCB has occurred due to an external factor such as a single wire contact.
4 is a view showing that an open load occurs due to a disconnection of the feedback loop due to a soldering failure or the like.
5, 6 and 7 are diagrams for explaining a conventional open-load diagnostic technique.
8 is a view for explaining a process of diagnosing an open load in a normal case.
9, 10, and 11 are diagrams showing an effect on output accuracy when performing OL diagnosis during a regulator operation.
12 is a diagram exemplarily showing a voltage regulator for diagnosing an open load using a micro-diagnostic current according to an embodiment of the present invention.
13 is a diagram illustrating an exemplary embodiment in which the current source of FIG. 12 is implemented as a transistor.
14 is a diagram exemplarily showing an embodiment in which the voltage regulator shown in FIG. 13 is implemented.
15 is a diagram illustrating a voltage regulator according to an embodiment of the present invention using an external variable resistance control.
16 is a diagram illustrating a voltage regulator according to another embodiment of the present invention using an external variable resistance control.
17 exemplarily shows a voltage regulator implemented with a variable resistor and a transistor.
18 is a diagram exemplarily showing an embodiment in which the voltage regulator shown in FIG. 17 is implemented.
19 exemplarily shows a voltage regulator implemented with a pair of interconnected current sources instead of resistors.
20 is a diagram exemplarily showing an embodiment in which the voltage regulator of FIG. 19 is implemented.
21 is a diagram illustrating a voltage regulator implemented in a combination of a fine current control method and an external resistance control method.
22 exemplarily shows a voltage regulator that cancels a diagnostic current using one external pin.
23 exemplarily shows a current path of the diagnostic current.
24 is a diagram showing an exemplary embodiment of a voltage regulator using a current mirror.
25 exemplarily shows a voltage regulator having a feedback resistor that can always drive a diagnostic current according to an embodiment of the present invention.
26 is a diagram exemplarily showing an embodiment in which the voltage regulator shown in FIG. 25 is implemented.
FIG. 27 is a diagram showing a simulation result by assuming an OL failure of the voltage regulator shown in FIG. 26.
28 is a flowchart exemplarily showing a method for diagnosing an open load of a voltage regulator according to an embodiment of the present invention.

Hereinafter, the contents of the present invention will be described clearly and in detail so that those skilled in the art of the present invention can easily implement the drawings using the drawings.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosure form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Terms such as first and second may be used to describe various components, but the components should not be limited by the terms.

The terms may be used for the purpose of distinguishing one component from other components. For example, the first component may be referred to as the second component without departing from the scope of the present invention, and similarly, the second component may also be referred to as the first component. When an element is said to be "connected" or "connected" to another component, it is understood that other components may be directly connected or connected to the other component, but other components may exist in the middle. It should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that no other component exists in the middle.

Other expressions describing the relationship between the components, such as "between" and "just between" or "neighboring to" and "directly neighboring to" should be interpreted as well. Terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise.

In this application, the terms "include" or "have" are intended to indicate the presence of a feature, number, step, action, component, part or combination thereof carried out, one or more other features or numbers. It should be understood that it does not preclude the existence or addition possibilities of, steps, actions, components, parts or combinations thereof. Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person skilled in the art to which the present invention pertains. Terms such as those defined in a commonly used dictionary should be interpreted as meanings consistent with meanings in the context of related technologies, and should not be interpreted as ideal or excessively formal meanings unless explicitly defined in the present application. .

The regulator according to an embodiment of the present invention and its diagnostic method may perform real-time open load diagnosis as well as open load diagnosis in an off state.

A typical programmable voltage regulator includes a feedback control for output voltage control.

1 is a view showing a typical linear regulator. Referring to FIG. 1, the linear regulator 10 includes a feedback control unit 12. The feedback control unit 12 distributes the resistance of the output voltage to the resistors R _S1 and R _S2 connected between the output pin OUT and the ground terminal GND to transfer it to the feedback pin FB. The linear regulator 10 outputs the battery voltage VBAT to the output pin OUT by comparing the voltage of the reference voltage REF and the feedback pin FB.

2 is a view showing a typical switching regulator. Referring to FIG. 2, the switching regulator 20 feedback-divides the voltage associated with the output pin OUT to resistors R _S1 and R _S2 and distributes the output voltage to the feedback pin FB. It includes.

Recently, semiconductors for automobiles are strengthening various diagnostic functions. The feedback control of the voltage regulator should also be capable of fault diagnosis. In general, fault diagnosis includes SCG (Short Circuit to Ground), SCB (Short Circuit to Battery), and OL (Open Load).

3 is a view showing that an SCG or SCB has occurred due to an external factor such as a single wire contact. As shown in FIG. 3, the SCB failure determines that the output voltage is high by feedback control and turns off the regulator output. Thus, SCB failure is a relatively safe failure compared to SCG / OL. However, the SCG / OL failure determines that the regulator output voltage is insufficient due to feedback control and raises the regulator output voltage to the maximum value, so that the load module may be damaged by high voltage. In particular, in the case of a boost converter among switching regulators, there is a high risk of high voltage damage of the load module. A fault diagnosis circuit is needed to protect the circuit from such damage.

Generally, SCG / SCB failures are relatively easy to respond to real-time failure diagnosis with a voltage monitoring circuit using a comparator, but in the case of OL failures, real-time diagnosis is difficult. 4 is a view showing that an open load occurs due to a disconnection of the feedback loop due to a soldering failure or the like.

A typical conventional OL diagnostic technique is illustrated by FIGS. 5, 6 and 7. As shown in FIG. 5, it is assumed that the FB pin is opened and the feedback loop is broken, thereby causing an OL failure. OL diagnosis is performed before activating the regulator, and in the first process, SCB is intentionally generated by closing the switch S ₁ as shown in FIG. 6. Since the FB pin is open, the FB node voltage rises to VDD, and the SCB is detected by a voltage monitor. Next, as shown in Fig. 7, the switch S ₁ is opened again, and the switch S ₂ is closed. Similarly, since the FB pin is open, the FB node voltage drops to the ground voltage, and SCG is detected by the voltage monitor. As described above, when the SCB and SCG signals are sequentially generated by S ₁ and S ₂ through a series of processes, the signals are processed and sensed as OL.

8 is a view for explaining a process of diagnosing an open load in a normal case. As shown in FIG. 8, if there is no fault in which the FB pin is open, R _S2 strongly holds it to GND, so even if the voltage is pushed to S ₁ and S ₂ , there is no voltage fluctuation at the FB node (however R _S1 , R _S2 << R _D1 , R _D2 ). For this reason, the operation of the switch S ₁ and S ₂ is identically generated by SCG and SCG, respectively. Through this, it is judged that there is no abnormality in OL diagnosis.

However, such a conventional OL diagnostic method can be performed only once before the regulator is activated, and it is not possible to diagnose the OL failure occurring during the operation of the regulator in real time. This is because, when applied to real-time diagnostics, the operation of S ₁ and S ₂ affects the voltage distribution values of the feedback resistors R _S1 and R _S2 , thereby reducing the accuracy of the regulator.

9, 10, and 11 are diagrams showing an effect on output accuracy when performing OL diagnosis during a regulator operation. If the regulator output V _OUT of FIG. 9 is 3.3V and VDD is 3.3V, the current flowing through the resistor dividers R _S1 and R _S2 is 33mA. As shown in FIG. 10, when S ₁ is turned on for OL diagnosis, an additional current of I _FB = 4 uA flows through the resistance as shown below. Because of this, the feedback voltage V _FB value should be 1.22V originally, but increases to 1.37V due to the additional leakage current I _FB .

Therefore, the regulator adjusts the output voltage V _OUT to about 2.95V to reduce the V _FB voltage to 1.22V. This causes output distortion. Eventually, the output voltage is distorted due to the operation of S ₁ for OL diagnosis, and the output voltage accuracy is reduced by about 10%. Depending on the application, since the output voltage accuracy is less than 3% and mostly 5%, an error of 10% is unacceptable. As shown in FIG. 11, even when S2 is operated for OL diagnosis, V _FB A distortion occurs at 1.13V, which causes the output voltage V _OUT to change to about 3.55V, resulting in an output voltage error of about 7.5%.

Meanwhile, in the following, a voltage regulator capable of real-time OL diagnosis will be described. The voltage regulator according to the embodiment of the present invention diagnoses OL by using a fine diagnostic current within an allowable limit of output voltage accuracy, or diagnoses OL by canceling the diagnostic current through variable control of external resistance, or by using one external pin. It is possible to diagnose OL by supplying a current for current cancellation, or to diagnose OL by enabling the driving of the diagnostic current through an external resistor design.

First, OL diagnosis using micro-diagnostic current

12 is a diagram exemplarily showing a voltage regulator for diagnosing an open load using a micro-diagnostic current according to an embodiment of the present invention. Referring to FIG. 12, the voltage regulator 100 may include a comparator COM, a transistor TR, a voltage monitor 110, and a current source 120 130.

The comparator COM may be implemented to compare the reference voltage REF_REG and the feedback voltage. Here, the feedback voltage may be the voltage of the feedback pin FB.

The transistor TR may be implemented to output the battery voltage VBAT to the output pin OUT in response to the output of the comparator COM. The voltage of the output pin OUT may be divided by the first shunt resistor R _S1 and the second shunt resistor R _S2 . The first end of the shunt resistor (R _S1) is connected to the output pin (OUT), the other end of the first shunt resistor (R _S1) may be connected to the feedback pin (FB). One end of the second shunt resistor R _S2 may be connected to the feedback pin FB, and the other end of the second shunt resistor R _S2 may be connected to the ground terminal GND.

The voltage monitor 110 may be implemented to receive the feedback voltage of the feedback pin FB and monitor the SCG / SCB / OL.

In an embodiment, the voltage regulator 100 may be implemented to diagnose OL using a microcurrent of 1 μA or less so as not to exceed the rated output voltage range. The effect of the current IS1 on the output voltage is as follows.

Therefore, the output voltage change rate A is as shown in the following equation.

Therefore, if the diagnostic currents I _S1 and I _S2 are less than ₁ uA, the output voltage accuracy can be satisfied by 3%. For example, when a diagnostic current of 100 nA is used, the output voltage change rate is 0.3%. FIG. 13 is a view exemplarily showing an embodiment in which the current sources 120 and 130 of FIG. 12 are implemented as transistors. The current source as shown in Figure _{13 (120, 130; I S1} , I S2) may be implemented using a MOSFET (metal oxide semiconductor filed effect transistor). If implemented as a resistor to create a microcurrent in the order of hundreds of nA, a large resistance in the order of several MΩ is required. This can be disadvantageous in terms of cost to implement in a semiconductor process. As shown in FIG. 13, it is advantageous to supply a diagnostic current by generating a reference current using a reference voltage REF_REG, and generating a fine current using a current mirror.

14 is a diagram exemplarily showing an embodiment in which the voltage regulator shown in FIG. 13 is implemented. Referring to FIG. 14, the voltage regulator 100 includes p-channel MOS (PMOS) transistors PM1, PM2, PM3, PM4, and PM5, and n-channel MOS (NMOS) transistors NM1 , NM2, NM3, NM4, NM5, NM6), and a current source (I _DC ).

The first PMOS transistor PM1 may be connected between the power terminal VINT and the feedback pin FB. The second and third PMOS transistors PM2 and PM3 may be connected between the power terminal VINT and the first node N1. Here, the first node N1 may be connected to gate terminals of the first and second PMOS transistors PM1 and PM2. The gate terminal of the third PMOS transistor PM2 may receive a pull-up off (PU_OFF) signal.

The fourth PMOS transistor PM4 may be connected between the power terminal VINT and the second node N2. The fifth PMOS transistor PM5 may be connected between the power terminal VINT and the third node N3. Gate terminals of the fourth and fifth PMOS transistors PM4 and PM5 may be connected to the third node N3.

The first NMOS transistor NM1 may be connected between the feedback pin FB and the ground terminal GND. The second and third NMOS transistors NM2 and NM3 may be connected between the second node N2 and the ground terminal GND. Gate terminals of the first and second NMOS transistors NM1 and NM2 may be connected to the second node N2. The gate end of the third NMOS transistor NM3 may receive a pull-down off (PD_OFF) signal.

The fourth NMOS transistor NM4 may be connected between the first node N1 and the ground terminal GND. The gate terminal of the fourth NMOS transistor NM4 may be connected to the fourth node N4. The fifth and sixth NMOS transistors NM5 and NM6 may be connected between the fourth node N4 and the ground terminal GND. Gate terminals of the fifth and sixth NMOS transistors NM5 and NM6 may be connected to the fourth node N4.

The current source I _DC may be connected between the power terminal VINT and the fourth node N4.

Meanwhile, the diagnostic current value may be calculated using Equations 7 to 12. As a result of the simulation, it was estimated that the level was 0.2%, and the output voltage had little effect.

Second, OL diagnosis by offsetting the diagnostic current through variable control of external resistance

The voltage regulator according to an embodiment of the present invention may diagnose an open load by using a strong diagnostic current to change the external resistance to cancel the diagnostic current.

15 is a diagram illustrating a voltage regulator according to an embodiment of the present invention using an external variable resistance control. Referring to FIG. 15, the voltage regulator 200 may include a second shunt resistor R _S2 having a variable resistor as compared to that shown in FIG. 9.

16 is a diagram illustrating a voltage regulator according to another embodiment of the present invention using an external variable resistance control. Referring to FIG. 16, the voltage regulator 200a may include a first shunt resistor R _S1 having a variable resistor as compared to that shown in FIG. 9.

Meanwhile, both the first and second shunt resistors may be implemented as variable resistors.

17 exemplarily shows a voltage regulator implemented with a variable resistor and a transistor. The voltage regulator 200b attaches the resistors R _VS1 and R _VS2 to be _changed, and then drives the M ₁ and M ₂ switches in synchronization with the operation of I _S1 and I _S2 , thereby making the R _VS1 and R _VS2 resistors visible or invisible to diagnose current. Can be offset.

Here, the values of RVS1 and RVS2 can be determined as follows.

Assuming R _S1 = 6.3k, R _S2 = 3.7k, I _FB = 100u, and V _OUT = 3.3, R _VS1 is as follows.

The second variable resistor R _VS2 can also be calculated with the same approach.

18 is a diagram exemplarily showing an embodiment in which the voltage regulator shown in FIG. 17 is implemented. Referring to FIG. 18, the voltage regulator 200b may be implemented using R _{VS1 and} R _VS2 values previously calculated. The internal configuration of the voltage regulator 200b for providing the diagnostic current can be implemented in the same way as that shown in FIG. 14.

The pull-down off end PD_OFF may be connected to the gate end of the third NMOS transistor NM3 for providing a diagnostic current. Also, the pull-down off end PD_OFF may be connected to the gate end of the first transistor M1. The first transistor M1 may be connected between the output pin OUT and the first variable resistor R _VS1 . One end of the first variable resistor R _VS1 may be connected to the drain terminal of the first transistor M1, and the other end of the first variable resistor R _VS1 may be connected to the feedback pin FB. In an embodiment, the first transistor M1 may include a PMOS transistor. The first shunt resistor R _S1 may be connected between the output pin OUT and the feedback pin FB.

The pull-up off end PU_OFF may be connected to the gate end of the third PMOS transistor PM3 for providing a diagnostic current. Also, the pull-up off end PU_OFF may be connected to the gate end of the second transistor M2. The second transistor M2 may be connected between the second variable resistor R _VS2 and the ground terminal GND. One end of the second variable resistor R _VS2 may be connected to the feedback pin FB, and the other end of the second variable resistor R _VS2 may be connected to the drain terminal of the second transistor M2. In an embodiment, the second transistor M2 may include an NMOS transistor. The second shunt resistor R _S2 may be connected between the feedback pin FB and the ground terminal GND.

Before applying the present invention, the output voltage VOUT changes greatly, but after application, it can be confirmed that there is little change in the output voltage even during diagnosis.

Meanwhile, the external resistor can be replaced by a pair of interconnected current sources.

19 exemplarily shows a voltage regulator implemented with a pair of interconnected current sources instead of resistors. Referring to FIG. 19, the voltage regulator 200c may be implemented to cancel the diagnostic current using a pair of current sources I _C1 and I _C2 interlocked instead of a resistor. Through this, R _VS1 and R _VS2 resistance can be reduced. A bias voltage for driving M ₁ and M ₂ in VBIAS_M1 and VBIAS_M2 can be provided.

20 is a diagram exemplarily showing an embodiment in which the voltage regulator 200c of FIG. 19 is implemented. Referring to FIG. 19, the first transistor M1 and the first shunt resistor R _S1 may be connected between the output pin OUT and the feedback pin FB. The gate terminal of the first transistor M1 may be connected to the first bias terminal VBIAS_M1.

The second transistor M2 and the second shunt resistor R _S2 may be connected between the feedback pin FB and the ground terminal GND. The gate terminal of the second transistor M2 may be connected to the second bias terminal VBIAS_M2.

Meanwhile, the voltage regulator according to an embodiment of the present invention may be implemented in a combination of a micro current control method and an external resistance control method.

21 is a diagram illustrating a voltage regulator implemented in a combination of a fine current control method and an external resistance control method. Referring to FIG. 21, the voltage regulator 200d is diagnosed as a micro-current during normal times, and when a strong diagnostic current is required, it can be applied in a combination that enhances the diagnostic current through PW_U and PW_D control signals and controls external resistance to cancel it. Do.

Third, supply the current for canceling the diagnostic current using one external pin.

In the case of the method of canceling the above-described diagnostic current, two external pins (PU_OFF, PN_OFF) were used. The more semiconductor products that have more functions such as functional safety, the more often the pin-oriented package is used than the die-size-oriented semiconductor package. Therefore, reducing the number of pins helps to reduce the cost.

22 exemplarily shows a voltage regulator that cancels a diagnostic current using one external pin. Referring to FIG. 22, the voltage regulator 300 may include a diagnostic pin (DIAG) for canceling a diagnostic current when diagnosing OL. The voltage regulator 300 of the present invention is advantageous for cost reduction because it does not require additional external elements such as resistors or transistors.

As shown in FIG. 22, the first switch S ₁ is turned on, the second switch S ₂ is turned off, the third switch S ₃ is turned off, and the fourth switch S ₄ is turned on. At this time, the first diagnostic current I _S1 may flow to the ground terminal GND via the feedback pin FB and the diagnostic pin DIAG.

23 exemplarily shows a current path of the second diagnostic current (I _S2 ). Referring to FIG. 23, when the first switch S ₁ is turned off, the second switch S ₂ is turned on, the third switch S ₃ is turned on, and when the fourth switch S ₄ is turned off, The second diagnostic current (I _S2 ) may flow from the power supply terminal (VDD) to the ground terminal (GND) via the feedback pin (FB) and the diagnostic pin (DIAG).

24 exemplarily shows an embodiment of the voltage regulator 300 using a current mirror. Referring to FIG. 24, the voltage regulator 300 may include PMOS transistors PM1 to PM8 and NMOS transistors NM1 to NM9.

The first PMOS transistor PM1 may be connected between the power terminal VINT and the feedback pin FB. The second PMOS transistor PM2 may be connected between the power terminal VINT and the first node N1. The gate terminals of the first and second PMOS transistors PM1 and PM2 may be connected to the first node N1. The third PMOS transistor PM3 may be connected between the power terminal VINT and the second node N2. The gate terminal of the third PMOS transistor PM3 may be connected to the fifth node N5. The fourth PMOS transistor PM4 may be connected between the power terminal VINT and the sixth node N6. The fifth PMOS transistor PM5 may be connected between the power terminal VINT and the third node N3. Gate terminals of the fourth and fifth PMOS transistors PM4 and PM5 may be connected to the third node N3.

The sixth, seventh, and eighth PMOS transistors PM6, PM7, and PM8 may be connected between the power terminal VINT and the fifth node N5. Gate terminals of the sixth and seventh PMOS transistors PM6 and PM7 may be connected to the fifth node N5. The gate terminal of the eighth PMOS transistor PM8 may receive a pull-up off (PU_OFF) signal.

The first NMOS transistor NM1 may be connected between the diagnostic pin DIAG and the ground terminal GND. The second NMOS transistor NM2 may be connected between the second node N2 and the ground terminal GND. Gates of the first and second NMOS transistors NM1 and NM2 may be connected to the second node N2. The third NMOS transistor NM3 may be connected between the first node N1 and the ground terminal GND. The gate terminal of the third NMOS transistor NM3 may be connected to the sixth node N6. The fourth NMOS transistor NM4 may be connected between the fifth node N5 and the ground terminal GND. The gate terminal of the fourth NMOS transistor NM4 may be connected to the fourth node N4. The fifth and sixth NMOS transistors NM5 and NM6 may be connected between the fourth node N4 and the ground terminal GND. Gates of the fifth and sixth NMOS transistors NM5 and NM6 may be connected to the fourth node N4.

The seventh, eighth and ninth NMOS transistors NM7, NM8, and NM9 may be connected between the sixth node N6 and the ground terminal GND. Gate terminals of the seventh and eighth NMOS transistors NM7 and NM8 may be connected to the sixth node N6. The gate terminal of the ninth NMOS transistor NM9 may receive a pull-down off (PD_OFF) signal.

As shown in FIG. 24, the voltage regulator 300 may supply a current for canceling the diagnostic current through an external pin (DIAG). The voltage regulator 300 can be easily implemented using a current mirror. PU_OFF and PD_OFF are driven for OL diagnosis, so the output voltage (VOUT) hardly changes even when the diagnostic current flows.

Fourth, the external resistor is designed to drive the diagnostic current all the time.

25 exemplarily shows a voltage regulator having a feedback resistor that can always drive a diagnostic current according to an embodiment of the present invention. Referring to FIG. 25, the voltage regulator 400 may appropriately select a resistance value of the first shunt resistor RS1. When designing the feedback resistor, the resistance value of R _S1 can be designed by reflecting the second diagnostic current (I _S2 ). Even if the I _S2 diagnostic current continuously flows during normal voltage regulator operation, do not affect the feedback voltage. This method does not require a separate external pin for canceling the diagnostic current even if a strong diagnostic current is used.

The diagnostic procedure of the voltage regulator 400 according to an embodiment of the present invention may be performed as follows. The voltage regulator 400 may be changed from an off state to an on state. At this time, at the same time, the second switch S ₂ is turned on, so that the diagnostic current I _S2 flows continuously. When designing the resistance value of the first shunt resistor R _S1 , the voltage regulator 400 can operate normally because it is designed in consideration of the current of I _S2 . If an OL failure occurs (ex. FB pin soldering falls), the SCG flag may be generated when I _S2 pulls down the feedback pin FB.

After the second switch S ₂ is turned off, the first switch S ₁ may be turned on. At this time, the SCB flag may be generated by the node voltage of the feedback pin FB being pulled up by the diagnostic current I _S1 .

Since the diagnostic flag of the present invention depends on the operation of the diagnostic currents I _S1 and I _S2 , it can be diagnosed as an OL failure through signal processing.

On the other hand, the always-on diagnostic current shown in FIG. 25 was the second diagnostic current (I _S2 ). However, it should be understood that the present invention is not limited to this. The constant-current diagnostic current of the present invention may select either I _S1 or I _S2 . In the following for convenience of description, we will assume a diagnosis current which always-I _S2 of the type pull-down current.

When I _S2 is used as a constant diagnostic current, the value of R _S1 can be calculated as follows. The feedback resistor sum value R _S is based on 10 kΩ. REF_REG = V _FB = 1.22 V is based.

26 is a diagram exemplarily showing an embodiment in which the voltage regulator 400 illustrated in FIG. 25 is implemented. Referring to FIG. 26, the voltage regulator 400 may include a first shunt resistor R _S1 to always flow a pull-down type diagnostic current to the internal configuration of the voltage regulator 100 shown in FIG. 14.

FIG. 27 is a diagram illustrating a simulation result when an OL failure of the voltage regulator 400 illustrated in FIG. 26 is assumed. Referring to FIG. 27, as a simulation result, by recognizing the SCG and SCB of the FB node in the process of ② to ④, it is possible to diagnose OL using the state variation of the FB node according to I _S1 and I _S2 .

Conventional voltage regulators have been able to diagnose OL only in the off state. On the other hand, the voltage regulator according to the embodiment of the present invention can perform real-time OL diagnosis. The voltage regulator of the present invention can be implemented in various ways to enable real-time OL diagnosis.

28 is a flowchart exemplarily showing a method for diagnosing an open load of a voltage regulator according to an embodiment of the present invention. 12 to 28, an open load diagnosis method of a voltage regulator may proceed as follows.

In the off state, an open load diagnosis may be performed (S110). In the on state, the open load diagnosis may be performed in real time (S110). Real-time open-load diagnostics may include providing a diagnostic current to the feedback pin and canceling the diagnostic current. Here, the real-time open load diagnosis operation can be implemented in various ways, as described in FIGS. 12 to 27. For example, a real-time open load diagnostic operation can diagnose OL using a fine diagnostic current within the output voltage accuracy tolerance, or diagnose OL by offsetting the diagnostic current through external resistance variable control, or use one external pin to diagnose current. OL can be diagnosed by supplying the offset current, or by enabling the driving of the diagnostic current through an external resistor design.

The steps and / or operations according to the present invention may occur simultaneously in other embodiments, in different order, or in parallel, or in different embodiments for different epochs, etc., as can be understood by one skilled in the art. You can.

Depending on the embodiment, some or all of the steps and / or actions drive instructions, programs, interactive data structures, clients and / or servers stored in one or more non-transitory computer-readable media. At least some may be implemented or performed using one or more processors. The one or more non-transitory computer-readable media may illustratively be software, firmware, hardware, and / or any combination thereof. Further, the functionality of the "module" discussed herein may be implemented in software, firmware, hardware, and / or any combination thereof.

One or more non-transitory computer-readable media and / or means for implementing / performing one or more operations / steps / modules of embodiments of the present invention include application-specific integrated circuits (ASICs), standard integrated circuits, Controllers that perform appropriate instructions, including microcontrollers, and / or embedded controllers, field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and the like. Does not.

Meanwhile, the present invention is not limited to a voltage regulator, and can be applied to any place where real-time OL diagnosis is required, such as a high-side (HS) switch, a low-side (LS) switch, and an actuator driver. The present invention can implement real-time OL diagnosis at an efficient cost.

Meanwhile, the above-described contents of the present invention are only specific embodiments for carrying out the invention. The present invention will include technical ideas that are abstract and conceptual ideas that can be utilized as future technologies as well as specific and practical means that can be used.

100, 200, 300, 400: voltage regulator
110, 210, 310, 410: voltage monitor
COM: comparator
TR: transistor
OUT: Output pin
FB: Feedback pin
DIAG: diagnostic pin
R _S1 : 1st shunt resistor
R _S2 : Second shunt resistor
R _VS1 : 1st variable shunt resistor
R _VS2 : 2nd variable shunt resistor
I ₁ : first diagnostic current
I ₂ : Second diagnostic current

Claims (20)

A comparator comparing the reference voltage and the feedback voltage of the feedback pin;
A transistor outputting an output voltage to an output pin in response to the output of the comparator;
A first shunt resistor having one end connected to the output pin;
A second shunt resistor connected between the other end of the first shunt resistor and a ground terminal; And
And a voltage monitor performing a short circuit diagnosis or an open load diagnosis by monitoring the feedback voltage of the feedback pin connected to the other end of the first shunt resistor,
When the open-load diagnosis, the voltage regulator, characterized in that to provide a diagnostic current to the feedback pin. The method of claim 1,
The diagnostic current is a voltage regulator, characterized in that the rate of change of the output voltage is determined to be equal to or less than a predetermined value. The method of claim 1,
A first PMOS transistor connected between a power supply terminal and the feedback pin and having a gate terminal connected to a first node;
A second PMOS transistor connected between the power supply terminal and the first node, and having a gate terminal connected to the first node;
A third PMOS transistor connected between the power terminal and the first node and having a gate terminal receiving a pull-up off signal; And
And a first diagnostic current source connected to the first node. The method of claim 1,
A first NMOS transistor connected between the feedback pin and the ground terminal and having a gate terminal connected to a second node;
A second NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to the second node;
A third NMOS transistor connected between the second node and the ground terminal and having a gate terminal receiving a pull-down signal; And
And a second diagnostic current source connected to the second node. The method of claim 1,
A first PMOS transistor connected between a power supply terminal and the feedback pin and having a gate terminal connected to a first node;
A second PMOS transistor connected between the power supply terminal and the first node, and having a gate terminal connected to the first node;
A third PMOS transistor connected between the power terminal and the first node and having a gate terminal receiving a pull-up off signal;
A fourth PMOS transistor connected between the power supply terminal and the second node and having a gate terminal connected to the third node;
A fifth PMOS transistor connected between the power supply terminal and the third node and having a gate terminal connected to the third node;
A first NMOS transistor connected between the feedback pin and the ground terminal and having a gate terminal connected to the second node;
A second NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to the second node;
A third NMOS transistor connected between the second node and the ground terminal and having a gate terminal receiving a pull-down signal;
A fourth NMOS transistor connected between the first node and the ground terminal and having a gate terminal connected to a fourth node;
A fifth NMOS transistor connected between the third node and the ground terminal and having a gate terminal connected to the fourth node;
A sixth NMOS transistor connected between the fourth node and the ground terminal, and having a gate terminal connected to the fourth node; And
And a voltage source connected between the power terminal and the fourth node. The method of claim 1,
A voltage regulator, characterized in that at least one of the first and second shunt resistors is a variable resistor. The method of claim 1,
The diagnostic current,
A first diagnostic current provided from the power supply terminal to the feedback pin; And
And a second diagnostic current flowing out from the feedback pin to the ground terminal. The method of claim 7,
A first transistor connected to the output pin and turned on when the second diagnostic current falls to the ground terminal; And
And a first variable shunt resistor connected between the drain terminal of the first transistor and the feedback pin. The method of claim 7,
A second transistor connected to the ground terminal and turned on when the first diagnostic current is provided to the feedback pin; And
And a first variable shunt resistor connected between the drain terminal of the second transistor and the feedback pin. The method of claim 1,
A first PMOS transistor connected between a power supply terminal and the feedback pin and having a gate terminal connected to a first node;
A second PMOS transistor connected between the power supply terminal and the first node, and having a gate terminal connected to the first node;
A third PMOS transistor connected between the power supply terminal and the first node and having a gate terminal connected to a pull-up off stage;
A fourth PMOS transistor connected between the power supply terminal and the second node and having a gate terminal connected to the third node;
A fifth PMOS transistor connected between the power supply terminal and the third node and having a gate terminal connected to the third node;
A first NMOS transistor connected between the feedback pin and the ground terminal and having a gate terminal connected to the second node;
A second NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to the second node;
A third NMOS transistor connected between the second node and the ground terminal, and having a gate terminal connected to a pull-down off terminal;
A fourth NMOS transistor connected between the first node and the ground terminal and having a gate terminal connected to a fourth node;
A fifth NMOS transistor connected between the third node and the ground terminal and having a gate terminal connected to the fourth node;
A sixth NMOS transistor connected between the fourth node and the ground terminal, and having a gate terminal connected to the fourth node;
A current source connected between the power terminal and the fourth node;
A first transistor connected to the output pin and having a gate terminal connected to the pull-down off stage;
A second transistor connected to the ground terminal and having a gate terminal connected to the pull-up off terminal;
A first variable shunt resistor connected between the drain terminal of the first transistor and the feedback pin; And
And a second variable shunt resistor connected between the feedback pin and the drain terminal of the second transistor. The method of claim 1,
The voltage regulator further includes one diagnostic pin for canceling the diagnostic current. The method of claim 11,
A first PMOS transistor connected between a power supply terminal and the diagnostic pin and having a gate terminal connected to a first node;
A second PMOS transistor connected between the power supply terminal and the first node, and having a gate terminal connected to the first node;
A third PMOS transistor connected between the power supply terminal and the first node, and having a gate terminal connected to a fifth node connected to the feedback pin;
A fourth PMOS transistor connected between the power terminal and the sixth node, and having a gate terminal connected to the third node;
A fifth PMOS transistor connected between the power supply terminal and the third node and having a gate terminal connected to the third node;
A sixth PMOS transistor connected between the power supply terminal and the feedback pin and having a gate terminal connected to the fifth node;
A seventh PMOS transistor connected between the power terminal and the fifth node, and having a gate terminal connected to the fifth node;
An eighth PMOS transistor connected between the power supply terminal and the fifth node and having a gate terminal receiving a pull-up off signal;
A first NMOS transistor connected between the diagnostic pin and the ground terminal and having a gate terminal connected to a second node;
A second NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to the second node;
A third NMOS transistor connected between the first node and the ground terminal, and having a gate terminal connected to the sixth node;
A fourth NMOS transistor connected between the fifth node and the ground terminal, and having a gate terminal connected to a fourth node;
A fifth NMOS transistor connected between the third node and the ground terminal and having a gate terminal connected to the fourth node;
A sixth NMOS transistor connected between the fourth node and the ground terminal, and having a gate terminal connected to the fourth node;
A seventh NMOS transistor connected between the feedback pin and the ground terminal and having a gate terminal connected to the sixth node;
An eighth NMOS transistor connected between the sixth node and the ground terminal and having a gate terminal connected to the sixth node;
A ninth NMOS transistor connected between the sixth node and the ground terminal and having a gate terminal receiving a pull-down signal; And
And a voltage source connected between the power terminal and the fourth node. The method of claim 1,
The diagnostic current includes a first diagnostic current of a pull-up type and a second diagnostic current of a pull-down type,
A voltage regulator, wherein the resistance value of the first shunt resistor is determined so that the second diagnostic current always flows during the open load diagnosis. The method of claim 1,
And a gate driver controlling on / off of the transistor using the output of the comparator. In the method of diagnosing the open load of a voltage regulator:
Diagnosing an open load in an off state; And
Real-time diagnostics of the open load in the on state,
The step of real-time diagnosis,
Providing a diagnostic current to the feedback pin; And
And canceling the diagnostic current. The method of claim 15,
The step of canceling the diagnostic current,
And canceling the diagnostic current through variable control of a shunt resistor connected between an output pin and a ground terminal. The method of claim 15,
The step of canceling the diagnostic current,
And providing a current that cancels the diagnostic current using a diagnostic pin. The method of claim 15,
A method characterized in that the value of the shunt resistor connected between the output pin and the feedback pin is determined so that the diagnostic current always flows. The method of claim 15,
The step of providing the diagnostic current,
And providing a first diagnostic current from the power supply terminal to the feedback pin. The method of claim 15,
The step of providing the diagnostic current,
And removing a second diagnostic current from the feedback pin to the ground terminal.

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