KR102119769B1 - Relay diagnosis circuit and diagnosis method thereof - Google Patents

Abstract

The operation method of the relay diagnostic circuit according to the present invention includes: performing a first fault diagnosis on a load in the off state of the relay, and turning on the relay when the load is in a normal state as a result of the first fault diagnosis, And performing a second fault diagnosis on the load in the on state of the relay, and operating the relay normally when the load is in a normal state as a result of the second fault diagnosis.

Description

RELAY DIAGNOSIS CIRCUIT AND DIAGNOSIS METHOD THEREOF

The present invention relates to a relay diagnostic circuit and its diagnostic method.

The relay acts as a switch. Using a control field effect transistor (FET), if a current is passed, the switch is connected, and if no current is passed, the switch is disconnected. Currently, many loads are controlled by relays in automobiles. In the case of the current high side relay diagnostic circuit, some types of faults are diagnosed only when the circuit is overloaded. When overloaded, the control FET or switch integrated circuit (IC) can also be burned. Even with a switch IC (integrated circuit) with protection function, it is continuously exposed to an overload environment because it protects the device by repeating turn on/off. This method is self-diagnosing, but can damage the circuit and consequently leads directly to the driver's safety.

Published Patent: 10-2017-0135206, Published Date: May 30, 2016, Title: ICU Diagnostic Device and Method. Japanese Patent Publication: JP 2005-080417, Publication date: September 1, 2003 Title: Motor drive control device.

It is an object of the present invention to provide a relay diagnostic circuit and a diagnostic method for performing the diagnosis before turning on the control FET.

A method of operating a relay diagnostic circuit according to an embodiment of the present invention includes: performing a first fault diagnosis for a load in a state in which the relay is off; Turning on the relay when the load is in a normal state as a result of the first fault diagnosis; Performing a second fault diagnosis on the load in the on state of the relay; And when the load is in a normal state as a result of the second fault diagnosis, operating the relay normally.

A relay diagnostic circuit according to an exemplary embodiment of the present invention includes a control transistor having a gate connected between a battery power terminal and an output terminal and connected to an input terminal receiving an input signal from a micro controller unit (MCU); In the turn-off state of the control transistor, a first fault diagnosis is performed on the load connected to the output terminal, and in the turn-on state of the control transistor, a second fault diagnosis is performed on the load, and the first and A diagnostic circuit that transmits a signal or information corresponding to a second failure diagnosis result to the MCU; And a turn-off circuit that does not turn on the control transistor according to the second fault diagnosis result.

The relay diagnostic circuit and its diagnostic method according to an embodiment of the present invention can improve stability by diagnosing a fault condition before relay operation.

In addition, the relay diagnostic circuit and its diagnostic method according to an embodiment of the present invention can protect the damage of the switch IC by turning off the control transistor when it is placed in an overload condition during relay operation.

The accompanying drawings are provided to help understand the present embodiment, and provide embodiments with detailed description. However, the technical features of the present embodiment are not limited to specific drawings, and the features disclosed in each drawing may be combined with each other to form a new embodiment.
1 is a view showing an exemplary relay diagnostic circuit 100 according to an embodiment of the present invention.
FIG. 2 is a diagram showing the diagnostic circuit 120 and the turn-off circuit 130 shown in FIG. 1 in more detail.
3 is a diagram showing a relay diagnostic circuit 200 according to another embodiment of the present invention by way of example.
4 is a diagram illustrating a relay diagnostic circuit 200 according to another embodiment of the present invention.
5 is a diagram showing a relay diagnostic circuit 400 according to another embodiment of the present invention by way of example.
6 is a flowchart illustrating an exemplary diagnostic method of the relay diagnostic circuit according to an exemplary embodiment of the present invention.

Hereinafter, the contents of the present invention will be described clearly and in detail so that those skilled in the art of the present invention can easily implement the drawings using the drawings.

The present invention can be applied to various changes and may have various forms, and specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosure form, and it should be understood as including all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Terms such as first and second may be used to describe various components, but the components should not be limited by the terms.

The terms may be used for the purpose of distinguishing one component from other components. For example, the first component may be referred to as the second component without departing from the scope of the present invention, and similarly, the second component may also be referred to as the first component. When an element is said to be "connected" or "connected" to another component, it is understood that other components may be directly connected to or connected to the other component, but other components may exist in the middle. It should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that no other component exists in the middle.

Other expressions describing the relationship between the components, such as "between" and "immediately between" or "neighboring to" and "directly neighboring to" should be interpreted as well. Terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise.

In this application, the terms "include" or "have" are intended to indicate that a feature, number, step, action, component, part, or combination thereof is implemented, and one or more other features or numbers. It should be understood that it does not preclude the existence or addition possibilities of, steps, actions, components, parts or combinations thereof. Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person skilled in the art to which the present invention pertains. Terms, such as those defined in the commonly used dictionary, should be interpreted as meanings consistent with meanings in the context of related technologies, and should not be interpreted as ideal or excessively formal meanings unless explicitly defined in the present application. .

1 is a view showing an exemplary relay diagnostic circuit 100 according to an embodiment of the present invention. Referring to FIG. 1, the relay diagnostic circuit 100 may include a control unit 110, a diagnostic circuit 120, and a turn-off circuit 130.

The control unit 110 may include a control transistor (FET) that is turned on/off according to control of a micro controller unit (MCU).

The control transistor FET may be connected between the battery power terminal Vbat and the load 200. In an embodiment, the transistor (FET) may include a metal on silicon field effect transistor (MOSFET). However, it should be understood that the transistor (FET) is not limited to the MOSFET. The transistor FET may be implemented with various types of transistors such as BJT and IGBT.

In an embodiment, an element may be added depending on whether the type of the control transistor (FET) is a discrete circuit or a smart IC circuit.

The diagnostic circuit 120 may be implemented to diagnose the state of the load 200 before turn-on of the control transistor (FET).

The turn-off circuit 130 may be implemented to turn off the control transistor (FET) when the load 200 is overload as a result of the advancement of the diagnostic circuit 120.

The fault condition diagnosis for the load 200 is different according to the on/off of the FET. The failure state may be classified into OL (Open Load), SCB (Battery Short), and SCG (Ground Short). Depending on the on/off of the FET, the load failure condition can be diagnosed by the following table.

SCB SCG OL ON X O X OFF O X O

On the high side, the SCB and OL are simply out of control of the relay, but in the case of the SCG it can cause permanent circuit failure. However, in the current diagnosis method, SCG diagnosis is possible only when the relay is turned ON and an overcurrent is applied to the circuit.

The relay diagnostic circuit 100 according to an embodiment of the present invention can improve stability by diagnosing a fault condition before the relay operation. In addition, the relay diagnostic circuit 100 according to an embodiment of the present invention may prevent a damage to the switch circuit by diagnosing a fault condition of the circuit (diagnosis can be classified) before relay control.

FIG. 2 is a diagram showing the diagnostic circuit 120 and the turn-off circuit 130 shown in FIG. 1 in more detail.

In an embodiment, the diagnostic circuit 120 includes a first transistor M1 turned on by an MCU, a first resistor R1 having one end connected to an internal power terminal, and a drain of the first transistor M1. The second resistor R2 connected between the ground terminal GND, the fourth resistor R4 connected between the drain of the first transistor M1 and the feedback terminal Output_ADC_FB, and the other terminal and the first terminal of the first resistor R1 It may include a first diode D1 connected to the source of the transistor M1, and a second diode D2 connected between the ground terminal GND and the feedback terminal Output_ADC_FB. Here, the drain of the first transistor M1 may be connected to the output terminal V_OUT.

In an embodiment, R4 and D2 are circuits for protecting the MCU pin, D1 is a device that prevents reverse current, and R1 and R2 are circuits that form a diagnostic voltage. The diagnostic circuit 120 may include an element that protects the MCU pin, an element that forms a diagnostic voltage, and an element that prevents reverse current.

In an embodiment, the turn-off circuit 130 may include a second transistor M2 connected between an input terminal (Input_MCU) receiving an input signal from the MCU and a gate of the control transistor M3.

In an embodiment, the turn-off circuit 130 compares the voltage between the internal power supply and the output terminal (V_OUT), comparator COM, and outputs the output value of the comparator COM and the voltage corresponding to the input terminal (Input_MCU). The logic circuit AND may include a ground resistance Rg connected between the gate of the control transistor M3 and the ground terminal GND. Here, the second transistor M2 may be turned on or off according to the result value of the logic circuit AND. In an embodiment, the result value of the logic circuit AND may be transmitted to the MCU through the error output terminal Out_Fault. In an embodiment, the turn-off circuit 130 may include a resistor (R) and a capacitor (C) to filter the signal received from the input terminal (Input_MCU). This RC filter can be used to delay the signal to prevent malfunction. Meanwhile, in addition to the RC filter, a circuit that prevents malfunction by adjusting timing is applicable.

When the FET is turned off in the relay off state, the diagnostic circuit 120 may operate as follows. Before the FET M3 is turned on, a signal for diagnosis in the MCU may be received through the diagnostic signal input terminal (Input_FB_MCU). Transistor M1 may be turned on in response to the diagnostic signal.

When the load 200 is in a normal state, the current will flow in the direction of V_5 → R1 → Diode → R3 by the diagnostic signal. A specific voltage corresponding to a normal state may be formed at the output terminal (Output_ADC_FB). For example, a specific voltage corresponding to a steady state may be 1V. However, it should be understood that the present invention is not limited to this.

When the load 200 is in the OL (open load) state, the current will flow in the direction of V_5 → R1 → Diode → R2 by the diagnostic signal. A specific voltage corresponding to the OL state may be formed at the output terminal (Output_ADC_FB). For example, a specific voltage corresponding to the OL state may be 3.5V. However, it should be understood that the present invention is not limited to this.

When the load 200 is in the SCG state, 0 V may be output to the output terminal (Output_ADC_FB). At this time, the current will flow from V_5 → R1 → Diode → Ground by the diagnostic signal. Therefore, the output voltage is 0V.

When the load 200 is in the SCB state, the controller internal power (eg, 5V) may be output to the output terminal (Output_ADC_FB). The current will flow in the direction of Vbat → R4 → D2 and Vbat → R2 by the diagnostic signal. The specific voltage at the output terminal (Output_ADC_FB) may be formed as 5V.

On the other hand, the MCU receives the voltage value through the ADC pin and can distinguish Normal, OL, SCB, and SCG. For example, the normal state is 1V, the OL state is 3.5V, the SCG state is 0V, and the SCB state is 5V. On the other hand, it should be understood that these figures do not limit the present invention.

Hereinafter, a system protection operation by the turn-off circuit 130 will be described.

When the FET input is at a low level, V_OUT may be in a low level state (0). The output value of the comparator is in a high level state, but since the Input_MCU value is low, the output value of the AND gate becomes a low level state and M2 can be turned on. In this situation, when a High signal comes out from Input_MCU, the AND gate goes into a high level state and turns M2 off, so you can use the RC Filter to delay the input signal. Eventually, V_out becomes a high-level signal first, and the value of the comparator changes to a low-level state. Then, even when a high signal is input from the Input_MCU, the AND output can maintain a low-level state.

In addition, when SCG occurs, the FET input may be in a high level state (1), and V_OUT may be in a low level state (0). The output value of the comparator COM may be in the high level state 1 and the output value of the AND gate may be in the high level state 1. Accordingly, the transistor M2 may be turned off in response to the high level state of the AND gate. At this time, the SCG generation signal may be transmitted to the MCU through an error output terminal (Output_fault). Subsequently, when the FET input changes to the low level state (0), the transistor M2 may be turned on again.

In an embodiment, the turn-off circuit 130 may be substituted for the fault diagnosis circuit 120 through software (SW) processing. The turn-off circuit 130 may protect the system in hardware for functional safety. For example, when the transistor M3 is turned on, the output terminal (Output_ADC_FB) should output 5V, but when it is the SCG, 0V is output. Therefore, when the transistor M3 is turned on, if the output terminal (Output_ADC_FB) is in a low level state, the state of the load 200 is SCG, so that the MCU can turn off the transistor M3.

3 is a diagram showing a relay diagnostic circuit 200 according to another embodiment of the present invention by way of example. Referring to FIG. 3, the relay diagnostic circuit 200 has a difference from the relay diagnostic circuit 100 shown in FIG. 2 in the relay off method when SCG occurs as a result of the load 200 diagnosis. Unlike the relay diagnosis circuit 200 shown in FIG. 3, the relay diagnosis circuit 200 may include transistors M2a and 230 that block relay connection when an SCG occurs.

4 is a diagram illustrating a relay diagnostic circuit 200 according to another embodiment of the present invention. Referring to FIG. 4, the relay diagnostic circuit 300 differs from the relay diagnostic circuits 100 and 200 illustrated in FIGS. 2 and 3 in the load diagnosis method. The relay diagnostic circuit 100 illustrated in FIGS. 2 and 3 may diagnose a fault condition after classifying the difference in voltage value using an ADC pin. On the other hand, the relay diagnostic circuit 300 shown in FIG. 4 may diagnose a fault condition by combining digital values.

5 is a diagram showing a relay diagnostic circuit 400 according to another embodiment of the present invention by way of example. Referring to FIG. 5, the relay diagnostic circuit 400 has different control units 410 compared to that of FIG. 1. The control unit 410 may control both a high side (HS) and a low side (LS) relay.

6 is a flowchart illustrating an exemplary diagnostic method of the relay diagnostic circuit according to an exemplary embodiment of the present invention. 1 to 6, the diagnostic method of the relay diagnostic circuit may proceed as follows.

Relay control may be initiated by the MCU (S110). Before the relay is turned on, a first fault diagnosis may be performed in the diagnostic circuit (S120). As a result of the diagnosis, it may be determined whether it is in a normal state (S130). That is, if it is not the SCB, OL, or SCG state, it can be determined as a normal state.

If it is normal, the relay may be turned on (S140). In the relay On state, the second fault diagnosis is performed in the diagnostic circuit, and it can be determined whether the state is normal (S150). If it is normal as a result of the diagnosis, the relay may perform a normal operation (S160). Thereafter, a fault diagnosis may be performed after the relay is turned off (S170). Thereafter, signal transmission and termination processing may be performed on the MCU (S180). On the other hand, when it is not a normal state in step S130 or S150, information on a related fault condition may be transmitted to the MCU.

The steps and/or operations according to the present invention may occur simultaneously in other embodiments, in different order, or in parallel, or in different embodiments for different epochs, etc., as can be understood by one skilled in the art. You can.

Depending on the embodiment, some or all of the steps and/or actions drive instructions, programs, interactive data structures, clients and/or servers stored in one or more non-transitory computer-readable media. At least some may be implemented or performed using one or more processors. The one or more non-transitory computer-readable media may illustratively be software, firmware, hardware, and/or any combination thereof. In addition, the functionality of the “module” discussed herein may be implemented in software, firmware, hardware, and/or any combination thereof.

One or more non-transitory computer-readable media and/or means for implementing/performing one or more operations/steps/modules of embodiments of the present invention include application-specific integrated circuits (ASICs), standard integrated circuits, Controllers that perform appropriate instructions, including microcontrollers, and/or embedded controllers, field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and the like. Does not.

Meanwhile, the above-described contents of the present invention are only specific embodiments for carrying out the invention. The present invention will include technical ideas that are abstract and conceptual ideas that can be utilized as future technologies, as well as the concrete and practical means available.

100, 200, 300, 400: relay diagnostic circuit
110: control unit
120: diagnostic circuit
130: turn-off circuit
FET: Control transistor
R1 ~ R5: Resistance
D1, D2: diode
M1, M2, M3, M2a: Transistor

Claims (14)

In the method of operation of the relay diagnostic circuit:
Performing a first fault diagnosis for the load in the off state of the relay;
Turning on the relay when the load is in a normal state as a result of the first fault diagnosis;
Performing a second fault diagnosis on the load in the on state of the relay; And
And operating the relay normally when the load is in a normal state as a result of the second fault diagnosis.
After operating the relay normally, turning off the relay; And
Further comprising the step of performing a first fault diagnosis for the load after turning off the relay,
The first fault diagnosis determines whether a short connected to battery (SCB), short connected to ground (SCG), or open load (OL) occurs,
And when the load is overload, SCB fault, SCG fault, or OL fault as a result of the first fault diagnosis, turning off the control transistor that turns the relay on/off. . According to claim 1,
And receiving a signal for initiating control of the relay diagnostic circuit from a micro controller unit (MCU). delete According to claim 1,
The second fault diagnosis method is characterized in that to determine the fault is overloaded control circuit. delete According to claim 1,
And as a result of the first and second failure diagnosis, transmitting a signal related to the micro controller unit (MCU) when the load is not in a normal state. delete According to claim 1,
The control transistor comprises a metal on silicon field effect transistor (MOSFET), BJT, IGBT. A control transistor connected between the battery power terminal and the output terminal and having a gate connected to an input terminal receiving an input signal from a micro controller unit (MCU);
In the turn-off state of the control transistor, a first fault diagnosis is performed on the load connected to the output terminal, and in the turn-on state of the control transistor, a second fault diagnosis is performed on the load, and the first and A diagnostic circuit that transmits a signal or information corresponding to a second failure diagnosis result to the MCU; And
And a turn-off circuit that does not turn on the control transistor according to the second fault diagnosis result,
The turn-off circuit, after operating the relay normally, turns off the relay by turning off the control transistor,
The diagnostic circuit performs the first fault diagnosis on the load after the relay is turned off,
The first fault diagnosis determines whether a short connected to battery (SCB), short connected to ground (SCG), or open load (OL) occurs,
The turn-off circuit is a relay diagnosis circuit that turns off the control transistor when the load is in an overload condition, an SCB failure state, an SCG failure state, or an OL failure state as a result of the first failure diagnosis. The method of claim 9,
The diagnostic circuit is a relay diagnostic circuit comprising an element that protects the MCU pin, an element that forms a diagnostic voltage, and an element that prevents reverse current. The method of claim 10,
The diagnostic circuit is a relay diagnostic circuit, characterized in that for generating the analog or digital values corresponding to the first and second fault diagnosis results, and transmitting the generated analog or digital values to the MCU. The method of claim 9,
The turn-off circuit,
And a second transistor connected between an input terminal receiving the input signal from the MCU and a gate of the control transistor. The method of claim 12,
The turn-off circuit,
A comparator comparing the voltage of the internal power supply and the output terminal; And
And a logic circuit for ANDing the output value of the comparator and the voltage corresponding to the input terminal,
A relay diagnostic circuit characterized in that the second transistor is turned on or off according to a result value in the logic circuit. The method of claim 10,
The turn-off circuit,
A second transistor connected between the output terminal and the load;
A comparator comparing the voltage of the internal power supply and the output terminal; And
And a logic circuit for ANDing the output value of the comparator and the voltage corresponding to the input terminal.

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