KR102163760B1 - Voltage regulator and open load diagnosis method thereof - Google Patents

Abstract

The voltage regulator according to the present invention includes a comparator for comparing a reference voltage and a feedback voltage of a feedback pin, a transistor for outputting an output voltage to an output pin in response to an output of the comparator, a first shunt resistor having one end connected to the output pin, A voltage monitor for performing short-circuit diagnosis or open-load diagnosis by monitoring a second shunt resistor connected between the other end of the first shunt resistor and a ground terminal, and a feedback voltage of the feedback pin connected to the other end of the first shunt resistor. And, when diagnosing the open load, a diagnosis current is provided to the feedback pin.

Description

Voltage regulator and its open load diagnostic method {VOLTAGE REGULATOR AND OPEN LOAD DIAGNOSIS METHOD THEREOF}

The present invention relates to a voltage regulator and a method for diagnosing an open load thereof.

The power precision control device is a key component of an in-vehicle power generator and is designed to maintain a constant output voltage even when the input voltage and output load change. This performs a key function to accurately and consistently maintain the fluctuation of the generator terminal voltage due to the fluctuation of the load speed in the vehicle, and when the electricity used in the car is charged to the battery, it is not possible to start a car or start a radio. It is used as a power source, and a constant voltage is supplied to the load (electrical component) by adjusting irregular fluctuations in voltage so that efficient distribution of power is achieved.

Patent Registration: 10-1651367, Registration Date: August 19, 2016, Title: Programmable Vehicle Regulator Japanese Patent Registration: JP 4925171, Registration Date: February 17, 2012, Title: Semiconductor Integrated Circuit and Its Diagnosis Method.

An object of the present invention is to provide a voltage regulator for performing real-time open load diagnosis and a method for diagnosing open load thereof.

A voltage regulator according to an embodiment of the present invention includes: a comparator for comparing a reference voltage and a feedback voltage of a feedback pin; A transistor configured to output an output voltage to an output pin in response to the output of the comparator; A first shunt resistor having one end connected to the output pin; A second shunt resistor connected between the other end of the first shunt resistor and a ground terminal; And a voltage monitor that performs short circuit diagnosis or open load diagnosis by monitoring a feedback voltage of the feedback pin connected to the other end of the first shunt resistor, and provides a diagnosis current to the feedback pin when diagnosing the open load, The diagnostic current may include: a first diagnostic current provided from a power terminal to the feedback pin; And a second diagnosis current canceling the first diagnosis current while being discharged from the feedback pin to the ground terminal.

In an embodiment, the first diagnostic current is determined such that a rate of change of the output voltage is equal to or less than a predetermined value.

In an embodiment, a first PMOS transistor connected between a power terminal and the feedback pin and having a gate terminal connected to a first node; A second PMOS transistor connected between the power supply terminal and the first node and having a gate terminal connected to the first node; A third PMOS transistor connected between the power supply terminal and the first node and having a gate terminal receiving a pull-up-off signal; And a first diagnostic current source connected to the first node.

In an embodiment, a first NMOS transistor connected between the feedback pin and the ground terminal and having a gate terminal connected to a second node; A second NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to the second node; A third NMOS transistor connected between the second node and the ground terminal and having a gate terminal receiving a pull-down-off signal; And a second diagnostic current source connected to the second node.

In an embodiment, a first PMOS transistor connected between a power terminal and the feedback pin and having a gate terminal connected to a first node; A second PMOS transistor connected between the power supply terminal and the first node and having a gate terminal connected to the first node; A third PMOS transistor connected between the power supply terminal and the first node and having a gate terminal receiving a pull-up-off signal; A fourth PMOS transistor connected between the power supply terminal and a second node and having a gate terminal connected to a third node; A fifth PMOS transistor connected between the power supply terminal and the third node and having a gate terminal connected to the third node; A first NMOS transistor connected between the feedback pin and the ground terminal and having a gate terminal connected to the second node; A second NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to the second node; A third NMOS transistor connected between the second node and the ground terminal and having a gate terminal receiving a pull-down-off signal; A fourth NMOS transistor connected between the first node and the ground terminal and having a gate terminal connected to a fourth node; A fifth NMOS transistor connected between the third node and the ground terminal and having a gate terminal connected to the fourth node; A sixth NMOS transistor connected between the fourth node and the ground terminal and having a gate terminal connected to the fourth node; And a current source connected between the power terminal and the fourth node.

In an embodiment, at least one of the first and second shunt resistors is a variable resistor.

In an embodiment, a first transistor connected to the output pin and turned on when the second diagnostic current falls to the ground terminal; And a first variable shunt resistor connected between the drain terminal of the first transistor and the feedback pin.

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In an embodiment, a second transistor connected to the ground terminal and turned on when the first diagnostic current is supplied to the feedback pin; And a second variable shunt resistor connected between the drain terminal of the second transistor and the feedback pin.

In an embodiment, a first PMOS transistor connected between a power terminal and the feedback pin and having a gate terminal connected to a first node; A second PMOS transistor connected between the power supply terminal and the first node and having a gate terminal connected to the first node; A third PMOS transistor connected between the power supply terminal and the first node and having a gate terminal connected to a pull-up-off terminal; A fourth PMOS transistor connected between the power supply terminal and a second node and having a gate terminal connected to a third node; A fifth PMOS transistor connected between the power supply terminal and the third node and having a gate terminal connected to the third node; A first NMOS transistor connected between the feedback pin and the ground terminal and having a gate terminal connected to the second node; A second NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to the second node; A third NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to a pull-down-off terminal; A fourth NMOS transistor connected between the first node and the ground terminal and having a gate terminal connected to a fourth node; A fifth NMOS transistor connected between the third node and the ground terminal and having a gate terminal connected to the fourth node; A sixth NMOS transistor connected between the fourth node and the ground terminal and having a gate terminal connected to the fourth node; A current source connected between the power terminal and the fourth node; A first transistor connected to the output pin and having a gate terminal connected to the pull-down terminal; A second transistor connected to the ground terminal and having a gate terminal connected to the pull-up-off terminal; A first variable shunt resistor connected between the drain terminal of the first transistor and the feedback pin; And a second variable shunt resistor connected between the feedback pin and the drain terminal of the second transistor.

In an embodiment, one diagnostic pin for canceling the first diagnostic current may be further included.

In an embodiment, a first PMOS transistor connected between a power terminal and the diagnostic pin and having a gate terminal connected to a first node; A second PMOS transistor connected between the power supply terminal and the first node and having a gate terminal connected to the first node; A third PMOS transistor connected between the power supply terminal and a second node and having a gate terminal connected to a fifth node connected to the feedback pin; A fourth PMOS transistor connected between the power supply terminal and a sixth node and having a gate terminal connected to a third node; A fifth PMOS transistor connected between the power supply terminal and the third node and having a gate terminal connected to the third node; A sixth PMOS transistor connected between the power supply terminal and the feedback pin and having a gate terminal connected to the fifth node; A seventh PMOS transistor connected between the power supply terminal and the fifth node and having a gate terminal connected to the fifth node; An eighth PMOS transistor connected between the power supply terminal and the fifth node and having a gate terminal receiving a pull-up-off signal; A first NMOS transistor connected between the diagnostic pin and the ground terminal and having a gate terminal connected to the second node; A second NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to the second node; A third NMOS transistor connected between the first node and the ground terminal and having a gate terminal connected to the sixth node; A fourth NMOS transistor connected between the fifth node and the ground terminal and having a gate terminal connected to a fourth node; A fifth NMOS transistor connected between the third node and the ground terminal and having a gate terminal connected to the fourth node; A sixth NMOS transistor connected between the fourth node and the ground terminal and having a gate terminal connected to the fourth node; A seventh NMOS transistor connected between the feedback pin and the ground terminal and having a gate terminal connected to the sixth node; An eighth NMOS transistor connected between the sixth node and the ground terminal and having a gate terminal connected to the sixth node; A ninth NMOS transistor connected between the sixth node and the ground terminal and having a gate terminal receiving a pull-down-off signal; And a current source connected between the power terminal and the fourth node.

In an embodiment, the diagnostic current includes the first diagnostic current of a pull-up type and the second diagnostic current of a pull-down type, and the second diagnostic current always flows when the open load is diagnosed. It is characterized in that the resistance value is determined.

In an embodiment, a gate driver controlling on/off of the transistor using the output of the comparator may be further included.

An open load diagnosis method of a voltage regulator according to an embodiment of the present invention includes: diagnosing an open load in an off state; And diagnosing an open load in real time in an on state, wherein the real-time diagnosis includes: providing a first diagnosis current to a feedback pin; And providing a second diagnostic current to cancel the first diagnostic current.

In an embodiment, the step of canceling the first diagnosis current may include canceling the first diagnosis current through variable control of a shunt resistance connected between the output pin and the ground terminal.

In an embodiment, the step of canceling the first diagnosis current may include providing the second diagnosis current for canceling the first diagnosis current using a diagnosis pin.

In an embodiment, a value of a shunt resistance connected between an output pin and the feedback pin is determined so that the second diagnostic current always flows.

In an embodiment, the providing of the first diagnosis current may further include providing the first diagnosis current from a power terminal to the feedback pin.

In an embodiment, the canceling of the first diagnostic current may further include subtracting the second diagnostic current from the feedback pin to a ground terminal.

The voltage regulator and its open load diagnosis method according to an exemplary embodiment of the present invention may perform real-time open load diagnosis by implementing various methods to generate a current that cancels the diagnosis current during diagnosis.

In addition, the voltage regulator and its open load diagnosis method according to an exemplary embodiment of the present invention are implemented in a simple configuration such as an external resistor and a diagnosis current source, so that open load can be diagnosed inexpensively and efficiently.

The accompanying drawings are provided to aid understanding of the present embodiment, and provide the embodiments together with a detailed description. However, the technical features of the present embodiment are not limited to a specific drawing, and features disclosed in each drawing may be combined with each other to constitute a new embodiment.
1 is a diagram showing a general linear regulator.
2 is a diagram showing a typical switching regulator.
3 is a diagram showing the occurrence of SCG or SCB due to external factors such as disconnection wiring contact.
4 is a diagram showing that an open load is generated by disconnection of a feedback loop due to poor soldering or the like.
5, 6, and 7 are diagrams for explaining a conventional open rod diagnosis technique.
8 is a diagram illustrating a process of diagnosing an open load in a normal case.
9, 10, and 11 are diagrams showing an effect on output accuracy when performing an OL diagnosis during a regulator operation.
12 is a diagram illustrating a voltage regulator for diagnosing an open load using a microdiagnostic current according to an exemplary embodiment of the present invention.
13 is a diagram illustrating an exemplary embodiment in which the current source of FIG. 12 is implemented as a transistor.
14 is a diagram illustrating an exemplary embodiment of implementing the voltage regulator shown in FIG. 13.
15 is a diagram illustrating a voltage regulator according to an embodiment of the present invention using an external resistance variable control.
16 is a diagram illustrating a voltage regulator according to another embodiment of the present invention using an external resistance variable control.
17 is a diagram illustrating a voltage regulator implemented with a variable resistor and a transistor as an example.
18 is a diagram illustrating an exemplary embodiment of implementing the voltage regulator illustrated in FIG. 17.
19 is a diagram illustrating a voltage regulator implemented by a pair of mutually interlocked current sources instead of a resistor.
FIG. 20 is a diagram illustrating an exemplary embodiment implementing the voltage regulator of FIG. 19.
21 is a diagram illustrating a voltage regulator implemented by a combination of a fine current control method and an external resistance control method.
22 is a diagram illustrating a voltage regulator that cancels a diagnosis current using one external pin.
23 is a diagram illustrating an exemplary current path of a diagnostic current.
24 is a diagram illustrating an exemplary embodiment of a voltage regulator using a current mirror.
25 is a diagram exemplarily showing a voltage regulator having a feedback resistor for always driving a diagnostic current according to an embodiment of the present invention.
FIG. 26 is a diagram illustrating an exemplary embodiment implementing the voltage regulator shown in FIG. 25.
FIG. 27 is a diagram illustrating a simulation result when an OL failure of the voltage regulator shown in FIG. 26 is assumed.
28 is a flowchart illustrating a method of diagnosing an open load of a voltage regulator according to an embodiment of the present invention.

In the following, the contents of the present invention will be described clearly and in detail to the extent that a person of ordinary skill in the technical field of the present invention can easily implement it using the drawings.

Since the present invention can apply various changes and have various forms, specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific form of disclosure, it is to be understood as including all changes, equivalents, or substitutes included in the spirit and scope of the present invention. Terms such as first and second may be used to describe various elements, but the elements should not be limited by the terms.

The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. When a component is referred to as being "connected" or "connected" to another component, it is understood that it may be directly connected or connected to the other component, but other components may exist in the middle Should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle.

Other expressions describing the relationship between components, such as "between" and "just between" or "adjacent to" and "directly adjacent to" should be interpreted as well. The terms used in the present application are used only to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise.

In the present application, terms such as "comprise" or "have" are intended to designate the existence of implemented features, numbers, steps, actions, components, parts, or a combination thereof, and one or more other features or numbers It is to be understood that the possibility of addition or presence of, steps, actions, components, parts, or combinations thereof is not preliminarily excluded. Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning of the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this application. .

The regulator and its diagnosis method according to an exemplary embodiment of the present invention not only perform open load diagnosis in the off state, but also perform real-time open load diagnosis.

A typical programmable voltage regulator includes a feedback controller to control the output voltage.

1 is a diagram showing a general linear regulator. Referring to FIG. 1, the linear regulator 10 includes a feedback control unit 12. The feedback controller 12 distributes the output voltage to the resistors R _S1 and R _S2 connected between the output pin OUT and the ground terminal GND and transfers the resistance to the feedback pin FB. The linear regulator 10 outputs the battery voltage VBAT to the output pin OUT by comparing the reference voltage REF and the voltage of the feedback pin FB.

2 is a diagram showing a typical switching regulator. Referring to FIG. 2, the switching regulator 20 is a feedback controller 22 that distributes the output voltage to the resistors R _S1 and R _S2 by resistively distributing the voltage associated with the output pin OUT and transfers it to the feedback pin FB. Includes.

Recently, automotive semiconductors are strengthening various diagnostic functions. The voltage regulator's feedback control must also be capable of fault diagnosis. In general, fault diagnosis includes SCG (Short Circuit to Ground), SCB (Short Circuit to Battery), and OL (Open Load).

3 is a diagram showing the occurrence of SCG or SCB due to external factors such as disconnection wiring contact. As shown in Fig. 3, the SCB failure determines that the output voltage is high by the feedback control, and turns off the regulator output. Therefore, SCB failure is a relatively safe failure compared to SCG/OL. However, in the case of a SCG/OL failure, since it is determined that the regulator output voltage is insufficient by feedback control and the regulator output voltage is raised to a maximum value, there is a risk of damage to the load module by the high voltage. In particular, in the case of a boost converter among switching regulators, there is a high risk of damage to the high voltage of the load module. To protect the circuit from this risk of damage, a fault diagnosis circuit is required.

In general, SCG/SCB failures are relatively easy to deal with real-time failure diagnosis with a voltage monitoring circuit using a comparator, but real-time diagnosis is difficult in case of an OL failure. 4 is a diagram showing that an open load is generated due to a disconnection of a feedback loop due to poor soldering or the like.

A typical conventional OL diagnosis technique is described with reference to FIGS. 5, 6 and 7. As shown in FIG. 5, it is assumed that the FB pin is opened and the feedback loop is cut, resulting in an OL failure. OL diagnosis is performed before activating the regulator, and as a first process, the switch S ₁ is closed as shown in FIG. 6 to intentionally generate the SCB. Because the FB pin is open, the FB node voltage rises to VDD, and the SCB is sensed by a voltage monitor. Next, as shown in FIG. 7, the switch S ₁ is opened again and the switch S ₂ is closed. Similarly, since the FB pin is open, the FB node voltage drops to ground voltage, and the SCG is sensed by the voltage monitor. As described above, when the SCB and SCG signals are sequentially generated by S ₁ and S ₂ through a series of processes, the signals are processed to detect them as OL.

8 is a diagram illustrating a process of diagnosing an open load in a normal case. As shown in Fig. 8, if there is no fault with the FB pin open, since R _S2 is strongly holding GND, there is no voltage fluctuation in the FB node even if the voltage is push-pulled with S ₁ and S ₂ (however, R _S1 , R _S2 << R _D1 , R _D2 ). For this reason, the S ₁ and S ₂ switch operations are identically generated in SCB and SCG, respectively. Through this, it is determined that OL diagnosis is not abnormal.

However, such a conventional OL diagnosis method can be performed only once before activation of the regulator, and it is not possible to diagnose OL failures occurring during the operation of the regulator in real time. This is because, when applied to real-time diagnosis, the operation of S ₁ and S ₂ affects the voltage distribution values of the feedback resistors R _S1 and R _S2 , reducing the accuracy of the regulator.

9, 10, and 11 are diagrams showing an effect on output accuracy when performing an OL diagnosis during a regulator operation. Assuming that the regulator output V _OUT of FIG. 9 is 3.3V and VDD is 3.3V, the current flowing through the resistor dividers R _S1 and R _S2 is 33 mA. As shown in FIG. 10, when S ₁ is turned on for OL diagnosis, the resistance is synthesized as follows, and an additional current of I _FB =4uA flows. This is because the value of the feedback voltage V _FB should be 1.22V originally, but it increases to 1.37V due to the additional leakage current I _FB .

Therefore, the regulator adjusts the output voltage V _OUT to about 2.95V to reduce the V _FB voltage to 1.22V. This causes output distortion. Eventually, due to the operation of S ₁ for OL diagnosis, the output voltage is changed, and the output voltage accuracy decreases by about 10%. Depending on the application, an error of 10% is unacceptable because the output voltage accuracy is less than 3% and most of it is 5%. As shown in Fig. 11, even when S2 is operated for OL diagnosis, V _FB Is distorted to 1.13V, and as a result, the output voltage V _OUT changes to about 3.55V, resulting in an output voltage error of about 7.5%.

Meanwhile, below, a voltage regulator capable of real-time OL diagnosis will be described. The voltage regulator according to an embodiment of the present invention diagnoses OL by using a microdiagnostic current within an allowable limit of output voltage accuracy, or by canceling the diagnosis current through variable external resistance control, or diagnoses using one external pin. OL can be diagnosed by supplying a current for canceling current, or by enabling the diagnostic current to be driven through an external resistor design.

First, OL diagnosis using microdiagnostic current

12 is a diagram illustrating a voltage regulator for diagnosing an open load using a microdiagnostic current according to an exemplary embodiment of the present invention. Referring to FIG. 12, the voltage regulator 100 may include a comparator COM, a transistor TR, a voltage monitor 110, and a current source 120 130.

The comparator COM may be implemented to compare the reference voltage REF_REG and the feedback voltage. Here, the feedback voltage may be the voltage of the feedback pin FB.

The transistor TR may be implemented to output the battery voltage VBAT to the output pin OUT in response to the output of the comparator COM. The voltage of the output pin OUT may be divided by the first shunt resistor R _S1 and the second shunt resistor R _S2 . The first end of the shunt resistor (R _S1) is connected to the output pin (OUT), the other end of the first shunt resistor (R _S1) may be connected to the feedback pin (FB). One end of the second shunt resistor R _S2 may be connected to the feedback pin FB, and the other end of the second shunt resistor R _S2 may be connected to the ground terminal GND.

The voltage monitor 110 may be implemented to receive a feedback voltage of the feedback pin FB and monitor SCG/SCB/OL.

In an embodiment, the voltage regulator 100 may be implemented to diagnose OL using a minute current of 1 μA or less so as not to deviate from the rated output voltage range. The effect of current IS1 on the output voltage is as follows.

Therefore, the output voltage change rate A is as shown in the following equation.

Therefore, if the diagnostic currents I _S1 and I _S2 are used below 1uA, the output voltage accuracy can be satisfied with 3%. For example, when a diagnostic current of 100nA is used, the rate of change of the output voltage is 0.3%. FIG. 13 is a diagram illustrating an exemplary embodiment in which the current sources 120 and 130 of FIG. 12 are implemented as transistors. As shown in FIG. 13, the current sources 120 and 130; I _S1 and I _S2 may be implemented using a metal oxide semiconductor filed effect transistor (MOSFET). If implemented as a resistor to make a minute current of several hundred nA units, a large resistance of several MΩ units is required. This can be disadvantageous in terms of cost to implement in a semiconductor process. As shown in FIG. 13, it is advantageous to supply a diagnostic current by generating a reference current using a reference voltage REF_REG and generating a minute current using a current mirror.

14 is a diagram illustrating an exemplary embodiment of implementing the voltage regulator shown in FIG. 13. Referring to FIG. 14, the voltage regulator 100 includes PMOS (p-channel MOS) transistors PM1, PM2, PM3, PM4, and PM5, and NMOS (n-channel MOS) transistors NM1. , NM2, NM3, NM4, NM5, NM6), and a current source (I _DC ).

The first PMOS transistor PM1 may be connected between the power terminal VINT and the feedback pin FB. The second and third PMOS transistors PM2 and PM3 may be connected between the power terminal VINT and the first node N1. Here, the first node N1 may be connected to gate terminals of the first and second PMOS transistors PM1 and PM2. The gate terminal of the third PMOS transistor PM2 may receive a pull-up-off (PU_OFF) signal.

The fourth PMOS transistor PM4 may be connected between the power terminal VINT and the second node N2. The fifth PMOS transistor PM5 may be connected between the power terminal VINT and the third node N3. Gate terminals of the fourth and fifth PMOS transistors PM4 and PM5 may be connected to the third node N3.

The first NMOS transistor NM1 may be connected between the feedback pin FB and the ground terminal GND. The second and third NMOS transistors NM2 and NM3 may be connected between the second node N2 and the ground terminal GND. Gate terminals of the first and second NMOS transistors NM1 and NM2 may be connected to the second node N2. The gate terminal of the third NMOS transistor NM3 may receive a pull-down (PD_OFF) signal.

The fourth NMOS transistor NM4 may be connected between the first node N1 and the ground terminal GND. The gate terminal of the fourth NMOS transistor NM4 may be connected to the fourth node N4. The fifth and sixth NMOS transistors NM5 and NM6 may be connected between the fourth node N4 and the ground terminal GND. Gate terminals of the fifth and sixth NMOS transistors NM5 and NM6 may be connected to the fourth node N4.

The current source I _DC may be connected between the power terminal VINT and the fourth node N4.

Meanwhile, the diagnostic current value may be calculated using Equations 7 to 12. As the simulation result estimated at 0.2%, it hardly affects the output voltage.

Second, OL diagnosis by offsetting the diagnosis current through variable control of external resistance

In the case of using a strong diagnostic current, the voltage regulator according to an embodiment of the present invention can diagnose an open load by offsetting the diagnostic current by changing an external resistance.

15 is a diagram illustrating a voltage regulator according to an embodiment of the present invention using an external resistance variable control. Referring to FIG. 15, the voltage regulator 200 may include a second shunt resistor R _S2 having a variable resistance compared to that shown in FIG. 9.

16 is a diagram illustrating a voltage regulator according to another embodiment of the present invention using an external resistance variable control. Referring to FIG. 16, the voltage regulator 200a may include a first shunt resistor R _S1 having a variable resistance compared to that shown in FIG. 9.

Meanwhile, both the first and second shunt resistors may be implemented as variable resistors.

17 is a diagram illustrating a voltage regulator implemented with a variable resistor and a transistor as an example. The voltage regulator 200b attaches resistors R _VS1 and R _VS2 to be variable, and then drives the M ₁ and M ₂ switches synchronously to the I _S1 and I _S2 operations, so that the R _VS1 and R _VS2 resistances are visible or invisible, and the diagnostic current Can be offset.

Here, the values of RVS1 and RVS2 can be determined as follows.

Assuming that R _S1 =6.3k, R _S2 =3.7k, I _FB =100u, and V _OUT =3.3, R _VS1 is as shown in the following equation.

The second variable resistor R _VS2 can also be calculated with the same approach.

18 is a diagram illustrating an exemplary embodiment of implementing the voltage regulator illustrated in FIG. 17. Referring to FIG. 18, a voltage regulator 200b may be implemented using values of R _{VS1 and} R _VS2 calculated above. The internal configuration of the voltage regulator 200b for providing the diagnostic current may be implemented in the same manner as that shown in FIG. 14.

The pull-down-off terminal PD_OFF may be connected to a gate terminal of the third NMOS transistor NM3 for providing a diagnostic current. In addition, the pull-down off terminal PD_OFF may be connected to the gate terminal of the first transistor M1. The first transistor M1 may be connected between the output pin OUT and the first variable resistor R _VS1 . One end of the first variable resistor R _VS1 may be connected to the drain terminal of the first transistor M1, and the other end of the first variable resistor R _VS1 may be connected to the feedback pin FB. In an embodiment, the first transistor M1 may include a PMOS transistor. The first shunt resistor R _S1 may be connected between the output pin OUT and the feedback pin FB.

The pull-up-off terminal PU_OFF may be connected to the gate terminal of the third PMOS transistor PM3 for providing a diagnostic current. Also, the pull-up off terminal PU_OFF may be connected to the gate terminal of the second transistor M2. The second transistor M2 may be connected between the second variable resistor R _VS2 and the ground terminal GND. One end of the second variable resistor R _VS2 may be connected to the feedback pin FB, and the other end of the second variable resistor R _VS2 may be connected to a drain terminal of the second transistor M2. In an embodiment, the second transistor M2 may include an NMOS transistor. The second shunt resistor R _S2 may be connected between the feedback pin FB and the ground terminal GND.

Before the application of the present invention, the output voltage VOUT changes significantly, but after application, it can be seen that there is almost no change in the output voltage even during diagnosis.

On the other hand, the external resistance can be replaced by a pair of mutually interlocked current sources.

19 is a diagram illustrating a voltage regulator implemented by a pair of mutually interlocked current sources instead of a resistor. Referring to FIG. 19, the voltage regulator 200c may be implemented to cancel a diagnosis current using a pair of current sources I _C1 and I _C2 interlocked with each other instead of a resistor. Through this, the resistance of R _VS1 and R _VS2 can be reduced. A bias voltage for driving M ₁ and M ₂ in VBIAS_M1 and VBIAS_M2 can be provided.

20 is a diagram illustrating an exemplary embodiment of implementing the voltage regulator 200c of FIG. 19. Referring to FIG. 19, a first transistor M1 and a first shunt resistor R _S1 may be connected between an output pin OUT and a feedback pin FB. The gate terminal of the first transistor M1 may be connected to the first bias terminal VBIAS_M1.

The second transistor M2 and the second shunt resistor R _S2 may be connected between the feedback pin FB and the ground terminal GND. The gate terminal of the second transistor M2 may be connected to the second bias terminal VBIAS_M2.

Meanwhile, the voltage regulator according to an embodiment of the present invention may be implemented in combination with a micro current control method and an external resistance control method.

21 is a diagram illustrating a voltage regulator implemented by a combination of a fine current control method and an external resistance control method. Referring to FIG. 21, the voltage regulator 200d is diagnosed as a microcurrent in normal times, and when a strong diagnostic current is needed, the diagnostic current is enhanced through the PW_U and PW_D control signals, and the external resistance is controlled to cancel it. Do.

Third, supply current for canceling diagnosis current using one external pin

In the case of canceling the above-described diagnostic current, two external pins (PU_OFF and PN_OFF) were used. As semiconductor products with more functions such as functional safety, most of the semiconductor packages are in the case of pin-oriented packages rather than die-size-oriented. Therefore, reducing the number of pins helps to reduce cost.

22 is a diagram illustrating a voltage regulator that cancels a diagnosis current using one external pin. Referring to FIG. 22, the voltage regulator 300 may include a diagnosis pin DIAG for canceling a diagnosis current when performing OL diagnosis. The voltage regulator 300 of the present invention is advantageous in cost reduction because additional external elements such as resistors or transistors are not required.

As shown in Fig. 22, the first switch (S ₁ ) is turned on, the second switch (S ₂ ) is turned off, the third switch (S ₃ ) is turned off, and the fourth switch (S ₄ ) is turned on. At this time, the first diagnostic current I _S1 may flow to the ground terminal GND through the feedback pin FB and the diagnostic pin DIAG.

23 is a diagram illustrating a current path of the second diagnostic current I _S2 by way of example. Referring to FIG. 23, when the first switch (S ₁ ) is turned off, the second switch (S ₂ ) is turned on, the third switch (S ₃ ) is turned on, and the fourth switch (S ₄ ) is turned off, The second diagnostic current I _S2 may flow from the power terminal VDD to the ground terminal GND through the feedback pin FB and the diagnostic pin DIAG.

24 is a diagram illustrating an exemplary embodiment of a voltage regulator 300 using a current mirror. Referring to FIG. 24, the voltage regulator 300 may include PMOS transistors PM1 to PM8 and NMOS transistors NM1 to NM9.

The first PMOS transistor PM1 may be connected between the power terminal VINT and the feedback pin FB. The second PMOS transistor PM2 may be connected between the power terminal VINT and the first node N1. Gate terminals of the first and second PMOS transistors PM1 and PM2 may be connected to the first node N1. The third PMOS transistor PM3 may be connected between the power terminal VINT and the second node N2. The gate terminal of the third PMOS transistor PM3 may be connected to the fifth node N5. The fourth PMOS transistor PM4 may be connected between the power terminal VINT and the sixth node N6. The fifth PMOS transistor PM5 may be connected between the power terminal VINT and the third node N3. Gate terminals of the fourth and fifth PMOS transistors PM4 and PM5 may be connected to the third node N3.

The sixth, seventh, and eighth PMOS transistors PM6, PM7, and PM8 may be connected between the power terminal VINT and the fifth node N5. Gate terminals of the sixth and seventh PMOS transistors PM6 and PM7 may be connected to the fifth node N5. The gate terminal of the eighth PMOS transistor PM8 may receive a pull-up-off (PU_OFF) signal.

The first NMOS transistor NM1 may be connected between the diagnostic pin DIAG and the ground terminal GND. The second NMOS transistor NM2 may be connected between the second node N2 and the ground terminal GND. Gates of the first and second NMOS transistors NM1 and NM2 may be connected to the second node N2. The third NMOS transistor NM3 may be connected between the first node N1 and the ground terminal GND. The gate terminal of the third NMOS transistor NM3 may be connected to the sixth node N6. The fourth NMOS transistor NM4 may be connected between the fifth node N5 and the ground terminal GND. The gate terminal of the fourth NMOS transistor NM4 may be connected to the fourth node N4. The fifth and sixth NMOS transistors NM5 and NM6 may be connected between the fourth node N4 and the ground terminal GND. Gates of the fifth and sixth NMOS transistors NM5 and NM6 may be connected to the fourth node N4.

The seventh, eighth, and ninth NMOS transistors NM7, NM8, and NM9 may be connected between the sixth node N6 and the ground terminal GND. Gate terminals of the seventh and eighth NMOS transistors NM7 and NM8 may be connected to the sixth node N6. The gate terminal of the ninth NMOS transistor NM9 may receive a pull-down (PD_OFF) signal.

As shown in FIG. 24, the voltage regulator 300 may supply a current for canceling a diagnosis current through an external pin DIAG. The voltage regulator 300 can be easily implemented using a current mirror. As PU_OFF and PD_OFF are driven for OL diagnosis, the output voltage (VOUT) hardly changes even when the diagnosis current flows.

Fourth, external resistance design to be able to drive diagnostic current at all times

25 is a diagram exemplarily showing a voltage regulator having a feedback resistor for always driving a diagnostic current according to an embodiment of the present invention. Referring to FIG. 25, the voltage regulator 400 may appropriately select a resistance value of the first shunt resistor RS1. When designing the feedback resistor, the resistance value of R _S1 may be designed by reflecting the second diagnostic current I _S2 . During normal voltage regulator operation, even if I _S2 diagnostic current continues to flow, the feedback voltage is not affected. This method does not require a separate external pin to cancel the diagnostic current even when using a strong diagnostic current.

The diagnosis procedure of the voltage regulator 400 according to an embodiment of the present invention may be performed as follows. The voltage regulator 400 may be changed from an off state to an on state. At this time, as the second switch S ₂ is turned on at the same time, the diagnosis current I _S2 continuously flows. When designing the resistance value of the first shunt resistor R _S1 , the voltage regulator 400 can operate normally because it is designed in consideration of the current I _S2 . If an OL failure occurs (ex. FB pin soldering off), I _S2 pulls down the feedback pin (FB), so that the SCG flag can be generated.

After the second switch S ₂ is turned off, the first switch S ₁ may be turned on. At this time, the node voltage of the feedback pin FB is pulled up by the diagnosis current I _S1 , thereby generating an SCB flag.

Since the diagnostic flag of the present invention is dependent on the operation of the diagnostic currents I _S1 and I _S2 , it can be diagnosed as an OL fault through signal processing.

Meanwhile, the always-operating diagnostic current shown in FIG. 25 was the second diagnostic current I _S2 . However, it should be understood that the present invention is not limited thereto. In the present invention, one of I _S1 or I _S2 may be selected as the diagnostic current that is always operating. In the following, for convenience of explanation, it is assumed that I _S2 , which is a pull-down type current, is a diagnostic current that always operates.

When I _S2 is used as the constant diagnostic current, the value of R _S1 can be calculated as follows. The sum of feedback resistance R _S is based on 10kΩ. REF_REG = V _FB = 1.22 V is a reference.

FIG. 26 is a diagram illustrating an exemplary embodiment implementing the voltage regulator 400 shown in FIG. 25. Referring to FIG. 26, the voltage regulator 400 may include a first shunt resistor R _S1 to always flow a pull-down type diagnostic current in the internal configuration of the voltage regulator 100 shown in FIG. 14.

FIG. 27 is a diagram illustrating a simulation result when an OL failure of the voltage regulator 400 illustrated in FIG. 26 is assumed. Referring to FIG. 27, as a result of the simulation, by recognizing the SCG and SCB of the FB node in the processes ② to ④, OL can be diagnosed using the change in the state of the FB node according to I _S1 and I _S2 .

Conventional voltage regulators can diagnose OL only in the off state. On the other hand, the voltage regulator according to an embodiment of the present invention can perform real-time OL diagnosis. The voltage regulator of the present invention can be implemented in various ways to enable real-time OL diagnosis.

28 is a flowchart illustrating a method of diagnosing an open load of a voltage regulator according to an embodiment of the present invention. 12 to 28, a method for diagnosing an open load of a voltage regulator may proceed as follows.

Open load diagnosis may be performed in the off state (S110). In the on state, open load diagnosis may be performed in real time (S110). Real-time open load diagnosis may include providing a diagnosis current to the feedback pin and canceling the diagnosis current. Here, the real-time open load diagnosis operation may be implemented in various ways, as described in FIGS. 12 to 27. For example, the real-time open load diagnosis operation is performed by diagnosing OL by using a micro-diagnosis current within the allowable limit of output voltage accuracy, or by offsetting the diagnosis current through external resistance variable control, or diagnosing current by using an external pin. OL can be diagnosed by supplying a canceling current, or OL can be diagnosed by enabling the diagnosis current to be driven through an external resistor design.

The steps and/or actions according to the invention may occur simultaneously in different embodiments in different orders, or in parallel, or in different embodiments for different epochs, etc., as will be appreciated by those skilled in the art. I can.

Depending on the embodiment, some or all of the steps and/or actions drive an instruction, program, interactive data structure, client and/or server stored on one or more non-transitory computer-readable media. At least some may be implemented or performed using one or more processors. The one or more non-transitory computer-readable media may be illustratively software, firmware, hardware, and/or any combination thereof. In addition, the functions of the "module" discussed herein may be implemented in software, firmware, hardware, and/or any combination thereof.

One or more non-transitory computer-readable media and/or means for implementing/performing one or more operations/steps/modules of embodiments of the present invention include application-specific integrated circuits (ASICs), standard integrated circuits, Controllers that perform appropriate instructions, including microcontrollers, and/or embedded controllers, field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and the like, but are not limited thereto. Does not.

Meanwhile, the present invention is not limited to a voltage regulator, but can be applied to any place requiring real-time OL diagnosis, such as a high-side (HS) switch, a low-side (LS) switch, and an actuator driver. The present invention can implement real-time OL diagnosis at an efficient cost.

On the other hand, the contents of the present invention described above are only specific examples for carrying out the invention. The present invention will include not only specific and practically usable means itself, but also technical ideas that are abstract and conceptual ideas that can be utilized as future technologies.

100, 200, 300, 400: voltage regulator
110, 210, 310, 410: voltage monitor
COM: comparator
TR: transistor
OUT: output pin
FB: Feedback pin
DIAG: diagnostic pin
R _S1 : first shunt resistor
R _S2 : second shunt resistor
R _VS1 : first variable shunt resistor
R _VS2 : 2nd variable shunt resistor
I ₁ : first diagnostic current
I ₂ : 2nd diagnostic current

Claims (20)

A comparator for comparing the reference voltage and the feedback voltage of the feedback pin;
A transistor configured to output an output voltage to an output pin in response to the output of the comparator;
A first shunt resistor having one end connected to the output pin;
A second shunt resistor connected between the other end of the first shunt resistor and a ground terminal; And
A voltage monitor for performing short-circuit diagnosis or open-load diagnosis by monitoring a feedback voltage of the feedback pin connected to the other end of the first shunt resistor,
When diagnosing the open load, a diagnosis current is provided to the feedback pin,
The diagnostic current is,
A first diagnostic current provided from a power terminal to the feedback pin; And
And a second diagnostic current to cancel the first diagnostic current while being discharged from the feedback pin to the ground terminal. The method of claim 1,
The first diagnostic current is a voltage regulator, characterized in that the rate of change of the output voltage is determined to be less than a predetermined value. The method of claim 1,
A first PMOS transistor connected between a power supply terminal and the feedback pin and having a gate terminal connected to a first node;
A second PMOS transistor connected between the power supply terminal and the first node and having a gate terminal connected to the first node;
A third PMOS transistor connected between the power supply terminal and the first node and having a gate terminal receiving a pull-up-off signal; And
A voltage regulator further comprising a first diagnostic current source connected to the first node. The method of claim 1,
A first NMOS transistor connected between the feedback pin and the ground terminal and having a gate terminal connected to a second node;
A second NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to the second node;
A third NMOS transistor connected between the second node and the ground terminal and having a gate terminal receiving a pull-down-off signal; And
A voltage regulator further comprising a second diagnostic current source connected to the second node. The method of claim 1,
A first PMOS transistor connected between a power supply terminal and the feedback pin and having a gate terminal connected to a first node;
A second PMOS transistor connected between the power supply terminal and the first node and having a gate terminal connected to the first node;
A third PMOS transistor connected between the power supply terminal and the first node and having a gate terminal receiving a pull-up-off signal;
A fourth PMOS transistor connected between the power supply terminal and a second node and having a gate terminal connected to a third node;
A fifth PMOS transistor connected between the power supply terminal and the third node and having a gate terminal connected to the third node;
A first NMOS transistor connected between the feedback pin and the ground terminal and having a gate terminal connected to the second node;
A second NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to the second node;
A third NMOS transistor connected between the second node and the ground terminal and having a gate terminal receiving a pull-down-off signal;
A fourth NMOS transistor connected between the first node and the ground terminal and having a gate terminal connected to a fourth node;
A fifth NMOS transistor connected between the third node and the ground terminal and having a gate terminal connected to the fourth node;
A sixth NMOS transistor connected between the fourth node and the ground terminal and having a gate terminal connected to the fourth node; And
A voltage regulator further comprising a current source connected between the power terminal and the fourth node. The method of claim 1,
At least one of the first and second shunt resistors is a variable resistor. delete The method of claim 1,
A first transistor connected to the output pin and turned on when the second diagnostic current falls to the ground terminal; And
A voltage regulator further comprising a first variable shunt resistor connected between the drain terminal of the first transistor and the feedback pin. The method of claim 1,
A second transistor connected to the ground terminal and turned on when the first diagnostic current is supplied to the feedback pin; And
A voltage regulator further comprising a second variable shunt resistor connected between the drain terminal of the second transistor and the feedback pin. The method of claim 1,
A first PMOS transistor connected between a power supply terminal and the feedback pin and having a gate terminal connected to a first node;
A second PMOS transistor connected between the power supply terminal and the first node and having a gate terminal connected to the first node;
A third PMOS transistor connected between the power supply terminal and the first node and having a gate terminal connected to a pull-up-off terminal;
A fourth PMOS transistor connected between the power supply terminal and a second node and having a gate terminal connected to a third node;
A fifth PMOS transistor connected between the power supply terminal and the third node and having a gate terminal connected to the third node;
A first NMOS transistor connected between the feedback pin and the ground terminal and having a gate terminal connected to the second node;
A second NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to the second node;
A third NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to a pull-down-off terminal;
A fourth NMOS transistor connected between the first node and the ground terminal and having a gate terminal connected to a fourth node;
A fifth NMOS transistor connected between the third node and the ground terminal and having a gate terminal connected to the fourth node;
A sixth NMOS transistor connected between the fourth node and the ground terminal and having a gate terminal connected to the fourth node;
A current source connected between the power terminal and the fourth node;
A first transistor connected to the output pin and having a gate terminal connected to the pull-down terminal;
A second transistor connected to the ground terminal and having a gate terminal connected to the pull-up-off terminal;
A first variable shunt resistor connected between the drain terminal of the first transistor and the feedback pin; And
A voltage regulator further comprising a second variable shunt resistor connected between the feedback pin and the drain terminal of the second transistor. The method of claim 1,
The voltage regulator further comprises one diagnostic pin for canceling the first diagnostic current. The method of claim 11,
A first PMOS transistor connected between a power supply terminal and the diagnostic pin and having a gate terminal connected to a first node;
A second PMOS transistor connected between the power supply terminal and the first node and having a gate terminal connected to the first node;
A third PMOS transistor connected between the power supply terminal and a second node and having a gate terminal connected to a fifth node connected to the feedback pin;
A fourth PMOS transistor connected between the power supply terminal and a sixth node and having a gate terminal connected to a third node;
A fifth PMOS transistor connected between the power supply terminal and the third node and having a gate terminal connected to the third node;
A sixth PMOS transistor connected between the power supply terminal and the feedback pin and having a gate terminal connected to the fifth node;
A seventh PMOS transistor connected between the power supply terminal and the fifth node and having a gate terminal connected to the fifth node;
An eighth PMOS transistor connected between the power supply terminal and the fifth node and having a gate terminal receiving a pull-up-off signal;
A first NMOS transistor connected between the diagnostic pin and the ground terminal and having a gate terminal connected to the second node;
A second NMOS transistor connected between the second node and the ground terminal and having a gate terminal connected to the second node;
A third NMOS transistor connected between the first node and the ground terminal and having a gate terminal connected to the sixth node;
A fourth NMOS transistor connected between the fifth node and the ground terminal and having a gate terminal connected to a fourth node;
A fifth NMOS transistor connected between the third node and the ground terminal and having a gate terminal connected to the fourth node;
A sixth NMOS transistor connected between the fourth node and the ground terminal and having a gate terminal connected to the fourth node;
A seventh NMOS transistor connected between the feedback pin and the ground terminal and having a gate terminal connected to the sixth node;
An eighth NMOS transistor connected between the sixth node and the ground terminal and having a gate terminal connected to the sixth node;
A ninth NMOS transistor connected between the sixth node and the ground terminal and having a gate terminal receiving a pull-down-off signal; And
A voltage regulator further comprising a current source connected between the power terminal and the fourth node. The method of claim 1,
The diagnostic current includes the first diagnostic current of a pull-up type and the second diagnostic current of a pull-down type,
And a resistance value of the first shunt resistor is determined so that the second diagnostic current always flows during the open load diagnosis. The method of claim 1,
A voltage regulator further comprising a gate driver for controlling on/off of the transistor using the output of the comparator. In the voltage regulator open load diagnostic method:
Diagnosing an open load in an off state; And
In the on state, including the step of real-time diagnosis of open load,
The real-time diagnosis step,
Providing a first diagnostic current to the feedback pin; And
Providing a second diagnostic current to cancel the first diagnostic current. The method of claim 15,
The step of canceling the first diagnostic current,
And canceling the first diagnostic current through variable control of a shunt resistance connected between an output pin and a ground terminal. The method of claim 15,
The step of canceling the first diagnostic current,
And providing the second diagnostic current canceling the first diagnostic current using a diagnostic pin. The method of claim 15,
The method of claim 1, wherein a value of a shunt resistor connected between the output pin and the feedback pin is determined so that the second diagnostic current always flows. The method of claim 15,
Providing the first diagnostic current,
The method further comprising providing the first diagnostic current from a power terminal to the feedback pin. The method of claim 15,
The step of canceling the first diagnostic current,
And subtracting the second diagnostic current from the feedback pin to a ground terminal.

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