KR20200024419A - Neuromorphic device using 3d crossbar memory - Google Patents

Abstract

The present invention relates to a neuromorphic device using a 3D crossbar memory structure, which is capable of implementing various kinds of artificial neural network structures. According to one embodiment of the present invention, the neuromorphic device comprises: a memory device having a 3D crossbar memory structure and formed by sequentially connecting a plurality of memory layers; and a control unit controlling the operation of the memory device, storing weight data in an n^th memory layer (n is a natural number), applying input data to the n^th memory layer to output an operation result of the input data and the weight data as output data, and inputting the corresponding output data to an (n+1)^th memory layer adjacent to the n^th memory layer as input data. Each memory layer comprises: a plurality of wordlines to which the input data are applied; and connection bitlines which are coupled to each word line with a resistive material layer interposed therebetween and outputting the output data, wherein the weight data is stored in the resistive material layer.

Description

Neuromorphic device using three-dimensional crossbar memory structure {NEUROMORPHIC DEVICE USING 3D CROSSBAR MEMORY}

The present invention relates to a neuromorphic device using a three-dimensional crossbar memory structure.

Recently, as interest in artificial neural networks increases, studies on neuromorphic devices that implement the hardware have been actively conducted.

Neuromorphic devices mimic the structures of neurons and synapses that make up the nervous system of the living body, and generally have a structure of pre neurons located before synapses, synapses, and post neurons located after synapses. In the case of a typical neuromorphic device, an input part, a synapse array, and an output part are provided. The input part is a pre-neuron, the output part is a post-neuron, and the synapse array is a synapse.

However, the neuromorphic device known in the art has a fixed structure in hardware, and thus cannot properly adjust the artificial neural networks of various structures that have been recently studied. In addition, the learning algorithm also has a structure in which it is difficult for a user to select and apply a representative learning algorithm and an autonomous learning algorithm.

Accordingly, in the present invention, it is possible to select a forward artificial neural network or a cyclic artificial neural network for a memory device that simulates a synaptic array, and a new neuromorphic device for selecting a self-learning algorithm and a supervised learning algorithm. To provide.

Republic of Korea Patent Publication No. 10-2017-0080441 (Neuromorphic device including gating lines having different widths)

SUMMARY OF THE INVENTION The present invention solves the problems of the prior art described above, and some embodiments of the present invention aim to provide a neuromorphic device using a three-dimensional crossbar memory structure.

As a technical means for achieving the above-described technical problem, a neuromorphic device using a three-dimensional crossbar memory structure according to an aspect of the present invention has a three-dimensional crossbar memory structure, a memory consisting of a plurality of memory layers are sequentially connected to each other Control operations of the device and the memory device, store weight data in an n-th memory layer, and apply input data to the n-th memory layer (n is a natural number) to calculate a result of calculating the input data and the weight data. And a control unit for outputting the output data as input data of the n + 1th memory layer adjacent to the nth memory layer. In this case, each memory layer includes a plurality of word lines to which input data is applied, and connection bit lines coupled to each of the word lines and the resistive material layer therebetween and outputting output data, wherein the bit lines are connected to the resistive material layer. The weight data is stored.

According to the above-described problem solving means of the present invention, it is possible to implement various kinds of artificial neural network structure through a neuromorphic device using a three-dimensional crossbar memory structure, it is possible to selectively apply various kinds of learning algorithms based on this.

1 is a block diagram illustrating a neuromorphic device according to an exemplary embodiment of the present invention.
2 is a diagram illustrating a synaptic memory device according to an embodiment of the present invention.
3 illustrates a synaptic memory device according to an embodiment of the present invention.
4 is a view showing the structure of a conventional artificial neural network.
5 is a diagram illustrating a structure of an artificial neural network that can be implemented through a neuromorphic device according to an embodiment of the present invention.
6 is a diagram illustrating a structure of an artificial neural network that can be implemented through a neuromorphic device according to an embodiment of the present invention.
7 is a view for explaining a learning algorithm that can be provided through a neuromorphic device according to an embodiment of the present invention.
8 is a diagram illustrating a learning algorithm that may be provided through a neuromorphic device according to an embodiment of the present invention.
9 is a view for explaining a learning algorithm that can be provided through a neuromorphic device according to an embodiment of the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another element in between. . In addition, when a part is said to "include" a certain component, this means that it may further include other components, except to exclude other components unless otherwise stated.

1 is a block diagram illustrating a neuromorphic device according to an exemplary embodiment of the present invention.

As shown, the neuromorphic element includes a memory element 10, a control unit 20, and a voltage supply unit 30.

The memory devices 10 are arranged in a synaptic array form using a resistive memory, and have a structure in which a plurality of memory layers are sequentially connected to each other. Each memory layer includes a plurality of word lines to which input data is applied, and connection word lines coupled to each word line and a resistive material layer therebetween and outputting output data. At this time, the weight data is stored in the resistive material layer. A detailed configuration of the memory device 10 will be described later.

The controller 20 controls the operation of the memory device 10. In particular, the controller 20 stores weight data in an n th memory layer (n is a natural number) and applies input data to output the calculation result of the input data and the weight data. Output as. Then, the output data is input as input data of the n + 1th memory layer adjacent to the nth memory layer.

In addition, the type of the artificial neural network implemented through the memory device 10 and the type of learning algorithm are adjusted to be changed. In addition, the voltage supply setting control signal for supplying the selected artificial neural network is supplied to the voltage supply unit 20. In the present invention, various types of artificial neural network structures and learning algorithms may be set for the memory device 10 to be described later, and the artificial neural network structure and the learning algorithm can be changed through the operation of the controller 20. Do.

To this end, the controller 20 adjusts the memory device 10 to operate in an omnidirectional neural network mode or a cyclic neural network mode according to an artificial neural network selection signal. In addition, the controller 20 adjusts the memory device 10 to operate in a supervised learning mode or an autonomous learning mode through a learning algorithm selection signal. At this time, the artificial neural network selection signal is shown as received from the outside of the control unit 20, but for convenience of description, the control unit 20 according to the conditions set in the control unit 20 artificial neural network selection signal or learning algorithm A selection signal can be generated.

In order to perform such an operation, the controller 20 may include modules such as a memory layer setting unit 22, a memory layer control unit 24, and a memory data management unit 26. The memory layer setting unit 22 sets a unit memory layer including word lines and synaptic structures in the memory device 10 to be described later, and outputs data sequentially to the next memory layer. . In particular, one memory layer may be configured to include word lines coupled to one side of the synaptic structure (the embodiment of FIG. 2), or one memory layer may be configured to include word lines coupled to both sides of the synaptic structure. It may be implemented (the embodiment of Figure 3).

The memory layer controller 24 outputs data sequentially and transmits the data to the next memory layer. In this case, the cyclic neural network structure adjusts the output of the last memory layer to be input to the first memory layer. In addition, an operation of applying input data to each word line through the memory data manager 26 to input input data to each memory layer, or receiving data output from each memory layer through an output bit line, 20 and temporarily store the data, and apply the input data through the word line of the next memory layer.

In addition, the memory layer controller 24 manages a weight value stored in the resistive material layer of each synaptic structure. In the initial operation, the preset weight is stored, and after the learning process, the weight stored in each synaptic structure is changed. The memory layer controller 24 may store a weight value or a target weight value for each memory layer during the initial operation. In addition, the weighting value may be updated according to the application of the learning algorithm. Each weight setting method may be changed according to a learning algorithm, which will be described later.

The memory data manager 26 manages input data to be stored in each memory layer in the memory device 10. The initial input data may be transmitted from the outside of the controller 20. As the input data is input to the memory layer, the output data output from the corresponding memory layer is transmitted to the memory data manager 26 and input to the next memory layer. It is managed as input data. To this end, an operation of storing and managing input data and output data for each memory layer is performed.

In addition, the controller 20 sets the voltage to be supplied to the bit line, the word line, and the selection line so that the memory device 10 operates with the selected artificial neural network.

The voltage supply unit 30 supplies voltages set to bit lines and word lines of the memory device 10, respectively. The voltage supply unit 20 supplies voltages of the power supply voltage Vdd and 0V to the bit lines and the word lines, respectively, or a voltage having a value located therebetween. In addition, according to the structure of the present invention, a voltage is supplied to a selection line that controls the activation of the bit line. At this time, the voltage to be supplied to each bit line and word line is set by the controller 20. Since the specific configuration of the other voltage supply unit 20 is similar to that of the conventional memory device, a detailed description thereof will be omitted.

2 is a diagram illustrating a memory device of a neuromorphic device according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the synaptic structures 210, 220, 230, and 240 and word lines 110, 120, 130, and 140 connected thereto are connected to ends of the synaptic structures 210, 220, 230, and 240. Output bit lines 310, 320, 330, 340 are included.

Each of the synaptic structures 210, 220, 230, and 240 may have connection bit lines 212 extending in a first direction and resistive material layers 214 and 216 stacked along both sides of the connection bit lines 212 along the first direction. ). As such, the synaptic structures are arranged parallel to each other along the second direction (210, 220, 230, 240), the group of synaptic structures arranged in this way is arranged by N lines to form a synaptic structure array.

In this case, the resistive material layers 214 and 216 constitute a general resistive memory device. The resistive material layers 214 and 216 have a high resistance state or a low resistance according to a voltage applied through a word line in contact with the resistive material layers 214 and 216. The state is changed, whereby the weight of each synaptic array constituting the artificial neural network can be determined.

Next, the first word lines 110, 112, and 114 extend in a second direction, and the resistive material layer 214 is stacked on one side of the first synaptic structures 210, 220, 230, and 240. And spaced apart from each other along the first direction. In addition, the second word lines 120, 122, and 124 may extend in a second direction, and the resistive material layer 216 may be stacked on the other side of the first synaptic structures 210, 220, 230, and 240. One side thereof is disposed to be in contact with each other, and spaced apart from each other in parallel with each other along the first direction. As described above, since each word line is sequentially arranged along the vertical direction of the synaptic structures 210, 220, 230, and 240 according to the crossbar memory structure, a cross-point memory having a two-dimensional structure in which a resistive material layer is disposed between individual word lines. The space utilization can be much improved compared to the structure.

The output bit lines 310, 320, 330, and 340 contact the ends of the first synaptic structure 210, 220, 230, and 240, and extend along the third direction. When N groups of synaptic structures form an array, each output bitline contacts the ends of the synaptic structures at the same position with respect to the axis extending in the second direction. That is, the output bit line 310 contacts the ends of the synaptic structures 210 and 280 at the same position with respect to the axis extending in the second direction, and the output bit line 320 is the synaptic structure 220 and 270. In contact with the end of the.

In this case, the first word lines 110, 112, 114, and 116 and the second word lines 120, 122, 124, and 126 function as free neurons, and the output bit lines 310, 320, and 330 It functions as a post neuron.

Meanwhile, a resistive material layer having the same structure as the first synaptic structures 210, 220, 230, and 240, and stacked on one side thereof, is formed on the other side of the second word lines 120, 122, 124, and 126. A plurality of second synaptic structures 250, 260, 270, and 280 disposed to be in contact with each other and disposed in parallel with each other along a second direction may be further included. In addition, the resistive material layer which is formed extending in the second direction and laminated on the other side of the second synaptic structures 250, 260, 270, and 280 and one side thereof is in contact with each other and is parallel to each other along the first direction. The plurality of third word lines 130, 132, 134, and 136 spaced apart from each other may be further included. In this case, the output bit lines 310, 320, 330, and 340 are also in contact with the end of the second synaptic structure 250, 260, 270, and 280, and the third word lines 130, 132, 134, and 136 may be It functions as a free neuron. In addition, a larger synaptic array may be formed through a structure in which word lines are disposed between the groups of synaptic structures.

In such a structure, the weight value of the neuromorphic device may be adjusted according to whether the resistance state of the resistive material layer at the point where the synaptic structures and the word lines contact each other is a high resistance state or a low resistance state.

In addition, the selection lines 410, 420, 430, and 440 extend in a second direction, are arranged to contact either side of the synaptic structures, and are combined in a group of synaptic structures to activate the synaptic structures in groups. Adjust Through such a configuration, the timing of output values output through the output bit lines 310, 320, 330, and 340 in units of synaptic structure groups may be adjusted.

That is, inputs through the first word line 110 and the second word line 120 are output through the first synaptic structure group 210, 220, 230, and 240, and the second word line 120 and the third word are output. An input through the word line 130 may be output through the second synaptic structure group 250, 260, 270, and 280, and the output timing may be adjusted for each synaptic structure group.

To this end, when any one of the selection lines 410, 420, 430, and 440 is turned on by the control logic circuit, the output of the synaptic structure group coupled to the turned on selection line is output through the output bit line.

3 is a diagram illustrating a memory device of a neuromorphic device according to an exemplary embodiment of the present invention.

The overall configuration is the same as the embodiment of FIG. 2, and data input through each word line is different.

That is, in FIG. 2, one unit memory layer includes a group of first word lines 110 to 116, first synaptic structures 210, 220, and 230, and a resistive material layer stacked on one side thereof. And may be specified as a first memory layer. The memory layer may be configured in another unit including the group of second word lines 120 to 126, the first synaptic structures 210, 220, and 230, and a resistive material layer stacked on the other side thereof. It may be specified as a second memory layer.

In contrast, in FIG. 3, the neuromorphic device may be implemented by applying the excitatory signal and the suppressive signal to each word line group. At this time, the excitatory signal and the suppressive signal are inputted to one word line group in time division. For example, the excitation signal and the suppression signal are input to the groups 110 to 116 of the first word lines and the groups 120 to 126 of the second word lines, respectively, and the groups 110 to 116 of one word lines. ), One unit memory layer may be configured based on the group of second word lines 120 to 126 and the first synaptic structures 210, 220, and 230, and may be specified as a first memory layer. The excitation signal and the suppression signal are input to the group of the second word lines 120 and the group of the third word lines 130, respectively, and the second synaptic structures 210, 220, and 230 coupled thereto. ) May be configured as one unit memory layer, and may be specified as a second memory layer. At this time, the excitation signal is input to the groups of second word lines 120 to 126 when the first memory layer is operated, and the suppressive signal is input to the second word lines.

4 is a view showing the structure of a conventional artificial neural network, Figure 5 is a view showing the structure of an artificial neural network that can be implemented through a neuromorphic device according to an embodiment of the present invention, Figure 6 is a view of the present invention 2 is a diagram illustrating a structure of an artificial neural network that can be implemented through a neuromorphic device according to an embodiment.

As shown in FIG. 4, a conventional artificial neural network simulates the structure of neurons and synapses, and has a configuration in which a plurality of layers for processing input data and outputting output data are sequentially connected. The unit memory layers mentioned in the above description of the memory device of FIGS. 2 and 3 correspond to each layer of the artificial neural network.

Meanwhile, in the present invention, the memory device 20 may be adjusted to operate in the forward neural network mode or the cyclic neural network mode through the neural network mode selection signal. As illustrated in FIG. 5, in the omnidirectional neural network mode, each memory layer processes input data to generate output data, and transmits the output data to the next adjacent memory layer. As shown in FIG. 6, in the cyclic neural network mode, each memory layer processes input data to generate output data, and transmits the output data to the next adjacent memory layer. It is input as input data of the first memory layer.

For example, the controller 20 outputs the output of the synaptic structures coupled to the selection line 440 located at the last of the synaptic structures in FIG. 2 through the output bit lines 310, 320, 330, and 340. Received by 20), it is controlled again in the form of input to the word line (110 ~ 116) connected to the synaptic structure coupled to the first selection line 410, to implement a cyclic neural network structure.

7 to 9 are views for explaining a learning algorithm that can be provided through a neuromorphic device according to an embodiment of the present invention.

First, as shown in FIG. 7, an artificial neural network that can be provided through the memory device 10 of the present invention includes a plurality of memory layers sequentially connected to each other. The controller 20 divides each unit memory layer in the memory device 10 through the memory layer setting unit 22 and manages data input / output to each unit memory layer. In particular, the output data of the n th memory layer is transmitted to the controller 20, and then the controller 20 transfers the corresponding data as input data of the n + 1 th memory layer. Accordingly, output data of the n th memory layer is input through the word line of the n + 1 th memory layer through the control unit 20.

8 illustrates a process in which learning is performed according to a supervised learning algorithm.

As shown, for convenience of description, first to fourth memory layers are shown.

The controller 20 classifies and manages each memory layer, and manages input data, weights, and output data for each memory layer.

First, when input data is input to the first memory layer (1), a weight stored in the first memory layer and a calculation result of the input data are output as output data, which is transmitted to the controller 20. The controller 20 inputs output data of the first memory layer as input data of the second memory layer (②). That is, the output data of the first memory layer is transferred to the controller 20 and then input to the second memory layer through the word line of the second memory layer. This procedure is sequentially performed from the first memory layer to the fourth memory layer. Thereafter, the fourth memory layer compares the output data with a target value previously stored in the controller 20 and calculates a change amount of the weight value stored in the corresponding memory layer based on the difference between the values. The changed weight value is programmed in each resistive material layer of the fourth memory layer so that the weight is updated (6, 7). As such, the process of calculating the change amount of the weight value may be performed through a back-propagation algorithm. According to the backpropagation algorithm, the output data output from each memory layer is compared with the output specified by supervised learning, and the weight of each memory layer is updated in proportion to an error corresponding to the difference. At this time, the direction of updating the weight is opposite to the direction in which the output data proceeds. That is, after the weight update is performed in the fourth memory layer, and in the reverse order to the data input procedure, the update of the weight value is performed as described above with respect to the third memory layer, the second memory layer, and the first memory layer. Iii).

By repeating the above steps, the weight of each memory layer can be adjusted to produce a result close to the target value. In addition, through this configuration, it is possible to implement a supervised learning algorithm in which a target value of learning is specified in advance through the memory element.

9 illustrates a process of learning according to an autonomous learning algorithm.

As shown, for convenience of description, first to fourth memory layers are shown.

The controller 20 classifies and manages each memory layer, and manages input data, weights, and output data for each memory layer.

In this case, the same number in the drawing means that each step is synchronized by a clock output at the same timing.

First, when the first input data is input to the first memory layer (①), the weight stored in the first memory layer and the calculation result of the input data are output as output data (②), which is transmitted to the controller 20 and Is transferred to the second memory layer (④). The controller 20 calculates a weight change amount based on the output data of the first memory layer, and updates the weight of the first memory layer by using the weight change amount (③).

The second memory layer inputs output data of the first memory layer as input data, and at this time, second input data is input to the first memory layer (④). The weight stored in the second memory layer and the operation result of the input data are output as output data (5), which is transferred to the control unit 20 and transferred to the third memory layer (7). In this case, output data and data transfer based on the second input data are simultaneously performed in the first memory layer. The controller 20 calculates a weight change amount based on the output data of the second memory layer, and updates the weight of the second memory layer using the weight change amount (⑥).

In this way, input of input data, weight update, and delivery of output data are performed independently in each memory ray. At this time, the weight updating process is performed using Spike-timing-dependent plasticity (STDP). That is, whether the weight increases or decreases is determined according to the state values of the n th memory layer and the n + 1 th memory layer. For example, when the output state value of the nth memory layer and the output state value of the n + 1th memory layer are equal to "0", the weight is maintained, and when the value is equal to "1", the weight is increased, When the output state value changes from "0" to "1" or from "1" to "0", the weight is decreased.

In addition, an embodiment of the present invention may also be implemented in the form of a recording medium including instructions executable by a computer, such as a program module executed by the computer. Computer readable media can be any available media that can be accessed by a computer and includes both volatile and nonvolatile media, removable and non-removable media. In addition, computer readable media may include all computer storage media. Computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data.

The foregoing description of the present invention is intended for illustration, and it will be understood by those skilled in the art that the present invention may be easily modified in other specific forms without changing the technical spirit or essential features of the present invention. will be. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive. For example, each component described as a single type may be implemented in a distributed manner, and similarly, components described as distributed may be implemented in a combined form.

The scope of the present invention is shown by the following claims rather than the above description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

10: memory device
20: control unit
30: voltage supply
110, 120, 130, 140: wordline
210, 220, 230, 240: synaptic structures
310, 320, 330, 340: output bit lines
410, 420, 430, 440: selection line

Claims (8)

In a neuromorphic device using a three-dimensional crossbar memory structure,
A memory device having a three-dimensional crossbar memory structure and having a plurality of memory layers sequentially connected to each other;
The operation of the memory device is controlled, weight data is stored in an n-th memory layer, and input data is applied to the n-th memory layer (n is a natural number), and output results of the calculation of the input data and the weight data are output data. And a control unit for outputting the output data as input data of the n + 1th memory layer adjacent to the nth memory layer,
Each of the memory layers may include a plurality of word lines to which input data is applied, and connection bit lines coupled between the word lines and a resistive material layer therebetween and outputting output data, wherein the weighted values of the resistive material layer are included. Neuromorphic device in which data is stored. The method of claim 1,
The memory device may include first to kth memory layers (k is a natural number greater than n),
The controller controls the memory device to operate in an omnidirectional neural network mode or a cyclic neural network mode through a neural network mode selection signal.
When operating in the omni-directional neural network mode, output data of the n th memory layer is transmitted as input data of the n + 1 th memory layer,
And a neuromorphic device configured to transmit output data of the kth memory layer as input data of the first memory layer when operating in the cyclic neural network mode. The method of claim 1,
The memory device may include first to k th memory layers (k is a natural number greater than n).
And the control unit controls the memory device to operate in a supervised learning mode or an autonomous learning mode through a learning algorithm selection signal. The method of claim 3, wherein
The neuromorphic device performs weight update stored in each memory layer according to a backpropagation algorithm when operating in the supervised learning mode. The method of claim 3, wherein
The neuromorphic device performs weight update on state values of each memory layer by using spike-timing-dependent plasticity (STDP) when operating in the autonomous learning mode. The method of claim 1,
The memory device is
A connection bit line extending in a first direction and a layer of resistive material stacked along the first direction on both sides of each connection bit line, and arranged parallel to each other along a second direction crossing the first direction; A plurality of first synaptic structures,
A plurality of word lines extending in the second direction and disposed to contact the resistive material layer stacked on one side of the synaptic structure, the plurality of word lines spaced apart from each other along the first direction;
A plurality of second electrodes extending in the second direction, disposed to contact the resistive material layer stacked on the other side of the first synaptic structure, and one side thereof, and spaced apart from one another in the first direction; Word Lines,
A plurality of output bit lines in contact with an end of the first synaptic structure and extending along a third direction crossing the first and second directions;
A selection line extending in the second direction and disposed to contact one side of the first synaptic structures, the selection line adjusting an activation state of the first synaptic structures according to voltage application;
Wherein the first word lines and the second word lines function as free neurons, and the output bit lines function as post neurons. The method of claim 6,
The synaptic structures are arranged in a plurality of groups, and includes a plurality of selection lines coupled to the sides of the synaptic structures of each group,
A neuromorphic device in which the activation state of the synaptic structures in contact with the selection line is adjusted based on the voltage applied to the selection line. The method of claim 1,
And a weight value adjusted according to whether the resistance state of the resistive material layer at the point where the synaptic structures and the word lines contact each other is a high resistance state or a low resistance state.

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