KR102114356B1 - Neuromorphic device using 3d crossbar memory - Google Patents

Abstract

In a neuromorphic device using a three-dimensional crossbar memory structure according to an aspect of the present invention, a memory device having a three-dimensional crossbar memory structure and a plurality of memory layers sequentially connected to each other and controlling operation of the memory device, , Storing weight data in the nth memory layer, applying input data to the nth memory layer (n is a natural number), outputting calculation results of the input data and the weight data as output data, and outputting the corresponding output data And a control unit for inputting as input data of an n + 1 memory layer adjacent to the nth memory layer, wherein each memory layer includes a plurality of word lines to which input data is applied, each of the word lines and the resistive material layer. Interleaved and coupled, including connection bit lines for outputting output data, weight data is stored in the resistive material layer.

Description

Neuromorphic device using 3D crossbar memory structure {NEUROMORPHIC DEVICE USING 3D CROSSBAR MEMORY}

The present invention relates to a neuromorphic device using a three-dimensional crossbar memory structure.

Recently, as interest in artificial neural networks has increased, studies on neuromorphic devices embodying them in hardware have been actively conducted.

The neuromorphic device mimics the structures of neurons and synapses that make up the brain's nervous system in a living body, and has a structure of pre neurons, synapses, and post neurons located after synapses. In the case of a general neuromorphic device, an input unit, a synaptic array, and an output unit are formed, and the input unit functions as a pre-neuron and an output unit as a post-neuron, and the synaptic array functions as a synapse.

However, since the neuromorphic device known in the related art has a fixed structure in hardware, it is not possible to properly control the neural network of various structures that have been recently studied. In addition, the learning algorithm also has a structure that is difficult to select and apply supervised learning algorithms and autonomous learning algorithms, which are typically known.

Accordingly, in the present invention, a new neuromorphic device that enables a user to select an omni-directional artificial neural network or a circulating artificial neural network, etc. for a memory device simulating a synaptic array, and also selects an autonomous learning algorithm and a supervised learning algorithm as a learning algorithm. Want to provide.

Korean Patent Publication No. 10-2017-0080441 (Neuromorphic device including gating lines having different widths)

The present invention is to solve the problems of the prior art described above, some embodiments of the present invention is to provide a neuromorphic device using a three-dimensional crossbar memory structure.

As a technical means for achieving the above-described technical problem, a neuromorphic device using a three-dimensional crossbar memory structure according to an aspect of the present invention has a three-dimensional crossbar memory structure, and a plurality of memory layers are sequentially connected to each other to form a memory Control the operation of the device and the memory device, store weight data in the n-th memory layer, apply input data to the n-th memory layer (n is a natural number), and calculate the calculation result of the input data and the weight data. And a control unit that outputs the output data as input data and inputs the output data as input data of an n + 1 memory layer adjacent to the n-th memory layer. At this time, each memory layer includes a plurality of word lines to which input data is applied, each of the word lines and a resistive material layer interposed therebetween, and including connection bit lines for outputting output data. Weight data is stored.

According to the above-described problem solving means of the present invention, various types of artificial neural network structures may be implemented through a neuromorphic device using a 3D crossbar memory structure, and various types of learning algorithms may be selectively applied on the basis of this.

1 is a block diagram illustrating a neuromorphic device according to an embodiment of the present invention.
2 is a view showing a memory device for synapses according to an embodiment of the present invention.
3 is a view showing a memory device for synapses according to an embodiment of the present invention.
4 is a view showing the structure of a typical artificial neural network.
5 is a diagram illustrating the structure of an artificial neural network that can be implemented through a neuromorphic device according to an embodiment of the present invention.
6 is a diagram showing the structure of an artificial neural network that can be implemented through a neuromorphic device according to an embodiment of the present invention.
7 is a view for explaining a learning algorithm that can be provided through a neuromorphic device according to an embodiment of the present invention.
8 is a view for explaining a learning algorithm that can be provided through a neuromorphic device according to an embodiment of the present invention.
9 is a diagram for explaining a learning algorithm that can be provided through a neuromorphic device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains may easily practice. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. In addition, in order to clearly describe the present invention in the drawings, parts irrelevant to the description are omitted, and like reference numerals are assigned to similar parts throughout the specification.

Throughout the specification, when a part is "connected" to another part, this includes not only "directly connected" but also "electrically connected" with another element in between. . Also, when a part “includes” a certain component, this means that other components may be further included, rather than excluding other components, unless otherwise specified.

1 is a block diagram illustrating a neuromorphic device according to an embodiment of the present invention.

As shown, the neuromorphic element includes a memory element 10, a control unit 20 and a voltage supply unit 30.

The memory elements 10 are arranged in a synaptic array form using a resistive memory, and have a structure in which a plurality of memory layers are sequentially connected to each other. In addition, each memory layer includes a plurality of word lines to which input data is applied, coupled with each word line and a layer of resistive material therebetween, and includes connection bit lines for outputting output data. At this time, the weight data is stored in the resistive material layer. The specific configuration of the memory element 10 will be described later.

The control unit 20 controls the operation of the memory element 10, in particular, stores weight data in the nth memory layer (n is a natural number), applies input data, and outputs calculation results of input data and weight data as output data Output as Then, an operation of inputting the corresponding output data as input data of the n + 1 memory layer adjacent to the n-th memory layer is performed.

In addition, the type of the artificial neural network implemented through the memory element 10 and the type of the learning algorithm are adjusted to be changed. In addition, a voltage supply setting control signal for implementing the selected artificial neural network is supplied to the voltage supply unit 20. In the present invention, various types of artificial neural network structures and learning algorithms can be set for the memory device 10 to be described later. Such an artificial neural network structure change and learning algorithm can be changed through the operation of the control unit 20. Do.

To this end, the controller 20 adjusts the memory element 10 to operate in an omni-directional neural network mode or a cyclic neural network mode according to the artificial neural network selection signal. In addition, the control unit 20 adjusts the memory element 10 to operate in a supervised learning mode or an autonomous learning mode through a learning algorithm selection signal. At this time, the artificial neural network selection signal is shown as received from the outside of the control unit 20, but this is for convenience of explanation, and the control unit 20 may select the artificial neural network selection signal or a learning algorithm according to conditions set in the control unit 20. It is possible to generate a selection signal.

To perform this operation, the control unit 20 may include modules such as a memory layer setting unit 22, a memory layer control unit 24, and a memory data management unit 26. The memory layer setting unit 22 sets a unit memory layer including word lines and synaptic structures in the memory element 10 to be described later, and the corresponding memory layer sequentially outputs data to be transferred to the next memory layer. . In particular, to configure one memory layer including word lines coupled to one side of the synaptic structure (the embodiment of FIG. 2), or to configure one memory layer including word lines coupled to both sides of the synaptic structure. It can be implemented (the embodiment of Figure 3).

The memory layer controller 24 allows the memory layers set as described above to sequentially output data and transfer the data to the next memory layer. At this time, in a cyclic neural network structure, the output of the last memory layer is adjusted to be input to the first memory layer. In addition, in order to input data to each memory layer, an operation of applying input data to each word line through the memory data management unit 26 or receiving data output from each memory layer through an output bit line, thereby controlling the controller ( 20), and perform operations for applying input data through the word line of the next memory layer.

In addition, the memory layer control unit 24 manages weight values stored in the resistive material layer of each synaptic structure. In the initial operation, preset weights are stored, and the weights stored in each synaptic structure are changed during a subsequent learning process. The memory layer control unit 24 may store a weight value for each memory layer during initial operation or a target weight value. In addition, an update operation of the weight value may be performed according to the application of the learning algorithm. Each weight setting method may be changed according to the learning algorithm, which will be described later.

The memory data management unit 26 manages input data to be stored for each memory layer in the memory element 10. The initial input data may be transmitted from the outside of the control unit 20, and as the input data is input to the memory layer, output data output from the memory layer is transmitted to the memory data management unit 26 and input to the next memory layer It is managed as input data. To this end, an operation of storing and managing input data and output data for each memory layer is performed.

In addition, the control unit 20 sets the voltage to be supplied to the bit line, word line, and selection line so that the memory element 10 operates as a selected artificial neural network.

The voltage supply unit 30 supplies voltages set to bit lines and word lines of the memory device 10, respectively. The voltage supply unit 20 supplies the voltages of the power supply voltages Vdd and 0V to the bit lines and the word lines, respectively, or supplies voltages having values located therebetween. In addition, a voltage is supplied to a selection line that controls activation of the bit line according to the structure of the present invention. At this time, the voltage to be supplied to each bit line and word line is set by the control unit 20. Since the specific configuration of the other voltage supply unit 20 is similar to that of the conventional memory device, detailed description thereof will be omitted.

2 is a diagram illustrating a memory device of a neuromorphic device according to an embodiment of the present invention.

As shown in FIG. 2, the synaptic structures 210, 220, 230, and 240 and the word lines 110, 120, 130, 140 connected thereto are connected to the ends of the synaptic structures 210, 220, 230, 240. Output bit lines 310, 320, 330, 340 are included.

Each of the synaptic structures 210, 220, 230, and 240 has a connection bit line 212 formed extending in a first direction, and resistive material layers 214 and 216 stacked along both sides of each connection bit line 212 along a first direction. ). As described above, the synaptic structures are arranged next to each other along the second direction (210, 220, 230, 240), and the groups of the synaptic structures arranged in this way are arranged by N lines to form an array of synaptic structures.

At this time, the resistive material layers 214 and 216 constitute a general resistive memory device, and the state of the resistance is high or low depending on the voltage applied through the word line contacted with the resistive material layers 214 and 216. The state is changed, and the weights of the synaptic arrays constituting the artificial neural network can be determined.

Next, the first word lines 110, 112, and 114 are formed to extend in the second direction, and the resistive material layer 214 is stacked on one side of the first synaptic structures 210, 220, 230, and 240. It is disposed to be in contact with, and spaced apart from each other along the first direction. In addition, the second word lines 120, 122, and 124 are formed to extend in the second direction, and the resistive material layer 216 stacked on the other side of the first synaptic structures 210, 220, 230, and 240. The one side is arranged to contact, and is spaced apart from each other along the first direction. As such, since each word line is sequentially arranged along the vertical direction of the synaptic structures 210, 220, 230, and 240 according to the crossbar memory structure, a cross-point memory having a two-dimensional structure in which a resistive material layer is disposed between individual word lines Space utilization can be much improved compared to structure.

The output bit lines 310, 320, 330, and 340 contact the ends of the first synapse structures 210, 220, 230, and 240, and extend along the third direction. When the group of N synaptic structures forms an array, each output bit line contacts the ends of synaptic structures at the same position with respect to the axis extending in the second direction. That is, the output bit lines 310 are in contact with the ends of the synaptic structures 210 and 280 in the same position with respect to the axis extending in the second direction, and the output bit lines 320 are synaptic structures 220 and 270 Is in contact with the end of.

At this time, the first word lines (110, 112, 114, 116) and the second word lines (120, 122, 124, 126) function as free neurons, and the output bit lines (310, 320, 330) It functions as a post neuron.

On the other hand, it has the same structure as the first synaptic structures 210, 220, 230, and 240, and a layer of resistive material stacked on one side thereof is formed on the other side of the second word lines 120, 122, 124, and 126. A plurality of second synaptic structures 250, 260, 270, and 280 disposed to be in contact with each other along the second direction may be further included. In addition, the resistance material layer stacked on the other side of the second synaptic structures 250, 260, 270, and 280 is formed to extend in the second direction and is disposed to contact one side thereof, and is aligned with each other along the first direction. A plurality of third word lines 130, 132, 134, and 136 spaced apart from each other may be further included. At this time, the output bit lines 310, 320, 330, and 340 contact the ends of the second synaptic structures 250, 260, 270, 280, and the third word lines 130, 132, 134, 136 It functions as a free neuron. Further, a larger synaptic array may be formed through a structure in which word lines are respectively disposed between the synaptic structure groups.

In such a structure, the weight value of the neuromorphic device may be adjusted according to whether the resistance state of the resistive material layer at the point where the synaptic structures and the word lines contact each other is a high resistance state or a low resistance state.

In addition, the selection lines 410, 420, 430, and 440 are formed to extend in the second direction, are arranged to contact any one side of the synaptic structures, and are combined in synaptic structure group units to activate the synaptic structures by group. Adjust. Through this configuration, the timing of output values output through the output bit lines 310, 320, 330, and 340 in units of synaptic structure groups may be adjusted.

That is, the input through the first word line 110 and the second word line 120 is output through the first synaptic structure group 210, 220, 230, 240, and the second word line 120 and the third The input through the word line 130 is output through the second synaptic structure groups 250, 260, 270, and 280, and the output timing can be adjusted in units of each synaptic structure group.

To this end, when any one of the selection lines 410, 420, 430, and 440 is turned on by the control logic circuit, the output of the group of synaptic structures coupled to the turned-on selection line is output through the output bit line.

3 is a diagram illustrating a memory device of a neuromorphic device according to an embodiment of the present invention.

The overall configuration is the same as the embodiment of FIG. 2, and data input through each word line is different.

That is, in FIG. 2, one unit memory layer including a group of first word lines 110 to 116 and first synaptic structures 210, 220 and 230 and a layer of a resistive material stacked on one side thereof is configured. And can be specified as the first memory layer. Further, a memory layer of another unit including a group of second word lines 120 to 126 and first synaptic structures 210, 220 and 230 and a resistive material layer stacked on the other side thereof may be configured, It may be specified as a second memory layer.

Alternatively, in FIG. 3, a neuromorphic device may be implemented in a form in which an excitatory signal and an inhibitory signal are applied together for each word line group. At this time, the excitatory signal and the inhibitory signal are temporally separated and input to one word line group. For example, the excitatory signal and the inhibitory signal are input to the groups of the first word lines 110 to 116 and the groups of the second word lines 120 to 126, respectively, and the groups of 1 word lines 110 to 116 ), One unit memory layer may be configured based on the group of second word lines 120 to 126 and the first synaptic structures 210, 220, and 230, and may be specified as the first memory layer. Then, the excitatory signal and the inhibitory signal are input to the group of the second word lines 120 and the group of the third word lines 130, and the second synaptic structures 210, 220, and 230 coupled thereto. ), One unit memory layer may be configured, and may be specified as a second memory layer. At this time, an excitability signal is input to the group of second word lines 120 to 126 when operating as the first memory layer, and an inhibitory signal is input when operating as the second memory layer.

4 is a view showing the structure of a conventional artificial neural network, Figure 5 is a view showing the structure of an artificial neural network that can be implemented through a neuromorphic device according to an embodiment of the present invention, Figure 6 is a view of the present invention This is a diagram showing the structure of an artificial neural network that can be implemented through a neuromorphic device according to an embodiment.

As shown in FIG. 4, a typical artificial neural network has a configuration in which a plurality of layers sequentially simulating the structures of neurons and synapses, processing input data, and outputting output data. The unit memory layers mentioned in the description of the memory elements of FIGS. 2 and 3 correspond to each layer of the artificial neural network.

Meanwhile, in the present invention, the memory device 20 may be controlled to operate in an omni-directional neural network mode or a cyclic neural network mode through a neural network mode selection signal. As illustrated in FIG. 5, in the omni-directional neural network mode, each memory layer processes input data to generate output data, and transmits it to an adjacent next memory layer. And, as illustrated in FIG. 6, in the cyclic neural network mode, each memory layer processes input data to generate output data, and transmits it to an adjacent next memory layer, and the output of the last memory layer is It is input as input data of the first memory layer.

For example, the control unit 20 outputs the outputs of the synaptic structures coupled to the selection line 440 located at the last of the synaptic structures in FIG. 2 through the output bit lines 310, 320, 330, and 340 ( 20) may be received, and control it in the form of inputting it to the word lines 110 to 116 connected to the synaptic structure coupled to the first selection line 410, thereby implementing a circulating neural network structure.

7 to 9 are diagrams for explaining a learning algorithm that can be provided through a neuromorphic device according to an embodiment of the present invention.

First, as illustrated in FIG. 7, an artificial neural network that can be provided through the memory device 10 of the present invention includes a plurality of memory layers sequentially connected to each other. Then, the control unit 20 separates each unit memory layer from the memory element 10 through the memory layer setting unit 22 and manages data input and output to each unit memory layer. In particular, the output data of the nth memory layer is transmitted to the control unit 20, and then the control unit 20 transfers the corresponding data as input data of the n + 1 memory layer. Therefore, the output data of the nth memory layer is input through the word line of the n + 1 memory layer through the control unit 20.

8 shows a process in which learning is performed according to a supervised learning algorithm.

As illustrated, for convenience of description, first to fourth memory layers are illustrated.

The controller 20 classifies and manages each memory layer, and manages input data, weights, and output data for each memory layer.

First, when input data is input to the first memory layer (①), the weights stored in the first memory layer and the calculation result of the input data are output as output data, which is transferred to the control unit 20. The control unit 20 inputs the output data of the first memory layer as input data of the second memory layer (②). That is, after the output data of the first memory layer is transferred to the control unit 20, it is input to the second memory layer through the word line of the second memory layer. This procedure is sequentially performed from the first memory layer to the fourth memory layer. Then, finally, the fourth memory layer compares the output data with the target value previously stored in the controller 20, and calculates a change amount of the weight value stored in the corresponding memory layer based on the difference between the values. Then, the changed weight value is programmed in each resistive material layer of the fourth memory layer so that the weight is updated (⑥, ⑦). The process of calculating the amount of change in the weight value may be performed through a back-propagation algorithm. According to the backpropagation algorithm, the output data output from each memory layer is compared with the output designated by supervised learning, and the weight of each memory layer is updated in proportion to an error corresponding to the difference. At this time, the direction in which the weight is updated is opposite to the direction in which the output data proceeds. That is, after the weight update is performed in the fourth memory layer, and in the reverse order from the data input procedure, the weight value is updated for the third memory layer, the second memory layer, and the first memory layer as described above (⑧ ~ ⑬).

By repeating these steps, it is possible to adjust the weight of each memory layer so that a result close to the target value is produced. In addition, through this configuration, a supervised learning algorithm in which a target value of learning is previously designated may be implemented through a memory element.

9 shows a process in which learning is performed according to an autonomous learning algorithm.

As illustrated, for convenience of description, first to fourth memory layers are illustrated.

The controller 20 classifies and manages each memory layer, and manages input data, weights, and output data for each memory layer.

At this time, the same number in the drawing means that each step is synchronized by a clock output at the same timing.

First, when the first input data is input to the first memory layer (①), the calculation result of the weight and input data stored in the first memory layer is output as the output data (②), which is transmitted to the control unit 20. It is transferred to the second memory layer (④). The control unit 20 calculates a weight change amount based on the output data of the first memory layer, and uses it to update the weight of the first memory layer (③).

Then, the second memory layer inputs the output data of the first memory layer as input data, and at this time, the second input data is input to the first memory layer (④). The calculation result of weight and input data stored in the second memory layer is output as output data (⑤), which is transferred to the control unit 20 and transferred to the third memory layer (⑦). At this time, output data output and data transfer based on the second input data are simultaneously performed in the first memory layer. Then, the control unit 20 calculates a weight change amount based on the output data of the second memory layer, and uses it to update the weight of the second memory layer (⑥).

In this way, input data input, weight update, and transfer of output data are performed independently of each other in each memory ray. At this time, the weight update process is performed using a spike-timing-dependent plasticity (STDP). That is, whether to increase or decrease the weight is determined according to the state values of the nth memory layer and the n + 1th memory layer. For example, if the output state value of the nth memory layer and the output state value of the nth + 1 memory layer are equal to “0”, the weight is maintained, and when equal to “1”, the weight is increased, When the output state value is changed from "0" to "1" or "1" to "0", the weight is decreased.

Also, an embodiment of the present invention may be implemented in the form of a recording medium including instructions executable by a computer, such as program modules, executed by a computer. Computer readable media can be any available media that can be accessed by a computer and includes both volatile and nonvolatile media, removable and non-removable media. Also, the computer-readable medium may include any computer storage medium. Computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data.

The above description of the present invention is for illustration only, and those skilled in the art to which the present invention pertains can understand that the present invention can be easily modified into other specific forms without changing the technical spirit or essential features of the present invention. will be. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. For example, each component described as a single type may be implemented in a distributed manner, and similarly, components described as distributed may be implemented in a combined form.

The scope of the present invention is indicated by the following claims rather than the above detailed description, and it should be interpreted that all changes or modified forms derived from the meaning and scope of the claims and equivalent concepts thereof are included in the scope of the present invention. do.

10: memory element
20: control unit
30: voltage supply
110, 120, 130, 140: word line
210, 220, 230, 240: synaptic structures
310, 320, 330, 340: output bit line
410, 420, 430, 440: selection line

Claims (8)

In a neuromorphic device using a three-dimensional crossbar memory structure,
A memory device having a three-dimensional crossbar memory structure and having a plurality of memory layers sequentially connected to each other, including a first memory layer to a k-th memory layer (k is a natural number greater than n) and
Control the operation of the memory element, store weight data in the nth memory layer, apply input data to the nth memory layer (n is a natural number), and output the calculation result of the input data and the weight data as output data And a control unit that outputs as and inputs the output data as input data of an n + 1 memory layer adjacent to the nth memory layer,
Each of the memory layers includes a plurality of word lines to which input data is applied, coupled with each of the word lines and a layer of resistive material therebetween, and connection bit lines for outputting output data, wherein the weight is applied to the layer of resistive material Data is stored,
The control unit controls the memory device to operate in an omni-directional neural network mode or a cyclic neural network mode through a neural network mode selection signal,
When operating in the omni-directional neural network mode, output data of the n-th memory layer is transmitted as input data of the n + 1 memory layer,
When operating in the cyclic neural network mode, the neuromorphic device is such that output data of the k-th memory layer is transmitted as input data of the first memory layer. delete According to claim 1,
The controller modulates the memory device to operate in a supervised learning mode or an autonomous learning mode through a learning algorithm selection signal. The method of claim 3,
When operating in the supervised learning mode, the neuromorphic device performs a weight update stored in each memory layer according to a backpropagation algorithm. The method of claim 3,
When operating in the self-learning mode, a neuromorphic device that performs weight update on a state value of each memory layer using a spike-timing-dependent plasticity (STDP). According to claim 1,
The memory element
A connection bit line formed extending in a first direction and a layer of resistive materials stacked along the first direction on both sides of each connection bit line, and arranged side by side with each other along a second direction intersecting the first direction A plurality of first synaptic structures,
A plurality of word lines extending in the second direction, disposed to contact the layer of resistive material stacked on one side of the synaptic structure, and spaced apart from each other along the first direction;
A plurality of second extensions extending in the second direction, arranged to contact one side of the layer of the resistive material stacked on the other side of the first synaptic structure, and spaced apart from each other along the first direction Word Lines,
A plurality of output bit lines contacting ends of the first synaptic structure and extending along a third direction intersecting the first direction and the second direction, and
It is formed extending in the second direction, respectively disposed to contact any one side of the first synaptic structures, and includes a selection line for adjusting the activation state of the first synaptic structures according to a voltage applied,
The neuromorphic device wherein the first word lines and the second word lines function as free neurons, and the output bit lines function as post neurons. The method of claim 6,
The synaptic structures are arranged in a plurality of groups, and include a plurality of selection lines coupled to the side surfaces of each group of synaptic structures,
A neuromorphic device in which activation states of synaptic structures contacting the selection line are adjusted based on a voltage applied to the selection line. According to claim 1,
A neuromorphic device whose weight value is adjusted according to whether the resistance state of the resistive material layer is a high resistance state or a low resistance state.

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