KR20200014164A - Apparatus and method for engaging plural memory system with each other to store data - Google Patents

Abstract

A technology of the present invention provides a data processing system including a host processing data in response to a command input from the outside and a plurality of memory systems capable of storing or outputting data in response to a request of the host while interworking with the host. In the data processing system, a first memory system, which is one among the plurality of memory systems, stores metadata for all the plurality of memory systems.

Description

A method and apparatus for interlocking a plurality of memory systems to store data

The present invention relates to a data processing apparatus including a memory system and a memory system, and more particularly, to a method and an apparatus for increasing the efficiency of storing or reading data in a data processing apparatus including a plurality of nonvolatile memory systems. will be.

Recently, the paradigm of the computer environment has been shifted to ubiquitous computing, which enables the use of computer systems anytime and anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, notebook computers, and the like is increasing rapidly. Such portable electronic devices generally use a memory system using a memory device, that is, a data storage device. The data storage device is used as a main memory device or an auxiliary memory device of a portable electronic device.

Unlike a hard disk, a data storage device using a nonvolatile memory device has no mechanical driving part, and thus has excellent stability and durability, and has an advantage of fast access to information and low power consumption. As an example of a memory system having such an advantage, a data storage device may include a universal serial bus (USB) memory device, a memory card having various interfaces, a solid state drive (SSD), and the like.

In addition, computing devices that support ubiquitous computing are evolving according to the needs of users to store more data in response to an increasing amount of content. Increasing the volume of data that can be stored in one device in a way to store more data may be limited, and the efficiency of operation may be lowered. Accordingly, in order to store more data, it is necessary to connect a plurality of memory systems including a plurality of nonvolatile memory devices to process a large amount of data.

Embodiments of the present invention constitute a method of establishing a link, a method of assigning an identifier or an ID, or an entire system for establishing a connection of each device for connecting a computing device and multiple devices (multiple memory systems). It is possible to provide an apparatus and method for the manner of doing so.

In addition, embodiments of the present invention minimize memory complexity and performance degradation of a memory system, maximize a use efficiency of a memory device, and can rapidly and stably process data with a memory device, a data processing system, and the same. It can provide a method of operation.

In addition, embodiments of the present invention, in a data processing system that includes a plurality of memory systems or a data processing system that can add a separate memory system inside or outside, give priority to each of the plurality of memory systems, By storing metadata about a plurality of memory systems in a memory system having a high priority, a method and an apparatus may more efficiently determine which one of the plurality of memory systems the data processing system uses.

In addition, embodiments of the present invention, in a data processing system including a plurality of memory systems or a data processing system in which a separate memory system may be added inside or outside, at least one of the plurality of memory systems is physically separated or When the operation state is less than or equal to a predetermined criterion, the data processing system can stably process data by resetting the priority of each of the plurality of memory systems or transferring the authority of the memory system having a higher priority to another memory system. And a device can be provided.

Technical problems to be achieved in the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned above will be clearly understood by those skilled in the art from the following description. Could be.

The present invention provides a memory system, a data processing system, and a method of operating and confirming the operation thereof.

In accordance with another aspect of the present invention, a data processing system includes a host configured to process data in response to an externally input command; And a plurality of memory systems interlocked with the host and capable of storing or outputting the data in response to a request of the host, wherein the plurality of memory systems include a first memory system which is one of the plurality of memory systems. Can store metadata about

Further, the first memory system among the plurality of memory systems is given a higher priority than other memory systems, and the first memory system assigns an identifier for logical identification to each of the plurality of memory systems. Can be.

In addition, when an operation state of the first memory system corresponds to a preset condition, the priority may be transferred to one of the other memory systems.

Also, the first memory system may be embedded in the host, and the other memory system may be detachable from the host.

In addition, even if at least one of the other memory systems is separated from the host, an identifier assigned to the separated memory system and metadata stored in the first memory system may be maintained.

In addition, when an operation state of at least one of the plurality of memory systems is impossible, the host may withdraw and reassign the identifier assigned to the memory system.

In addition, the metadata may include first mapping information for identifying a physical address corresponding to a logical address.

In addition, each of the plurality of memory systems may include second mapping information for identifying a logical address corresponding to a physical address.

In addition, each of the plurality of memory systems may perform garbage collection by autonomous determination. The memory system may perform garbage collection on the metadata.

In addition, when power is applied to the host and the first memory system, the first memory system transmits the metadata to the host, and when the first memory system generates or modifies the metadata, the first memory system The memory system may inform the host of the need to update the metadata.

A memory system according to another embodiment of the present invention is a memory device capable of storing data; And a controller capable of storing, deleting, or reading the data in the memory device, and when interworking with a host, receives a partial region of the memory in the host, and the priority determined for interworking with the host is a preset value. The controller determines an identifier for at least one other memory system associated with the host, transmits the identifier to the host, stores metadata for the at least one other memory system, in the memory device, and partially At least one of the metadata or user data transmitted from the host may be stored in the region.

The meta data may include first mapping information for identifying a physical address corresponding to a logical address, and if the priority is not the preset value, the first mapping information. You may not save it.

In addition, regardless of the priority, second mapping information for identifying a logical address corresponding to a physical address may be stored in the memory device.

In addition, garbage collection may be performed using the second mapping information without a command of the host.

In a system interoperating with a host and at least one other memory system in accordance with another embodiment of the present invention and including at least one processor, at least one memory and a program instruction, the program instruction is the at least one processor and the at least Transmitting, by a system, metadata to a part of a host memory included in the host through a memory; Receiving a read command and a first logical address from the host; Identifying a first physical address corresponding to the first logical address conveyed with the read command in the at least one memory; If the first physical address is not verified, requesting a part of the metadata including the first logical address; Receiving and storing some of the metadata corresponding to the request in the at least one memory; Translating the first logical address into the first physical address based on some of the metadata; And outputting data by accessing a memory device to the first physical address.

The program command may further include: receiving, by the system, a write command from the host; If the data corresponding to the write command is greater than a preset amount, requesting the host to copy the data to the partial area; Confirming that the copy is completed, and notifying the host of whether the write command is fulfilled; And moving the data copied to the partial region to a memory device while there is no command transmitted from the host.

The program command may further cause the system to assign an identifier corresponding to the at least one other memory system.

In addition, the program command may cause the system to perform the step of copying the metadata to one of the at least one other memory system when the operating state of the memory device corresponds to a preset condition.

The memory device may include a first area for storing the metadata and a second area for storing user data.

In addition, the metadata may include first mapping information for identifying a physical address corresponding to a logical address of the user data and data stored in the at least one other memory system. .

The above aspects of the present invention are merely some of the preferred embodiments of the present invention, and various embodiments in which the technical features of the present invention are reflected will be described in detail below by those skilled in the art. Can be derived and understood.

The effects on the apparatus according to the present invention are described as follows.

According to the present invention, in a data processing system interoperating with a plurality of memory systems, priority is given to a plurality of memory systems, and a high priority memory system manages metadata and the like, thereby improving efficiency in interworking with other memory systems. have.

In addition, when the operating state of a high priority memory system is less than or equal to a preset criterion, the authority may be transferred to another memory system to remove the memory system having a poor operating state from among the plurality of memory systems. There is an advantage that the interworking can be made continuously.

In addition, the present invention, in the data processing system including a plurality of memory system in accordance with the operating state of the plurality of memory system to dynamically move the information for the interlocking of the memory system, the advantage of being able to flexibly manage the plurality of memory system There is this.

Effects obtained in the present invention are not limited to the above-mentioned effects, and other effects not mentioned above may be clearly understood by those skilled in the art to which the present invention pertains.

1 illustrates a data processing system including a plurality of memory systems according to an embodiment of the present invention.
2 schematically illustrates an example of a data processing system including a memory system according to an exemplary embodiment of the inventive concept.
3 illustrates a controller in a memory system according to another embodiment of the present invention.
4 to 5 schematically illustrate an example of performing a plurality of command operations corresponding to a plurality of commands in a memory system according to an embodiment of the present disclosure.
6 to 11 illustrate examples of improving operating efficiency of a memory system.
12 illustrates a configuration of a plurality of memory systems.
13 illustrates an example of improving operation efficiency of a plurality of memory systems.
14 illustrates an operation when some memory systems are separated from a plurality of memory systems.
15 illustrates a method of updating metadata for a plurality of memory systems.
16 illustrates a privilege transfer method in a plurality of memory systems.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only parts necessary for understanding the operation according to the present invention will be described, and descriptions of other parts will be omitted so as not to distract from the gist of the present invention.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings.

1 illustrates a data processing system including a plurality of memory systems according to an embodiment of the present invention.

Referring to FIG. 1, the data processing system 100 may include a host 102 and a plurality of memory systems 110A, 110B, and 110C. The plurality of memory systems 110A, 110B, and 110C may store or output data in response to a request of the host 102.

Although FIG. 1 illustrates that the data processing system 100 includes at least three memory systems, in some embodiments, the data processing system 100 may include two or more memory systems.

Each of the memory systems 110A, 110B, and 110C may include a controller 130, a memory 144, and a plurality of memory devices 152, 154, 156, and 158. In some embodiments, the plurality of memory devices 152, 154, 156, and 158 included in the memory systems 110A, 110B, and 110C may include a nonvolatile memory device capable of storing data even when the power is turned off. In FIG. 1, each of the memory systems 110A, 110B, and 110C includes four memory devices, but according to an embodiment, the memory device may include at least one memory device.

Although not shown, the memory devices 152, 154, 156, and 158 may include at least one block, and each block may include a plurality of pages. The internal structure and specific operations of the memory devices 152, 154, 156, and 158 will be described later with reference to FIGS. 2 to 5.

Host 102 can include a computing device that a user can use. For example, the host 102 may include a personal computer such as a desktop or a laptop, a mobile device such as a mobile phone, or a server that can be used in an office, a school, a laboratory, or the like. As the amount of data required by the user increases, the number of memory systems 110A, 110B, and 110C that interact with the host 102 may increase.

The host 102 and the plurality of memory systems 110A, 110B, and 110C may transmit and receive commands and data at high speed. To this end, the plurality of memory systems 110A, 110B, and 110C and the host 102 may support serial communication. For example, the serial communication method may include at least one protocol of MIPI M-PHY, Universal Asynchronous Receiver Transmitter (UART), Serial Peripheral Interface Bus (SPI), Inter Integrated Circuit (I2C), and Universal Serial Bus (USB). Can be.

For example, when the plurality of memory systems 110A, 110B, and 110C support the specifications of universal flash storage (UFS) and the embedded UFS (eUFS), the plurality of memory systems 110A, 110B, and 110C may be used. ) And the host 102 may use a high speed serial communication interface of the Mobile Industry Processor Interface (MIPI) M-PHY. Here, M-PHY at the physical layer is an embedded clock serial interface technology with very high bandwidth capabilities developed for the extreme performance and low power requirements of mobile applications. In addition, the plurality of memory systems 110A, 110B, and 110C may support UniPro standard technology in a link layer.

The host 102 interoperating with the plurality of memory systems 110A, 110B, and 110C may recognize the plurality of memory systems 110A, 110B, and 110C by distinguishing them. To this end, the host 102 may assign an identifier or ID to each of the memory systems 110A, 110B, and 110C.

Priority may be given to the plurality of memory systems 110A, 110B, and 110C that cooperate with the host 102. For example, the priority may be divided into primary and secondary. According to an embodiment, the priority may be set at more levels or levels, and given to the plurality of memory systems 110A, 110B, 110C.

According to an embodiment, the first memory system (eg, 110A), which is one of the plurality of memory systems 110A, 110B, and 110C, may be given a higher priority than other memory systems. In this case, metadata about all of the plurality of memory systems 110A, 110B, and 110C may be stored in the first memory system 110A.

According to an embodiment, metadata for all of the plurality of memory systems 110A, 110B, and 110C stored in the first memory system 110A may be determined to identify a physical address corresponding to a logical address. It may include the first mapping information for.

According to an embodiment, a first memory system to which a high priority among the plurality of memory systems 110A, 110B and 110C is assigned is embedded in the host 102 and the plurality of memory systems 110A, 110B and 110C. The other memory system may be detachable from the host 102.

In some embodiments, the first memory system to which the high priority is assigned among the plurality of memory systems 110A, 110B, and 110C may not be embedded in the host 102. However, while power is supplied to the host 102, the first memory system may be electrically connected to the host 102 to support an operation of the host 102 to operate with the plurality of memory systems 110A, 110B, and 110C. Can be.

Hereinafter, an example of an operation of the data processing system 100 including the host 102 interoperating with the plurality of memory systems 110A, 110B, and 110C will be described with reference to FIG. 1. First, it is assumed that the first memory system 110A among the plurality of memory systems 110A, 110B, and 110C has been assigned a priority of primary, and is built-in or embedded in the host 102. Assume that there is.

When the host 102 detects other memory systems 110B and 110C among the plurality of memory systems 110A, 110B and 110C, the host 102 may add another memory system 110B and 110C to the first memory system 110A. It can inform the operation information about.

The first memory system 110A may determine a logical identifier corresponding to the other memory systems 110B and 110C among the unassigned identifiers and notify the host 102. Based on this, the host 102 may assign a logical identifier to the other memory systems 110B and 110C.

In addition, according to an embodiment, the first memory system 110A or the host 102 may determine and give priority to the other memory systems 110B and 110C. If the host 102 determines priorities for the other memory systems 110B and 110C, it notifies the first memory system 110A so that the first memory system 110A operates the other memory systems 110B and 110C. Information can be stored.

Meanwhile, other memory systems 110B and 110C may store logical identifiers assigned to them. The other memory systems 110B and 110C may transmit and receive data using the stored logical identifier whenever the host 102 interworks with the host 102.

In some embodiments, the plurality of memory systems 110A, 110B, and 110C may store a plurality of logical identifiers. The plurality of memory systems 110A, 110B, and 110C may use logical identifiers differently depending on which host 102 they work with. For example, when the second memory system 110B interoperates with the host 102, a logical identifier of 'AB' may be used, but when interworking with another host (not shown), a logical identifier of 'ED' may be used. It may be. Here, the logical identifier used by the plurality of memory systems 110A, 110B, and 110C for communication with the host 102 is a logical address concept, which is used to determine the location of data in one data processing system. According to an embodiment, logical identifiers that may be used between the host 102 and the plurality of memory systems 110A, 110B, 110C may be set differently.

In order for the host 102 to physically recognize the plurality of memory systems 110A, 110B, and 110C, the host 102 may utilize unique information of the plurality of memory systems 110A, 110B, and 110C. For example, an example that can be used between the host 102 and the plurality of memory systems 110A, 110B, 110C is a universally unique identifier (UUID). The universal unique identifier (UUID) may comprise a number of 16 octets (128 bits). In the standard format, the Universal Unique Identifier (UUID) is represented by 32 hexadecimal digits and is hyphenated by five groups, 8-4-4-4-12, with a total of 36 characters (32 characters and 4 hyphens). Can be. Here, the universally unique identifier (UUID) is the host 102 and the plurality of memory systems (110A, 110B, 110C) together with the logical identifier preset between the host 102 and the plurality of memory systems (110A, 110B, 110C). It may be used as information included in a header in a packet whose format is determined according to a predetermined communication protocol.

Information for identification between the host 102 and the plurality of memory systems 110A, 110B, and 110C may be stored in a specific region (eg, Master Boot Record (MBR)) of the first memory system 110A. When power is supplied to the host 102 and the plurality of memory systems 110A, 110B, and 110C, since the data or firmware stored in some areas of the first memory system 110A is executed first, the first memory system 110A is performed. ) May store basic information for physically recognizing the host 102 and the plurality of memory systems 110A, 110B, and 110C in a specific region.

Data is transmitted and received through a communication protocol connected between the host 102 and the plurality of memory systems 110A, 110B, and 110C through a preset logical identifier between the host 102 and the plurality of memory systems 110A, 110B, and 110C. can do. The communication protocol used between the host 102 and the plurality of memory systems 110A, 110B, and 110C may support at least one master and at least one slave. If the communication protocol supports one master, the host 102 may be a master and the plurality of memory systems 110A, 110B, 110C may be slaves. Meanwhile, when a communication protocol supports a plurality of masters, a first memory system (eg, 110A) assigned a high priority to a host may be a master, and the other memory systems 110B and 110C may be slaves.

When the host 102 recognizes the other memory systems 110B and 110C, it may notify the first memory system 110A. The first memory system 110A may receive metadata stored in the other memory systems 110B and 110C.

When the first memory system 110A is a master, the first memory system 110A may directly request metadata for the other memory systems 110B and 110C notified from the host 102. The other memory systems 110B and 110C may transfer the metadata stored therein to the first memory system 110A in response to a request of the first memory system 110A.

Meanwhile, when the first memory system 110A is a slave, the host 102 may receive metadata of the other memory systems 110B and 110C and transmit the metadata to the first memory system 110A.

Upon receiving the metadata of the other memory systems 110B and 110C from the host 102, the first memory system 110A adds logical identifiers assigned to the respective memory systems, so that all memory systems that interoperate with the host 102. Metadata of 110A, 110B, and 110C can be completed.

According to an exemplary embodiment, the other memory systems 110B and 110C may maintain the metadata stored therein or delete the metadata after transferring the metadata to the first memory system 110A. When the other memory systems 110B and 110C maintain the metadata, it may be used as a backup concept of the metadata managed by the first memory system 110A. Meanwhile, when the other memory systems 110B and 110C do not maintain the metadata, they may receive the metadata corresponding to themselves from the first memory system 110A or the host 102 before being separated into the host 102. have. In both cases described above, other memory systems 110B and 110C may be kept separate from host 102 to maintain minimal metadata for use in other computing systems.

If metadata for the other memory systems 110B and 110C connected to the host 102 is not recognized, the first memory system 110A may newly generate metadata for the other memory systems 110B and 110C. Can be. For example, when the other memory systems 110B and 110C are empty without data or are not available or compatible with the host 102 even though the data is stored, the first memory system 110A may be a different memory system. Meta data for 110B and 110C may be generated. In some cases, the first memory system 110A may perform garbage collection in order to secure a storage space for new metadata.

Meanwhile, the first memory system 110A may no longer perform an operation as a device having a high priority assigned thereto. For example, the first memory system 110A may no longer have space to generate metadata, or the first memory system 110A may wear-out or run-out. ) May be in a state. In this case, the first memory system 110A may migrate its status and authority as a device having a high priority to one of the other memory systems 110B and 110C.

When all logical identifiers are applied together with the physical recognition of the plurality of memory systems 110A, 110B, and 110C in cooperation with the host 102, the host 102 reads and writes the memory systems 110A, 110B, and 110C. , Delete (Read, Write.Erase) operation can be performed. The host 102 may broadcast commands or data to the plurality of memory systems 110A, 110B, and 110C as a master. Since the host 102 and the plurality of memory systems 110A, 110B, and 110C interoperate with 1: N (N is a natural number of two or more), the host 102 designates a specific memory system to transmit a command or data. It may be more efficient to broadcast toward a plurality of memory systems 110A, 110B, 110C. The plurality of memory systems 110A, 110B, and 110C may identify a packet including at least one of a logical identifier and a universal unique identifier, and may selectively receive only a packet corresponding to the plurality of memory systems 110A, 110B, and 110C.

The host 102 selects a plurality of memory systems 110A, 110B, and 110C and sends metadata about the plurality of memory systems 110A, 110B, and 110C from the first memory system 110A in order to send a command or data. Can be loaded. For example, a portion of the memory included in the host 102 may be designated to store metadata about the plurality of memory systems 110A, 110B, and 110C.

According to an embodiment, the method of using some areas of the memory included in the host 102 may vary. A method of using a part of the memory included in the host 102 will be described later with reference to FIGS. 6 through 11.

Meanwhile, a device having a high priority in the first memory system 110A while the host 102 performs a read, write, or erase operation on the memory systems 110A, 110B, and 110C. May not be able to perform the operation as. In this case, in the data processing system 100, among the other memory systems 110B and 110C from the first memory system 110A, than the read, write and erase operations performed through the host 102. An operation of migrating authority to one may be performed first. For example, when transferring a right due to an expected loss of the first memory system 110A, which is the primary device, the block of the second memory system 110B, which is the secondary device, is deleted, and the first memory system 110A is deleted. The data stored in the second memory system 110B may be moved. Thereafter, the host 102 may load metadata from the second memory system 110B.

2 is a diagram schematically illustrating an example of a data processing system including a memory system according to an exemplary embodiment of the inventive concept.

Referring to FIG. 2, the data processing system 100 includes a host 102 and a memory system 110.

In addition, the host 102 includes electronic devices, such as portable electronic devices such as mobile phones, MP3 players, laptop computers, or the like, or electronic devices such as desktop computers, game consoles, TVs, projectors, and the like, that is, wired and wireless electronic devices.

In addition, the host 102 includes at least one operating system (OS), and the operating system manages and controls the functions and operations of the host 102 as a whole, and the data processing system 100 or Provides interaction between the user and host 102 using the memory system 110. Here, the operating system supports functions and operations corresponding to a user's purpose and purpose of use, and may be classified into a general operating system and a mobile operating system according to, for example, mobility of the host 102. In addition, the general operating system system in the operating system may be divided into a personal operating system and a corporate operating system according to the user's use environment. For example, the personal operating system is characterized to support a service providing function for the general user. The system includes windows and chrome, and the enterprise operating system is a system specialized to secure and support high performance, such as windows server, linux and unix. It may include. In addition, the mobile operating system in the operating system is a system specialized to support the mobility service providing function and the power saving function of the user, and may include Android, iOS, Windows mobile and the like. . In this case, the host 102 may include a plurality of operating systems, and also executes the operating system to perform an operation with the memory system 110 corresponding to a user request. ) Transmits a plurality of commands corresponding to the user request to the memory system 110, and accordingly, the memory system 110 performs operations corresponding to the commands, that is, operations corresponding to the user request.

In addition, the memory system 110 operates in response to a request from the host 102 and, in particular, stores data accessed by the host 102. In other words, the memory system 110 may be used as a main memory or an auxiliary memory of the host 102. The memory system 110 may be implemented as one of various types of storage devices according to a host interface protocol connected to the host 102. For example, the memory system 110 may include a solid state drive (SSD), an MMC, an embedded MMC (eMMC), a reduced size MMC (RS-MMC), and a micro-MMC type multimedia card (MMC). Multi Media Card (SD), Secure Digital (SD) cards in the form of SD, mini-SD, micro-SD, Universal Storage Bus (USB) storage devices, Universal Flash Storage (UFS) devices, Compact Flash (CF) cards, The storage device may be implemented as one of various types of storage devices such as a smart media card, a memory stick, and the like.

In addition, the storage devices for implementing the memory system 110 may include volatile memory devices such as dynamic random access memory (DRAM) and static RAM (SRAM), read only memory (ROM), mask ROM (MROM), and programmable PROM (PROM). Non-volatile memory devices such as ROM, erasable ROM (EPROM), electrically erasable ROM (EEPROM), ferromagnetic ROM (FRAM), phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and flash memory. Can be implemented.

The memory system 110 includes a memory device 150 that stores data accessed by the host 102, and a controller 130 that controls data storage in the memory device 150.

Here, the controller 130 and the memory device 150 may be integrated into one semiconductor device. For example, the controller 130 and the memory device 150 may be integrated into one semiconductor device to form an SSD. When the memory system 110 is used as an SSD, an operating speed of the host 102 connected to the memory system 110 may be further improved. In addition, the controller 130 and the memory device 150 may be integrated into one semiconductor device to configure a memory card. For example, a PC card (PCMCIA: Personal Computer Memory Card International Association), a compact flash card (CF) Memory cards such as smart media cards (SM, SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), universal flash storage (UFS), etc. can do.

In another example, the memory system 110 may include a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, and a web tablet. ), Tablet computer, wireless phone, mobile phone, smart phone, e-book, portable multimedia player, portable game console, navigation (navigation) devices, black boxes, digital cameras, digital multimedia broadcasting (DMB) players, 3-dimensional televisions, smart televisions, digital audio recorders recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder, digital video player, data center Make up Storage, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, RFID (radio frequency identification) device, or one of various components constituting the computing system.

Meanwhile, the memory device 150 in the memory system 110 may maintain stored data even when power is not supplied. In particular, the memory device 150 may store data provided from the host 102 through a write operation and read the data. The stored data is provided to the host 102 through the operation. Here, the memory device 150 includes a plurality of memory blocks 152, 154, and 156, and each of the memory blocks 152, 154, and 156 includes a plurality of pages, and each page Includes a plurality of memory cells to which a plurality of word lines (WL) are connected. In addition, the memory device 150 includes a plurality of planes each including a plurality of memory blocks 152, 154, and 156, and in particular, a plurality of memory dies each including a plurality of planes. Can include them. In addition, the memory device 150 may be a nonvolatile memory device, for example, a flash memory, and in this case, the flash memory may have a three-dimensional stack structure.

The controller 130 in the memory system 110 controls the memory device 150 in response to a request from the host 102. For example, the controller 130 provides the data read from the memory device 150 to the host 102, and stores the data provided from the host 102 in the memory device 150. The memory device 150 controls operations of read, write, program, erase, and the like of the memory device 150.

More specifically, the controller 130 may include a host interface unit (132), a processor (134), an error correction code (ECC) unit 138, and power management. A unit (PMU), a memory interface (Memory I / F) unit 142, and a memory 144.

In addition, the host interface unit 132 processes commands and data of the host 102, and includes a universal serial bus (USB), a multi-media card (MMC), and a peripheral component interconnect-express (PCI-E). , Serial-attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), MIPI (MIPI) And may be configured to communicate with the host 102 via at least one of various interface protocols, such as Mobile Industry Processor Interface. Here, the host interface unit 132 is an area for exchanging data with the host 102 and is driven through firmware called a host interface layer (HIL). Can be.

In addition, the ECC unit 138 may correct an error bit of data processed by the memory device 150 and may include an ECC encoder and an ECC decoder. In this case, the ECC encoder may error correct encoding data to be programmed in the memory device 150 to generate data to which parity bits are added, and the data to which parity bits are added, It may be stored in the memory device 150. When the ECC decoder reads data stored in the memory device 150, the ECC decoder detects and corrects an error included in the data read from the memory device 150. In other words, the ECC unit 138, after error correction decoding the data read from the memory device 150, determines whether the error correction decoding is successful, and according to the determination result, an indication signal, for example, an error A success / fail signal may be output and a parity bit generated during ECC encoding may be used to correct an error bit of read data. At this time, the ECC unit 138 may not correct the error bit if the number of error bits exceeds the correctable error bit limit value, and may output an error correction failure signal corresponding to the error bit failure.

In this case, the ECC unit 138 includes a low density parity check (LDPC) code, a BCH (Bose, Chaudhri, Hocquenghem) code, a turbo code, a Reed-Solomon code, and a convolution. Error correction may be performed using coded modulation such as a convolution code, a recursive systematic code (RSC), trellis-coded modulation (TCM), and block coded modulation (BCM). It is not. In addition, the ECC unit 138 may include all of a circuit, a module, a system, or an apparatus for error correction.

The PMU 140 provides and manages the power of the controller 130, that is, the power of the components included in the controller 130.

In addition, the memory interface unit 142 performs an interface between the controller 130 and the memory device 150 in order for the controller 130 to control the memory device 150 in response to a request from the host 102. It becomes a memory / storage interface. Here, the memory interface unit 142 is a NAND flash controller (NFC) when the memory device 150 is a flash memory, particularly, for example, the memory device 150 is a NAND flash memory. According to the control of the memory device 150 generates a control signal and processes the data. In addition, the memory interface unit 142 may be an interface for processing commands and data between the controller 130 and the memory device 150, for example, an operation of a NAND flash interface, in particular, data between the controller 130 and the memory device 150. It supports input / output and may be driven through firmware called a flash interface layer (FIL) as an area for exchanging data with the memory device 150.

In addition, the memory 144 is an operating memory of the memory system 110 and the controller 130, and stores data for driving the memory system 110 and the controller 130. More specifically, the memory 144 controls the memory device 150 in response to a request from the host 102, such that the controller 130 is read from the memory device 150. The data is provided to the host 102, and the data provided from the host 102 is stored in the memory device 150. To this end, the controller 130 may read, write, program or erase the memory device 150. In the case of controlling an operation such as erase), data necessary for performing such an operation between the memory system 110, that is, the controller 130 and the memory device 150 is stored.

Herein, the memory 144 may be implemented as a volatile memory, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), or the like. In addition, as shown in FIG. 2, the memory 144 may exist inside the controller 130 or outside the controller 130. In this case, data may be stored from the controller 130 through the memory interface. It may be implemented as an external volatile memory input and output.

In addition, as described above, the memory 144 may include data necessary for performing operations such as data write and read between the host 102 and the memory device 150, and data when performing operations such as data write and read. For storing such data, program memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, map buffer / cache, and the like are included.

The processor 134 controls the overall operation of the memory system 110, and in particular, controls the program operation or the read operation of the memory device 150 in response to a write request or a read request from the host 102. do. Here, the processor 134 drives a firmware called a flash translation layer (FTL) to control the overall operation of the memory system 110. In addition, the processor 134 may be implemented as a microprocessor or a central processing unit (CPU).

For example, the controller 130 performs an operation requested by the host 102 in the memory device 150 through the processor 134 implemented as a microprocessor or a central processing unit (CPU), that is, the host ( The command operation corresponding to the command received from 102 is performed with the memory device 150. Here, the controller 130 performs a foreground operation with a command operation corresponding to a command received from the host 102, for example, a program operation corresponding to a write command, a read operation corresponding to a read command, and an erase operation. An erase operation corresponding to a command (erase command), a parameter set operation corresponding to a set parameter command or a set feature command may be performed using a set command.

In addition, the controller 130 may perform a background operation on the memory device 150 through the processor 134 implemented as a microprocessor or a central processing unit (CPU). The background operation of the memory device 150 may include copying and storing data stored in an arbitrary memory block into another arbitrary memory block in the memory blocks 152, 154, and 156 of the memory device 150. For example, a garbage collection (GC) operation, swapping between memory blocks 152, 154, and 156 of the memory device 150 or data stored in the memory blocks 152, 154, and 156 are processed. For example, a wear leveling (WL) operation, an operation of storing map data stored in the controller 130 to the memory blocks 152, 154, and 156 of the memory device 150, and an example of flushing a map map flush, or bad management of the memory device 150, for example, by identifying a bad block in a plurality of memory blocks 152, 154, and 156 included in the memory device 150. Bad block managemen t) operation and the like.

In addition, in the memory system according to an embodiment of the present disclosure, for example, the controller 130 may correspond to a plurality of command operations corresponding to a plurality of commands received from the host 102, for example, a plurality of write commands. In the memory device 150, a plurality of program operations, a plurality of read operations corresponding to a plurality of read commands, and a plurality of erase operations corresponding to a plurality of erase commands are performed in the memory device 150. In a plurality of channels (or ways) connected with a plurality of memory dies included in 150, after determining the best channels (or ways), the best channels (or Results of the execution of the command operations from the memory dies which transmit the commands received from the host 102 to the corresponding memory dies, and which have performed the command operations corresponding to the commands, , Via the best channel (or the way), and provides the execution result of the received then command the operation to the host (120). In particular, in the memory system according to an embodiment of the present disclosure, when receiving a plurality of commands from the host 102, the state of the plurality of channels (or ways) connected to the memory dies of the memory device 150 may be checked. Then, determine the best transmission channels (or transmission ways) corresponding to the state of the channels (or ways), and, via the best transmission channels (or transmission ways), a plurality of received from the host 102 Send commands to the corresponding memory dies. In addition, in the memory system according to an embodiment of the present disclosure, after performing command operations corresponding to a plurality of commands received from the host 102 in the memory dies of the memory device 150, the memory of the memory device 150 is performed. In a plurality of channels (or ways) connected to the dies, the execution results of the command operations are performed through the best receiving channels (or receiving ways) corresponding to the state of the channels (or ways). Receive from the memory dies of the device 150 and provide the performance results received from the memory dies of the memory device 150 to the host 102 in response to a plurality of commands received from the host 102. do.

Here, the controller 130 checks the state of the plurality of channels (or ways) connected to the plurality of memory dies included in the memory device 150, for example, the busy of the channels (or ways). After checking the state, ready state, active state, idle state, normal state, abnormal state, etc., the best channels according to the state of the channels (or ways) (Or ways) receive a plurality of commands received from the host 102 to the corresponding memory dies, that is, received from the host 102 via the best transport channels (or transmission ways). The memory dies are requested to perform command operations corresponding to the plurality of commands. In addition, the controller 130 receives the results of performing the command operations from the corresponding memory dies, corresponding to the request of performing the command operations on the best transmission channels (or transmission ways), wherein the channels (or ways) are performed. ) Receive the results of performing command operations on the best channels (or ways), that is to say the best receiving channels (or receiving ways), depending on the state of the " In addition, the controller 130 may determine between a descriptor of commands transmitted through the best transmission channels (or transmission ways) and a descriptor of performance results received through the best reception channels (or reception ways). After matching, the host 102 provides the host 102 with the results of performing command operations corresponding to the commands received from the host 102.

Here, the descriptor of the command may include data information or position information corresponding to the commands, for example, an address of data corresponding to write commands or read commands (for example, a logical page number of data) or an address of a location where data is stored ( For example, the physical page information of the memory device 150, and the like, and indication information of the transmission channels (or transmission ways) to which the commands are transmitted, for example, an identifier of the transmission channels (or transmission ways) (for example, a channel). Number (or way number)) and the like. In addition, the descriptor of the execution results may include data information or position information corresponding to the execution results, for example, data of program operations corresponding to write commands or data of read operations corresponding to read commands (eg, data The logical page number) or the address of the location where the program operations or read operations were performed (e.g., the physical page information of the memory device 150), and the channels (or ways) for which the command operations were requested, again. In other words, the indication information of the transmission channels (or transmission ways) through which the commands are transmitted may be included, for example, an identifier (eg, a channel number (or way number)) of the transmission channels (or transmission ways). In addition, information included in the descriptor of the command and the descriptor of the execution results, for example, data information, location information, or indication information of channels (or ways), may be in the form of a context or a tag. Can be included.

That is, in the memory system 110 according to an embodiment of the present disclosure, a plurality of commands received from the host 102 and a result of performing a plurality of command operations corresponding to the commands are stored in the memory of the memory device 150. Transmit and receive over the best channels (or ways) in a plurality of channels (or ways) connected to the dies. In particular, in the memory system 110 according to an embodiment of the present disclosure, the commands may be generated in response to a state of a plurality of channels (or ways) connected to memory dies of the memory device 150. Independently manages the transmission channels (or transmission ways) transmitted to the memory dies and the reception channels (or reception ways) from which the execution results of the command operations are received from the memory dies of the memory device 150, respectively. do. For example, the controller 130 in the memory system 110 may correspond to a state of a plurality of channels (or ways), in which the first command is transmitted in a plurality of channels (or ways). Or a transmission way) and a reception channel (or reception way) on which a result of performing a first command operation corresponding to the first command is received, is determined as the independent best channels (or ways), for example, a transmission channel ( Or determine the transmission way) as the first best channel (or way), determine the reception channel (or reception way) as the first best channel (or way), or determine the second best channel (or way), and then independently On top of the best channels (or ways), the transmission of the first command and the reception result of the execution of the first command operation are performed.

Therefore, in the memory system 110 according to an exemplary embodiment of the present invention, a plurality of channels (or ways) connected to a plurality of memory dies of the memory device 150 are more efficiently used, and each independent best Through the channels (or ways), the plurality of commands received from the host 102 and the execution results of command operations corresponding to the commands are respectively transmitted and received, thereby further improving the operating performance of the memory system 110. You can. Here, in the embodiment of the present invention to be described later, for convenience of description, the host (via a plurality of channels (or ways) for the memory dies included in the memory device 150 of the memory system 110, Although a case of transmitting / receiving a plurality of commands received from the 102 and execution results of command operations corresponding to the commands are described as an example, a plurality of memory systems each including the controller 130 and the memory device 150 are described. In this example, the plurality of commands received from the host 102 and the command operations corresponding to the commands are performed in the respective memory systems through the plurality of channels (or ways) for the respective memory systems. The results of the subsequent executions can be equally applied to transmission and reception. And, when receiving a plurality of commands from the host 102 in the memory system according to an embodiment of the present invention, transmitting a plurality of commands, performing command operations corresponding to the plurality of commands, and performing the command operations Processing of the transmission of the results will be described in more detail below with reference to FIGS. 5 to 9, and thus a detailed description thereof will be omitted.

In addition, the processor 134 of the controller 130 may include a management unit (not shown) for performing bad management of the memory device 150, and the management unit includes a plurality of management units included in the memory device 150. After checking the bad block in the memory blocks 152, 154, and 156, bad block management is performed to badly process the identified bad block. Here, in the bad management, when the memory device 150 is a flash memory, for example, a NAND flash memory, a program fail may occur during a data write, for example, a data program due to the characteristics of the NAND. After bad processing of a memory block in which a failure occurs, the program failed data is written into a new memory block, that is, programming. In addition, when the memory device 150 has a three-dimensional solid stack structure as described above, when the corresponding block is treated as a bad block in response to a program failure, the memory device 150 uses the memory device 100 and the memory system 100 ), The reliability of the CB is rapidly deteriorated, so it is necessary to perform more reliable bad block management.

3 illustrates a controller in a memory system according to another embodiment of the present invention.

Referring to FIG. 3, the controller 130 interoperating with the host 102 and the memory device 150 may include a host interface unit 132, a flash translation layer (FTL) unit 40, a memory interface unit 142, and a memory. Element 144 may be included.

Although not shown in FIG. 3, according to an embodiment, the ECC unit 138 described in FIG. 2 may be included in the flash translation layer (FTL) unit 40. According to an embodiment, the ECC unit 138 may be implemented as a separate module, circuit, firmware, or the like in the controller 130.

The host interface unit 132 is for exchanging commands and data transmitted from the host 102. For example, the host interface unit 132 sequentially stores the commands, data, and the like transmitted from the host 102, and then delivers the commands from the command queue 56 and the command queue 56, which may be output in the stored order. A buffer manager 52 capable of classifying commands or data, or adjusting processing order thereof, and an event queue 54 for sequentially delivering events for processing commands, data, etc. delivered from the buffer manager 52. It may include.

Commands and data from the host 102 may be successively delivered with a plurality of the same characteristics, or may be delivered with a mixture of instructions and data of different characteristics. For example, a plurality of instructions for reading data may be delivered, or read and program instructions may be alternately delivered. The host interface unit 132 sequentially stores the commands, data, and the like transmitted from the host 102 in the command queue 56 first. Thereafter, the controller 130 may predict what operation the controller 130 performs according to the characteristics of the command, data, and the like transmitted from the host 102, and may determine the processing order or priority of the command, the data, and the like based on this. In addition, depending on the characteristics of commands, data, and the like transmitted from the host 102, the buffer manager 52 in the host interface unit 132 stores the commands, data, and the like in the memory device 144, or the flash translation layer (FTL). It may also determine whether to deliver to the unit (40). The event queue 54 receives an event that the memory system or the controller 130 needs to execute and process internally according to the command, data, etc. transmitted from the host 102 from the buffer manager 52 and then flashes in the received order. May be passed to the transform layer (FTL) unit 40.

According to an embodiment, the flash translation layer (FTL) unit 40 is a host request manager (HRM) 46 for managing events received from the event rule 54, map data for managing map data. A map manager (MM) 44, a state manager 42 for performing garbage collection or wear leveling, and a block manager 48 for executing a command on a block in a memory device may be included.

For example, the host request manager (HRM) 46 uses the map data manager (MM, 44) and the block manager 48 to process read and program commands received from the host interface unit 132 and requests according to events. can do. The host request manager (HRM) 46 sends an inquiry request to the map data manager (MM, 44) to determine the physical address corresponding to the logical address of the forwarded request and flash reads to the memory interface unit 142 for the physical address. You can send a request to handle read requests. The host request manager (HRM) 46, on the other hand, first programs the data to a specific page of the unwritten (no data) memory device by sending a program request to the block manager 48, and then the map data manager (MM, 44). By transmitting a map update request for the program request, the content of the data programmed in the mapping information of the logical-physical address can be updated.

Here, the block manager 48 converts the program request requested by the host request manager (HRM) 46, the map data manager (MM, 44), and the state manager 42 into a program request for the memory device 150 to store the memory. Blocks within the device 150 may be managed. In order to maximize the program or write performance of the memory system 110 (see FIG. 2), the block manager 48 may collect program requests and send flash program requests to the memory interface unit 142 for multi-plane and one-shot program operations. have. In addition, various outstanding flash program requests may be sent to the memory interface unit 142 to maximize parallelism of the multi-channel and multi-directional flash controllers.

On the other hand, the block manager 48 manages flash blocks according to the number of valid pages, selects and erases blocks without valid pages when free blocks are needed, and blocks containing least valid pages when garbage collection is required. Can be selected. In order for the block manager 48 to have enough free blocks, the state manager 42 may perform garbage collection to collect valid data, move it to an empty block, and delete blocks that contained the moved valid data. When the block manager 48 provides the state manager 42 with information about the block to be deleted, the state manager 42 may first check all the flash pages of the block to be deleted to determine whether each page is valid. . For example, to determine the validity of each page, state manager 42 identifies the logical address recorded in the Out Of Band (OOB) area of each page, and then the physical address and map manager 44 of the page. You can compare the actual addresses that are mapped to the logical addresses obtained from the query request. The state manager 42 may transmit a program request to the block manager 48 for each valid page, and when the program work is completed, the mapping table may be updated by updating the map manager 44.

The map manager 44 manages logical-physical mapping tables and can handle requests such as queries, updates, etc. generated by the host request manager (HRM) 46 and the state manager 42. The map manager 44 may store the entire mapping table in the flash memory, and cache the mapping item according to the capacity of the device 144 in the memory. If a map cache miss occurs while processing an inquiry and update request, the map manager 44 may send a read request to the memory interface unit 142 to load the mapping table stored in the memory device 150. . If the number of dirty cache blocks in map manager 44 exceeds a certain threshold, a program request may be sent to block manager 48 to create a clean cache block and the dirty map table may be stored in memory device 150.

On the other hand, if garbage collection is performed, the host request manager (HRM) 46 may program the latest version of the data for the same logical address of the page and issue an update request simultaneously while the state manager 42 copies a valid page. Can be. The map manager 44 may not perform the mapping table update when the state manager 42 requests the map update while the copy of the valid page is not normally completed. The map manager 44 can perform map update only if the latest map table still points to the old physical address to ensure accuracy.

The memory device 150 may include a single level cell (SLC) memory block and a multi level cell (MLC) according to the number of bits capable of storing or representing a plurality of memory blocks in one memory cell. Cell) memory block, or the like. In this case, the SLC memory block includes a plurality of pages implemented by memory cells that store 1-bit data in one memory cell, and has fast data operation performance and high durability. The MLC memory block includes a plurality of pages implemented by memory cells that store multi-bit data (for example, two bits or more bits) in one memory cell, and store data larger than the SLC memory block. It can have space, that is, it can be highly integrated. In particular, the memory device 150 is an MLC memory block that includes three MLC memory blocks as well as an MLC memory block including a plurality of pages implemented by memory cells capable of storing 2-bit data in one memory cell. Triple Level Cell (TLC) memory block comprising a plurality of pages implemented by memory cells capable of storing bit data, multiple implemented by memory cells capable of storing 4-bit data in one memory cell A multi-level cell comprising a quadruple level cell (QLC) memory block containing pages of a plurality of pages implemented by memory cells capable of storing five or more bits of data in one memory cell It may include a cell (multiple level cell) memory block.

Here, in an embodiment of the present disclosure, for convenience of description, the memory device 150 is implemented as a nonvolatile memory such as a flash memory, for example, a NAND flash memory. Phase Change Random Access Memory (RRAM), Resistive Random Access Memory (RRAM), Ferroelectrics Random Access Memory (FRAM), and Spin Injection Magnetic Memory (STT-MRAM): Spin Transfer Torque Magnetic Random Access Memory) may be implemented as any one of memories.

4 to 5 are diagrams for describing an example in the case of performing a plurality of command operations corresponding to a plurality of commands in a memory system according to an embodiment of the present invention. Here, in the embodiment of the present disclosure, for convenience of description, the memory system 110 illustrated in FIG. 2 receives a plurality of commands from the host 102 to perform command operations corresponding to the commands, for example, a host ( Receive a plurality of write commands from the 102 to perform program operations corresponding to the write commands, or receive a plurality of read commands from the host 102 to read the corresponding commands. Perform the erase operations corresponding to the erase commands by receiving a plurality of erase commands received from the host 102, or perform a plurality of write commands and a plurality of reads from the host 102. Receiving commands together to perform program operations and read operations corresponding to write commands and read commands One example will be described in detail.

Here, in an embodiment of the present disclosure, when receiving a plurality of commands from the host 102, and performing a plurality of command operations corresponding to the commands received from the host 102, the plurality of commands received from the host 102 Commands of the controller 130 through the plurality of channels (or ways) between the controller 130 and the memory device 150, in particular for the plurality of memory dies included in the memory device 150, A plurality of channels (or ways) that transmit the results of the command operations performed on the memory device 150, in particular the corresponding memory dies of the memory device 150, and also performed on the memory dies of the memory device 150. And then, in response to commands received from the host 102, provide the execution results to the host 102. Here, the controller 130 in the memory system 110 according to an embodiment of the present invention, after checking the state of the plurality of channels (or ways), in accordance with the state of the channels or ways, a plurality of In channels (or ways), each independently determines the best channels (or ways), and over the best channels (or ways), commands received from host 102, Send and receive results of execution of command operations corresponding to commands.

That is, in an embodiment of the present disclosure, when receiving a plurality of commands from the host 102, after checking a state of a plurality of channels (or ways) in the memory device 150 including the plurality of memory dies, Determine the best channels (or ways) according to the state of the channels (or ways) as the transmission channels (or transmission ways) of the commands, and also correspond to the commands received from the host 102. When performing the command operations in the memory dies of the memory device 150, the best channels (or ways) corresponding to the state of the channels (or ways), the receiving channel of the performance results for the command operations To determine (or receive ways). Here, the controller 130 in the memory system 110 according to an embodiment of the present invention, the busy state, the ready state, the active state, the active state of the plurality of channels (or ways), After checking the idle state, the normal state, the abnormal state, and the like, depending on the state of the channels (or ways), the best channels (or ways) in the plurality of channels (or ways). ) Are independently determined as transmission channels (or transmission ways) of commands and reception channels (or reception ways) of performance results, respectively. For example, the controller 130 may select first best channels (or ways) in a plurality of channels (or ways), and transmit channels (or transmission way) for first commands received from the host 102. And the first best channels (or ways) or the second best channels (or ways) as received channels for the results of performing first command operations corresponding to the first commands. Or reception ways), and perform the transmission of the first commands and the reception of the execution results of the first command operations through respective independent best channels (or ways).

In addition, the controller 130 of the memory system 110 according to an embodiment of the present invention may perform a plurality of commands received from the host 102 and execution results of command operations received from the memory device 150. After matching, the result of performing command operations corresponding to the plurality of commands received from the host 102 is provided to the host 102. In this case, the controller 130 may determine between a descriptor of commands transmitted through the best transmission channels (or transmission ways) and a descriptor of performance results received through the best reception channels (or reception ways). After matching, the results of performing command operations corresponding to the commands received from the host 102 are provided to the host 102 in response to the commands. Here, the descriptor of the command may include data information or position information corresponding to the commands, for example, an address of data corresponding to write commands or read commands (for example, a logical page number of data) or an address of a location where data is stored ( For example, the physical page information of the memory device 150, and the like, and indication information of the transmission channels (or transmission ways) to which the commands are transmitted, for example, an identifier of the transmission channels (or transmission ways) (for example, a channel). Number (or way number)) and the like. In addition, the descriptor of the execution results may include data information or position information corresponding to the execution results, for example, data of program operations corresponding to write commands or data of read operations corresponding to read commands (eg, data The logical page number) or the address of the location where the program operations or read operations were performed (e.g., the physical page information of the memory device 150), and the channels (or ways) for which the command operations were requested, again. In other words, the indication information of the transmission channels (or transmission ways) through which the commands are transmitted may be included, for example, an identifier (eg, a channel number (or way number)) of the transmission channels (or transmission ways). In addition, information included in the descriptor of the command and the descriptor of the execution results, for example, data information, location information, or indication information of channels (or ways), may be in the form of a context or a tag. Can be included.

Therefore, in the memory system 110 according to an exemplary embodiment of the present invention, a plurality of channels (or ways) connected to a plurality of memory dies of the memory device 150 are more efficiently used, and each independent best Through the channels (or ways), the plurality of commands received from the host 102 and the execution results of command operations corresponding to the commands are respectively transmitted and received, thereby further improving the operating performance of the memory system 110. You can. Here, in an embodiment of the present disclosure, for convenience of description, the host 102 may be configured through a plurality of channels (or ways) for memory dies included in the memory device 150 of the memory system 110. Although a case of transmitting / receiving a plurality of commands received from the command and execution results of command operations corresponding to the commands is described as an example, in a plurality of memory systems including the controller 130 and the memory device 150, respectively, After the plurality of commands received from the host 102 and the command operations corresponding to the commands are performed in the respective memory systems through the plurality of channels (or ways) for the respective memory systems, The same may be applied to the case of transmitting / receiving the execution results of.

In other words, in an embodiment of the present disclosure, when the memory system 110 including the controller 130 and the memory device 150 receives a plurality of commands from the host 102 in a data processing system in which a plurality of data systems exist, The plurality of commands received from the host 102 may be configured to perform command operations corresponding to the plurality of commands in the plurality of memory systems including the controller 130 and the memory device 150, respectively. Transmits through a plurality of channels (or ways) for a plurality of channels, and also receives, through a plurality of channels (or ways), a result of performing command operations in a plurality of memory systems. do. At this time, in the embodiment of the present invention, any memory system, such as a master memory system that performs control and management functions for the plurality of memory systems, may include a plurality of channels (or Ways), then independently determine the best transmit channels (or transmit ways) and receive channels (or receive ways), and then the best transmit channels (or transmit ways) and receive channels (or receive ways). Through the plurality of commands and the results of performing the command operations, respectively.

Here, in an embodiment of the present invention, corresponding to the information of the plurality of memory systems, the first memory system in the plurality of memory systems to determine the master memory system, or through the contention (contention) between the plurality of memory systems After determining the first memory system as the master memory system, the remaining memory systems are determined as slave memory systems. In addition, in an embodiment of the present invention, after the controller of the master memory system checks the states of the plurality of channels (or ways) for the plurality of memory systems, the controller of the master memory system corresponds to the state of the channels (or ways). The best channels (or ways) are determined independently of the transmission channels (or transmission ways) and the reception channels (or reception ways), respectively. In an embodiment of the present disclosure, the controller of the master memory system may transmit a plurality of commands received from the host 102 through the best transmission channels (or transmission ways) to correspond to the corresponding memory in the plurality of memory systems. Send to the systems, receive the results of the execution of the command operations corresponding to the plurality of commands from the corresponding memory systems in the plurality of memory systems, via the best receive channels (or receive ways), and the command operation Provide the results of the performance to the host 102 in response to the plurality of commands received from the host 102. Here, in the embodiment of the present invention, the master memory system is changed from the first memory system to the other remaining memory systems according to the information of the memory systems or through the competition between the memory systems, that is, in the slave memory systems. The second memory system may be dynamically changed. When the second memory system becomes a master memory system, the first memory system becomes a slave memory system.

That is, in the exemplary embodiment of the present invention, as described above, the controller 130 included in the memory system 110 includes a plurality of channels (or ways) for the memory device 150 of the memory system 110. In particular, the state of the channels (or ways) between the plurality of memory dies included in the memory device 150 and the controller 130 may be checked, or any memory system in the plurality of memory systems, such as a master memory system. The controller of the state of the plurality of channels (or ways) for the plurality of memory systems, in particular the state of the channels (or ways) between the master memory system and the remaining memory systems, such as the master memory system and slave memory systems Check it. In other words, in an embodiment of the present invention, a plurality of channels (or ways) for memory dies of the memory device 150, or a plurality of channels (or ways) for a plurality of memory systems, Check if busy, ready, active, idle, normal, abnormal, etc. Here, in an embodiment of the present invention, channels (or ways) in a ready state or an idle state may be determined as the best channels (or ways) in a normal state. In particular, in an embodiment of the present invention, in a plurality of channels (or ways), a channel in which the available capacity of the channel (or way) is in the normal range or the operating level of the channel (or way) is in the normal range Determine the (or ways) the best channels. Here, the operation level of a channel (or way) may be determined by an operation clock, a power level, a current / voltage level, an operation timing, a temperature level, and the like in each channel (or ways).

In addition, in an embodiment of the present invention, write data corresponding to a plurality of write commands received from the host 102 is stored in a buffer / cache included in the memory 144 of the controller 130. After storing, the data stored in the buffer / cache is programmed into a plurality of memory blocks included in the memory device 150 to store, that is, perform program operations, and also correspond to program operations to the memory device 150. After updating the map data, when the updated map data is stored in the plurality of memory blocks included in the memory device 150, that is, program operations corresponding to the plurality of write commands received from the host 102 may be performed. The case will be described as an example. In an embodiment of the present disclosure, when a plurality of read commands are received from the host 102 with respect to the data stored in the memory device 150, the map data of the data corresponding to the read commands is checked and the memory device is checked. Data corresponding to the read commands is read from the 150, and the read data is stored in the buffer / cache included in the memory 144 of the controller 130, and then the data stored in the buffer / cache is stored in the host 102. For example, a case in which read operations corresponding to a plurality of read commands received from the host 102 are performed will be described. In addition, in an embodiment of the present disclosure, when a plurality of erase commands are received from the host 102 with respect to the memory blocks included in the memory device 150, after checking the memory blocks corresponding to the erase commands, And erasing the data stored in the checked memory blocks, updating the map data corresponding to the erased data, and then storing the updated map data in the plurality of memory blocks included in the memory device 150. A case of performing erase operations corresponding to a plurality of erase commands received from the host 102 will be described as an example. In addition, in the embodiment of the present invention, in addition, in the embodiment of the present invention, a plurality of write commands, a plurality of read commands and a plurality of erase commands are received from the host 102 described above, and thus a plurality of program operations are performed. And read operations and erase operations will be described as an example.

In addition, in the embodiment of the present disclosure, for convenience of description, the controller 130 performs command operations in the memory system 110 as an example, but as described above, the controller 130 The included processor 134 may perform, eg, via FTL. For example, in an embodiment of the present disclosure, the controller 130 may include user data and metadata corresponding to write commands received from the host 102 in the memory device 150. Program the user data and the meta data corresponding to the read commands received from the host 102 or store the user data and metadata corresponding to the read commands received from the host 102. The plurality of memory blocks included in the memory device 150 may be read from any memory blocks and provided to the host 102 or the user data and metadata corresponding to the erase commands received from the host 102. Erases in any memory blocks.

Here, the meta data may include logical / physical (L2P) information (hereinafter, referred to as 'logical information') of data stored in the memory blocks, corresponding to a program operation. Second map data including first map data and physical to logical (P2L) information (hereinafter referred to as 'physical information'), and also received from the host 102. Information about the command data corresponding to the command, information about the command operation corresponding to the command, information about the memory blocks of the memory device 150 where the command operation is performed, and map data corresponding to the command operation May be included. In other words, the metadata may include all the information and data except for the user data corresponding to the command received from the host 102.

That is, in the embodiment of the present invention, when the controller 130 performs command operations corresponding to the plurality of commands received from the host 102, for example, when receiving the plurality of write commands from the host 102, the write command is performed. Program operations corresponding to the first and second write operations, wherein the user data corresponding to the write commands is stored in the memory blocks of the memory device 150, for example, the empty memory blocks in which the erase operation is performed on the memory blocks. Write and store in open memory blocks or free memory blocks, and also between logical and physical addresses for user data stored in the memory blocks. First map data including mapping information, that is, L2P map table or L2P map list in which logical information is recorded, and memory in which user data is stored. Mapping information between physical addresses and logical addresses for the blocks, that is, second map data including a P2L map table or a P2L map list on which physical information is recorded, the empty memory blocks in the memory blocks of the memory device 150, Write to and store in open memory blocks or free memory blocks.

Here, when receiving the write commands from the host 102, the controller 130 writes and stores user data corresponding to the write commands in the memory blocks, and first maps the user data stored in the memory blocks. Meta data including data, second map data, and the like are stored in memory blocks. In particular, the controller 130 corresponds to meta segments of metadata, i.e., maps of map data, as data segments of user data are stored in memory blocks of the memory device 150. After generating and updating the L2P segments of the first map data and the P2L segments of the second map data into segments, the memory blocks are stored in the memory blocks of the memory device 150. The map segments stored in the memory blocks of the controller 130 are loaded into the memory 144 included in the controller 130 to update the map segments.

In particular, in the embodiment of the present invention, as described above, when receiving a plurality of write commands from the host 102, the state of the plurality of channels (or ways) to the memory device 150, particularly, After checking a state of a plurality of channels (or ways) connected to a plurality of memory dies included in the memory device 150, the best transport channels (or transmissions) corresponding to the state of the channels (or ways) are determined. Ways) and the best receive channels (or receive ways) are each determined independently. In an embodiment of the present invention, the user data and metadata corresponding to the write command are transmitted to the corresponding memory dies of the memory device 150 through the best transmission channels (or transmission ways), and stored. That is, to perform program operations, and to perform the results of the program operations on corresponding memory dies of the memory device 150, through the best receive channels (or receive ways), to the corresponding memory die of the memory device 150. Received from the server, and provided to the host 102.

In addition, when the controller 130 receives a plurality of read commands from the host 102, the controller 130 reads read data corresponding to the read commands from the memory device 150, and thus the memory 144 of the controller 130. After storing the buffer / cache included in the, data stored in the buffer / cache is provided from the host 102 to perform read operations corresponding to the plurality of read commands.

In particular, in the embodiment of the present invention, as described above, when receiving a plurality of read commands from the host 102, the state of the plurality of channels (or ways) to the memory device 150, particularly, After checking a state of a plurality of channels (or ways) connected to a plurality of memory dies included in the memory device 150, the best transport channels (or transmissions) corresponding to the state of the channels (or ways) are determined. Ways) and the best receive channels (or receive ways) are each determined independently. In an embodiment of the present disclosure, a read request of user data and metadata corresponding to a read command is transmitted to corresponding memory dies of the memory device 150 through the best transmission channels (or transmission ways). Performing the read operations, and also performing the results of performing the read operations in corresponding memory dies of the memory device 150, ie, user data and metadata corresponding to the read command, for the best receive channels (or receive ways). ) Is received from corresponding memory dies of memory device 150 to provide user data to host 102.

In addition, when the controller 130 receives a plurality of erase commands from the host 102, the controller 130 checks the memory blocks of the memory device 150 corresponding to the erase commands, and then erases the memory blocks. Perform them.

In particular, according to an embodiment of the present invention, when receiving a plurality of erase commands from the host 102, as described above, the status of the plurality of channels (or ways) for the memory device 150, In particular, after checking a state of a plurality of channels (or ways) connected to a plurality of memory dies included in the memory device 150, corresponding to the state of the channels (or ways), the best transport channels (or Transmit ways) and the best receive channels (or receive ways) are each determined independently. In addition, according to an embodiment of the present invention, an erase request for memory blocks in memory dies of the memory device 150 corresponding to the erase command may be performed through the best transmission channels (or transmission ways). Transmits to corresponding memory dies of 150 to perform erase operations, and also performs results of performing erase operations on corresponding memory dies of memory device 150 to the best receive channels (or receive ways). Through the received from the corresponding memory die of the memory device 150, it provides to the host (102).

Thus, in the memory system 110 according to the embodiment of the present invention, when receiving a plurality of commands from the host 102, that is, a plurality of write commands, a plurality of read commands and a plurality of erase commands, in particular, When the plurality of commands are sequentially received at the same time, as described above, after checking the states of the plurality of channels (or ways) with respect to the memory device 150, the states corresponding to the states of the channels (or ways) are determined. A command corresponding to a plurality of commands, independently determining the best transmission channels (or transmission ways) and the best reception channels (or reception ways), and through the best transmission channels (or transmission ways) Request the performance of the operations to the memory device 150, in particular the execution of corresponding command operations in a plurality of memory dies included in the memory device 150, Through the channels (or reception-way), it receives the execution result for the command operation, from a memory die of a memory device 150. In the memory system 110 according to an embodiment of the present invention, commands transmitted through the best transmission channels (or transmission ways) and execution results received through the best reception channels (or reception ways). The match is provided to provide the host 102 with a response to the plurality of commands received from the host 102.

Here, in the exemplary embodiment of the present invention, as described above, the controller 130 included in the memory system 110 includes a plurality of channels (or ways) for the memory device 150 of the memory system 110. In particular, after checking the state of the channels (or ways) between the plurality of memory dies included in the memory device 150 and the controller 130, the best transport channels (or transfer ways) for the memory device 150 are determined. ) And the best receive channels (or receive ways) independently of each other, as well as the controller of any memory system, such as a master memory system, in a plurality of memory systems, a plurality of channels for the plurality of memory systems (Or ways), in particular after checking the status of the channels (or ways) between the master memory system and the remaining memory systems, such as the master memory system and the slave memory systems, The best transmission channels (or transmission ways) and the best reception channels (or reception ways) for the memory systems are each determined independently. In other words, in an embodiment of the present invention, a plurality of channels (or ways) for memory dies of the memory device 150, or a plurality of channels (or ways) for a plurality of memory systems, Check if busy, ready, active, idle, normal, abnormal, etc., and determine the channels (or ways) of the ready or idle state in the normal state as the best channels (or ways), for example. do. In particular, in an embodiment of the present invention, in a plurality of channels (or ways), a channel in which the available capacity of the channel (or way) is in the normal range or the operating level of the channel (or way) is in the normal range Determine the (or ways) the best channels. Here, the operation level of a channel (or way) may be determined by an operation clock, a power level, a current / voltage level, an operation timing, a temperature level, and the like in each channel (or ways). In addition, in an embodiment of the present invention, information of each memory system, for example, the capability of command operations in the controller 130 and the memory device 150 included in each memory system or each memory system, For example, in a plurality of memory systems, a master memory system may be configured to correspond to performance capability, process capability, process speed, process latency, and the like for command operations. Decide Here, the master memory system may be determined through competition between a plurality of memory systems. For example, the master memory system may be determined through competition according to a connection order between the host 102 and each memory system. Next, the execution of command operations corresponding to a plurality of commands in the memory system of the present invention will be described in more detail with reference to FIGS. 4 to 5.

First, referring to FIG. 4, the controller 130 performs command operations corresponding to a plurality of commands received from the host 102, for example, a program corresponding to a plurality of write commands received from the host 102. In this case, the user data corresponding to the write commands is programmed and stored in the memory blocks 552, 554, 562, 564, 572, 574, 582, and 584 of the memory device 150, and the user data corresponding to the program operations to the memory blocks 552, 554, 562, 564, 572, 574,582, 584. After generating and updating the metadata for the memory, the memory block 150 is stored in the memory blocks 552, 554, 562, 564, 572, 574, 582 and 584 of the memory device 150.

Herein, the controller 130 generates and updates information indicating that user data is stored in pages included in 552, 554, 562, 564, 572, 574, 582 and 584 of the memory device 150, for example, the first map data and the second map data. Pages included in the memory blocks 552, 554, 562, 564, 572, 574, 582, and 584 of the memory device 150 after creating and updating logical segments of one map data, that is, L2P segments, and second physical map segments, that is, P2L segments. Store in the field.

For example, the controller 130 may cache and buffer user data corresponding to write commands received from the host 102 to the first buffer 510 included in the memory 144 of the controller 130. (buffering), that is, after storing the data segments 512 of the user data in the first buffer 510 which is a data buffer / cache, the data segments 512 stored in the first buffer 510 are stored in the memory device ( And the pages included in the memory blocks 552, 554, 562, 564, 572, 574, 582, and 584 of 150. The controller 130 may include data segments 512 of user data corresponding to write commands received from the host 102 in pages included in the memory blocks 552, 554, 562, 564, 572, 574, 582, and 584 of the memory device 150. As programmed and stored, the first map data and the second map data are generated and updated, and stored in the second buffer 520 included in the memory 144 of the controller 130, that is, the first map for the user data. The L2P segments 522 of data and the P2L segments 524 of the second map data are stored in the second buffer 520 which is a map buffer / cache. Here, the L2P segments 522 of the first map data and the P2L segments 524 of the second map data are stored in the second buffer 520 in the memory 144 of the controller 130 as described above. Alternatively, the map list for the L2P segments 522 of the first map data and the map list for the P2L segments 524 of the second map data may be stored. In addition, the controller 130 may include the L2P segments 522 of the first map data and the P2L segments 524 of the second map data stored in the second buffer 520, and the memory blocks of the memory device 150. It stores in the pages included in (552,554,562,564,572,574,582,584).

In addition, the controller 130 performs command operations corresponding to the plurality of commands received from the host 102, for example, performs read operations corresponding to the plurality of read commands received from the host 102. Map segments of the user data corresponding to the read commands, for example, the L2P segments 522 of the first map data and the P2L segments 524 of the second map data, are loaded into the second buffer 520 and then checked. Reads the user data stored in the pages of the corresponding memory blocks from the memory blocks 552, 554, 562, 564, 572, 574, 582 and 584 of the memory device 150, and stores the data segments 512 of the read user data in the first buffer 510. The host 102 then provides the host 102.

In addition, the controller 130 performs command operations corresponding to the plurality of commands received from the host 102, for example, performs the erase operations corresponding to the plurality of erase commands received from the host 102. In this case, the memory blocks corresponding to the erase commands are checked in the memory blocks 552, 554, 562, 564, 572, 574, 582 and 584 of the memory device 150, and then the erase blocks are performed on the identified memory blocks.

Also, referring to FIG. 5, the memory device 150 may include a plurality of memory dies, for example, memory die 0 610, memory die 1 630, memory die 2 650, and memory die 3. 670, each of the memory dies 610, 630, 650, 670 including a plurality of planes, such as memory die 0 610, plane 0 612, plane 1 616, Plane 2 620, plane 3 624, memory die 1 630, plane 0 632, plane 1 636, plane 2 640, plane 3 ( Memory die 2 650 includes plane 0 652, plane 1 656, plane 2 660, plane 3 664, and memory die 3 670; ) Includes plane 0 672, plane 1 676, plane 2 680, and plane 3 684. The planes 612, 616, 620, 624, 632, 636, 640, 644, 652, 656, 660, 664, 672, and 676 of the memory dies 610, 630, 650, and 670 included in the memory device 150. , 680, 684 include a plurality of memory blocks 614, 618, 622, 626, 634, 638, 642, 646, 654, 658, 662, 666, 674, 678, 682, 686, for example, prior to as explained in Figure 2, includes an N number of blocks (Block0, Block1, ..., block N-1) comprising a plurality of pages, for example, 2 ^M in pages (pages 2 ^M). In addition, the memory device 150 may correspond to a plurality of buffers corresponding to each of the memory dies 610, 630, 650, and 670, for example, the buffer 0 628 corresponding to the memory die 0 610 and the memory die 1 630. Buffer 1 648, buffer 2 668 corresponding to memory die 2 650, and buffer 3 688 corresponding to memory die 3 670.

The buffers 628, 648, 668, and 688 included in the memory device 150 store data corresponding to the command operations when the command operations corresponding to the plurality of commands received from the host 102 are performed. For example, when performing program operations, data corresponding to the program operations are stored in the buffers 628, 648, 668, and 688, and then stored in pages included in the memory blocks of the memory dies 610, 630, 650, and 670, and performing read operations. In this case, the data corresponding to the read operations are read from the pages included in the memory blocks of the memory dies 610, 630, 650, 670 and stored in the buffers 628, 648, 668, 688, and then the controller 130 is connected to the host 102. Is provided.

In this embodiment, the buffers 628, 648, 668, and 688 included in the memory device 150 are disposed outside the corresponding memory dies 610, 630, 650, and 670, respectively. However, according to an exemplary embodiment, each of the memory dies 610, 630, 650, 670 may be included in the memory dies 610, 630, 650, and 670. Further, in accordance with an embodiment, the plurality of buffers 628, 648, 668, 688 may each include planes 612, 616, 620, 624, 632, 636, 640, 644, 652, 656, included in each memory die 610, 630, 650, 670. 660, 664, 672, 676, 680, 684 or each memory block (614, 618, 622, 626, 634, 638, 642, 646, 654, 658, 662, 666, 674, 678, 682, 686) It may correspond to. Also, according to an embodiment, the buffers 628, 648, 668, and 688 included in the memory device 150 may be a plurality of caches or a plurality of registers included in the memory device 150.

Hereinafter, a method and apparatus for transferring data in the above-described memory system, for example, the memory system 110 including the controller 130 and the memory device 150 will be described in more detail. The amount of data stored in the memory system 110 is growing larger, and the memory system 110 is required to read or store a large amount of data at a time. Meanwhile, a time for reading data stored in the memory device 150 in the memory system 110 or a time for writing data in the memory device 150 may be a time for the controller 130 to process data or a controller 130 and a memory device ( 150) longer than the time data is passed between them. Since the time to read or write data to the memory device 150 has a relatively large difference (eg, twice) than the speed at which the controller 130 or the host processes the data, the memory system 110 operates faster. In order to more efficiently improve the process of transferring data, this may affect the size of the buffer included in the memory system 110.

6 to 11 illustrate examples of improving operating efficiency of a memory system. Specifically, FIGS. 6 to 8 illustrate a case where a memory included in the host is used as a cache device for storing metadata, and FIGS. 9 to 11 illustrate metadata of a partial region of the memory included in the host. In addition, the case where the user data is used as a temporary storage device will be described.

Referring to FIG. 6, the host 102 may include a processor 104, a memory 106, and a host controller interface 108. The memory system 110 may include a controller 130 and a memory device 150. The controller 130 and the memory device 150 described with reference to FIG. 6 may be similar to the controller 130 and the memory device 150 described with reference to FIGS. 1 to 5.

Hereinafter, descriptions will be given based on the technically distinguishable contents of the controller 130 and the memory device 150 described with reference to FIG. 6 and the controller 130 and the memory device 150 described with reference to FIGS. 1 to 5. . In particular, the logic block 160 in the controller 130 may correspond to the flash translation layer (FTL) unit 40 described in FIG. 3. However, in some embodiments, the logic block 160 in the controller 130 may further perform roles and functions not described in the flash translation layer (FTL) unit 40.

The host 102 may include a high performance processor 104 and a large memory 106 as compared to the memory system 110 that cooperates with the host 102. Unlike the memory system 110, the processor 104 and the memory 106 in the host 102 have less space constraints, and hardware upgrade of the processor 104 and the memory 106 can be performed if necessary. have. Therefore, the memory system 110 may utilize resources of the host 102 in order to increase operational efficiency.

As the amount of data that the memory system 110 can store increases, the amount of metadata corresponding to the data stored in the memory system 110 also increases. Since the space of the memory 144 in which the controller 130 in the memory system 110 can load the metadata is limited, an increase in the amount of metadata burdens the operation of the controller 130. For example, the controller 130 may load some but not all of the metadata due to space constraints in the memory 144 that the controller 130 may allocate for the metadata. If the location that the host 102 wants to access is not included in the partially loaded metadata, the controller 130 must store the loaded metadata again in the memory device 150 if some of the loaded metadata is updated. The metadata corresponding to the location that the host 102 wants to access should be read from the memory device 150. These operations may be necessary for the controller 130 to perform a read or write operation required by the host 102, and may degrade operating performance of the memory system 110.

In some embodiments, the storage space of the memory 106 included in the host 102 may be several tens to thousands of times larger than the memory 144 that the controller 130 may use. Accordingly, the memory system 110 transmits the meta data 166 used by the controller 130 to the memory 106 in the host 102, so that the memory 106 in the host 102 is stored in the memory system 110. Can be used as cache memory for address translation. In this case, the host 102 does not send the logical address with the command to the memory system 110, but converts the logical address into a physical address based on the metadata 166 stored in the memory 106 and then with the command. The physical address may be passed to the memory system 110. The memory system 110 may omit the process of converting a logical address into a physical address and may access the memory device 150 based on the transferred physical address. In this case, the controller 130 described above can solve the operation burden generated while using the memory 144, the operation efficiency of the memory system 110 can be very high.

On the other hand, even if the memory system 110 transmits the metadata 166 to the host 102, the memory system 110 manages information (ie, updating, deleting, or Generation, etc.). The controller 130 in the memory system 110 may perform background operations such as garbage collection and wear leveling according to the operating state of the memory device 150, and may transmit data transferred from the host 102 to the memory device 150. The physical address of the data in the memory device 150 may be changed since the physical location (physical address) of storing the data in the memory device may be determined. Therefore, the memory system 110 may take charge of managing a source of the metadata 166.

That is, when it is determined that the memory system 110 needs to modify and update the metadata 166 transmitted to the host 102 in the process of managing the metadata 166, the memory system 110 determines that the host ( 102 may be requested to update the metadata 166. The host 102 may update the metadata 166 stored in the memory 106 in response to a request of the memory system 110. Through this, the metadata 166 stored in the memory 106 in the host 102 may be kept up to date, and the host controller interface 108 may use the metadata 166 stored in the memory 106 using the memory system. Even if the address value to be transmitted to 110 is converted, the operation may not occur.

Meanwhile, the metadata 166 stored in the memory 106 may include first mapping information for identifying a physical address corresponding to a logical address. Referring to FIG. 4, in the metadata corresponding to a logical address and a physical address, first mapping information for identifying a physical address corresponding to the logical address and a logical address corresponding to the physical address are identified. Second mapping information may be included. Among these, the metadata 166 stored in the memory 106 may include first mapping information. The second mapping information is mainly used for the internal operation of the memory system 110, and the host 102 may store data in the memory system 110 or read data from the memory system 110 corresponding to a specific logical address. It may not be used for operation. In some embodiments, the second mapping information may not be transmitted from the memory system 110 to the host 102.

Meanwhile, the controller 130 in the memory system 110 manages (creates, deletes, or updates) the first mapping information or the second mapping information, and transmits the first mapping information or the second mapping information to the memory device 150. Can be stored. Since the memory 106 in the host 102 is a volatile memory device, the memory 106 in the host 102 is stored in the memory 106 in the host 102 when an event such as a power supply interruption occurs in the host 102 and the memory system 110. Meta data 166 may disappear. Accordingly, the controller 130 in the memory system 110 not only maintains the metadata 166 stored in the memory 106 in the host 102 in the latest state, but also maintains the first mapping information or the second mapping information in the latest state. It may be stored in the memory device 150.

6 and 7, when the meta data 166 is stored in the memory 106 in the host 102, an operation of reading the data in the memory system 110 by the host 102 will be described.

Power is supplied to the host 102 and the memory system 110, and the host 102 and the memory system 110 may interoperate. When the host 102 and the memory system 110 interoperate, metadata L2P MAP stored in the memory device 150 may be transmitted to the host memory 106.

When a read command is generated by the processor 104 in the host 102, the read command is sent to the host controller interface 108. After receiving the read command, the host controller interface 108 transmits a logical address corresponding to the read command to the host memory 106. Based on the metadata L2P MAP stored in the host memory 106, the host controller interface 108 may recognize a physical address corresponding to a logical address.

The host controller interface 108 transmits a read command (Read CMD) together with the physical address to the controller 130 in the memory system 110. The controller 130 may access the memory device 150 based on the received read command and the physical address. Data stored at a location corresponding to a physical address in the memory device 150 may be transferred to the host memory 106.

The process of reading data from the memory device 150 including the nonvolatile memory device may take more time than the process of reading data from the host memory 106, which is another nonvolatile memory. In the above-described reading process, the controller 130 may receive a logical address from the host 102 and find a corresponding physical address. In particular, in the process of finding the physical address, the controller 130 may disappear from accessing the memory device 150 to read metadata. Through this, the process of reading the data stored in the memory system 110 by the host 102 may be faster.

6 and 8, a process of updating the meta data L2P MAP stored in the host memory 106 will be described.

The memory system 110 interworking with the host 102 may perform a read operation, a write operation, and a delete operation of data required by the host 102. After performing a read operation, a write operation, or a delete operation on the data required by the host 102, the memory system 110 may update the metadata when a change in the position of the data in the memory device 150 occurs. Meanwhile, even when the host 102 does not request it, the memory system 110 updates metadata in response to a change in the position of the data in the memory device 150 in the process of performing a background operation (eg, garbage collection or wear leveling). can do. The controller 130 in the memory system 110 may detect whether metadata is updated through the above-described operation. That is, the controller 130 may check the dirty map as the metadata undergoes a process of generating, updating, and deleting.

If the metadata is messy, the controller 130 notifies the host controller interface 108 of the need to update the metadata. The host controller interface 108 may request metadata to be updated from the controller 130 (request map info.). The controller 130 may transmit metadata that needs to be updated in response to a request of the host controller interface 108 (send map info.). The host controller interface 108 may transfer the transferred metadata to the host memory 106 to update the stored metadata (L2P map update).

Referring to FIG. 9, the controller 130 and the memory device 150 in the memory system 110 interoperating with the host 102 may include the controller 130 and the memory device 150 in the memory system 110 described with reference to FIG. 6. Similar to However, the configuration, operation, or role of the controller 130 in the memory system 110 may be technically distinguished from the controller 130 described with reference to FIG. 6.

In addition, the host 102 may include a processor 104, a memory 106, and a host controller interface 108. The host 102 described with reference to FIG. 9 may have a configuration similar to that of the host 102 described with reference to FIG. 6, but with respect to the configuration, operation, or role of the memory 106 and the host controller interface 108. It can be technically distinguished from the embodiment.

In FIG. 6, the memory system 110 included in the host 102 may be used as a cache memory that stores the metadata 166 in FIG. 6. However, the memory system 110 described in FIG. ) Can be used as a buffer for storing user data 168. In FIG. 9, the memory 106 included in the host 102 stores user data 168 as an example. However, not only the user data 168 but also metadata may be stored.

Referring to FIG. 9, the memory 106 included in the host 102 may be divided into an operation region and an integrated region. Here, the operation region of the memory 106 may be a space used for storing data in the process of the host 102 performing some operation through the processor 104. On the other hand, the unified area of the memory 106 may be an area used to support the operation of the memory system 110 rather than the host 102.

In the unified area, the host 102 allocates a part of the memory 106 to the memory system 110 and may not use the unified area for the operation of the host 102. The memory system 110 may include a memory device 150 that is a nonvolatile memory device that takes more time to read, write, and erase than the memory 106 in the host 102, which is a volatile memory device. When the time required to read and write data in response to the request of the host 102 becomes long, a latency may occur in the memory system 110 to continuously perform the read and write commands required. Therefore, in order to increase the operational efficiency of the memory system 110, an integrated area in the host 102 may be used as a temporary storage device of the memory system 110.

For example, when the host 102 wants to write a large amount of data to the memory system 110, it may take a long time for the memory system 110 to program a large amount of data into the memory device 150. When the host 102 wants to write or read other data to or from the memory system 110, the host 102 may write other data due to the time that the memory system 110 programs a large amount of data in the memory device 150. Writing or reading may be delayed. In this case, the memory system 110 may request the host 102 to copy the large amount of data to the integrated area of the memory 106 in the host without programming the large amount of data in the memory device 150. Since the time required for copying data inside the host 102 is much shorter than the time required for the memory system 110 to program a large amount of data into the memory device 150, the operation of writing or reading other data is prevented from being delayed. can do. Thereafter, when the memory system 110 does not receive a command to read, write, or delete data from the host 102, the memory device 110 stores data stored in an integrated area of the memory 106 in the host 102. Can be moved to In this way, the user is not aware of the problem that the operation may be slowed by the memory system 110 including the nonvolatile memory device and the host 102 and the memory system 110 handle the user's request at a high speed. I can think of it.

The controller 130 in the memory system 110 is allocated a portion of the memory 106 in the host 102 (eg, an integrated area) from the host 102, while the host 102 is internal to the memory system 110. It may not be involved in the operation. The host 102 may transmit a read, write, or delete command to the memory system 110 along with the logical address, and the controller 130 in the memory system 110 may convert the logical address into a physical address. If the storage capacity of the memory 144 in the controller 130 is so small that it cannot load the metadata used to translate the logical address into a physical address, the controller 130 may execute the memory 106 in the host 102. You can store metadata in the integration area of). The controller 130 may recognize the physical address corresponding to the logical address transferred from the host 102 through metadata stored in the integrated area of the memory 106 in the host.

The operating speed of the memory 106 in the host and the communication speed between the host 102 and the controller 130 may be faster than the speed at which the controller 130 accesses the memory device 150 to read data. Thus, rather than reading the metadata from the memory device 150 as needed, the controller 130 loads the metadata into the memory 106 in the host 102 and then retrieves the metadata from the memory 106 as needed. Reading may be faster.

9 and 10, when the meta data L2P MAP is stored in the memory 106 in the host 102, an operation of reading the data in the memory system 110 by the host 102 will be described.

Power is supplied to the host 102 and the memory system 110, and the host 102 and the memory system 110 may interoperate. When the host 102 and the memory system 110 interoperate, metadata L2P MAP stored in the memory device 150 may be transmitted to the host memory 106. The storage capacity of the host memory 106 may be larger than the storage capacity of the memory 144 used by the controller 130 in the memory system 110. Therefore, even if all or a part of the metadata (L2P MAP) stored in the memory device 150 is transmitted to the host memory 106, but not part of the metadata (L2P MAP) may not burden the operation of the host 102 and memory system 110. . In this case, the meta data L2P MAP transferred to the host memory 106 may be stored in the integrated area described with reference to FIG. 9.

When a read command is generated by the processor 104 in the host 102, the read command is sent to the host controller interface 108. After receiving the read command, the host controller interface 108 may transmit the read command along with the logical address to the controller 130 in the memory system 110.

The controller 130 in the memory system 110 may request meta data corresponding to the logical address from the host controller interface 108 (L2P Request). The host controller interface 108 may transmit a portion of the meta data L2P MAP stored in the host memory 106 to the memory system 110 in response to a request of the controller 130.

As the storage capacity of the memory device 150 increases, the range of logical addresses may also widen. For example, the value of the logical address may be millions or more (eg, LBN1 to LBN2 * 10 ⁹ ) corresponding to the storage capacity of the memory device 150, and the host memory 106 may be configured to most or all logical address values. While sufficient storage space may be secured to store corresponding metadata, the memory 144 in the memory system 110 may not. Since the logical address passed by the host 102 with a read command may belong to a specific range (eg, LBN120-LBN600), the controller 130 may specify a specific range of logical addresses delivered by the host 102 (eg, LBN120-LBN600). Only the meta data (eg, LBN100 to LBN800) that may include may request the host controller interface 108. The host controller interface 108 may transfer the metadata L2P MAP in a range requested by the controller 130, and the transferred metadata L2P MAP may be stored in the memory 144 in the memory system 110. have.

The controller 130 may recognize a physical address corresponding to a logical address transmitted by the host 102 based on the meta data L2P MAP stored in the memory 144. The controller 130 may access the memory device 150 using a physical address, and data requested by the host 102 may be transferred from the memory device 150 to the host memory 106. . In this case, the data transferred from the memory device 150 may be stored in an operation area of the host memory 106.

As described above, by using the host memory 106 as a buffer for storing the metadata L2P MAP, the metadata L2P MAP is stored in the memory due to the limitation of the storage space of the memory 144 in the memory system 110. The process of reading from the device 150 and storing again may be omitted. Through this, the operating efficiency of the memory system 110 may be increased.

9 and 11, an example in which the memory system 110 uses the memory 106 in the host 102 as a data buffer will be described in response to the write command of the host 102. In FIG. 11, the memory 106 in the host 102 is divided into an operation region 106A and an integrated region 106B.

When a write command is issued by the processor 104 in the host 102, the write command is sent to the host controller interface 108. Here, the write command may be accompanied by data. The amount of data transferred with the write command may be equal to or smaller than one page, or larger than or equal to a plurality of pages or blocks. Here, it may be assumed that the size of data accompanying the write command is very large.

The host controller interface 108 notifies a write command (Write CMD) to the controller 130 in the memory system 110. In this case, the controller 130 may request the host controller interface 108 to copy data corresponding to the write command (Write CMD) (Copy Data). That is, the controller 130 may use the integrated area 106B as a write buffer instead of receiving data accompanying the write command.

The host controller interface 108 may copy data corresponding to the write command Write CMD stored in the operation area 106A to the integration area 106B. Thereafter, the host controller interface 108 may notify the controller 130 that the copy is completed in response to the copy request (Copy Ack). When the controller 130 confirms that the data corresponding to the write command Write CMD is copied from the host controller interface 108 to the integration area 106B, the controller 130 performs an operation corresponding to the write command Write CMD to the host controller interface 108. It may notify that it is completed (Write Response).

When the operation for the write command (Write CMD) involving a large amount of data is completed through the above-described process, the memory system 110 may be in a state capable of performing the next command of the host 102. have.

Meanwhile, data corresponding to the write command Write CMD stored in the integration area 106B may be transferred to the memory device 150 by the memory system 110 when there is no command from the host 102.

As described above, the operation efficiency of the memory system 110 may be improved based on the different embodiments described with reference to FIGS. 6 to 8 and 9 to 11. The memory system 110 uses a portion of the memory 106 included in the host 102 as a cache or a buffer, stores metadata or user data, and controls the controller in the memory system 110. The storage space of the memory 144 used by the 130 may be overcome.

12 illustrates a configuration of a plurality of memory systems. Specifically, in the configuration of the plurality of memory systems described with reference to FIG. 12, the plurality of memory systems 100A, 100B,..., And 100N interwork with one host 102 (see FIGS. 1 through 3 and 6 through 11). It can be applied to the data processing system 100 (see FIG. 1).

Referring to FIG. 12, the plurality of memory systems 100A, 100B,..., And 100N may include a first memory system 100A having a higher priority than other memory systems 100B,..., 100N. The number of the plurality of memory systems 100A, 100B, ..., 100N may be determined according to the system configuration.

Each of the plurality of memory systems 100A, 100B,..., 100N may include a configuration capable of operating independently of the host 102. For example, even if the second memory system 100B is disconnected from the host 102 with which the second memory system 100B is currently interworking, the second memory system 100B may be connected to and used with another host. Accordingly, each of the plurality of memory systems 100A, 100B,..., 100N may include a specific area (eg, Master Boot Record (MBR), 40_1, etc.) that can store information for connecting to other devices. .

According to an embodiment, when a plurality of memory systems 100A, 100B, ..., 100N interlock with one host 102, the first memory system has a higher priority than other memory systems 100B, ..., 100N. The 100A may include a metadata block 40_2 that stores metadata about the plurality of memory systems 100A, 100B,..., 100N. The host 102 uses metadata of the first memory system 100A having a high priority to determine which device among the plurality of memory systems 100A, 100B, ..., 100N to store, delete, or read data. I can deliver it.

According to an embodiment, unlike the first memory system 100A for storing metadata, other memory systems 100B, ..., 100N include a user data block 40_3 for storing user data without storing metadata. can do. Since the metadata is stored in the first memory system 100A, other memory systems 100B, ..., 100N can allocate more space for user data.

Meanwhile, the first memory system 100A may include a user data block 40_3 as well as a metadata block 40_2 that stores metadata. As metadata for the plurality of memory systems 100A, 100B,..., 100N increases, the number of metadata blocks 40_2 in the first memory system 100A may increase. In this case, the number of user data blocks 40_3 in the first memory system 100A may decrease.

The first memory system 100A having a high priority may allocate an address, invalidate an assigned address, or reallocate an invalidated address for the plurality of memory systems 100A, 100B,..., 100N. . For example, when a memory system is recognized by the host 102, the first memory system 100A may assign a logical identifier to the recognized memory system. The first memory system 100A may determine a logical identifier for the recognized memory system, and reserve a space for storing metadata for the recognized memory system in the metadata block 40_2 in the first memory system 100A. have. In addition, the first memory system 100A may notify the host 102 of a logical identifier for the recognized memory system.

On the other hand, when the first memory system 100A having a high priority has a problem or is predicted in operation, the priority and the role assigned to the first memory system 100A may be different from those of the other memory systems 100B, ..., 100N. Can be handed over to either. According to an embodiment, when the first memory system 100A is detachable and the interworking with the host is to be broken, the first memory system 100A may attach itself to one of the other memory systems 100B,..., 100N. You can transfer the privileges and roles you were playing.

According to an embodiment, at least one of the other memory systems 100B,..., 100N having a lower priority than the first memory system 110A may be disconnected from the host. Since at least one of the other memory systems 100B,..., 100N, which are disconnected from the host, may be interoperable with another host, metadata about data stored by the host when the linkage with the host is lost. May be transferred from the first memory system 110A. In this process, the host may transmit information on at least one of the other memory systems 100B,..., 100N, which will be disconnected from the host, to the first memory system 110A. The first memory system 110A may transmit metadata corresponding to at least one of the other memory systems 100B,..., 100N to be disconnected in response to the information received from the host.

According to an embodiment, the first memory system 110A may be connected to the first memory system 110A even if at least one of the other memory systems 100B,..., 100N that cooperates with the same host is electrically disconnected or disconnected. Meta data associated with at least one of the other memory systems 100B, ..., 100N stored may not be deleted. This is because at least one of the other memory systems 100B, ..., 100N, which have been temporarily disconnected, may interwork with the same host again.

The first memory system 110A may reconfigure the meta data when the preset condition is met. For example, when at least one of the other memory systems 100B,..., 100N is no longer available or reconnected for a predetermined period of time, the first memory system 110A may have a logical identifier assigned to the memory system. Maintaining the metadata area can lead to waste of resources. Accordingly, when the first memory system 110A reaches a preset condition, the first memory system 110A may perform reconstruction (eg, garbage collection) on metadata of the plurality of memory systems 100A, 100B,..., And 100N stored therein. Can be. In some embodiments, the reconstruction of the metadata for the plurality of memory systems 100A, 100B,..., And 100N may be performed every predetermined period (eg, 1 day, 1 week, or January).

13 illustrates an example of improving operation efficiency of a plurality of memory systems. In detail, when the plurality of memory systems 110A, 110B, and 110C interoperate with one host, the host memory 106 may be buffered in order to increase operational efficiency between the plurality of memory systems 110A, 110B, and 110C. buffer) is explained.

Referring to FIG. 13, metadata L2P MAP stored in the first memory system 110A having the highest priority among the plurality of memory systems 110A, 110B, and 110C may be transferred to the host memory 106.

When the host controller interface 108 receives a read command, the host controller interface 108 transmits a logical address corresponding to the read command to the first memory system 110A.

The controller in the first memory system 110A may attempt to convert a physical address based on metadata corresponding to a logical address corresponding to a read command. However, if the controller in the first memory system 110A does not find the metadata corresponding to the logical address, the host controller interface 108 may request the metadata corresponding to the logical address.

The host controller interface 108 may transfer a portion of the meta data stored in the host memory 106 corresponding to the logical address to the first memory system 110A. The first memory system 110A may translate a logical address into a physical address through some metadata transmitted from the host memory 106, and transmit the logical address to the host controller interface 108.

The host controller interface 108 may transmit a physical address and a read command to one of the plurality of memory systems 110A, 110B, and 110C, which may be selected corresponding to the physical address.

One of the plurality of memory systems 110A, 110B, and 110C having received the physical address and the read command may access a location corresponding to the physical address to transfer data to the host memory 106.

Through the above-described process, instead of reading metadata from the nonvolatile memory device in the address translation process that the first memory system 110A having the highest priority among the plurality of memory systems 110A, 110B, and 110C may perform. There is an advantage that the host memory 106 can be converted to a physical address corresponding to a logical address more quickly.

Although not shown, when a write command is transmitted from the host controller interface 108, the first memory system 110A may have a partial area (eg, as shown in FIGS. 9 and 11) of the host memory 106. The integration area 106B can also be used as a write buffer.

14 illustrates an operation when some memory systems are separated from a plurality of memory systems. Specifically, a case in which interworking with the host is temporarily stopped in at least one of the plurality of memory systems 110A, 110B, and 110C interworking with the host will be described.

Referring to FIG. 14, the host controller interface 108 may determine whether it is possible to transmit and receive data with respect to the plurality of memory systems 110A, 110B, and 110C. For example, the host controller interface 108 may transmit a request signal Alive for confirming connection to each of the plurality of memory systems 110A, 110B, and 110C.

In FIG. 14, an example in which the host controller interface 108 individually transmits a request signal Alive to each of the plurality of memory systems 110A, 110B, and 110C will be described. In some embodiments, the host controller interface 108 may broadcast at least one request signal Alive to the plurality of memory systems 110A, 110B, and 110C.

The plurality of memory systems 110A, 110B, and 110C having received the request signal Alive from the host controller interface 108 may transmit a response signal to the request signal Alive. In FIG. 14, it is assumed that the second memory system 110B does not transmit a response to the request signal Alive transmitted from the host controller interface 108 (No response). Through this, the host controller interface 108 can recognize that the second memory system 110B cannot be accessed.

The host controller interface 108 may not notify the first memory system 110A of the contents when the second memory system 110B temporarily stops responding. However, in some embodiments, the host controller interface 108 may notify the first memory system 110A that the second memory system 110B is not responding.

Regardless of whether the host controller interface 108 notifies the first memory system 110A that the second memory system 110B is temporarily unresponsive, the first memory system 110A does not receive metadata (L2P MAP). ) May not be updated (NO UPDATE). The first memory system 110A may transfer the meta data L2P MAP to the host memory 106 without any update. Here, the metadata L2P MAP delivered by the first memory system 110A may include metadata about the second memory system 110B that does not temporarily respond.

The reasons why a particular memory system temporarily stops responding can vary widely. Therefore, when the host controller interface 108 needs to update metadata every time it determines that the second memory system 110B temporarily stops responding, the metadata may be updated too unnecessarily and frequently. Therefore, even if the host controller interface 108 determines that the second memory system 110B temporarily stops responding, the host controller interface 108 may assume that the interworking with the second memory system 110B can be resumed at any time.

15 illustrates a method of updating metadata for a plurality of memory systems. Specifically, FIG. 15 illustrates a case in which interworking with the host becomes impossible in at least one of the plurality of memory systems 110A, 110B, and 110C working with the host.

Referring to FIG. 15, the host controller interface 108 may transmit a disable confirmation signal (Disable) for checking whether one of the plurality of memory systems 110A, 110B, and 110C is disabled. Here, the disable confirmation signal (Disable) is technically different from the request signal (Alive) described in FIG. The request signal Alive is transmitted or individually transmitted to all memory systems interworking with the host periodically or at a preset time point, while the disable signal (Disable) is preset by the host controller interface 108. It is delivered separately for the specific memory system that is determined to meet the conditions. For example, the host controller may not respond to the request signal Alive sent by the host controller interface 108 for a preset time or to the memory system that does not respond to the preset request signal Alive. The interface 108 may transmit a disable confirmation signal (Disable). In addition, when the host controller interface 108 transmits that the normal operation is not possible in one of the plurality of memory systems 110A, 110B, and 110C, the host controller interface 108 disables the disable signal. You can check if it is disabled by passing).

In FIG. 15, it is assumed that the second memory system 110B is disabled. When the host controller interface 108 recognizes that the second memory system 110B is disabled through the disable confirmation signal, the host controller interface 108 requests the first memory system 110A to reconstruct the metadata. Request for Reconfig. In response to a request of the host controller interface 108, the first memory system 110A may invalidate all logical identifiers and metadata allocated to the second memory system 110B. Thereafter, the first memory system 110A may update the metadata and transfer the updated metadata to the host memory 106.

In addition, the first memory system 110A may invalidate all information about the second memory system 110B, and then assign the invalidated data to another memory system (eg, a newly recognized memory system).

Although not shown, if the host controller interface 108 recognizes that the second memory system 110B is disabled through the disable confirmation signal, the host controller interface 108 reconfigures the metadata. You can also perform (reconfiguration). For example, the host controller interface 108 may invalidate all metadata allocated to the second memory system 110B. The host controller interface 108 may notify the first memory system 110A of the result after reconfiguration of the metadata. The first memory system 110A may update the metadata based on a result of reconfiguration of the metadata transmitted from the host controller interface 108. Thereafter, the first memory system 110A may transfer the updated metadata to the host memory 106.

16 illustrates a privilege transfer method in a plurality of memory systems.

Referring to FIG. 16, a host interoperating with a plurality of memory systems 110A, 110B, and 110C through the host controller interface 108 may perform a plurality of operations. It is assumed that the first memory system 110A among the plurality of memory systems 110A, 110B, and 110C has a higher priority than the other memory systems 110B and 110C.

The first memory system 110A may monitor its operating state. The first memory system 110A may determine that it is difficult to perform a normal operation through a self-diagnosis (for example, an operating state such as wear-out or ran-out) (Expected Wear Out). In this case, the first memory system 110A may migrate its rights and roles to one of the other memory systems 110B and 110C. For example, the metadata stored in the first memory system 110A may be moved to one of the other memory systems 110B and 110C. When the transfer is completed from the first memory system 110A to one of the other memory systems 110B and 110C, the transferred memory system may transfer the metadata to the host memory 106.

Although not shown, an emergency situation occurs in the first memory system 110A so that the first memory system 110A transfers its authority and role to one of the other memory systems 110B and 110C. You may not be able to. Referring to FIG. 13, when the metadata cannot be copied or moved in the first memory system 110A, the metadata stored in the host memory 106 may be utilized.

In addition, when the other memory systems 110B and 110C have backup information on metadata stored in the first memory system 110A, each of the other memory systems 110B and 110C recovers the metadata. You can also perform an operation. In this case, the interworking with the host controller interface 108 may be restarted based on the metadata restored from each of the available memory systems 110B and 110C. For example, it may be determined via the host controller interface 108 which memory system among the available memory systems 110B, 110C will be given a high priority.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

Claims (20)

A host processing data in response to an externally input command; And
And a plurality of memory systems interoperating with the host and capable of storing or outputting the data in response to a request of the host
A first memory system, one of the plurality of memory systems, stores metadata for all of the plurality of memory systems.
The method of claim 1,
Among the plurality of memory systems, the first memory system is given a higher priority than other memory systems,
The first memory system assigns an identifier for logical identification to each of the plurality of memory systems,
Data processing system.
The method of claim 2,
When the operation state corresponds to a preset condition in the first memory system, the priority is transferred to one of the other memory systems.
Data processing system.
The method of claim 2,
The first memory system is embedded in the host, and the other memory system is detachable from the host,
Data processing system.
The method of claim 4, wherein
Even if at least one of the other memory systems is separated from the host, the identifier assigned to the separated memory system and the metadata stored in the first memory system are maintained.
Data processing system.
The method of claim 1,
When the host is incapable of operating at least one of the plurality of memory systems, the identifier assigned to the memory system may be withdrawn and reassigned.
Data processing system.
The method of claim 1,
The meta data includes first mapping information for identifying a physical address corresponding to a logical address.
Data processing system.
The method of claim 1,
Each of the plurality of memory systems includes second mapping information for identifying a logical address corresponding to a physical address.
Data processing system.
The method of claim 1,
Each of the plurality of memory systems may perform garbage collection by autonomous judgment.
When reconfiguration of the metadata is performed by the host, the first memory system performs garbage collection on the metadata.
Data processing system.
The method of claim 1,
When power is applied to the host and the first memory system, the first memory system transmits the metadata to the host,
When the first memory system generates or modifies the metadata, the first memory system notifies the host of a need to update the metadata.
Data processing system.
A memory device capable of storing data; And
A controller capable of storing, deleting, or reading the data in the memory device,
When interlocked with a host, a portion of memory in the host is allocated,
When the priority determined for interworking with the host is a preset value, the controller determines an identifier for at least one other memory system interworking with the host, transmits the identifier to the host, and transmits the identifier to the host. Store metadata about the memory device,
Storing at least one of the metadata or user data transmitted from the host in the partial region;
Memory system.
The method of claim 11,
The meta data includes first mapping information for identifying a physical address corresponding to a logical address.
If the priority is not the preset value, the first mapping information is not stored.
Memory system.
The method of claim 12,
Storing second mapping information in the memory device to identify a logical address corresponding to a physical address regardless of the priority;
Memory system.
The method of claim 13,
Garbage collection may be performed using the second mapping information without a command from the host.
Memory system.
A system in association with a host and at least one other memory system, the system comprising at least one processor, at least one memory, and program instructions, wherein the program instructions are configured to be communicated via the at least one processor and the at least one memory. ,
Transmitting metadata to a portion of a host memory included in the host;
Receiving a read command and a first logical address from the host;
Identifying a first physical address corresponding to the first logical address conveyed with the read command in the at least one memory;
If the first physical address is not verified, requesting a part of the metadata including the first logical address;
Receiving and storing some of the metadata corresponding to the request in the at least one memory;
Translating the first logical address into the first physical address based on some of the metadata; And
Outputting data by accessing a memory device at the first physical address
Including, the system.
The method of claim 15,
Receiving a write command from the host;
If the data corresponding to the write command is greater than a preset amount, requesting the host to copy the data to the partial area;
Confirming that the copy is completed, and notifying the host of whether the write command is fulfilled; And
Moving the data copied to the partial region to a memory device while there is no command from the host.
System to perform more.
The method of claim 15,
Assigning an identifier corresponding to the at least one other memory system
System to perform more.
The method of claim 15,
If the operating state of the memory device corresponds to a preset condition, copying the metadata to one of the at least one other memory system
System to perform more.
The method of claim 15,
The memory device includes a first area for storing the metadata and a second area for storing user data.
system.
The method of claim 15,
The metadata includes first mapping information for identifying a physical address corresponding to a logical address for the user data and data stored in the at least one other memory system.
system.

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