KR20210063814A - Apparatus and method for reading operation in memory system - Google Patents

Abstract

The present invention includes: a non-volatile memory device for storing user data and metadata of the user data; and a controller controlling the non-volatile memory device. The controller includes a memory system which determines whether a physical address received together with a read request and metadata from the host is valid, using the metadata stored in the physical address. Accordingly, overhead of the memory system may be reduced and a lifespan of the memory system may be improved.

Description

Method and apparatus for read operation of a memory system {APPARATUS AND METHOD FOR READING OPERATION IN MEMORY SYSTEM}

The present invention relates to a memory system and a data processing apparatus including the memory system, and more particularly, to a method and apparatus for a read operation of a memory system.

Recently, a paradigm for a computer environment is shifting to ubiquitous computing, which allows a computer system to be used anytime, anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers is rapidly increasing. Such portable electronic devices generally use a memory system using a memory device, that is, a data storage device. A data storage device is used as a main storage device or a secondary storage device of a portable electronic device.

A data storage device using a memory device, unlike a hard disk, does not have a mechanical driving part, so it has excellent stability and durability, and also has an advantage of very fast information access speed and low power consumption. As an example of a memory system having such an advantage, a data storage device includes a Universal Serial Bus (USB) memory device, a memory card having various interfaces, a solid state drive (SSD), and the like.

SUMMARY Embodiments of the present invention may provide a memory system, a data processing system, and a driving method thereof, which can reduce overhead of a memory system, improve the lifespan of the memory system, and improve a read operation execution speed .

The memory system, the data processing system, and the operating method thereof according to an embodiment of the present invention do not download the map data from the memory device when the read operation corresponding to the read command transmitted from the host is performed, so that the overhead of the memory system is increased. It is possible to provide a memory system, a data processing system, and a driving method thereof, which can reduce the size of the memory system, improve the lifespan of the memory system, and improve the read operation execution speed.

In addition, embodiments of memory system and a data processing system according to, and their method of operation of the present invention when performing a read operation, to determine the validity of the host physical address received from the host, a valid physical address in case a separate map data search procedure It is possible to provide a memory system, a data processing system, and a driving method thereof, in which a read operation execution speed is improved by accessing a corresponding physical address without the need of access.

Further, between the embodiment the memory system and a data processing system according to, and their method of operation of the invention because of administrative rights with respect to the host-physical address received with the read command is to have a memory system that is not a host, a host and the memory system, It is possible to provide a memory system, a data processing system, and a driving method thereof that can be implemented by changing and utilizing an existing interface without the need to change the interface and without adding additional hardware configuration or resources.

The technical problems to be achieved in the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those of ordinary skill in the art to which the present invention belongs from the description below. will be able

A memory system according to an embodiment of the present invention includes: a nonvolatile memory device for storing user data and metadata of the user data; and a controller for controlling the nonvolatile memory device, wherein the controller may determine whether a physical address received from the host together with a read command and metadata is valid, using metadata stored in the physical address. If the physical address is valid, the controller may transmit user data stored in the physical address to the host. In order to determine whether the physical address is valid, the controller may read-out user data stored in the physical address while reading out the metadata stored in the physical address from the nonvolatile memory device and temporarily store the same. If the physical address is valid, the controller can send the temporarily stored user data to the host. and a volatile memory for storing the latest metadata stored in the non-volatile memory device, wherein the controller determines whether the latest metadata stored in the volatile memory is the same as the metadata received from the host, and if the same, the validity of the physical address It is determined, and the latest metadata may be updated whenever a physical address corresponding to a logical address is changed. While determining whether they are the same, the user data stored in the physical address may be read out from the nonvolatile memory device and temporarily stored. The metadata may include a logical address and a map version of L2P map information including logical addresses. If the physical address is invalid, the controller may search for a physical address corresponding to the logical address received from the host, and transmit user data stored in the retrieved physical address to the host. The map version received from the host may have a status value when the L2P map information received from the host is transmitted from the memory system. The map version stored in the physical address has a state value at the time when user data is programmed into the physical address, and the logical address stored in the physical address may be a logical address corresponding to the user data stored in the physical address.

According to an embodiment of the present invention, there is provided a method of operating a memory system including a non-volatile memory device for storing user data and meta data of user data and a controller for storing the latest version of meta data together with a read command and meta data from a host. receiving a physical address; and determining the validity of the physical address by using the metadata stored in the nonvolatile memory device. The controller may further include, if the physical address is valid, transmitting user data stored in the physical address to the host. The method may further include reading out user data stored in the physical address and temporarily storing the user data stored in the physical address while reading out the metadata stored in the physical address from the nonvolatile memory device. If the physical address is valid, the method may further include transmitting the temporarily stored user data to the host. determining whether the latest metadata is the same as the metadata received from the host; and determining whether the physical address is valid when the latest metadata and the metadata received from the host are the same. Determining whether the data is the same may include reading out user data stored in a physical address from a nonvolatile memory device and temporarily storing the user data. The metadata may include a logical address and a map version of L2P map information including logical addresses. if the physical address is invalid, retrieving a physical address corresponding to the logical address received from the host; and transmitting the user data stored in the found physical address to the host. The map version received from the host may have a status value when the L2P map information received from the host is transmitted from the memory system. The map version stored in the physical address has a state value at the time when user data is programmed into the physical address, and the logical address stored in the physical address may be a logical address corresponding to the user data stored in the physical address.

The effects of the memory system, the data processing system, and the driving method thereof according to the present invention will be described as follows.

Embodiments of the present invention may reduce the overhead of the memory system, improve the lifespan of the memory system, and provide the effect of improving the performance speed of the read operation.

In addition, embodiments of the present invention can provide an effect of improving the read operation execution speed and of quickly and accurately determining the validity of a physical address received from a host.

In addition, embodiments of the present invention may provide an effect of improving the efficiency and reliability of a read operation.

The effects obtainable in the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those of ordinary skill in the art to which the present invention belongs from the following description.

1 illustrates a method of sharing map information according to an embodiment of the present invention.
2 schematically illustrates an example of a data processing system including a memory system according to an embodiment of the present invention.
3 illustrates a controller in a memory system according to an embodiment of the present invention.
4 illustrates the configuration of a host and a memory system in a data processing system according to an embodiment of the present invention.
5 illustrates a read operation between a host and a memory system in a data processing system according to an embodiment of the present invention.
6A and 6B illustrate first and second examples of a transaction between a host and a memory system in a data processing system according to an embodiment of the present invention.
7A to 7D illustrate first to fourth operations of a host and a memory system according to an embodiment of the present invention.
8A to 8C illustrate a read operation of a memory system according to an exemplary embodiment of the present invention.
9 to 12 illustrate a write operation of a memory system according to an embodiment of the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. It should be noted that, in the following description, only parts necessary for understanding the operation according to the present invention are described, and descriptions of other parts will be omitted so as not to obscure the gist of the present invention.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings.

1 illustrates a method of sharing map information according to an embodiment of the present invention.

Referring to FIG. 1 , the host 102 and the memory system 110 may interwork. The host 102 may be understood as a computing device, and may be implemented in the form of a mobile device, computer, server, or the like. The memory system 110 interworking with the host 102 may receive a command from the host 102 and store or output data in response to the received command.

The memory system 110 may have a storage space including nonvolatile memory cells. For example, the memory system 110 may be implemented in the form of a flash memory, a solid-state drive (SSD), or the like.

In order to store data requested by the host 102 in the storage space including the non-volatile memory cell , the memory system 110 connects the file system used by the host 102 and the storage space including the non-volatile memory cell. mapping can be performed. For example, an address of data according to a file system used by the host 102 may be called a logical address or a logical block address, and an address of data in a storage space including a nonvolatile memory cell is a physical address or a physical block address. can be called When the host 102 transmits the logical address to the memory system 110 along with the read command, the memory system 110 searches for a physical address corresponding to the logical address and then transfers data stored in the searched physical address to the host 102 . ) can be printed. During this process, mapping may be performed while the memory system 110 searches for a physical address corresponding to the logical address transmitted by the host 102 .

If the host 102 can perform the mapping performed by the memory system 110 , the time required for the memory system 110 to output data corresponding to the read command transmitted from the host 102 may be reduced. To this end, in order for the host 102 to transfer a physical address to the memory system 110 through mapping, the host 102 may store map information for performing mapping or directly access the map information.

Referring to FIG. 1 , the memory system 110 may transmit map information MAP INFO. to the host 102 . The host 102 receiving the map information from the memory system 110 may store the map information in a memory included in the host 102 . If the memory system 110 is transmitting the entire map information to the host 102 and host 102 can store the entire transmission map information, the memory system 110 may not need to record the log. However, it may be difficult for the host 102 to allocate a storage space in the memory to store the entire map information managed by the memory system 110 . Therefore, the memory system 110 may transmit the selective to the host 102 the data or map information on the logical address to the host (102) is often used.

Meanwhile, the memory system 110 that has transmitted the map information to the host 102 may generate a log for the transmitted map information. The format and form of the generated log may vary, and may be stored in a memory device or a storage area including a non-volatile memory cell. According to an embodiment, the log is in the form of data such as history, and whenever an event in which the memory system 110 transmits the map information to the host 102 occurs, the transmitted map information may be recorded. have. The memory system 110 may determine the amount of transmitted map information recorded in the log or history corresponding to the size of the map information that can be transmitted to the host 102 . For example, it may be assumed that the size of map information that the memory system 110 can transmit to the host 102 is 512 KB. Although the memory system 110 may transmit a larger amount of map information to the host 102 than 512 KB, the amount of transmitted map information written to a log may be limited to 512 KB. The amount of map information that the memory system 110 can transmit to the host 102 at one time may be smaller than the amount of map information that the host 102 can store. For example, the map information may be transmitted to the host 102 in units of segments. The memory system 110 may transmit the map information to the host 102 through a plurality of transmissions, and may continuously or intermittently transmit the map information to the host 102 .

According to the embodiment, when memory system 110 is transmitting a large amount of map information than 1MB in the host 102, host 102 is a memory system 110 is sent to delete the old map information according to the time sequence can Also, update information may be included in the map information transmitted from the memory system 110 to the host 102 . Since the space allocated by the host 102 to store the map information transmitted from the memory system 110 includes volatile memory cells, the host 102 updates (updates) the corresponding map information without deleting other map information. )You may.

The host 102 may include a physical address (PBA) in a command transmitted to the memory system 110 based on the stored map information. The host 102 performing the mapping may be found in map information storing a physical address corresponding to the logical address based on the logical address corresponding to the command transmitted to the memory system 110 . If the physical address exists, the host 102 may send a command including the physical address to the memory system 110 .

The memory system 110 receiving the command including the physical address from the host 102 may perform a command operation corresponding to the command. As in the above-described example, when the host 102 transmits a physical address corresponding to the read command, the memory system 110 uses the corresponding physical address to access and output data, thereby taking a command operation corresponding to the read command. time can be reduced.

When power is not supplied to the host 102 and the memory system 110 , all map information stored in the storage space including the volatile memory cell in the host 102 disappears. Power supply to the host 102 and the memory system 110 may be generated by a user's request or may occur in an undesired situation regardless of a user's request. When power supply to the host 102 and the memory system 110 is resumed (power on), the memory system 110 transmits the map information to the host 102 and then, based on the log or history recorded, the host 102 ) to select map information to be transmitted. Then, the memory system 110 to send the map information prepared in the host 102, before the power failure, the host 102 is a command to perform the mapping includes a physical address to forward to the memory system (110) It can be quickly restored to the state it was in.

Before the power supply is stopped and after the power supply is resumed, the needs and usage patterns of users who use the host 102 and the memory system 110 may be similar or different. If user needs and usage patterns are similar, the host 102 may use or access the same data more frequently. If the host 102 performs mapping on such data so that the memory system 110 can output data more quickly , the user's satisfaction with the host 102 and the memory system 110 may be increased.

2 is a diagram schematically illustrating an example of a data processing system including a memory system according to an embodiment of the present invention.

Referring to FIG. 2 , the data processing system 100 includes a host 102 and a memory system 110 . Host 102 may include electronic devices such as portable electronic devices such as mobile phones, MP3 players, laptop computers, etc., or electronic devices such as desktop computers, game consoles, TVs, projectors, etc., that is, computing devices or wired and wireless electronic devices. have.

In addition, the host 102 includes at least one operating system (OS), which generally manages and controls functions and operations of the host 102 , the data processing system 100 or Provides interaction between a user using the memory system 110 and the host 102 . Here, the operating system supports functions and operations corresponding to the purpose and use of the user, and may be divided into, for example, a general operating system and a mobile operating system according to the mobility of the host 102 . In addition, the general operating system in the operating system can be divided into a personal operating system and an enterprise operating system according to the user's use environment. For example, the personal operating system is specialized to support a service provision function for general users. As a system, it includes windows and chrome, and the enterprise operating system is a system specialized to secure and support high performance, such as windows server, Linux and unix. may include. In addition, the mobile operating system in the operating system is a system specialized to support a function of providing a mobility service to users and a power saving function of the system, and may include Android, iOS, Windows mobile, and the like. . In this case, the host 102 may include a plurality of operating systems, and also executes the operating system to perform an operation with the memory system 110 corresponding to a user request, where the host 102 ) transmits a plurality of commands corresponding to a user request to the memory system 110 , and accordingly, the memory system 110 performs operations corresponding to the commands, that is, operations corresponding to the user request.

In addition, the memory system 110, and operates in response to requests from the host 102, and particularly stores data accessed by a host (102). In other words, the memory system 110 may be used as a main storage device or an auxiliary storage device of the host 102 . Here, the memory system 110 may be implemented in accordance with a host interface protocol that is associated with the host 102, by any of a variety of types of storage devices. For example, the memory system 110 is a solid state drive (SSD: Solid State Drive), MMC, eMMC (embedded MMC), RS-MMC (Reduced Size MMC), micro-MMC type multi-media card (MMC: Multi Media Card), SD, mini-SD, micro-SD type Secure Digital (SD) card, USB (Universal Storage Bus) storage device, UFS (Universal Flash Storage) device, CF (Compact Flash) card, It may be implemented as any one of various types of storage devices, such as a smart media card and a memory stick.

In addition, storage devices implementing the memory system 110 include volatile memory devices such as dynamic random access memory (DRAM) and static RAM (SRAM), read only memory (ROM), mask ROM (MROM), and programmable memory (PROM). ROM), Erasable ROM (EPROM), Electrically Erasable ROM (EEPROM), Ferromagnetic ROM (FRAM), Phase change RAM (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), Flash memory, etc. can be implemented.

In addition, the memory system 110 includes a memory device 150 for storing data accessed by the host 102 , and a controller 130 for controlling data storage in the memory device 150 .

Here, the controller 130 and the memory device 150 may be integrated into one semiconductor device. For example, the controller 130 and the memory device 150 may be integrated into one semiconductor device to constitute an SSD. When the memory system 110 is used as an SSD, the operating speed of the host 102 connected to the memory system 110 may be further improved. In addition, the controller 130 and the memory device 150 may be integrated into one semiconductor device to constitute a memory card, for example, a PC card (PCMCIA: Personal Computer Memory Card International Association), a compact flash card (CF). , configure memory cards such as smart media cards (SM, SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), universal flash storage devices (UFS), etc. can do.

In addition, as another example, the memory system 110 is a computer, an Ultra Mobile PC (UMPC), a workstation, a net-book, a Personal Digital Assistants (PDA), a portable computer, a web tablet. ), tablet computer, wireless phone, mobile phone, smart phone, e-book, PMP (portable multimedia player), portable game machine, navigation (navigation) device, black box, digital camera, DMB (Digital Multimedia Broadcasting) player, 3-dimensional television, smart television, digital audio recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder, digital video player, data center storage constituting a storage device, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, and one of various electronic devices constituting a telematics network. One, a radio frequency identification (RFID) device, or one of various components constituting a computing system may be configured.

Meanwhile, the memory device 150 in the memory system 110 may maintain stored data even when power is not supplied, and in particular, stores data provided from the host 102 through a write operation, and reads the data. ) provides the stored data to the host 102 through the operation. Here, the memory device 150 includes a plurality of memory blocks 152 , 154 , and 156 , and each of the memory blocks 152 , 154 , 156 includes a plurality of pages, and each page These include a plurality of memory cells to which a plurality of word lines (WL) are connected. Also, the memory device 150 includes a plurality of planes each including a plurality of memory blocks 152 , 154 , and 156 , and in particular, a plurality of memory dies each including a plurality of planes. may include In addition, the memory device 150 may be a non-volatile memory device, for example, a flash memory, and in this case, the flash memory may have a three-dimensional (3D) stereoscopic stack structure.

In addition, the controller 130 in the memory system 110 controls the memory device 150 in response to a request from the host 102 . For example, the controller 130 provides data read from the memory device 150 to the host 102 , and stores the data provided from the host 102 in the memory device 150 . , controls operations such as read, write, program, and erase of the memory device 150 .

More specifically, the controller 130 includes a host interface (Host I/F) unit 132 , a processor 134 , an error correction code (ECC) unit 138 , and power management. It includes a power management unit (PMU) 140 , a memory interface (Memory I/F) unit 142 , and a memory 144 .

In addition, the host interface unit 132 processes a command and data of the host 102 , a Universal Serial Bus (USB), a Multi-Media Card (MMC), and a Peripheral Component Interconnect-Express (PCI-E). , Serial-attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESD), Integrated Drive Electronics (IDE), MIPI ( and may be configured to communicate with the host 102 via at least one of a variety of interface protocols, such as a Mobile Industry Processor Interface). Here, the host interface unit 132 is an area for exchanging data with the host 102 and is to be driven through firmware called a host interface layer (HIL: Host Interface Layer, hereinafter referred to as 'HIL'). can

In addition, the ECC unit 138 corrects an error bit of data processed by the memory device 150 , and may include an ECC encoder and an ECC decoder. Here, the ECC encoder performs error correction encoding on data to be programmed in the memory device 150 to generate data to which a parity bit is added, and the data to which the parity bit is added is, It may be stored in the memory device 150 . In addition, when reading data stored in the memory device 150 , the ECC decoder detects and corrects errors included in data read from the memory device 150 . In other words, the ECC unit 138 performs error correction decoding on the data read from the memory device 150 , and then determines whether the error correction decoding succeeds or not, and according to the determination result, an indication signal, for example, an error A correction success/fail signal may be output, and an error bit of the read data may be corrected using a parity bit generated during the ECC encoding process. At this time, when the number of error bits is greater than or equal to the correctable error bit limit, the ECC unit 138 may not correct the error bits and may output an error correction failure signal corresponding to the failure to correct the error bits.

Here, the ECC unit 138, LDPC (low density parity check) code (code), BCH (Bose, Chaudhri, Hocquenghem) code, turbo code (turbo code), Reed-Solomon code (Reed-Solomon code), convolution Error correction can be performed using coded modulation such as convolution code, recursive systematic code (RSC), trellis-coded modulation (TCM), and block coded modulation (BCM). it is not In addition, the ECC unit 138 may include all circuits, modules, systems, or devices for error correction.

In addition, the PMU 140 provides and manages the power of the controller 130 , that is, the power of components included in the controller 130 .

In addition, the memory interface unit 142 performs interfacing between the controller 130 and the memory device 150 so that the controller 130 controls the memory device 150 in response to a request from the host 102 . It becomes a memory/storage interface. Here, the memory interface unit 142 is a NAND flash controller (NFC) when the memory device 150 is a flash memory, in particular, for example, when the memory device 150 is a NAND flash memory, the processor 134 . A control signal of the memory device 150 is generated and data is processed under the control of . In addition, the memory interface unit 142 is an interface for processing commands and data between the controller 130 and the memory device 150 , for example, an operation of a NAND flash interface, in particular, data between the controller 130 and the memory device 150 . It supports input/output and is an area for exchanging data with the memory device 150 and may be driven through firmware called a Flash Interface Layer (FIL) (hereinafter referred to as 'FIL').

In addition, the memory 144 is an operating memory of the memory system 110 and the controller 130 , and may store data for driving the memory system 110 and the controller 130 . More specifically, the memory 144, the controller 130 is the data read from the memory device 150 of the process in response to the request for controlling the memory device 150, the host (102 from the host 102 ) can be temporarily saved before being provided. Also, the controller 130 may temporarily store data provided from the host 102 in the memory 144 before storing the data in the memory device 150 . When controlling operations such as read, write, program, and erase of the memory device 150 , data transferred or generated between the controller 130 and the memory device 150 in the memory system 110 is stored in the memory. (144) may be stored. For example, the memory 144 may store data required to perform data write and read operations between the host 102 and the memory device 150 , and data when data write and read operations are performed. . For storing such data, the memory 144 may include a program memory, data memory, write buffer/cache, read buffer/cache, data buffer/cache, map buffer/cache, and the like. have.

Here, the memory 144 may be implemented as a volatile memory, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), or the like. In addition, as shown in FIG. 1 , the memory 144 may exist inside the controller 130 or may exist outside the controller 130 , in which case data is transferred from the controller 130 through the memory interface. It may be implemented as an input/output external volatile memory.

In addition, the processor 134 controls the overall operation of the memory system 110 , and in particular, in response to a write request or a read command from the host 102 , controls a program operation or a read operation for the memory device 150 . do. Here, the processor 134 drives firmware called a Flash Translation Layer (FTL) to control the overall operation of the memory system 110 . In addition, the processor 134 may be implemented as a microprocessor or a central processing unit (CPU).

For example, the controller 130 performs an operation requested from the host 102 in the memory device 150 through the processor 134 implemented as a microprocessor or central processing unit (CPU), that is, the host ( A command operation corresponding to the command received from 102 is performed with the memory device 150 . Here, the controller 130 performs a foreground operation as a command operation corresponding to a command received from the host 102 , for example, a program operation corresponding to a write command, a read operation corresponding to a read command, and an erase operation. An erase operation corresponding to an erase command or a parameter set operation corresponding to a set parameter command or a set feature command may be performed as a set command.

Through the processor 134 implemented as a microprocessor or a central processing unit (CPU), the controller 130 may perform a background operation on the memory device 150 . The background operation of the memory device 150 is an operation of copying data stored in one memory block in the memory blocks 152 , 154 , and 156 of the memory device 150 to another arbitrary memory block and processing it. , for example, a garbage collection (GC) operation, swapping between the memory blocks 152 , 154 , and 156 of the memory device 150 or data stored in the memory blocks 152 , 154 and 156 . and processing, for example, a wear leveling (WL) operation, and storing map data stored in the controller 130 into the memory blocks 152 , 154 and 156 of the memory device 150 , for example, a map A map flush operation, or an operation of bad management for the memory device 150, for example, checking and processing bad blocks in a plurality of memory blocks 152, 154, 156 included in the memory device 150 It may include a bad block management operation and the like.

In response to a plurality of command operations corresponding to a plurality of commands received from the host 102 , the controller 130 performs a plurality of channels connected to a plurality of memory dies included in the memory device 150 or A plurality of command operations may be smoothly performed by selecting at least one of the ways. The controller 130 performs a plurality of command operations corresponding to a plurality of commands transmitted from the host 102 , for example, a plurality of program operations corresponding to a plurality of write commands and a plurality of read commands corresponding to a plurality of read commands. A plurality of erase operations corresponding to read operations and a plurality of erase commands may be received. When a plurality of operations are performed by the memory device 150 , the controller 130 may determine appropriate channels (or ways) based on states of the plurality of channels or ways. Through the determined best channels (or ways), the controller 130 may transmit commands received from the host 102 to corresponding memory dies, and from the memory dies that performed command operations corresponding to the commands. It is possible to receive execution results of command operations. Thereafter, the controller 130 may provide the execution results of the command operations to the host 120 .

The controller 130 may check the states of a plurality of channels (or ways) connected to a plurality of memory dies included in the memory device 150 . For example, the states of channels or ways may be classified into a busy state, a ready state, an active state, an idle state, a normal state, an abnormal state, and the like. The controller determination of the channel or method over which instructions (and/or data) is passed may be associated with the physical block address over which instructions (and/or data) are passed. The controller 130 may refer to a descriptor transmitted from the memory device 150 . A descriptor is data having a predetermined format or structure, and may include a block or page of parameters that describe something about the memory device 150 . For example, descriptors may include device descriptors, configuration descriptors, unit descriptors, and the like. The controller 130 references or uses the descriptor to determine over which channel(s) or method(s) commands or data are exchanged.

The processor 134 of the controller 130 may include a management unit (not shown) for performing bad management of the memory device 150 . The management unit may identify a bad block in the plurality of memory blocks 152 , 154 , and 156 included in the memory device 150 , and then perform bad block management of processing the checked bad block as bad. Here, in the bad block management, when the memory device 150 is a flash memory, for example, a NAND flash memory, a program failure may occur during data writing, for example, a data program due to the characteristics of the NAND, This refers to writing, ie, programming, data of the program failure to a new memory block after bad processing of the memory block in which the program failure has occurred. In addition, when the memory device 150 has a three-dimensional stack structure, as described above, if a corresponding block is treated as a bad block due to a program failure, the efficiency of use of the memory device 150 and the memory system 100 ) is rapidly reduced, so more reliable bad block management is required.

3 illustrates a controller in a memory system according to an embodiment of the present invention.

Referring to FIG. 3 , the controller 130 interworking with the host 102 and the memory device 150 includes a host interface unit 132 , a flash translation layer (FTL) unit 40 , a memory interface unit 142 , and a memory. (144). The controller 130 described in FIG. 4 may be an example of the controller 130 included in the plurality of memory systems 110A, 110B, and 110C described in FIG. 1 .

Although not shown in FIG. 3 , according to an embodiment, the ECC unit 138 described in FIG. 2 may be included in the flash translation layer (FTL) unit 40 . According to an embodiment, the ECC unit 138 may be implemented as a separate module, circuit, or firmware in the controller 130 .

The host interface unit 132 is for sending and receiving commands and data transmitted from the host 102 . For example, the host interface unit 132 sequentially stores commands and data transmitted from the host 102 , and then transfers them from the command queue 56 and the command queue 56 that can be output according to the stored order. A buffer manager 52 capable of classifying commands, data, etc. or adjusting the processing sequence, and an event queue 54 for sequentially delivering events for processing commands, data, etc., delivered from the buffer manager 52 may include

A plurality of commands and data having the same characteristics may be continuously transmitted from the host 102, or commands and data having different characteristics may be mixed and transmitted. For example, a plurality of commands for reading data may be transmitted, or read and program commands may be transmitted alternately. The host interface unit 132 sequentially stores commands and data transmitted from the host 102 in the command queue 56 first. Thereafter, it is possible to predict what kind of operation the controller 130 will perform according to the characteristics of the command and data transmitted from the host 102 , and based on this, the processing order or priority of the command and data may be determined. In addition, according to the characteristics of the command, data, etc. transmitted from the host 102 , the buffer manager 52 in the host interface unit 132 stores the command, data, etc. in the memory 144 , the flash translation layer (FTL) It may also decide whether to forward to the unit 40 . The event queue 54 receives events to be internally executed and processed by the memory system or controller 130 according to commands and data transmitted from the host 102 from the buffer manager 52 and then flashes in the received order. may be passed to a transform layer (FTL) unit 40 .

According to the embodiment, a flash translation layer (FTL) unit 40 is a map for managing the host request manager (Host Request Manager (HRM), 46), the map data for managing the event received from the event rules 54, data It may include a manager (Map Manager (MM) 44), a state manager 42 for performing garbage collection or wear leveling, and a block manager 48 for performing commands on blocks in the memory device.

For example, the host request manager (HRM) 46 uses the map data manager (MM, 44) and the block manager 48 to process read and program commands received from the host interface unit 132, and requests according to events. can do. The host request manager (HRM, 46) sends an inquiry request to the map data manager (MM, 44) to determine the physical address corresponding to the logical address of the forwarded request, and flash reads the memory interface unit 142 for the physical address. The read command may be processed by sending the command. On the other hand, the host request manager (HRM, 46) first sends a program request to the block manager 48 to program data in a specific page of an unrecorded (no data) memory device, and then the map data manager (MM, 44) By sending a map update request for the program request to , it is possible to update the contents of data programmed in the mapping information of logical-physical addresses.

Here, the block manager 48 converts the program request requested by the host request manager (HRM, 46), the map data manager (MM, 44), and the state manager 42 into a program request for the memory device 150 and converts the memory Blocks in the device 150 may be managed. To maximize the program or write performance of the memory system 110 (see FIG. 2 ), the block manager 48 may collect program requests and send flash program requests for multi-plane and one-shot program operations to the memory interface unit 142 . have. It may also send several outstanding flash program requests to the memory interface unit 142 to maximize the parallel processing of the multi-channel and multi-directional flash controller.

On the other hand, the block manager 48 manages flash blocks according to the number of valid pages, selects and erases blocks without valid pages when free blocks are needed, and when garbage collection is required, blocks containing the least valid pages can be selected. In order for the block manager 48 to have sufficient free blocks, the state manager 42 may perform garbage collection to collect valid data, move it to an empty block, and delete blocks including the moved valid data. When the block manager 48 provides information about the blocks to be deleted to the state manager 42, the state manager 42 can first check all the flash pages of the block to be deleted to determine whether each page is valid. . For example, in order to determine the validity of each page, the state manager 42 identifies the logical address recorded in the Out Of Band (OOB) area of each page, and then the physical address of the page and the map manager 44 ) can compare the physical address mapped to the logical address obtained from the lookup request. The state manager 42 sends a program request to the block manager 48 for each valid page, and when the program operation is completed, the mapping table may be updated through the update of the map manager 44 .

The map manager 44 may manage a logical-physical mapping table, and may process requests such as inquiry, update, etc. generated by the host request manager (HRM) 46 and the state manager 42 . The map manager 44 may store the entire mapping table in the flash memory, and cache the mapping items according to the capacity of the device 144 upon memory loss. If a map cache miss occurs while processing an inquiry and update request, the map manager 44 may transmit a read command to the memory interface unit 142 to load the mapping table stored in the memory device 150 . . When the number of dirty cache blocks of the map manager 44 exceeds a certain threshold, a program request is sent to the block manager 48 to create a clean cache block, and the dirty map table may be stored in the memory device 150 .

On the other hand, when garbage collection is performed, the host request manager (HRM) 46 will program the latest version of the data for the same logical address of the page and issue an update request at the same time while the state manager 42 copies valid pages. can When the state manager 42 requests a map update in a state where copying of a valid page is not normally completed, the map manager 44 may not perform the mapping table update. The map manager 44 can ensure accuracy by performing map updates only when the latest map table still points to the old real address.

The memory device 150 stores a plurality of memory blocks in a single level cell (SLC) memory block and a multi level cell (MLC) according to the number of bits that can be stored or expressed in one memory cell. Cell) may be included as a memory block or the like. Here, the SLC memory block includes a plurality of pages implemented by memory cells storing 1-bit data in one memory cell, and has fast data operation performance and high durability. In addition, the MLC memory block includes a plurality of pages implemented by memory cells that store multi-bit data (eg, 2 bits or more bits) in one memory cell, and stores larger data than the SLC memory block. Having space, that is, it can be highly integrated. In particular, the memory device 150 is an MLC memory block, which includes not only an MLC memory block including a plurality of pages implemented by memory cells capable of storing 2-bit data in one memory cell, but also 3 in one memory cell. A triple level cell (TLC) memory block including a plurality of pages implemented by memory cells capable of storing bit data, a plurality of memory cells capable of storing 4-bit data in one memory cell A quadruple level cell (QLC) memory block containing pages of a multi-level including a plurality of pages implemented by memory cells capable of storing 5 bits or more bits of data in one memory cell It may include a multiple level cell memory block and the like.

Here, in the embodiment of the present invention, for convenience of description, the memory device 150 is implemented as a flash memory, for example, a non-volatile memory such as a NAND flash memory, etc. as an example, but a phase change memory (PCRAM: Phase Change Random Access Memory (RRAM): Resistive Random Access Memory (RRAM), Ferroelectrics Random Access Memory (FRAM), and Spin Injection Magnetic Memory (STT-RAM (STT-MRAM): Spin Transfer Torque) Magnetic Random Access Memory) may be implemented as any one of memories.

According to an embodiment, the controller 130 included in the memory system 110 is included in a plurality of channels (or ways) for the memory device 150 of the memory system 110 , in particular, the memory device 150 . Checking the status of channels (or ways) between the plurality of memory dies and the controller 130, or a memory system in a plurality of memory systems, for example, a controller of a master memory system, Check the status of a plurality of channels (or ways) for , in particular, channels (or ways) between the master memory system and the remaining memory systems, eg, between the master memory system and the slave memory systems. In other words, in an embodiment of the present invention, a plurality of channels (or ways) for memory dies of the memory device 150, or a plurality of channels (or ways) for a plurality of memory systems, Check whether it is in a busy state, ready state, active state, idle state, normal state, or abnormal state. Here, in an embodiment of the present invention, it is possible to determine the channels (or ways) of the ready state or the idle state in the normal state as the best channels (or ways). In particular, in an embodiment of the present invention, in a plurality of channels (or ways), the usable capacity of the channel (or way) is in the normal range or the operating level of the channel (or the way) is in the normal range. Determines (or ways) as the best channels. Here, the operation level of the channel (or way) may be determined by the operation clock, power level, current/voltage level, operation timing, temperature level, and the like in each channel (or ways).

In addition, according to an embodiment of the present invention, write data corresponding to a plurality of write commands received from the host 102 is stored in a buffer/cache included in the memory 144 of the controller 130 . After storing, the data stored in the buffer/cache is programmed into a plurality of memory blocks included in the memory device 150 and stored, that is, program operations are performed, and also corresponding to the program operations to the memory device 150 . After updating the map data, when the updated map data is stored in a plurality of memory blocks included in the memory device 150 , that is, program operations corresponding to a plurality of write commands received from the host 102 are performed. A case will be described as an example. Further, in an embodiment of the present invention, when a plurality of read commands are received from the host 102 with respect to data stored in the memory device 150 , map data of data corresponding to the read commands is checked, and the memory device The host 102 reads data corresponding to the read commands from 150 , stores the read data in a buffer/cache included in the memory 144 of the controller 130 , and then transfers the data stored in the buffer/cache to the host 102 . A case in which read operations corresponding to a plurality of read commands received from the host 102 are performed will be described as an example. In addition, in an embodiment of the present invention, when receiving a plurality of erase commands from the host 102 with respect to memory blocks included in the memory device 150 , after checking the memory blocks corresponding to the erase commands, , when data stored in the checked memory blocks is erased, and the map data is updated according to the erased data, and then the updated map data is stored in a plurality of memory blocks included in the memory device 150 , that is, A case in which erase operations corresponding to a plurality of erase commands received from the host 102 are performed will be described as an example. In addition, according to an embodiment of the present invention, a plurality of write commands, a plurality of read commands, and a plurality of erase commands are received from the above-described host 102 to perform a plurality of program operations. A case of performing read operations and erase operations will be described as an example.

In addition, in the embodiment of the present invention, for convenience of description, command operations in the memory system 110 are described as an example that the controller 130 performs, but, as described above, the controller 130 The included processor 134 may perform, for example, via FTL. For example, in an embodiment of the present invention, the controller 130 includes user data and meta data corresponding to write commands received from the host 102 in the memory device 150 . User data and metadata corresponding to read commands received from the host 102 are programmed and stored in arbitrary memory blocks of the plurality of memory blocks included in the memory device 150 . A plurality of memory blocks included in the memory device 150 include user data and metadata corresponding to erase commands read from arbitrary memory blocks and provided to the host 102 or received from the host 102 . Erases from any memory blocks of

Herein, the metadata includes logical/physical (L2P) information (hereinafter referred to as 'logical information') on data stored in memory blocks corresponding to a program operation. The first map data and the second map data including physical/logical (P2L: Physical to Logical) information (hereinafter referred to as 'physical information') are included, and also received from the host 102 Information on command data corresponding to a command, information on a command operation corresponding to the command, information on memory blocks of the memory device 150 on which the command operation is performed, and information on map data corresponding to the command operation, etc. may be included. In other words, the metadata may include all other information and data except for user data corresponding to a command received from the host 102 .

That is, in the embodiment of the present invention, when the controller 130 receives a plurality of write commands from performing a command operation corresponding to the plurality of commands received from host 102, such as host 102, write command, Program operations corresponding to the above are performed, and in this case, the user data corresponding to the write commands are stored in memory blocks of the memory device 150 , for example, empty memory blocks in which an erase operation is performed on the memory blocks; It is written and stored in open memory blocks or free memory blocks, and between a logical address and a physical address for user data stored in the memory blocks. Mapping information, that is, first map data including an L2P map table or L2P map list in which logical information is recorded, and mapping information between physical addresses and logical addresses for memory blocks in which user data is stored, that is, P2L map in which physical information is recorded The second map data including the table or P2L map list is written and stored in empty memory blocks, open memory blocks, or free memory blocks in the memory blocks of the memory device 150 .

Here, when receiving write commands from the host 102 , the controller 130 writes and stores user data corresponding to the write commands in memory blocks, and stores a first map for the user data stored in the memory blocks. Meta data including data and second map data is stored in memory blocks. In particular, the controller 130 stores meta segments of meta data, that is, a map of map data, in response to data segments of user data being stored in memory blocks of the memory device 150 . After generating and updating the L2P segments of the first map data and the P2L segments of the second map data as map segments, they are stored in memory blocks of the memory device 150 , at this time the memory device 150 . Map segments stored in the memory blocks of , are loaded into the memory 144 included in the controller 130 to update the map segments.

According to an embodiment, when receiving a plurality of write commands from the host 102 , the state of a plurality of channels (or ways) for the memory device 150 is checked, in particular, a plurality of write commands included in the memory device 150 . After confirming the status of a plurality of channels (or ways) connected to the memory dies of , corresponding to the status of the channels (or ways), the best transmission channels (or transmission ways) and the best reception channels ( or reception ways) are independently determined. In addition, in an embodiment of the present invention, user data and metadata corresponding to the write command are transmitted and stored to the corresponding memory dies of the memory device 150 through the best transmission channels (or transmission ways); That is, program operations are performed, and the results of the program operations in the corresponding memory dies of the memory device 150 are displayed on the corresponding memory die of the memory device 150 through the best reception channels (or reception ways). received from the host 102 and provided to the host 102 .

In addition, when receiving a plurality of read commands from the host 102 , the controller 130 reads read data corresponding to the read commands from the memory device 150 , and the memory 144 of the controller 130 . After being stored in the buffer/cache included in , the data stored in the buffer/cache is provided from the host 102 to perform read operations corresponding to a plurality of read commands.

According to an embodiment, when receiving a plurality of read commands from the host 102 , states of a plurality of channels (or ways) of the memory device 150 are checked, and in particular, a plurality of read commands included in the memory device 150 are checked. After confirming the status of a plurality of channels (or ways) connected to the memory dies of , corresponding to the status of the channels (or ways), the best transmission channels (or transmission ways) and the best reception channels ( or reception ways) are independently determined. In addition, in an embodiment of the present invention, a read command of user data and metadata corresponding to the read command is transmitted to the corresponding memory dies of the memory device 150 through the best transmission channels (or transmission ways). to perform read operations, and also to transmit results of read operations from corresponding memory dies of the memory device 150 , that is, user data and metadata corresponding to a read command, to the best reception channels (or reception ways). ), and provides user data to the host 102 by receiving from the corresponding memory dies of the memory device 150 .

Also, when receiving a plurality of erase commands from the host 102 , the controller 130 checks the memory blocks of the memory device 150 corresponding to the erase commands, and then performs an erase operation on the memory blocks. carry out the

According to an embodiment, when receiving a plurality of erase commands from the host 102 , the state of a plurality of channels (or ways) for the memory device 150 is checked, and in particular, the state of the plurality of channels (or ways) for the memory device 150 is checked. After checking the status of the plurality of channels (or ways) connected to the plurality of memory dies, the best transmission channels (or transmission ways) and the best reception channels according to the status of the channels (or ways) (or reception ways) are each independently determined. In addition, in an embodiment of the present invention, an erase request for memory blocks from the memory dies of the memory device 150 corresponding to the erase command is transmitted through the best transmission channels (or transmission ways) to the memory device. The erase operations are performed by transmitting to the corresponding memory dies of the memory device 150 , and the results of the erase operations in the corresponding memory dies of the memory device 150 are transmitted to the best reception channels (or reception ways). Through , received from the corresponding memory dies of the memory device 150, and provided to the host (102).

In the memory system 110 , when receiving a plurality of commands, that is, a plurality of write commands, a plurality of read commands, and a plurality of erase commands from the host 102 , in particular, the plurality of commands are sequentially and simultaneously received. In this case, as described above, after checking the status of a plurality of channels (or ways) for the memory device 150 , the best transmission channels (or transmission channels) according to the status of the channels (or ways) Ways) and best reception channels (or reception ways) are each independently determined, and command operations corresponding to a plurality of commands are performed through the best transmission channels (or transmission ways), the memory device ( 150), in particular, requesting execution of corresponding command operations on a plurality of memory dies included in the memory device 150, and also performing command operations through the best reception channels (or reception ways). Results are received from memory dies of memory device 150 . And, in the memory system 110 according to an embodiment of the present invention, commands transmitted through the best transmission channels (or transmission ways) and execution results received through the best reception channels (or reception ways) a match to, a response to a plurality of commands received from host 102 between, and provides it to the host 102. the

According to an embodiment, the controller 130 included in the memory system 110 is included in a plurality of channels (or ways) for the memory device 150 of the memory system 110 , in particular, the memory device 150 . After checking the status of channels (or ways) between the plurality of memory dies and the controller 130 , the best transmission channels (or transmission ways) and the best reception channels (or reception) for the memory device 150 . Ways) each independently, as well as a plurality of channels (or ways) for the plurality of memory systems, in particular the master memory, by a controller of any memory system in the plurality of memory systems, for example the master memory system. After checking the status of the channels (or ways) between the system and the rest of the memory systems, eg the master memory system and the slave memory systems, the best transmit channels (or transmit ways) and the best receive channels for the memory systems. (or reception ways) are each independently determined. In other words, in an embodiment of the present invention, a plurality of channels (or ways) for memory dies of the memory device 150, or a plurality of channels (or ways) for a plurality of memory systems, Check whether it is a busy state, a ready state, an active state, an idle state, a normal state, an abnormal state, etc., for example, determine the channels (or ways) in the ready state or idle state as the best channels (or ways) in the normal state do. In particular, in an embodiment of the present invention, in a plurality of channels (or ways), the usable capacity of the channel (or way) is in the normal range or the operating level of the channel (or the way) is in the normal range. Determines (or ways) as the best channels. Here, the operation level of the channel (or way) may be determined by the operation clock, power level, current/voltage level, operation timing, temperature level, and the like in each channel (or ways). In addition, in an embodiment of the present invention, information on each memory system, for example, the ability for command operations in each memory system or the controller 130 and the memory device 150 included in each memory system, For example, in a plurality of memory systems, the master memory system is configured to correspond to performance capability, process capability, process speed, and process latency for command operations. decide Here, the master memory system may be determined through competition between a plurality of memory systems, for example, through competition between the host 102 and each memory system according to a connection order between the memory systems.

In relation to the embodiment, FIGS. 4 and 5 describe an example of using a memory included in a host as a cache device for storing metadata.

Referring to FIG. 4 , the host 102 may include a processor 104 , a host memory 106 , and a host controller interface 108 . The memory system 110 may include a controller 130 and a memory device 150 . The controller 130 and the memory device 150 described in FIG. 4 may be similar to the controller 130 and the memory device 150 described in FIGS. 2 to 3 .

Hereinafter, content that can be technically distinguished from the controller 130 and the memory device 150 described in FIG. 4 and the controller 130 and the memory device 150 described in FIGS. 2 to 3 will be mainly described. . In particular, the logic block 160 in the controller 130 may correspond to the flash translation layer (FTL) unit 40 described in FIG. 3 . However, according to an embodiment, the logic block 160 in the controller 130 may further perform roles and functions not described in the flash translation layer (FTL) unit 40 .

The host 102 may include a high-performance processor 104 and a large-capacity host memory 106 compared to the memory system 110 interworking with the host 102 . Host 102 within the processor 104 and host memory 106 is low, unlike space constraints, and the memory system 110, as needed, the hardware upgrade (upgrade) of the processor 104 and host memory 106 as possible There are advantages. Accordingly, in order to increase the operating efficiency of the memory system 110 , the resource of the host 102 may be utilized.

As the amount of data that the memory system 110 can store increases, the amount of metadata corresponding to data stored in the memory system 110 also increases. Since the space of the memory 144 in which the controller 130 can load meta data in the memory system 110 is limited, an increase in the amount of meta data places a burden on the operation of the controller 130 . For example, due to the limitation of the space in the memory 144 that the controller 130 can allocate for the meta data, some but not all of the meta data may be loaded. If the location that the host 102 wants to access is not included in the partially loaded metadata, the controller 130 must re-store the loaded metadata in the memory device 150 if a portion of the loaded metadata is updated, Meta data corresponding to a location to be accessed by the host 102 must be read from the memory device 150 . These operations may be necessary for the controller 130 to perform a read or write operation requested by the host 102 , and may degrade the operating performance of the memory system 110 .

Depending on the embodiment, the storage space of the host memory 106, including a host (102) as compared to a controller 130, memory 144 that can be used may be thousands of times greater in several orders of magnitude. Therefore, the memory system 110 includes controller 130 that the metadata 166 is used to transfer to the host 102 within the host memory 106, the host 102 within the host memory 106, a memory system (110 ) can be used as a cache memory for the address translation process. In this case, the host 102 does not transmit the logical address together with the command to the memory system 110, but converts the logical address into a physical address based on the metadata 166 stored in the host memory 106 and then executes the command and Together, the physical address may be transferred to the memory system 110 . The memory system 110 may omit a process of converting a logical address into a physical address, and may access the memory device 150 based on the transferred physical address. In this case, since the above-described controller 130 can relieve the operational burden generated while using the memory 144 , the operational efficiency of the memory system 110 can be very high.

Meanwhile, even if the memory system 110 transmits the meta data 166 to the host 102 , the memory system 110 manages information that is a reference to the meta data 166 (that is, updates, deletes, and creation, etc.). The controller 130 in the memory system 110 may perform a background operation such as garbage collection and wear leveling according to the operating state of the memory device 150 , and transfer the data transmitted from the host 102 to the memory device 150 . ), a physical location (physical address) to be stored in the memory device 150 may be determined, so the physical address of data in the memory device 150 may be changed. Accordingly, the management of the information (source) serving as a reference for the meta data 166 may be managed by the memory system 110 .

That is, when the memory system 110 determines that it is necessary to modify or update the metadata 166 transmitted to the host 102 in the process of managing the metadata 166, the memory system 110 sends the metadata 166 to the host ( 102 ) may request an update of the metadata 166 . The host 102 may update the metadata 166 stored in the host memory 106 in response to a request from the memory system 110 . Through this, the metadata 166 stored in the host 102 within the host memory 106 may maintain a current state, and a host controller interface 108 uses the metadata 166 stored in the host memory 106 Even if the address value to be transmitted to the memory system 110 is converted, an operation problem may not occur.

Meanwhile, the metadata 166 stored in the host memory 106 may include first mapping information for identifying a physical address corresponding to a logical address. Referring to FIG. 4 , in metadata corresponding to a logical address and a physical address, first mapping information for identifying a physical address corresponding to the logical address and a logical address corresponding to the physical address are checked Second mapping information for Among them, the metadata 166 stored in the host memory 106 may include first mapping information. The second mapping information is mainly used for an internal operation of the memory system 110 , and the host 102 stores data in the memory system 110 or reads data corresponding to a specific logical address from the memory system 110 . May not be used for action. According to an embodiment, the memory system 110 may not transmit the second mapping information to the host 102 .

Meanwhile, the controller 130 in the memory system 110 manages (creates, deletes, updates, etc.) the first mapping information or the second mapping information, and transmits the first mapping information or the second mapping information to the memory device 150 . can be saved Host 102 within the host memory (106) is a volatile memory device, the host 102, and if the memory system (110) for an event such as a power outage occurs, the host 102 within the host memory 106 Meta data 166 stored in may disappear. Therefore, the memory system 110 within the controller 130 includes a host 102 within the host as to maintain the metadata 166 stored in the memory 106 to the latest state as the current state the first mapping information or the second mapping information may be stored in the memory device 150 .

4 and 5 and, in the case where the metadata 166 stored in the host 102 within the host memory 106, the operation reads the data in the host 102, a memory system 110.

Power is supplied to the host 102 and the memory system 110, a can associate the host 102 and the memory system 110. When the host 102 and the memory system 110 work together, metadata (L2P MAP) stored in the memory device 150 may be transmitted to the host memory 106 .

When a read command is generated by the processor 104 in the host 102 , the read command is transmitted to the host controller interface 108 . After receiving the read command, the host controller interface 108 transmits a logical address corresponding to the read command to the host memory 106 . Based on the meta data (L2P MAP) stored in the host memory 106 , the host controller interface 108 may recognize a physical address corresponding to the logical address.

The host controller interface 108 transmits a read command (Read CMD) together with a physical address to the controller 130 in the memory system 110 . The controller 130 may access the memory device 150 based on the received read command and the physical address. Data stored in a location corresponding to a physical address in the memory device 150 may be transferred to the host memory 106 .

The process of reading data from the memory device 150 including the non-volatile memory device may take more time than the process of reading data from the host memory 106, which is another non-volatile memory. In the above-described read process, a process in which the controller 130 receives a logical address from the host 102 and finds a corresponding physical address may be omitted. In particular, while the controller 130 finds the physical address, the operation of accessing the memory device 150 and reading the metadata may disappear. Through this, a process by which the host 102 reads data stored in the memory system 110 may be further accelerated.

6A illustrates a first example of a transaction between a host and a memory system in a data processing system according to an embodiment of the present invention.

Referring to FIG. 6A , the host 102 storing the map information (MAP INFO.) may transmit a read command (READ COMMAND) including a logical address (LBA) and a physical address (PBA) to the memory system 110 . have. When there is a physical address (PBA) corresponding to a logical address (LBA) corresponding to a read command (READ COMMAND) in the map information stored by the host 102 , the host 102 provides a logical address (LBA) and a physical address ( A read command (READ COMMAND) including PBA) may be transmitted to the memory system 110 . However, if there is no physical address (PBA) corresponding to the logical address (LBA) corresponding to the host map information within the read commands (102) is stored (READ COMMAND), the host 102 is not a physical address (PBA) A read command including only the logical address LBA may be transmitted to the memory system 110 .

Although FIG. 6A is exemplified by a read command (READ COMMAND), it may also be applied to a write command or a delete command that the host 102 can transmit to the memory system 110 according to an embodiment.

6B illustrates a second example of a transaction between a host and a memory system in a data processing system according to an embodiment of the present invention.

Referring to FIG. 6B , the memory system 110 may transmit map information MAP INFO. to the host 102 . The memory system 110 may transmit the map information MAP INFO. using the response RESPONSE to the command of the host 102 .

There may be no special restrictions on the response RESPONSE for transmitting map information. For example, the memory system 110 may transmit the map information to the host 102 using a response corresponding to a read command, a response corresponding to a write command, or a response corresponding to a delete command.

The memory system 110 and the host 102 may send and receive commands and responses according to a unit format set according to a preset protocol. For example, the format of the response RESPONSE may include a basic header, a command due to success or failure of the command transmitted by the host 102 , and additional information indicating the state of the memory system 110 . The memory system 110 may transmit the map information to the host 102 by including the map information in the response RESPONSE.

7A illustrates a first operation of a host and a memory system according to an embodiment of the present invention. Specifically, FIG. 7A shows the specific operation of a host and a memory system that transmits and receives a command including a logical address (LBA) and a physical address (PBA), such as the host 102 and the memory system 110 described in FIG. 6A. explain about

Referring to FIG. 7A , the host may generate a command COMMAND including a logical address LBA ( 812 ). Thereafter, the host may check whether a physical address (PBA) corresponding to the logical address (LBA) is present in the map information ( 814 ). If there is no physical address (PBA) (NO in 814), the host may send a command (COMMAND) including a logical address (LBA) (818).

On the other hand, if there is a physical address (PBA) (YES in 814), the host may add the physical address (PBA) to the command (COMMAND) including the logical address (LBA) (816). The host may send a command (COMMAND) including a logical address (LBA) and a physical address (PBA) (818).

The memory system may receive an externally transmitted command ( 822 ). The memory system may check whether a physical address (PBA) is included in the received command ( 814 ). If there is no physical address (PBA) in the received command (NO in 824), the memory system may search for a physical address corresponding to the logical address included in the received command (832).

If the received command includes the physical address (PBA) (YES in 824), the memory system may check whether the physical address (PBA) is valid (826). The memory system transmits the map information to the host , and the host performs mapping based on the map information transmitted by the memory system, so that the physical address (PBA) can be included in the command and delivered. However, after the memory system transmits the map information to the host , the map information managed by the memory system may be changed or updated. As such, when the map information is dirty, the physical address (PBA) delivered by the host cannot be used as it is, so the memory system can determine whether the physical address (PBA) included in the received command is valid. If the physical address (PBA) included in the received command is valid (YES in 826), the memory system may use the physical address (PBA) to perform an operation corresponding to the command (830).

If the physical address (PBA) included in the received command is not valid (NO in 826 ), the memory system may ignore the physical address (PBA) included in the received command ( 828 ). In this case, the memory system may search for a physical address (PBA) based on the logical address (LBA) included in the received command ( 832 ).

7B illustrates a second operation of a host and a memory system according to an embodiment of the present invention. Specifically, FIG. 7B illustrates a process in which the host 102 requests map information from the memory system 110 and the memory system 110 transmits the map information in response to the request of the host 102 .

Referring to FIG. 7B , a need for map information may arise in the host 102 . For example, when the host 102 allocates a space for storing map information or expects faster data input/output from the memory system 110 in response to a command, the host 102 provides information about the map information. Needs may arise. Also, a need for map information may occur in the host 102 according to a user's request.

The host 102 may request map information from the memory system 110 , and the memory system 110 may prepare the map information in response to the request of the host 102 . Depending on the implementation, the host 102 may specifically request map information necessary for the memory system 110 . Meanwhile, in another embodiment, the host 102 may only request map information from the memory system 110 and the memory system 110 may determine which map information to provide.

The memory system 110 may transmit the prepared map information to the host 102 . The host 102 may store the map information transmitted from the memory system 110 in an internal storage space (eg, the host memory 106 described in FIG. 4 ).

The host 102 may include the physical address PBA in a command COMMAND transmitted to the memory system 110 by using the stored map information. The memory system 110 may perform a corresponding operation using the physical address PBA included in the command COMMAND.

7C illustrates a third operation of a host and a memory system according to an embodiment of the present invention. Specifically, Figure 7c illustrates a process of a memory system 110 receives the map information in response to the request of the need to pass the map information to the host 102, and host 102, a memory system 110.

Referring to FIG. 7C , the memory system 110 may notify the host 102 to transmit map information. In response to the notification related to the map information transmitted from the memory system 110 , the host 102 may check whether the map information in the host 102 can be stored. When the host 102 can receive the map information transmitted from the memory system 110 , the host 102 may allow the memory system 110 to transmit the map information. After preparing the map information to be transmitted to the host 102 , the memory system 110 may transmit the map information to the host 102 .

Thereafter, the host 102 may store the received map information in an internal storage space (eg, the host memory 106 described in FIG. 4 ). After performing mapping based on the stored map information, the host 102 may include a physical address (PBA) in a command to be transmitted to the memory system 110 .

The memory system 110 may check whether a physical address (PBA) is included in the command transmitted from the host 102 , and may perform an operation corresponding to the command using the physical address (PBA).

In relation to the transmission of the map information, if the operation of the host 102 and the memory system 110 described in Figure 7b the host 102 are performed in a directed, the host 102 is described in Figure 7c, and a memory system (110) The operation may be different from that performed by the memory system 110 . According to an embodiment, the memory system 102 and the host 110 may selectively use the method of transmitting the map information described with reference to FIGS. 7B and 7C according to an operating environment.

7D illustrates a fourth operation of the host and the memory system according to an embodiment of the present invention. Specifically, FIG. 7D illustrates a case in which the memory system transmits map information to the host while the host and the memory system are interworking.

Referring to FIG. 7D , the memory system may check whether an operation corresponding to the command transmitted from the host is completed ( 862 ). After the operation corresponding to the command is completed, the memory system may check whether there is map information to be transmitted to the host before transmitting the response RESPONSE corresponding to the command ( 864 ). If there is no map information to send to the host (NO of 864), the memory system can send a response (RESPONSE) including information on whether the operation corresponding to the command sent from the host has been completed (success or failure). There is (866).

When there is map information to be transmitted to the host by the memory system (YES in 864), the memory system may check whether a notification for transmitting the map information is made (868). Here, the NOTICE may be similar to that described in FIG. 7C . If the memory system wants to transmit the map information, but the memory system transmits the map information to the host , if a notice has not been made in advance (NO in 868), the memory system sends a notification (NOTICE) to the response (RESPONSE). In addition, it can be delivered to the host (870).

If the notification (NOTICE) for transmitting the map information has already been made (YES in 868), the memory system may add the map information to the response (872). The memory system may then send a response including the map information (874).

The host may receive at least one of a response (RESPONSE) transmitted from the memory system, a response including a notification (RESPONSE WITH NOTICE), and a response including map information (RESPOSNE WITH MAP INFO.) (842).

The host may check whether the received response includes a notification (844). If the received response includes a notification (YES in 844), the host may prepare to receive and store map information that can be delivered at a later time (846). Thereafter, the host may check a response corresponding to the previous command (852). For example, the host can check the response to determine whether the previous command succeeded or failed.

If the received response does not include a notification (NO in 844), the host may check whether the response includes map information (848). If the response does not include map information (NO in 848), the host can check the response corresponding to the previous command (852).

When the received response includes the map information (YES in 848), the host may store the map information included in the response in the host internal storage space or update the already stored map information (850). Thereafter, the host may check a response corresponding to the previous command (852).

Based on the above-described embodiment, the memory system may transmit map information to the host. After processing the command sent by the host , the memory system may transmit map information using a response corresponding to the command. Furthermore, after the memory system transmits the map information to the host , the memory system may generate and store a log or history of the transmitted map information. Even if power supply is resumed after power supply to the host and the memory system is interrupted, the memory system may transmit map information to the host using the aforementioned log or history. The host can transmit a command based on the transmitted map information, and the data input/output performance of the memory system can be improved according to the command.

On the other hand, although specific embodiments have been described in the detailed description of the present invention, various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments and should be defined by the claims described below as well as the claims and equivalents.

8A illustrates an example of a memory system that performs a read operation according to an embodiment of the present invention. 8B and 8C illustrate examples of a method of performing a read operation by a memory system according to an embodiment of the present invention.

Hereinafter, a read operation according to the first embodiment of the present invention will be described with reference to FIGS. 8A and 8B . 8A and 8B , the memory system 110 controls the nonvolatile memory device 150 that stores user data UDAT and metadata of the user data UDAT and the nonvolatile memory device 150 . A controller 130 may be included.

The controller 130 receives the map version (HV#) of the L2P map information (L2P_MAP) including the read command (RD_CMD), the logical address (HLBA), the physical address (HPBA), and the logical address (HLBA) from the host 102 . can be received (S100). The map version V# received from the host 102 may have a state value at a time when the L2P map information L2P_MAP including the logical address HLBA is transmitted from the memory system 110 to the host 102. .

The controller 130 receives from the host 102 using the map version (CV#) of the L2P map information (L2P_MAP) stored in the memory 144 and including the logical address (HLBA) received from the host 102 . It is possible to determine the validity of the assigned physical address (HPBA). The L2P map information (L2P_MAP) stored in the memory 144 of the controller 130 may be newer than the L2P map information (L2P_MAP) stored in the host and the memory device. The map version CV# stored in the memory 144 of the controller 130 may be updated whenever the physical address PBA corresponding to the logical address LBA included in the L2P map information L2P_MAP is changed.

That is, the controller 130 determines the validity of the physical address HPBA received from the host 102 , the map version CV# stored in the memory 144 , which is an inactive memory, and the map received from the host 102 . It may be determined whether the versions (HV#) are the same (S300a, first verification operation).

As a result of the determination of S300a, if the map version CV# and the map version HV# are not the same, the controller 130 may determine that the logical address HLBA received from the host 102 is invalid. Accordingly, the controller 130 performs a normal read operation (S200). The normal read operation searches for a physical address corresponding to the logical address (HLBA) received from the host 102 from L2P map information (L2P_MAP) stored in the memory system, and refers to a read operation performed on user data stored in the retrieved physical address. do.

As a result of the determination of S300a, if the map version (CV#) and the map version (HV#) are the same, the controller 130 determines whether the physical address (HPBA) received from the host 102 is valid. The meta data MDAT stored in the meta area 200 of the page corresponding to the HPBA) may be read out and temporarily stored in the memory 144 ( S300b ). In this case, the controller 130 may also read-out the user data UDAT stored in the user area 100 of the page corresponding to the physical address HPBA and temporarily store it ( S300b ). The metadata MDAT stored in the meta area 200 of the page corresponding to the physical address HPBA includes a logical address (MLBA) and a logical address (MLBA) of the user data (UDAT) stored in the user area 100 . It may include a map version (MV#) of the L2P map information (L2P_MAP). The map version MV# stored in the meta area 200 of the page corresponding to the physical address HPBA may have a state value at the time when the user data UDAT is programmed.

The controller 130 uses the logical address (MLBA) and the map version (MV#) output from the non-volatile memory device 150 corresponding to the physical address (HPBA) received from the host 102 , the host 102 . It is possible to determine the validity of the received physical address (HPBA) from (S300c, second verification operation). That is, in the controller 130 , the map version HV# received from the host 102 and the map version MV# read out from the memory device 150 are the same, and the logical address (HV#) received from the host 102 is HLBA) and the logical address MLBA read out from the memory device 150 may be the same.

As a result of the determination of S300c, if the map version (HV#) and the map version (MV#) are the same and the logical address (HLBA) and the logical address (MLBA) are the same, the S300b transmits the temporarily stored user data (UDAT) to the host. can be (S700). As such, an embodiment of the present invention reduces latency due to an address translation operation by performing a read operation on the first physical address HPBA without a separate address translation operation for converting a logical address (HLBA) into a physical address. can be reduced Accordingly, the speed of the read operation may be improved. In addition, since the read operation is performed on the physical address whose validity has been verified through the first and second validation operations according to the embodiment of the present invention, reliability of the read operation may be improved.

As a result of the determination of S300c, if the map version (HV#) and the map version (MV#) are not the same or the logical address (HLBA) and the logical address (MLBA) are not the same, the controller 130 sends the It may be determined that the received logical address (HLBA) is invalid.

For example, if the logical address (HLBA) and the logical address (MLBA) are not the same, but the map version (HV#) and the map version (MV#) are the same, the physical address (HPBA) corresponds to the logical address (HLBA). It may include a case where data corresponding to a logical address other than data is stored. Accordingly, the controller 130 may determine that the physical address HPBA is invalid.

Also, if the logical address (HLBA) and logical address (MLBA) are the same, but the map version (HV#) is different from the map version (MV#), the physical address (HPBA) contains old data corresponding to the logical address (HLBA). It may include a case where it is stored. Accordingly, the controller 130 may determine that the physical address HPBA is invalid.

In addition, when the map version (HV#) is a lower version than the map version (CV#) or the map version (MV#), the controller 130 determines that the data corresponding to the logical address (HLBA) is not the physical address (HPBA). , it can be determined that the copy has been moved to another physical address. That is, since the physical address HPBA is an old physical address, the controller 130 may determine that the physical address HPBA is invalid.

Also, when the map version (HV#) is higher than the map version (CV#) or the map version (MV#), the controller 130 determines that an error such as a bit flip has occurred in the map version (HV#). can The error is a process in which the controller 130 uploads L2P map information to the host 102 or the process in which the host 102 transmits a physical address (HPBA) and map version (HV#) to the controller 130 along with a read command. most likely occurred in That is, since the physical address HPBA is a physical address including an error, the controller 130 may determine that the physical address HPBA is invalid.

Accordingly, the controller 130 may delete the temporarily stored user data UDAT in S300b. And the controller 130 performs a normal read operation (S200).

On the other hand, when the controller 130 does not store (HIT) the map version (CV#) corresponding to the logical address (HLBA) in the memory 144 (MISS), the controller 130 stores the map version (CV#) corresponding to the logical address (HLBA) in the physical address (HPBA). The validity of the physical address (HPBA) can be verified by using the logical address (MLBA) and the second map version (MV#) stored in the corresponding page. As such, in the embodiment of the present invention, even if the map version (CV#) corresponding to the logical address (HLBA) is not stored in the controller 130 (MISS), a separate method for converting the logical address (HLBA) into a physical address Without an address translation operation, the validity of the first physical address HPBA received from the host 102 may be verified using the logical address MLBA and the map information MV# stored in the memory device 150 . .

Hereinafter, a read operation according to a second embodiment of the present invention will be described with reference to FIGS. 8A and 8C . In the description of FIG. 8C , differences from FIG. 8B and technically distinct differences will be mainly described.

While the first validation operation of the physical address (HPBA) received from the host 102 of S300a of FIG. 8C is performed, the controller 130 performs logic for the second validation operation of the physical address (HPBA) of FIG. 300B . A readout operation of the address (MLBA) and the map version (MV#) may be performed ( FIG. 300B ). Accordingly, since the validation process of the physical address (HPBA) can be performed faster than FIG. 8B , the latency of the read operation can be reduced.

Hereinafter, a specific method of performing a write operation and a read operation by the memory system 110 of the present invention will be described with reference to FIGS. 9 to 12 .

9 shows that the first user data UDAT1 corresponding to the first logical address LBA1 is converted to the first physical address PBA1 of the memory device 150 by the first write command WT_CMD1 received from the host 102 . ) and an operation in which L2P map information is generated and transmitted to the host 102 will be described.

FIG. 10 shows that the first user data UDAT1 stored in the first physical address PBA1 is copied to the physical address PBA2 and stored in the first physical address PBA1 by an internal background operation of the memory system 110 . An operation for erasing the first user data UDAT1 and a first read operation for the first read command RD_CMD1 received from the host will be described.

11 is a diagram of programming the second user data UDAT2 corresponding to the second logical address LBA2 to the first physical address PBA1 in the erased state by the second write command WT_CMD2 received from the host 102. An operation and a second read operation for the second read command RD_CMD2 received from the host will be described.

12 shows an operation in which third user data UDAT3 corresponding to a first logical address LBA1 is programmed into a physical address PBA3 by the third write command WT_CMD3 received from the host 102 and from the host A third read operation with respect to the received third read command RD_CMD3 will be described.

Referring to FIG. 9 , the controller 130 may receive a first write command WT_CMD1 and a first logical address LBA1 and first user data UDAT1 from the host 102 ( S405 ). The first logical address LBA1 received in operation S405 may be a newly allocated logical address that does not correspond to user data currently stored in the memory device 150 .

The controller 130 sets the state value of the map version V# for the first logical address LBA1 to the initial value "00" and stores it in the memory 144 (S410).

Thereafter, the controller 130 controls the memory device 150 so that the first user data UDAT1, the first logical address LBA1, and the map version V# are programmed into the memory device 150 (S415). Accordingly, the memory device 150 stores the first user data UDAT1 in the user area 100 of the page PAGE1, and the first logical address LBA1 and the map version in the meta area 200 of the page PAGE1. (V00) is programmed (S415).

The memory device 150 may transmit the first physical address PBA1 of the page PAGE1 on which the program operation is performed to the controller 130 together with a response indicating that the program operation is completed. Accordingly, the controller 130 may check the first physical address PBA1 on which the program operation is performed ( S420 ).

The controller 130 associates the first physical address PBA1 with the first logical address LBA1 to generate L2P map information L2P_MAP ( S425 ). The controller 130 may transmit the L2P map information (L2P_MAP) generated in step S425 and the map version V00 generated in step S410 to the host 102 (S430). Accordingly, the host 102 may store the L2P map information and the map version V00 received from the controller 130 . That is, the L2P map information (L2P_MAP) and the map version (V00) stored in the host 102 may be the same as the map version (V00) generated by the controller 130 in S410 and the L2P map information generated in S425. .

Hereinafter, referring to FIG. 10 , after step S430 of FIG. 9 , the first user data UDAT1 stored in the first physical address PBA1 is converted to the physical address PBA2 by the internal background operation of the memory system 110 . After the first user data UDAT1 copied and stored in the first physical address PBA1 is erased, a first read operation with respect to the first read command RD_CMD1 received from the host will be described.

After step S430 of FIG. 9 , the controller 130 may determine the memory block including the page PAGE1 corresponding to the first physical address PBA1 as the victim block on which the background operation is to be performed ( S440 ). The first user data UDAT1 is stored in the user area 100 of the page PAGE1 corresponding to the first physical address PBA1, and the first logical address LBA1 and the map version V00 are stored in the meta area 200. is stored (refer to S415 in FIG. 9).

The controller 130 updates the map version V# of the L2P map information including the controller first logical address LBA1 from “00” to “01” and stores it in the memory 144 ( S450 ).

The controller 130 copies the first user data UDAT1, the first logical address LBA1, and the updated map version V01 stored in the first physical address PBA1 to the physical address PBA2 to the memory device. (150) is controlled (S460). Accordingly, the memory device 150 copies the first user data UDAT1 to the user area 100 of the page PAGE2 in the erased state, and the first logical address LBA1 to the meta area 200 of the page PAGE2. And the updated map version (V01) is copied (S460).

The memory device 150 may transmit the physical address PBA2 of the program operation PAGE2 to the controller 130 together with a response indicating that the program operation is completed. Accordingly, the controller 130 may check the physical address PBA2 on which the copy operation is performed (S465).

The controller 130 updates the L2P map information L2P_MAP by mapping the physical address PBA2 instead of the first physical address PBA1 mapped to the first logical address LBA1 ( S470 ).

The controller 130 invalidates the first physical address PBA1 ( S475 ), and performs an erase operation on the victim block including the page PAGE1 corresponding to the invalidated first physical address PBA1 to store user data ( UDAT) can be erased (S480). Accordingly, the page PAGE1 may be in an erased state.

Thereafter, after the erase operation is performed on the first physical address (PBA1) in S480, the map version (V#) updated in S450 and the L2P map information updated in S470 are not uploaded to the host 102. 102 may transmit the first logical address LBA1 , the first physical address PBA1 , and the map version V00 together with the first read command RD_CMD1 to the memory system 110 .

The controller 130 may receive the first logical address LBA1, the first physical address PBA1, and the map version V00 along with the first read command RD_CMD1 from the host 102 (S485). Accordingly, the controller may perform the read operation described with reference to FIGS. 8B and 8C of the present invention.

In this case, while the map version V00 is transmitted from the host 102 , an error such as a bit flip may occur, and the map version V00 may be changed to the map version V01 .

If, in the read operation process, the validity of the first physical address PBA1 received from the host 102 is checked only by the first verification of step S300a without performing the secondary verification process of step S300c described in FIGS. 8b and 8c. If so, the controller 130 may erroneously determine the invalid first physical address PBA1 as valid.

In this case, the map version V00 transmitted from the host 102 and the map version V01 stored in the memory 144 are not actually the same. However, due to an error, the controller 130 may determine that the map version V01 transmitted from the host 102 and the map version V01 stored in the memory 144 are the same. That is, the controller 130 may erroneously determine the first physical address PBA1 received from the host 102 as a valid physical address even though it is out of date. Accordingly, the controller 130 may transmit, to the host 102 , data in an erased state, not the user data UDAT1 corresponding to the first logical address LBA1 requested by the host (abnormal read operation).

Accordingly, the controller 130 according to an embodiment of the present invention may recognize that the page corresponding to the first physical address PBA1 is in the erased state through the second verification operation of S300c described with reference to FIGS. 8B and 8C . . That is, by the second verification operation of S300c, the controller 130 may recognize that the page corresponding to the first physical address PBA1 received from the host 102 is in the erased state. Accordingly, the first physical address ( PBA1) can be judged to be invalid.

As described above, according to the embodiment of the present invention, when the read operation is performed, the validity of the first physical address PBA1 received together with the read command RD_CMD is determined through the second verification operation of S300c, and is received from the host 102 . Even if an error occurs in the map version V#, the validity of the first physical address PBA1 received from the host 102 can be more accurately determined.

Hereinafter, with reference to FIG. 11 , after the erase operation is performed on the first physical address PBA1 in step S480 of FIG. 10 , a method of performing the second write command WT_CMD2 received from the host 102 and the host ( A method of performing a read operation on the second read command RD_CMD2 received from 102 will be described.

The controller 130 may receive the second logical address LBA2 and the second user data UDAT2 along with the second write command WT_CMD2 from the host 102 ( S500 ). The second logical address LBA2 received in operation S405 may be a newly allocated logical address that does not correspond to user data currently stored in the memory device 150 .

The controller 130 sets the state value of the map version V# for the second logical address LBA2 to the initial value "00" and stores it in the memory 144 (S510).

Thereafter, the controller 130 controls the memory device 150 so that the first user data UDAT1, the first logical address LBA1, and the map version V# are programmed in the memory device 150 (S515). Accordingly, the memory device 150 stores the second user data UDAT2 in the user area 100 of the page PAGE1 that is in an erased state by the erase operation performed in S460, and the meta area 200 of the page PAGE1. The second logical address (LBA2) and the map version (V00) are programmed in (S515).

The memory device 150 may transmit the first physical address PBA1 of the page PAGE1 on which the program operation is performed to the controller 130 together with a response indicating that the program operation is completed. Accordingly, the controller 130 may check the first physical address PBA1 on which the program operation is performed (S525). The controller 130 associates the first physical address PBA1 with the second logical address LBA2 to generate L2P map information L2P_MAP ( S530 ).

After the program operation of the map version (V00), the second logical address (LBA2), and the user data (UDAT2) is performed on the first physical address (PBA1) in S515, the map version (V#) generated in S510 and the map version (V#) generated in S530 In a state in which the generated L2P map information is not uploaded to the host 102 , the host 102 transmits the first logical address LBA1, the first physical address PBA1, and the map version (PBA1) together with the second read command RD_CMD2. V00) may be transmitted to the memory system 110 . The controller 130 may receive the first logical address LBA1 , the first physical address PBA1 , and the map version V00 along with the second read command RD_CMD2 from the host 102 ( S535 ). Accordingly, the controller may perform the read operation described with reference to FIGS. 8B and 8C of the present invention.

If, in the read operation process, the validity of the first physical address PBA1 received from the host 102 is checked only by the first verification of step S300a without performing the secondary verification process of step S300c described in FIGS. 8b and 8c. If it is determined, since the map version 00 transmitted from the host 102 and the map version V00 stored in the memory 144 are the same, the controller 130 controls the first physical address PBA1 received from the host 102 . ) may be incorrectly determined as an effective physical address.

That is, the user data UDAT2 corresponding to the second logical address LBA2 is stored in the first physical address PBA1 that is in the erased state by step S515 . Accordingly, the controller 130 stores the first physical address PBA1 instead of the user data UDAT1 corresponding to the first logical address LBA1 requested by the host and stores the user corresponding to the second logical address LBA2. Data UDAT2 may be transmitted to the host 102 (abnormal read operation).

Accordingly, the controller 130 according to an embodiment of the present invention performs the second verification operation of S300c described with reference to FIGS. 8B and 8C , the meta area 200 of the page PAGE1 corresponding to the first physical address PBA1. ), it can be recognized that the second logical address LBA2 is stored. That is, by the second verification operation of S300c, the controller 130 receives from the host 102 and the second logical address LBA2 stored in the page corresponding to the first physical address PBA1 received from the host 102 . Since the first logical addresses LBA1 are not identical, it may be determined that the first physical addresses PBA1 received from the host 102 are invalid.

Hereinafter, with reference to FIG. 12 , after step S430 of FIG. 9 , a method of performing a write operation on the third write command WT_CMD3 received from the host 102 and the third read command received from the host 102 ( A method of performing a read operation on RD_CMD) will be described.

After step S430 , the controller 130 may receive the first logical address LBA1 and the third user data UDAT3 along with the third write command WT_CMD3 from the host 102 ( S540 ).

The first logical address LBA1 received in operation S540 may be a logical address corresponding to user data currently stored in the memory device 150 . That is, the host 102 may invalidate the first user data UDAT1 corresponding to the first logical address LBA1 , and may newly associate the third user data UDAT3 with the first logical address LBA1 . The controller 130 initializes the state value of the map version 00 for the first logical address LBA1 as the map version V00 and stores it in the memory 144 ( S550 ).

Thereafter, the controller 130 controls the memory device 150 so that the third user data UDAT3, the first logical address LBA1, and the map version V01 are programmed into the memory device 150 (S555). Accordingly, the memory device 150 stores the third user data UDAT3 in the user area 100 of the page PAGE3 in the erased state and the first logical address LBA1 in the meta area 200 of the page PAGE3. and program the map version (V00) (S555).

The memory device 150 may transmit the physical address PBA3 of the page PAGE3 on which the program operation is performed to the controller 130 together with a response indicating that the program operation is completed. Accordingly, the controller 130 may check the physical address PBA3 on which the program operation is performed (S560).

The controller 130 associates the physical address PBA3 with the first logical address LBA1 to generate L2P map information L2P_MAP ( S565 ).

Thereafter, the controller 130 may invalidate the first physical address PBA1 storing the first user data UDAT1 that is the old data ( S575 ). Thereafter, the controller 130 may perform an erase operation on the user block including the first physical address PBA1 ( S580 ).

Between steps S575 and S580 , the host 102 transmits the first logical address LBA1 , the first physical address PBA1 , and the map version V00 along with the third read command RD_CMD3 to the memory system 110 . can The controller 130 may receive the first logical address LBA1 , the first physical address PBA1 , and the map version V00 along with the third read command RD_CMD3 from the host 102 ( S578 ). Accordingly, the controller may perform the read operation described with reference to FIGS. 8B and 8C of the present invention.

If, in the read operation process, the validity of the first physical address PBA1 received from the host 102 is determined only by the first verification of step S300a without performing the secondary verification process of step S300c, the controller 130 is The invalid first physical address PBA1 may be erroneously determined as valid.

By step S420 of FIG. 9 , the first logical address LBA1, V(00), and the first user data UDAT are stored in the first physical address PBA1. The first physical address PBA1 invalidated by step S575 still stores the first user data UDAT1, which is old data corresponding to the first logical address LBA1.

Accordingly, the controller 130 controls the first user data UDAT1, which is old data stored in the first physical address PBA1, rather than the third user data UDAT3 corresponding to the first logical address LBA1 requested by the host. to the host 102 (abnormal read operation).

Accordingly, the controller 130 according to an embodiment of the present invention performs the second verification operation of S300c described with reference to FIGS. 8B and 8C , the meta area 200 of the page PAGE1 corresponding to the first physical address PBA1. It can be recognized that the map version 00 stored in ) and the map version 00 stored in the memory 144 are not the same. Accordingly, the controller 130 may determine that the first physical address PBA1 received from the host 102 is invalid.

As such, according to an embodiment of the present invention, the validity of the host physical address (PBA), which is invalidated as the user data (UDAT) corresponding to the logical address and the physical address (PBA) is changed, can be more accurately determined.

As described above, by using the host memory 106 as a buffer memory for storing the map data (L2P MAP), meta data (L2P MAP) is stored due to the limitation of the storage space of the memory 144 in the memory system 110 . The process of reading from the memory device 150 and storing again may be omitted. Through this, the operating efficiency of the memory system 110 may be increased.

In addition, the memory system 110 according to an embodiment of the present invention uses a partial area of the host memory 106 included in the host 102 as a cache or buffer, and stores metadata, It is possible to overcome the limitation of the storage space of the memory 144 used by the controller 130 in the memory system 110 .

On the other hand, although specific embodiments have been described in the detailed description of the present invention, various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments and should be defined by the claims described below as well as the claims and equivalents.

Claims (20)

a nonvolatile memory device for storing user data and metadata of the user data; and
a controller for controlling the non-volatile memory device;
The controller determines whether the physical address received along with the read request and metadata from the host is valid, using metadata stored in the physical address.
The method of claim 1,
If the physical address is valid, the controller transmits the user data stored in the physical address to the host.
The method of claim 1,
the controller is
In order to determine whether the physical address is valid, while the metadata stored in the physical address is read out from the nonvolatile memory device, the user data stored in the physical address is also read out and temporarily stored.
The method of claim 3,
If the physical address is valid, the controller transmits the temporarily stored user data to the host.
The method of claim 1,
Further comprising a volatile memory for storing the latest metadata stored in the non-volatile memory device,
The controller determines whether the latest metadata stored in the volatile memory is the same as the metadata received from the host, and if the same, determines whether the physical address is valid;
The latest metadata is updated whenever a physical address corresponding to a logical address is changed.
The method of claim 5,
A memory system for reading out the user data stored in the physical address from the nonvolatile memory device and temporarily storing the user data stored in the physical address while determining whether the data is the same.
The method of claim 1,
The metadata includes a logical address and a map version of L2P map information including the logical address.
The method of claim 7,
If the physical address is invalid, the controller searches for a physical address corresponding to the logical address received from the host, and transmits user data stored in the searched physical address to the host.
The method of claim 7,
The map version received from the host has a state value at a time when the L2P map information received from the host is transmitted from the memory system.
The method of claim 7,
The map version stored in the physical address has a state value at the time when the user data is programmed in the physical address,
The logical address stored in the physical address is a logical address corresponding to the user data stored in the physical address.
A method of operating a memory system comprising: a non-volatile memory device for storing user data and metadata of the user data; and a controller for storing the latest version of the metadata, the method comprising:
receiving a physical address together with a read request and metadata from a host; and
and determining the validity of the physical address by using metadata stored in the nonvolatile memory device.
The method of claim 11,
and transmitting, by the controller, user data stored in the physical address to the host if the physical address is valid.
The method of claim 11,
and temporarily storing the user data stored in the physical address while reading out the metadata stored in the physical address from the nonvolatile memory device.
The method of claim 13,
and transmitting the temporarily stored user data to the host if the physical address is valid.
The method of claim 11,
determining whether the latest metadata is the same as the metadata received from the host; and
and determining whether the physical address is valid when the latest metadata is the same as the metadata received from the host.
The method of claim 15,
The step of determining whether the same
and reading out the user data stored in the physical address from the nonvolatile memory device and temporarily storing the user data.
The method of claim 11,
The metadata includes a logical address and a map version of L2P map information including the logical address.
The method of claim 17,
if the physical address is invalid, searching for a physical address corresponding to the logical address received from the host; and
and transmitting user data stored in the found physical address to the host.
The method of claim 17,
The method of operating a memory system, wherein the map version received from the host has a state value at a time when the L2P map information received from the host is transmitted from the memory system.
The method of claim 17,
The map version stored in the physical address has a state value at the time when the user data is programmed in the physical address,
The logical address stored in the physical address is a logical address corresponding to the user data stored in the physical address.

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