KR20190118393A - Semiconductor device - Google Patents

Abstract

According to an embodiment of the present invention, a semiconductor element comprises: a substrate; and a semiconductor structure arranged on the substrate and including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer arranged between the first conductive semiconductor layer and the second conductive semiconductor layer. The semiconductor structure includes a plurality of irregularities arranged on an upper surface thereof. The active layer generates ultraviolet light. AI composition of the plurality of irregularities is larger than Al composition of the active layer. A width of the plurality of irregularities is 1.5 to 2.5 times a wavelength of the ultraviolet light. A thickness of the semiconductor structure is three to nine times surface roughness (RMS: root mean square) of the plurality of irregularities.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The embodiment relates to a semiconductor device.

A semiconductor device including a compound such as GaN, AlGaN, etc. has many advantages, such as having a wide and easy-to-adjust band gap energy, and can be used in various ways as a light emitting device, a light receiving device, and various diodes.

Particularly, light emitting devices such as light emitting diodes and laser diodes using semiconductors of Group 3-5 or Group 2-6 compound semiconductors have been developed through the development of thin film growth technology and device materials. Various colors such as blue and ultraviolet light can be realized, and efficient white light can be realized by using fluorescent materials or combining colors.Low power consumption, semi-permanent lifespan, and fast response speed compared to conventional light sources such as fluorescent and incandescent lamps can be realized. It has the advantages of safety, environmental friendliness.

In addition, when a light-receiving device such as a photodetector or a solar cell is also manufactured using a group 3-5 or 2-6 compound semiconductor material of a semiconductor, the development of device materials absorbs light in various wavelength ranges to generate a photocurrent. As a result, light in various wavelengths can be used from gamma rays to radio wavelengths. It also has the advantages of fast response speed, safety, environmental friendliness and easy control of device materials, making it easy to use in power control or microwave circuits or communication modules.

Therefore, the semiconductor device may replace a light emitting diode backlight, a fluorescent lamp, or an incandescent bulb, which replaces a cold cathode tube (CCFL) constituting a backlight module of an optical communication means, a backlight of a liquid crystal display (LCD) display device. Applications are expanding to include white LED lighting devices, automotive headlights and traffic lights, and sensors that detect gas or fire. In addition, the semiconductor device may be extended to high frequency application circuits, other power control devices, and communication modules.

In particular, the light emitting device that emits light in the ultraviolet wavelength region may be used for curing, medical treatment, and sterilization by curing or sterilizing.

Recently, the research on the ultraviolet light emitting device is active, but the ultraviolet light emitting device has a problem of improving the light output, it is difficult to implement a vertical type, there is a problem that the crystallinity is degraded in the process of separating the substrate.

The embodiment provides a vertical ultraviolet light emitting device.

Further, a light emitting device excellent in crystallinity is provided.

In addition, a light emitting device having improved light output is provided.

The problem to be solved in the examples is not limited thereto, and the object or effect that can be grasped from the solution means or the embodiment described below will also be included.

A semiconductor device according to an embodiment includes a substrate; And a semiconductor structure disposed on the substrate, the semiconductor structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer. The semiconductor structure includes a plurality of irregularities disposed on the upper surface, wherein the active layer generates ultraviolet light, the Al composition of the plurality of irregularities is greater than the Al composition of the active layer, the width of the plurality of irregularities Is 1.5 to 2.5 times the wavelength of the ultraviolet light, the thickness of the semiconductor structure may be 3 to 9 times the surface roughness (RMS: root mean square) of the plurality of irregularities.

The thickness of the semiconductor structure may be 2.5 to 7 times the width of the irregularities.

The second conductivity type semiconductor layer may be adjacent to the substrate as compared with the first conductivity type semiconductor layer, and the substrate may be electrically connected to the first conductivity type semiconductor layer.

The semiconductor device may further include a first conductive layer disposed between the semiconductor structure and the substrate and electrically connecting the first conductive semiconductor layer and the substrate.

The display device may further include a second conductive layer electrically connected to the second conductive semiconductor layer, an electrode pad disposed on the second conductive layer, and a bonding layer disposed between the first conductive layer and the substrate.

And a first insulating layer disposed between the semiconductor structure and the second conductive layer, and a second insulating layer disposed between the second conductive layer and the first conductive layer.

The thickness of the semiconductor structure may be 0.02 to 0.05 times the thickness of the substrate.

The thickness of the substrate may be 100 times to 300 times the surface roughness of the unevenness.

The thickness of the substrate may be 80 times to 240 times the width of the unevenness.

The surface roughness of the plurality of irregularities may be 0.4 μm to 0.8 μm.

The Al composition of the unevenness may be 1.1 to 1.8 times the Al composition of the active layer.

According to the embodiment it is possible to manufacture a vertical ultraviolet light emitting device.

In addition, the crystallinity of the ultraviolet light emitting device can be improved.

In addition, the light output can be improved.

Various and advantageous advantages and effects of the present invention are not limited to the above description, and will be more readily understood in the course of describing specific embodiments of the present invention.

1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
2 is an enlarged view of a portion B in FIG. 1,
3 is an enlarged view of a portion C in FIG. 2,
4A to 4C are images illustrating changes in size of irregularities according to wavelengths in a semiconductor device according to an embodiment of the present disclosure.
5 is a graph showing the composition of a semiconductor device according to an embodiment of the present invention;
6 is a conceptual diagram of a semiconductor device package according to an embodiment of the present disclosure;
7 is a plan view of a semiconductor device package according to an embodiment of the present disclosure;
8A to 8M are flowcharts illustrating a method of manufacturing a semiconductor device according to an embodiment.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated and described in the drawings. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms including ordinal numbers, such as second and first, may be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be referred to as the first component, and similarly, the first component may also be referred to as the second component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings, and the same or corresponding components will be given the same reference numerals regardless of the reference numerals, and redundant description thereof will be omitted.

1 is a cross-sectional view of a semiconductor device according to an embodiment of the inventive concept, FIG. 2 is an enlarged view of a portion B in FIG. 3, FIG. 3 is an enlarged view of a portion C in FIG. 2, and FIGS. In the semiconductor device according to the embodiment of the present invention, the image showing the size change of the unevenness according to the wavelength, and FIG.

1 to 5, the semiconductor device 10 according to the embodiment includes a semiconductor structure 120 including a first conductive semiconductor layer 121, a second conductive semiconductor layer 123, and an active layer 122. ), A first electrode 141 electrically connected to the first conductive semiconductor layer 121, a second electrode 143 and a first electrode electrically connected to the second conductive semiconductor layer 123. The first conductive layer 165 electrically connected to the 141, the second conductive layer 146 electrically connected to the second electrode 143, and the bonding layer 160 disposed under the first conductive layer 165. And a substrate 170 disposed under the bonding layer 160.

The semiconductor structure 120 according to the embodiment may output light in the ultraviolet wavelength band. For example, the semiconductor structure 120 may output light in the near ultraviolet wavelength band (UV-A), may output light in the far ultraviolet wavelength band (UV-B), or light in the deep ultraviolet wavelength band (UV-A). C) can be released. The ultraviolet wavelength band may be determined by the composition ratio of Al of the semiconductor structure 120.

For example, the light (UV-A) in the near ultraviolet wavelength band may have a wavelength in the range of 320 nm to 420 nm, the light in the far ultraviolet wavelength band (UV-B) may have a wavelength in the range of 280 nm to 320 nm, and deep ultraviolet light Light in the wavelength band (UV-C) may have a wavelength in the range of 100nm to 280nm.

First, the semiconductor structure 120 includes a first conductive semiconductor layer 121, an active layer 122, and a second conductive semiconductor layer 123, and the second conductive semiconductor layer 123 and the active layer 122. It may include a recess 128 and a stepped portion 129 penetrating through and exposed to a portion of the first conductivity-type semiconductor layer 121.

When the Al composition of the semiconductor structure 120 is increased, current spreading characteristics may be degraded in the semiconductor structure 120. In addition, the amount of light emitted to the side of the active layer 122 is increased compared to the GaN-based blue light emitting device (TM mode). Such TM mode may occur in an ultraviolet semiconductor device. Here, the thickness T1 of the semiconductor structure 120 may be 2.5 μm to 3.5 μm.

The first conductive semiconductor layer 121, the active layer 122, and the second conductive semiconductor layer 123 may be disposed in a second direction (Y direction). Hereinafter, the second direction (Y direction), which is the thickness direction of each layer, is defined as the vertical direction, and the first direction (X direction) perpendicular to the second direction (Y direction) is defined as the horizontal direction, and the third direction ( Z direction) is defined as a direction perpendicular to the first direction (X direction) and the second direction (Y direction).

The first conductive semiconductor layer 121 may be formed of a compound semiconductor such as a group III-V group or a group II-VI, and may be doped with a first dopant. The first conductive semiconductor layer 121 is a semiconductor material having a composition formula of Inx1Aly1Ga1-x1-y1N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ x1 + y1 ≦ 1), for example, GaN, AlGaN, InGaN, InAlGaN and the like can be selected. The first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te. When the first dopant is an n-type dopant, the first conductive semiconductor layer 121 doped with the first dopant may be an n-type semiconductor layer.

The active layer 122 may be disposed between the first conductive semiconductor layer 121 and the second conductive semiconductor layer 123. The active layer 122 is a layer where electrons (or holes) injected through the first conductive semiconductor layer 121 and holes (or electrons) injected through the second conductive semiconductor layer 123 meet each other. The active layer 122 transitions to a low energy level as electrons and holes recombine, and may generate light having an ultraviolet wavelength.

In particular, the active layer 122 includes aluminum (Al), the composition of Al can be adjusted according to the desired ultraviolet wavelength band, through which the active layer 122 can generate light having a UV-C wavelength.

Meanwhile, referring to FIG. 5, the Al composition of the active layer 122 may be about 45% to 55%.

Here, FIG. 5 illustrates a microstructure of a semiconductor device by using a transmission electron microscope (TEM) or a scanning electron microscope (SEM), and the like to determine element composition ratios of regions, crystal grains, interfaces, etc., which are different in color from each phase in the microstructure. The elemental composition of the semiconductor device according to the embodiment may be analyzed by measuring by energy dispersive X-ray spectroscopy (EDS).

Meanwhile, in FIG. 5, the first section A1 may be a section corresponding to the unevenness R, the second section A2 may be a section corresponding to the first conductive semiconductor layer 121, and a third section. The section A3 may be a section corresponding to the active layer 122, and the fourth section A4 may be a section corresponding to the second conductive semiconductor layer 123.

In addition, at the interface between the second section A2 and the third section A3, a second-first section A2-1 corresponding to the first electrode 141 electrically connected to the first conductive semiconductor layer 121. ) May be arranged.

The active layer 122 may have any one of a single well structure, a multi well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum line structure, and the active layer 122 The second conductivity type semiconductor layer 123 is disposed on the active layer 122, and may be implemented as a compound semiconductor such as a group III-V group or a group II-VI. The second dopant may be doped in the semiconductor layer 123. The second conductivity-type semiconductor layer 123 is a semiconductor material having a composition formula of Inx5Aly2Ga1-x5-y2N (0≤x5≤1, 0≤y2≤1, 0≤x5 + y2≤1) or AlInN, AlGaAs, GaP, GaAs It may be formed of a material selected from GaAsP, AlGaInP. When the second dopant is a p-type dopant such as Mg, Zn, Ca, Sr, or Ba, the second conductive semiconductor layer 126 doped with the second dopant may be a p-type semiconductor layer.

In addition, an electron blocking layer (not shown) may be disposed between the active layer 122 and the second conductive semiconductor layer 123. The electron blocking layer (not shown) blocks the flow of electrons supplied from the first conductivity-type semiconductor layer 121 to the second conductivity-type semiconductor layer 123, whereby electrons and holes in the active layer 122 It can increase the probability of recombination. The energy band gap of the electron blocking layer (not shown) may be larger than the energy band gap of the active layer 122 and / or the second conductivity type semiconductor layer 123.

Meanwhile, irregularities R may be formed on the upper surface of the semiconductor structure 120. That is, the unevenness R may be formed on the top surface of the first conductivity-type semiconductor layer 121.

The unevenness R may be disposed so that the top surface of the first conductivity type semiconductor layer 121 has a surface roughness.

The average roughness of the unevenness R may be a value obtained by calculating a height difference of the unevenness formed on the upper surface of the first conductivity type semiconductor layer 121. The average roughness may be a root-mean-square value measured by an atomic force microscope (AFM).

The thickness T2 of the unevenness R may be a difference between the heights of the low point and the high point on the upper surface of the first conductivity type semiconductor layer 121. Meanwhile, the surface roughness of the upper surface of the first conductivity type semiconductor layer 121 is RMS (Root). Mean Square).

Here, the surface roughness of the irregularities R may be defined by the thickness T2 of the irregularities R and may be 0.4 μm to 0.8 μm.

That is, the thickness T1 of the semiconductor structure 120 may be configured to 3 to 9 times the thickness T2 of the unevenness R.

Here, when the thickness T1 of the semiconductor structure 120 is less than three times the thickness T2 of the unevenness R, the unevenness R is extracted to the first conductivity-type semiconductor layer 121 as the unevenness R becomes larger than necessary. It is difficult to expect the light extraction efficiency of the ultraviolet wavelength due to the low probability of diffuse reflection of light, on the contrary, if the thickness T1 of the semiconductor structure 120 is 9 times or more than the thickness T2 of the unevenness R, the unevenness R is fine. Light extraction efficiency by (R) may be difficult to expect.

In addition, the width (cone size, W1) of the unevenness (R) may be composed of 0.5μm to 1μm.

That is, the thickness T1 of the semiconductor structure 120 may be 2.5 to 7 times the width W1 of the unevenness R.

Here, when the thickness T1 of the semiconductor structure 120 is less than 2.5 times the width W1 of the unevenness R, the unevenness R is extracted as the first conductivity type semiconductor layer 121 as the unevenness becomes larger than necessary. It is difficult to expect the light extraction efficiency of the ultraviolet wavelength due to the low probability of diffuse reflection of light, on the contrary, if the thickness T1 of the semiconductor structure 120 is 7 times or more than the width W1 of the unevenness R, the unevenness R is fine. Light extraction efficiency by (R) may be difficult to expect.

Here, as described above, since the light of the ultraviolet wavelength band may be generated in the active layer 122 of the semiconductor structure 120, the width W1 of the unevenness R may be set to approximately twice the ultraviolet wavelength band. Preferably, the width W1 of the unevenness R may be set to 1.5 times to 2.5 times the ultraviolet wavelength band.

Meanwhile, referring to FIG. 5, the Al composition of the unevenness R may be about 60% to 80%. That is, the Al composition of the irregularities R may be 1.1 to 1.8 times the Al composition of the active layer 122.

Here, when the Al composition of the unevenness R is less than 1.1 times the Al composition of the active layer 122, it is difficult to expect an effect of adjusting the Al composition of the unevenness R, and the Al composition of the unevenness R is determined by the active layer 122. If the Al composition exceeds 1.8 times, the current spreading characteristic may be degraded more than necessary as the Al composition increases.

The Al composition of the first conductive semiconductor layer 121 is increased than the Al composition of the active layer 122, and the Al composition of the unevenness R is made of the Al composition of the first conductive semiconductor layer 121 and the Al composition of the active layer 122. Increasingly, the advancing direction of the lattice defects transmitted from the bottom of the semiconductor structure 120 may be changed at the interface of the unevenness R. As the plurality of lattice defects merge with each other at the interface, the lattice defects traveling to the upper portion of the semiconductor structure 120 may be reduced. Therefore, lattice defects of the epitaxial layer growing on the active layer 122 may be reduced and crystallinity may be improved.

In addition, by selectively increasing the Al composition of the uneven (R), it is possible to improve the light extraction efficiency by reducing the difference in refractive index between the interface between the uneven (R) and the passivation layer 180 or between the uneven (R) and the interface of the air layer. .

Here, referring to FIGS. 4A, 4B, and 4C, it is possible to confirm the change in the size of the unevenness in the same region, and the wavelength of the light generated according to the structure of FIGS. 4A, 4B, and 4C is 4A, 4B. In FIG. 4C, the wavelength of light decreases.

As described above, according to the Al composition of the semiconductor structure 120, a TM mode may be performed in which the current spreading property is lowered in the semiconductor structure 120 and the amount of light emitted to the side from the active layer 122 increases.

In the TM mode, the light generated in the active layer 122 may reduce diffuse reflection or total reflectance at the interface between the unevenness R and the passivation layer 180 according to the shape of the unevenness R, thereby reducing light loss. Accordingly, the light extraction efficiency of the semiconductor device 10 may be improved.

That is, arranged in a pattern of triangles (cone) of the irregularities (R), the width (W1) of the irregularities (R) is set to approximately twice the ultraviolet wavelength band, to reduce the light loss due to light absorption of the irregularities (R) Can be. Accordingly, the light extraction efficiency of the semiconductor device 10 may be improved.

Meanwhile, the unevenness R may be configured by a wet etching method, and may be performed by wet etching using any one material of KOH, NaOH, H ₂ SO _4, and H ₂ PO ₄ . Of course, in addition to using an electron beam irradiation method, it may be configured through at least one of the heat treatment process, IR irradiation, UV irradiation in a vacuum or inert atmosphere.

Here, the concave-convex (R) structure is not formed regularly due to the characteristics of the wet etching, and as the wet time increases, a small cone may be differentiated from the cone of a predetermined size, and thus, the width (W 1) of the concave-convex (R). May be an average value of the entire cone shape.

An electron blocking layer (not shown) is a semiconductor material having a composition formula of In _x1 Al _y1 Ga _{1 -x1- y1} N (0≤x1≤1, 0≤y1≤1, 0≤x1 + y1≤1), for example For example, it may be selected from AlGaN, InGaN, InAlGaN and the like, but is not limited thereto. The electron blocking layer (not shown) may alternately include a first layer having a high Al composition (not shown) and a second layer having a low Al composition (not shown).

The recess 128 may penetrate the second conductive semiconductor layer 123 and the active layer 122 to a part of the first conductive semiconductor layer 121.

The plurality of recesses 128 may be provided in the semiconductor structure 120, and may be spaced apart at predetermined intervals. For example, when the semiconductor structure 120 has a high bandgap energy, the current spreading characteristic of the semiconductor structure 120 may be degraded, but the recess 128 may have a current spreading and current injection characteristic in the semiconductor structure 120. Can be arranged to be improved. By such a configuration, in the semiconductor device 10 according to the embodiment, the recess 128 may improve current dispersion characteristics of the semiconductor structure 120 and increase the emission area.

In addition, the stepped portion 129 may be continuously disposed along the side surface of the semiconductor structure 120, such as the recess 128. Accordingly, the stepped portion 129 may be spaced apart from the side surface of the semiconductor structure 120 in the horizontal direction (X direction) and may have at least one inclined surface continuously disposed along the side surface. The stepped portion 129 may be disposed to surround the plurality of recesses 128 in the semiconductor structure 120. That is, the stepped portion 129 may be closed-loop in a plane (XZ plane) in the semiconductor structure 120, and the stepped portion 129 may be disposed to surround the active layer 122. By such a configuration, the separation distance between the side surface of the semiconductor structure 120 and the active layer 122 in contact with the passivation layer 180 is increased, so that even if the passivation layer 180 is peeled or the like, contaminants, moisture, and the like are prevented from the outside. It may be difficult to reach the active layer 122. As such, the stepped portion 129 may prevent the active layer 122 from being oxidized by contaminants and moisture, thereby preventing the problem of lowering the light efficiency.

The first insulating layer 131 may be disposed under the semiconductor structure 120, and may be disposed under the recess 128 and the stepped portion 129. The first insulating layer 131 electrically insulates the first conductive semiconductor layer 121 and the second conductive semiconductor layer 123 from the sidewall of the semiconductor structure 120, and makes the first electrode 141 an active layer. It may be electrically insulated from the 122 and the second conductivity-type semiconductor layer 123. The first insulating layer 131 may include a material of insulating material. For example, the first insulating layer 131 may be formed by selecting at least one selected from the group consisting of SiO ₂ , SixOy, Si ₃ N ₄ , SixNy, SiOxNy, Al ₂ O ₃ , TiO ₂ , AlN, and the like. I never do that.

In addition, the first insulating layer 131 may be formed as a single layer or multiple layers. The first insulating layer 131 may be formed of multiple layers to form an interface between adjacent layers. Accordingly, the first insulating layer 131 may reduce the spread of moisture, contaminants, etc. into the semiconductor structure 120 through the first insulating layer 131 due to a defect.

In addition, the first insulating layer 131 may be a distributed Bragg reflector (DBR) having a multilayer structure including an Si oxide or a Ti compound. However, the present invention is not limited thereto, and the first insulating layer 131 may include various reflective structures. As a result, the first insulating layer 131 may improve light extraction efficiency.

The first electrode 141 may be disposed under the semiconductor structure 120 and in the recess 128. As a result, the first electrode 141 may be electrically connected to the first conductivity-type semiconductor layer 121 exposed by the recess 128. The first electrode 141 may be in ohmic contact with the first conductivity-type semiconductor layer 121, and thus may be an ohmic electrode. For example, the first electrode 141 may be indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), or indium IGTO (IGTO). gallium tin oxide (AZO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IZO (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au, or Ni / IrOx / Au / ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn , Pt, Au, Hf may be formed to include, but is not limited to such materials. In addition, the first electrode 141 may be formed of a plurality of layers of metal material.

Here, referring to FIG. 5, the Al concentration decreases and the Ga concentration increases relatively between the first conductive semiconductor layer 121 and the first electrode 141 electrically connected to the first conductive semiconductor layer 121. That is, electrical resistance between the first conductivity type semiconductor layer 121 and the first electrode 141 may decrease.

 The second electrode 143 may be disposed under the semiconductor structure 120 and under the second conductive semiconductor layer 123. Accordingly, the second electrode 143 may be electrically connected to the second conductive semiconductor layer 123.

In detail, the second electrode 143 may be in contact with the second conductivity type semiconductor layer 123 and may extend below the first insulating layer 131 to partially cover the first insulating layer 131. By such a configuration, the area of the second electrode 143 in contact with the second conductivity-type semiconductor layer 123 is maximized, thereby increasing the current injection area, thereby improving light extraction efficiency.

In addition, the second electrode 143 may be an ohmic electrode in ohmic contact with the second conductivity-type semiconductor layer 123. For example, the second electrode 143 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), and indium IGTO (IGTO). gallium tin oxide (AZO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IZO (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au, or Ni / IrOx / Au / ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn , Pt, Au, Hf may be formed to include, but is not limited to such materials. For example, the second electrode 143 may be ITO.

The second reflective layer 145 may be disposed under the second electrode 143 to be electrically connected to the second electrode 143, and may reflect light generated by the active layer 122 to the upper portion of the semiconductor structure 120. In addition, the second electrode 143 may be partially covered by the second conductive layer 146, and may be electrically connected to the second conductive layer 146.

The second reflective layer 145 may include a material which is conductive and has a reflective function. For example, the second reflective layer 145 may include any one of Ag and Rh, but is not limited thereto. The second reflective layer 145 may include aluminum, but in this case, since the step coverage is relatively poor, only the part of the second electrode 143 may be covered. However, it is not limited to these materials.

The second conductive layer 146 may be disposed under the second reflective layer 145 to partially cover the second reflective layer 145 and the second electrode 143. Accordingly, the electrode pad 166, the second conductive layer 146, the second reflective layer 145, and the second electrode 143 may form one electrical channel.

The second conductive layer 146 may be disposed to surround the second reflective layer 145, and may be disposed under the second reflective layer 145, the second electrode 143, and the first insulating layer 131. The second conductive layer 146 may include a material having good adhesion with the first insulating layer 131, and for example, at least one selected from the group consisting of materials such as Cr, Ti, Ni, and Au. It may be made of a material and an alloy thereof, and may be made of a single layer or a plurality of layers.

The second conductive layer 146 may be disposed between the first insulating layer 131 and the second insulating layer 132, and the first insulating layer 131 and the second insulating layer from penetration of external moisture or contaminants. 132 may be protected. In addition, the second conductive layer 146 may be disposed inside the semiconductor device 10 and may be wrapped by the second insulating layer 132 so as not to be exposed to the outermost surface of the semiconductor device 10.

The second insulating layer 132 may electrically insulate the second electrode 143, the second reflective layer 145, and the second conductive layer 146 from the first conductive layer 165. The first conductive layer 165 may be electrically connected to the first electrode 141 through the second insulating layer 132.

The second insulating layer 132 and the first insulating layer 131 may be made of the same material, and are made of SiO ₂ , SixOy, Si ₃ N ₄ , SixNy, SiOxNy, Al ₂ O ₃ , TiO ₂ , AlN, or the like. At least one selected from may be formed, but is not limited thereto. However, the material is not limited thereto, and the second insulating layer 132 may be formed of a material different from that of the first insulating layer 131.

In addition, according to the embodiment, since the second insulating layer 132 is disposed on the first insulating layer 131 between the first electrode 141 and the second electrode 143, the second insulating layer 132 In the case where a defect occurs, the first insulating layer 131 may secondarily prevent penetration of external moisture and / or other contaminants. For example, when the first insulating layer 131 and the second insulating layer 132 are formed of one layer, defects such as cracks may easily propagate in the thickness direction. Therefore, external moisture or contaminants may penetrate into the semiconductor structure 120 through defects exposed to the outside.

However, according to the embodiment, since a separate second insulating layer 132 is disposed on the first insulating layer 131, defects formed in the first insulating layer 131 are difficult to propagate to the second insulating layer 132. . That is, the interface between the first insulating layer 131 and the second insulating layer 132 may serve to shield the propagation of defects.

The first reflective layer 147 may be disposed under the second insulating layer 132 and may be disposed under the first electrode 141 through the second insulating layer 132 to be electrically connected to the first electrode 141. have. In addition, since the first reflective layer 147 includes a conductive and reflective material, the first reflective layer 147 may reflect the light generated by the active layer 122 to the upper portion of the semiconductor structure 120.

The first reflective layer 147 may include, for example, any one of Ag and Rh, but is not limited thereto. The first reflective layer 147 may partially extend to cover the lower portion of the first electrode 141 and to cover the lower portion of the second insulating layer 132.

The first conductive layer 165 may be disposed under the second insulating layer 132 and the first reflective layer 147. As described above, the first conductive layer 165 may be electrically connected to the first electrode 141 through the second insulating layer 132 and may also be electrically connected to the lower substrate 170. Accordingly, the first conductive layer 165 may form an electrical channel with the first electrode 141 and the substrate 170. The first conductive layer 165 may be made of at least one material selected from the group consisting of materials such as Cr, Ti, Ni, Au, and alloys thereof, and may be formed of a single layer or a plurality of layers.

The first conductive layer 165 may be entirely formed in the semiconductor device 10. The first conductive layer 165 may be divided into a first region S1 and a second region S2, and in the first region S1, the semiconductor structure 120 and the first conductive layer 165 are perpendicular to each other. The semiconductor structure 120 and the first conductive layer 165 do not overlap in the vertical direction (Y direction), and the second region S2 is an area other than the first region S1. That is not an area. This will be described in detail with reference to FIG. 4.

The metal layer 150 may be disposed between the first conductive layer 165 and the semiconductor structure 120. In the semiconductor device 10 according to the embodiment, the metal layer 150 may be formed on the first conductive layer 165, between the second insulating layer 132 and the second conductive layer 146, and the second conductive layer 146. It may be disposed on at least one of the first insulating layer 131.

Hereinafter, the metal layer 150 will be described based on the arrangement between the first conductive layer 165 and the second insulating layer 132. The metal layer 150 may be disposed between the first conductive layer 165 and the second insulating layer 132 and may overlap the electrode pad 166 in a vertical direction (Y direction).

The metal layer 150 prevents the electrode pad 166 and the like on the interface IS from being peeled off due to the gap between the interface IS of the bonding layer 160, thereby improving reliability of the semiconductor device 10. It can be improved.

In detail, the semiconductor structure 120 has a stepped portion 129 at an outer surface thereof, such that the first insulating layer 131, the second conductive layer 146, and the second insulating layer disposed under the semiconductor structure 120 are provided. The layer 132 may have slopes I1, I2, and I3 formed corresponding to the stepped portion 129.

For example, the first insulating layer 131 has a first inclined surface I1 on the upper surface, the second conductive layer 146 has a second inclined surface I2 on the upper surface, and the second insulating layer 132 is on the upper surface. It may have a third inclined surface (I3).

The first inclined plane I1, the second inclined plane I2, and the third inclined plane I3 may be disposed in the stepped portion 129 in the outward direction of the semiconductor device 10. The height differences h1, h2, and h3 of the first inclined plane I1, the second inclined plane I2, and the third inclined plane I3 may be the same as the height difference of the stepped part 129. Accordingly, when the bonding layer 160 adheres to the substrate 170, the upper surface of the first bonding layer 160a has the same inclination as that of the inclined surface, and thus, the first bonding layer 160a and the second bonding layer are formed. In the bonding layer 160 formed by the bonding of the 160b, pores may be formed due to the height difference due to the inclination at the interface IS of the first and second bonding layers 160a and 160b. In this case, the voids may be arranged in various shapes and sizes at the interface IS in the bonding layer 160. In addition, the voids may be formed of a plurality of layers (first conductive layer 165, second insulating layer 132, second conductive layer 146, electrode pad 166, etc.) disposed on the bonding layer 160. The bonding force with the bonding layer 160 may be lowered. Thus, when a pressure or the like is applied to the plurality of layers positioned on the upper portion, it may cause a peel off problem in which the plurality of layers are peeled off. As a result, the semiconductor device may degrade reliability. However, as described above, the metal layer 150 is disposed between the first metal layer 150 and the semiconductor structure 120 and above the bonding layer 160 to compensate for the height difference of the interface IS in the bonding layer 160. can do. Accordingly, the metal layer 150 may prevent the formation of voids at the interface IS, and as a result, the electrode pad 166 may be prevented from peeling off.

In addition, the metal layer 150 may include a metal material, and may include, for example, Au, Rb, Ag, and the like, but is not limited thereto.

As described above, the electrode pad 166 is disposed on the second conductive layer 146 through the first insulating layer 131, and the second conductive layer 146, the second reflective layer 145, and the second electrode are disposed on the second conductive layer 146. An electrical channel may be formed with the 143 to be electrically connected to the second conductive semiconductor layer 123.

The electrode pad 166 may have a single layer or a multilayer structure and may include titanium (Ti), nickel (Ni), silver (Ag), and gold (Au). For example, the electrode pad 166 may have a structure of Ti / Ni / Ti / Ni / Ti / Au.

The bonding layer 160 may comprise a conductive material. For example, the bonding layer 160 may include a material selected from the group consisting of gold, tin, indium, aluminum, silicon, silver, nickel, and copper, or an alloy thereof. As described above, the bonding layer 160 may include the first bonding layer 160a and the second bonding layer 160b, and the first bonding layer 160a may be disposed on the bonding layer 160 and disposed thereon. The second insulating layer 132 may be in contact with the second bonding layer 160b to be in contact with the substrate 170.

The substrate 170 is disposed under the bonding layer 160 and may be made of a conductive material. In exemplary embodiments, the substrate 170 may include a metal or a semiconductor material. The substrate 170 may be a metal having excellent electrical conductivity and / or thermal conductivity. In this case, the substrate 170 may quickly release heat generated while the semiconductor device 10 operates to the outside. In addition, when the substrate 170 is made of a conductive material, the first electrode 141 may receive a current from the outside through the substrate 170.

Meanwhile, the thickness T3 of the substrate 170 may be 80 μm to 120 μm.

A bonding layer 171 may be disposed on the bottom surface of the substrate 170 to be bonded to the circuit board. Here, the thickness of the bonding layer 171 may be 8μm to 12μm. However, the present invention is not limited thereto.

The thickness T1 of the semiconductor structure 120 may be configured to 0.02 times to 0.05 times the thickness T3 of the substrate 170.

That is, the thickness T3 of the substrate 170 may be about 20 to 50 times the thickness T1 of the semiconductor structure 120.

That is, as described above, as the wavelength of the light emitted from the semiconductor structure 120 decreases, the thickness T1 of the semiconductor structure 120, the thickness T2 of the unevenness R, and the width W1 of the unevenness R As a result, the thickness T3 of the substrate 170 may be reduced.

As a result, the thickness T3 of the substrate 170 does not need to be larger than necessary, and thus the semiconductor device 10 may be thinned. In addition, as the unevenness R decreases according to the wavelength of light emitted from the semiconductor structure 120, even if the thickness T3 of the substrate 170 serving as the electrode is reduced, the wiring resistance of the electrode is larger than that of the large unevenness of the conventional light emitting region. It may have equivalent or improved properties compared to that formed.

On the other hand, when the thickness T3 of the substrate 170 is less than 20 times the thickness T1 of the semiconductor structure 120, the substrate 170 may not sufficiently support the semiconductor structure 120, which may cause reliability problems. . In addition, when the thickness T3 of the substrate 170 is greater than 50 times the thickness T1 of the semiconductor structure 120, the thickness of the substrate 170 may be greater than necessary, which may cause difficulty in processing the substrate 170. As the substrate 170 is processed, the device on the substrate 170 may be deteriorated.

In addition, the thickness T3 of the substrate 170 may be configured to be 100 to 300 times the thickness T2 of the unevenness R.

In addition, the thickness T3 of the substrate 170 may be configured to be 80 to 240 times the width W1 of the unevenness R.

The passivation layer 180 may be disposed to surround the outer surface of the semiconductor device 10. In detail, the passivation layer 180 may be disposed on the upper surface of the semiconductor structure 120, the first insulating layer 131, and the electrode pad 166, and may be disposed to expose a portion of the electrode pad 166. Thus, the electrode pad 166 may be electrically connected to the outside through wire bonding or the like.

The passivation layer 180 may have a thickness of 200 nm or more and 500 nm or less. When the thickness is 200 nm or more, the device may be protected from external moisture or foreign matter, thereby improving the electrical and optical reliability of the device. When the thickness is less than 500 nm, the stress applied to the semiconductor device 10 may be reduced. As a result of lowering optical and electrical reliability of the c) or a longer process time of the semiconductor device 10, the cost of the semiconductor device 10 may be improved.

7 is a plan view illustrating a semiconductor structure, a first conductive layer, and a second conductive layer according to an embodiment, and FIG. 8 is a plan view illustrating a semiconductor structure, a metal layer, a second reflective layer, and a second conductive layer according to an embodiment. .

Referring to FIG. 7, as described above, the first conductive layer 165 may be partitioned into a first region S1 and a second region S2, depending on whether the first conductive layer 165 overlaps the semiconductor structure 120 in a vertical direction.

The area of the first region S1 and the area of the second region S2 may be 1: 0.27 to 1: 0.62. Such a configuration can improve current injection and light output efficiency in the semiconductor device.

When the area of the first region S1 and the area of the second region S2 are smaller than 1: 0.27, there may be a problem that the size of the electrode pad is reduced and current injection is lowered. When the area of the first region S1 and the area of the second region S2 are larger than 1: 0.62, there may be a limit in that the size of the semiconductor structure is reduced, the emission area is reduced, and light extraction is reduced.

In addition, the second conductive layer 146 may be disposed to overlap the first region S1 and the second region S2. In this configuration, the electrode pad 166 may be electrically connected in the second region S2, and may be electrically connected to the second conductive semiconductor layer 123 of the semiconductor structure 120 in the first region S1. have.

In addition, the second conductive layer 146 may include a plurality of holes h so as not to overlap the recess 128. Accordingly, the second conductive layer 146 may be electrically separated from the first electrode 141 disposed in the recess 128.

Referring to FIG. 7, the metal layer 150 may overlap the second region S2 in the vertical direction (Y direction) and may not overlap the first region S1. In addition, the metal layer 150 may be disposed on one side of the semiconductor device 10, and the semiconductor structure 120 may be disposed on the other side of the semiconductor device 10 and may not overlap each other in the vertical direction (Y direction).

In addition, the area S3 of the metal layer 150 may have an area ratio of 1: 1.02 to 1: 2.28.

If the area S3 of the metal layer 150 is smaller than the area and area ratio of the second area S2 of 1: 1.02, there may be a problem that the metal layer is exposed to the outside. In addition, when the area and the area ratio of the first region S1 are greater than 1: 2.28, the area of the metal layer 150 may have a limit in that the pad size is also reduced and current injection is reduced.

In addition, the hole h of the second conductive layer 146 described above may be disposed to surround the first reflective layer 147. That is, the hole h of the second conductive layer 146 may overlap the first reflective layer 147 in the vertical direction (Y direction). Accordingly, since the first reflective layer 147 reflects light passing through the hole h of the second conductive layer 146, the light extraction efficiency may be improved.

9 is a plan view illustrating a semiconductor structure, an electrode pad, a metal layer, and a second reflective layer according to the embodiment.

Referring to FIG. 9, the electrode pad 166 may overlap the metal layer 150 in a vertical direction (Y direction). As described above, according to this configuration, the metal layer 150 compensates for the height difference at the interface of the bonding layer 160 in response to the inclination of the stepped portion 129, so that the electrode pad 166 of the bonding layer 160 is formed. Peel-off from the interface IS can be prevented.

Specifically, the area ratio of the area S4 of the electrode pad 166 to the area S3 of the metal layer 150 may be 1: 1.01 to 1: 2.23.

When the area ratio of the area S4 of the electrode pad 166 and the area S3 of the metal layer 150 is smaller than 1: 1.01, reliability deterioration occurs due to a gap in the bonding layer 160 under the electrode pad 166. There may be a limit. When the area ratio of the area S4 of the electrode pad 166 to the area S3 of the metal layer 150 is larger than 1: 2.23, a problem may occur in that light extraction efficiency is lowered.

In addition, the electrode pad 166 may include a plurality of corners. For example, the electrode pad 166 may include first corner E1 to fourth corner E4. The first corner E1 and the third corner E3 may be disposed to face each other, and the second corner E2 and the fourth corner E4 may be disposed to face each other.

In addition, the second corner E2 is disposed at the outermost side in the first 1-2 directions (X2 directions) of the electrode pad 166, and the fourth corner E4 is disposed in the first-1 direction (1-1) in the electrode pad 166. In the X1 direction). The third edge E3 and the first edge E1 are disposed at the outermost side in the 3-1 direction (Z1 direction) of the electrode pad 166, and the third edge E3 is formed at the electrode pad 166. It may be disposed at the outermost side in the 3-2 direction (Z2 direction).

In the metal layer 150, the second edge E2 except for the first edge E1, the third edge E3, and the fourth edge E4 is disposed in the electrode pad 166 in the first and second directions (X2 direction). It may be extended form. That is, the metal layer 150 may extend from the stepped portion 129 toward the first stepped portion 129a disposed adjacent to the electrode pad 166. The stepped part 129 may have various shapes according to the shape of the semiconductor structure 120. Here, the stepped part 129 may be the first stepped part 129a to the fourth stepped part 129d according to the position. The surface closest to the electrode pad 166 may be referred to as a first stepped portion 129a, and the remainder may be referred to as second to fourth stepped portions 129b, 129c, and 129d.

As a result, the metal layer 150 may extend to be adjacent to the first stepped portion 129a to compensate for the height difference of the inclined surface due to the stepped portion disposed between the semiconductor structure 120 and the electrode pad 166. As a result, the metal layer 150 may reduce the size and number of pores of the bonding layer 160 disposed under the electrode pad 166.

The maximum width L1 of the first direction (X-axis direction) of the electrode pad 166 may be 1: 1.17 to 1: 2.64 with the maximum width L2 of the first direction (X-axis direction) of the metal layer 150.

When the ratio between the maximum width L1 of the first direction (X-axis direction) of the electrode pad 166 and the maximum width L2 of the first direction (X-axis direction) of the metal layer 150 is smaller than 1: 1.17, the bonding is performed. There may exist a problem that the reliability of the semiconductor device is degraded due to the voids generated in the layer. When the ratio of the maximum width L1 of the first direction (X-axis direction) of the electrode pad 166 and the maximum width L2 of the first direction (X-axis direction) of the metal layer 150 is greater than 1: 2.64, There is a limit that the emission area is reduced.

6 is a conceptual diagram of a semiconductor device package according to an embodiment of the present invention, and FIG. 7 is a plan view of a semiconductor device package according to an embodiment of the present invention.

Referring to FIG. 6, a package of a semiconductor device 10 is disposed in a body 2 having grooves (openings 3), a semiconductor device 10 disposed in the body 2, and a body 2. 10 may include a pair of lead frames 5a and 5b electrically connected to each other. The semiconductor device 10 may include all of the above configurations.

The body 2 may include a material or a coating layer that reflects ultraviolet light. The body 2 may be formed by stacking a plurality of layers 2a, 2b, 2c, 2d, and 2e. The plurality of layers 2a, 2b, 2c, 2d, and 2e may be the same material or may include different materials. For example, the plurality of layers 2a, 2b, 2c, 2d, and 2e may include an Al material.

The groove 3 may be wider as it moves away from the semiconductor device 10, and a step 3a may be formed on the inclined surface.

The light transmitting layer 4 may cover the groove 3. The light transmitting layer 4 may be made of glass, but is not limited thereto. The light transmitting layer 4 is not particularly limited as long as it is a material that can effectively transmit ultraviolet light. The inside of the groove 3 may be an empty space.

Referring to FIG. 7, the semiconductor device 10 may be disposed on the first lead frame 5a and connected to the second lead frame 5b by the wire 15. In this case, the second lead frame 5b may be disposed to surround side surfaces of the first lead frame.

8A to 8K are flowcharts illustrating a method of manufacturing a semiconductor device according to an embodiment.

In another embodiment, a method of manufacturing a semiconductor device 10 includes disposing a separation layer 20 and growing a semiconductor structure 120; Disposing the recess 128 and the stepped portion 129, disposing the first insulating layer 131, the first electrode 141, and the second electrode 143, and the second reflective layer 145 and the second reflective layer 145. Disposing the second conductive layer 146, disposing the second insulating layer 132, disposing the metal layer 150, disposing the bonding layer 160, and disposing the first conductive layer 165. The method may include disposing the separation layer 20, forming the unevenness R, and disposing the passivation layer 180 and the electrode pad 166.

First, referring to FIG. 8A, the separation layer 20 may be disposed and the semiconductor structure 120 may be grown. The separation layer 20 may be disposed on the temporary substrate T, and the semiconductor structure 120 may be grown on the separation layer 20. For example, the first conductive semiconductor layer 121 may be disposed on the temporary substrate T. FIG. ), The active layer 122 and the second conductive semiconductor layer 123 may be grown.

The temporary substrate T may be a growth substrate 170. For example, the temporary substrate T may be formed of at least one of sapphire (Al 2 O 3), SiC, GaAs, GaN, ZnO, Si, GaP, InP, or Ge, but is not limited thereto.

The separation layer 20 may be an AlN layer. The separation layer 20 may be a layer that is separated by absorbing a laser in the LLO process. In general, the energy bandgap of the AlN layer is relatively lower than that of the AlGaN layer. Therefore, most lasers may be absorbed by the separation layer 20 during the LLO process. Therefore, light extraction efficiency can be improved.

Meanwhile, the separation layer 20 may be separated by laser light on the surface of the first conductivity-type semiconductor layer 121, which is an AlGaN layer.

The thickness of the separation layer 20 may be 1 nm to 20 nm. When the thickness of the separation layer 20 satisfies 1 nm to 20 nm, the laser layer may be sufficiently absorbed by the laser, and may not deteriorate the function of the buffer layer to mitigate lattice mismatch.

Since the separation layer 20 has a high laser absorption rate, the separation layer 20 may have a relatively thin thickness.

In addition, the separation layer 20 may have an Al content to the extent that the laser can be absorbed.

In this case, the separation layer 20 may have an Al content of at least 45% at an optimal laser absorption rate.

In addition, the semiconductor structure 120 may include, for example, Metal Organic Chemical Vapor Deposition (MOCVD), Chemical Vapor Deposition (CVD), Plasma-Enhanced Chemical Vapor Deposition (PECVD), Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), and the like may be formed using, but are not limited thereto.

The descriptions of the first conductive semiconductor layer 121, the active layer 122, and the second conductive semiconductor layer 123 may be the same.

Referring to FIG. 8B, the recess 128 and the stepped portion 129 may be formed. The recess 128 may be formed through the second conductive semiconductor layer 123 and the active layer 122 to expose a portion of the first conductive semiconductor layer 121. Similarly to the recess 128, the stepped portion 129 penetrates through the second conductive semiconductor layer 123 and the active layer 122 so as to expose a portion of the first conductive semiconductor layer 121. 120 may be continuously spaced apart from each other.

In addition, the stepped portion 129 may be formed at the same time by the recess 128 and etching. In this way, the process can be minimized. In addition, as described above, the recess 128 and the stepped portion 129 may have the same inclination angle and the same thickness in the vertical direction.

Referring to FIG. 8C, the first insulating layer 131 may be formed on the upper surface of the semiconductor structure 120. The first insulating layer 131 may be separated from the first insulating layer 131 at the position where the first electrode 141 and the second electrode 143 are formed. In detail, the first insulating layer 131 may be etched to expose the first conductive semiconductor layer 121 on the recess 128. Similarly, the first insulating layer 131 may be etched to expose the second conductive semiconductor layer 123.

Referring to FIG. 8D, the first electrode 141 and the second electrode 143 may be disposed. The second electrode 143 may be disposed on the second conductive semiconductor layer 123 exposed by the first insulating layer 131, and a part of the second electrode 143 may be disposed on the first insulating layer 131. The first electrode 141 may be in contact with the exposed first conductive semiconductor layer 121 disposed in the recess 128. However, the present invention is not limited thereto and the forming order may be variously applied. In addition, the second electrode 143 may be formed, and the second reflective layer 145 may be formed on the second electrode 143. The second electrode 143 and the second reflective layer 145 have a larger area than the second conductive semiconductor layer 123 exposed by etching the first insulating layer 131, thereby improving current spreading and light reflection. have.

Referring to FIG. 8E, the second conductive layer 146 may be disposed on the top surface of the first insulating layer 131. Accordingly, the first insulating layer 131 may electrically insulate the second conductive layer 146 from the first conductive semiconductor layer 121. In addition, the second conductive layer 146 may be electrically connected to the second electrode 143 to form an electrical channel. In addition, the second conductive layer 146 may be etched so as not to be exposed to the outer surface of the semiconductor device 10.

Referring to FIG. 8F, a second insulating layer 132 may be disposed on the semiconductor structure 120. The second insulating layer 132 is formed on the second conductive layer 146, the first insulating layer 131, the second reflective layer 145, the second electrode 143, and the first electrode 141. The second conductive layer 146, the first insulating layer 131, the second reflective layer 145, the second electrode 143, and the first electrode 141 may be disposed to surround the same. In addition, the second insulating layer 132 is disposed on the first insulating layer 131 so that even if a crack occurs in the first insulating layer 131, the second insulating layer 132 secondary the semiconductor structure 120. I can protect it. The second insulating layer 132 may be disposed to expose a portion of the upper surface of the first electrode 141. For example, the second insulating layer 132 may be formed through a portion of the upper surface of the first electrode 141. The second insulating layer 132 may electrically insulate the second electrode 143 from the first conductive layer 165.

Referring to FIG. 8G, a metal layer 150 may be formed on the second insulating layer 132. As described above, the metal layer 150 may compensate for the height difference between the slopes of the plurality of layers formed by the stepped portion 129.

In addition, the first reflective layer 147 may be formed on the first electrode 141 to be electrically connected to the first electrode 141. A portion of the first reflective layer 147 may be formed on the second insulating layer 132. The first reflective layer 147 may be formed by the same process when the metal layer 150 is formed. In this way, the manufacturing process can be simplified. However, it is not limited to this method.

Referring to FIG. 8H, the first conductive layer 165 may be disposed on the exposed top surface of the first electrode 141. As a result, the first conductive layer 165 may be electrically connected to the first reflective layer 147 so that the first conductive layer 165, the first electrode 141, and the first reflective layer 147 may form an electrical channel. have. In addition, a first bonding layer 160a may be formed on the first conductive layer 165.

Referring to FIG. 8I, a first bonding layer 160a may be disposed on the first conductive layer 165, and a second bonding layer 160b may be disposed under the substrate 170. In addition, the first bonding layer 160a and the second bonding layer 160b may be bonded to each other to be bonded under a predetermined temperature and pressure. In this case, the upper surface of the first bonding layer 160a and the lower surface of the second bonding layer 160b may contact each other, and the lower surface of the second bonding layer 160b may be flat. Alternatively, the first bonding layer 160a may have an upper surface having the same shape as the upper surface of the first conductive layer 165, and the upper surface of the first bonding layer 160a may have a height difference.

In addition, the metal layer 150 described above may prevent the inclined surface corresponding to the stepped portion 129 from being formed on the upper surface of the first bonding layer 160a. Therefore, when the first bonding layer 160a is combined with the second bonding layer 160b, it is possible to prevent the formation of voids between the lower surface of the second bonding layer 160b and the upper surface of the first bonding layer 160a. have. That is, as described above, the metal layer 150 may prevent the gap from being formed at the interface IS between the first bonding layer 160a and the second bonding layer 160b.

The bonding layer 160 may include a conductive material. For example, the bonding layer 160 may include a material selected from the group consisting of gold, tin, indium, Al, silicon, silver, nickel, and copper, or an alloy thereof.

In addition, the substrate 170 may be disposed on the second bonding layer 160b. Thus, as described in FIG. 1, the substrate 170 may be made of a conductive material. In exemplary embodiments, the substrate 170 may include a metal or a semiconductor material. The substrate 170 may be a metal having excellent electrical conductivity and / or thermal conductivity. In this case, heat generated during the operation of the semiconductor device 10 may be quickly released to the outside. In addition, when the substrate 170 is made of a conductive material, the first electrode 141 may receive a current from the outside through the substrate 170.

The substrate 170 may include a material selected from the group consisting of silicon, molybdenum, silicon, tungsten, copper, and Al or an alloy thereof.

8K, the temporary substrate T may be separated from the semiconductor structure 120. As described above, the semiconductor structure 120 and the temporary substrate T may be separated by separating the separation layer 20 by irradiating the separation layer 20 with a laser. However, it is not limited to this method.

The laser may be absorbed and separated from the separation layer 20 at the interface between the semiconductor structure 120 and the separation layer 20. That is, the separation layer 20 on the upper surface of the semiconductor structure 120 may be completely separated, and the residual separation layer 21 may exist on the temporary substrate T side.

Referring to FIG. 8L, a plurality of patterns R may be formed by etching the first conductive semiconductor layer 121 in a portion of the semiconductor structure 120. The first insulating layer 131 may be etched to expose the second conductive layer 146 in the etched region. In addition, the electrode pad 166 may be formed in the hole formed through etching.

The description of the pattern R may be equally applied.

In addition, the passivation layer 180 may be disposed on the top and side surfaces of the semiconductor structure 120. As mentioned above, the passivation layer 180 may have a thickness of 200 nm or more and 500 nm or less. When the thickness is 200 nm or more, the device may be protected from external moisture or foreign matter, thereby improving the electrical and optical reliability of the device. When the thickness is less than 500 nm, the stress applied to the semiconductor device 10 may be reduced. As the optical and electrical reliability is lowered or the processing time of the semiconductor device 10 is longer, the problem that the cost of the semiconductor device 10 is increased may be improved. However, it is not limited to this structure.

In addition, before the passivation layer 180 is disposed, irregularities may be formed on the upper surface of the semiconductor structure 120. Such unevenness may improve extraction efficiency of light emitted from the semiconductor structure 120. The unevenness may be adjusted differently according to the wavelength of the light generated by the semiconductor structure 120.

As described above with reference to FIG. 7, the semiconductor structure may be disposed on a lead frame of the semiconductor device package or on a circuit pattern of a circuit board. The semiconductor device can be applied to various kinds of light source devices. For example, the light source device may be a concept including a sterilizing device, a curing device, a lighting device, and a display device and a vehicle lamp. That is, the semiconductor device may be applied to various electronic devices disposed in a case to provide light.

The sterilization apparatus may include a semiconductor device according to the embodiment to sterilize a desired region. The sterilizer may be applied to household appliances such as water purifiers, air conditioners and refrigerators, but is not necessarily limited thereto. That is, the sterilization apparatus can be applied to all the various products (eg, medical devices) requiring sterilization.

Illustratively, the water purifier may be provided with a sterilizing device according to the embodiment to sterilize the circulating water. The sterilization apparatus may be disposed at a nozzle or a discharge port through which water circulates to irradiate ultraviolet rays. At this time, the sterilization apparatus may include a waterproof structure.

The curing apparatus includes a semiconductor device according to an embodiment to cure various kinds of liquids. Liquids can be the broadest concept that includes all of the various materials that cure when irradiated with ultraviolet light. By way of example, the curing apparatus may cure various kinds of resins. Alternatively, the curing device may be applied to cure a cosmetic product such as a nail polish.

The lighting apparatus may include a light source module including a substrate and the semiconductor device of the embodiment, a heat dissipation unit for dissipating heat of the light source module, and a power supply unit for processing or converting an electrical signal provided from the outside and providing the light source module to the light source module. In addition, the lighting apparatus may include a lamp, a head lamp, or a street lamp.

The display device may include a bottom cover, a reflector, a light emitting module, a light guide plate, an optical sheet, a display panel, an image signal output circuit, and a color filter. The bottom cover, the reflector, the light emitting module, the light guide plate, and the optical sheet may constitute a backlight unit.

The reflecting plate is disposed on the bottom cover, and the light emitting module may emit light. The light guide plate may be disposed in front of the reflective plate to guide light emitted from the light emitting module to the front, and the optical sheet may include a prism sheet or the like to be disposed in front of the light guide plate. The display panel is disposed in front of the optical sheet, the image signal output circuit supplies an image signal to the display panel, and the color filter may be disposed in front of the display panel.

The semiconductor device may be used as an edge type backlight unit or a direct type backlight unit when used as a backlight unit of a display device.

The semiconductor element may be a laser diode in addition to the light emitting diode described above.

Like the light emitting device, the laser diode may include the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer having the above-described structure. In addition, although the p-type first conductive semiconductor and the n-type second conductive semiconductor are bonded to each other, an electro-luminescence phenomenon in which light is emitted when a current is flowed is used. There is a difference in and phase. That is, a laser diode may emit light having a specific wavelength (monochromatic beam) in the same direction with the same phase by using a phenomenon called stimulated emission and a constructive interference phenomenon. Due to this, it can be used for optical communication, medical equipment and semiconductor processing equipment.

For example, a photodetector may be a photodetector, which is a type of transducer that detects light and converts its intensity into an electrical signal. Such photodetectors include photovoltaic cells (silicon, selenium), photoelectric devices (cadmium sulfide, cadmium selenide), photodiodes (eg PDs with peak wavelengths in visible blind or true blind spectral regions) Transistors, optoelectronic multipliers, phototubes (vacuum, gas encapsulation), infrared (Infra-Red) detectors, and the like, but embodiments are not limited thereto.

In addition, a semiconductor device such as a photodetector may generally be manufactured using a direct bandgap semiconductor having excellent light conversion efficiency. Alternatively, the photodetector has various structures, and the most common structures include a pin photodetector using a pn junction, a Schottky photodetector using a Schottky junction, a metal semiconductor metal (MSM) photodetector, and the like. have.

Like a light emitting device, a photodiode may include a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer having the above-described structure, and have a pn junction or pin structure. The photodiode operates by applying a reverse bias or zero bias. When light is incident on the photodiode, electrons and holes are generated and current flows. In this case, the magnitude of the current may be approximately proportional to the intensity of light incident on the photodiode.

Photovoltaic cells or solar cells are a type of photodiodes that can convert light into electrical current. The solar cell may include the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer having the above-described structure, similarly to the light emitting device.

In addition, through the rectification characteristics of a general diode using a p-n junction it may be used as a rectifier of an electronic circuit, it may be applied to an ultra-high frequency circuit and an oscillation circuit.

In addition, the semiconductor device described above is not necessarily implemented as a semiconductor and may further include a metal material in some cases. For example, a semiconductor device such as a light receiving device may be implemented using at least one of Ag, Al, Au, In, Ga, N, Zn, Se, P, or As, and may be implemented by a p-type or n-type dopant. It may also be implemented using a doped semiconductor material or an intrinsic semiconductor material.

Although the above description has been made based on the embodiments, these are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains may not have been exemplified above without departing from the essential characteristics of the present embodiments. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

Claims (11)

Board; And
A semiconductor structure disposed on the substrate, the semiconductor structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; Including,
The semiconductor structure includes a plurality of irregularities disposed on the upper surface,
The active layer generates ultraviolet light,
Al composition of the plurality of irregularities is larger than Al composition of the active layer,
The width of the unevenness is 1.5 to 2.5 times the wavelength of the ultraviolet light,
The semiconductor structure has a thickness of 3 to 9 times the surface roughness (RMS: root mean square) of the plurality of irregularities.
The method of claim 1,
The semiconductor structure has a thickness of 2.5 to 7 times the width of the unevenness.
The method of claim 1,
The second conductivity type semiconductor layer is closer to the substrate than the first conductivity type semiconductor layer,
The substrate is a semiconductor device electrically connected to the first conductive semiconductor layer.
The method of claim 3, wherein
A first conductive layer disposed between the semiconductor structure and the substrate and electrically connecting the first conductive semiconductor layer and the substrate; A semiconductor device further comprising.
The method of claim 4, wherein
A second conductive layer electrically connected to the second conductive semiconductor layer;
An electrode pad disposed on the second conductive layer; And
A bonding layer disposed between the first conductive layer and the substrate; A semiconductor device further comprising.
The method of claim 5,
A first insulating layer disposed between the semiconductor structure and the second conductive layer; And
And a second insulating layer disposed between the second conductive layer and the first conductive layer.
The method of claim 6,
The semiconductor device has a thickness of 0.02 to 0.05 times the thickness of the substrate.
The method of claim 6,
The substrate has a thickness of 100 to 300 times the surface roughness of the unevenness.
The method of claim 6,
The thickness of the substrate is a semiconductor device 80 to 240 times the width of the irregularities.
The method of claim 1,
Surface roughness of the plurality of irregularities is a semiconductor device of 0.4μm to 0.8μm.
The method of claim 1,
The uneven Al composition is 1.1 to 1.8 times the Al composition of the active layer.

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