KR20190114510A - Method for Processing Branch Command in PLC - Google Patents

Abstract

The present invention relates to a processing method of extending a moving offset value of branch commands having limited moving support of an MPU used in a PLC without changes of hardware specifications. The method for processing a branch command of a PLC comprises: (A) a step of generating PLC operation commands by compilation when a PLC program in which branch commands are used is written, calculating an offset value of branch commands to store the offset value in a first register of an MPU, and generating a jump command processing function for performing a jump command; (B) a step of using a PLC to sequentially perform PLC operation commands written in an area of an operating system when progressed in a run mode; (C) a step of storing a current PLC program position where the jump command processing function occurs while performing the PLC operation commands in a second register of the MPU; (D) a step of calling the jump command processing function to branch to an address where a command address table is stored; and (E) a step of calculating the current program position stored in the second register and a moving offset stored in the first register to jump to a calculated value as an address value based on the called jump command processing function.

Description

Method for Processing Branch Command in PLC

The present invention relates to a branch instruction processing method of a programmable logic controller (PLC), and more particularly, to a processing method of extending movement offset values of branch instructions having limited movement support of an MPU used in a PLC. .

PLC is widely used as an industrial control system. After reading the input data from the input module, the program is executed once from the beginning to the end, and the result of writing the result to the output module is called one scan. Is a PLC scan program.

There are many functions or function blocks in the PLC, and these are PLC instructions for performing various operations or functions. The process of executing and processing commands in the compilation area in the PLC is called a run.

That is, the user compiles a PLC program written using PADT (Programming and Debugging Tool), which is a ladder program such as Mitsubishi's GX Works2 and LSIS's XG5000, into a format for PLC operation. The PLC drives the compiled PLC operation instructions using PLC instructions provided by the MPU (Micro Processor Unit).

As such, the PLC performs operations such as movement, operation, and processing by the combination of instructions of the MPU according to the PLC program written by the user. At this time, there are various differences such as the instructions supported by the MPU performance, the manufacturer, and the operable range.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view for explaining a process of driving a PLC program created by a user using a PADT in a conventional PLC.

Referring to FIG. 1, when a user writes a PLC program with the instruction combination 1 of the MPU using the PADT 10, the PADT 10 processes a process according to each operation based on a PLC program written by the user in the compiler. (2) to generate PLC operation instructions (12). At this time, if the instruction to be compiled is a branch instruction, the PADT 10 calculates an offset value as much as moving from the current program position.

The PADT 10 performs a process of writing (3) the compiled PLC operation instructions to the operating system area of the PLC.

When the PLC 20 proceeds to the run mode, the PLC 20 operates and processes PLC operation instructions written in the operating system area using PLC instructions provided by the MPU. At this time, branch instructions such as BEQ, BCC, etc. among PLC operation instructions are driven by moving (branching) (4) inside the operating system (O / S) area based on the offset value calculated by the PADT compiler according to the execution condition. Will be.

Branch instructions of the MPU, on the other hand, support only 16 bits (-32766 to +32768). In this case, although it may support up to 32 bits depending on the performance, manufacturer, etc. of the MPU, in the present specification, only the case of supporting up to 16 bits will be described for easy description.

The branch instructions of the MPU support only up to 16 bits, meaning that when the branch instructions move inside the PLC operating system area to operate, it is impossible to move to a position over 16 bits. Therefore, if the calculated offset value exceeds 16 bits, the operation of the branch instruction is impossible.

Therefore, if a branch instruction needs to be processed with a value of 16 bits or more in a PLC program written by a user, it is impossible to move to a desired address value. In fact, values greater than 16 bits are treated as negative values, causing the PLC to fall into an abnormal state.

FIG. 2 is a diagram illustrating an operation performed correctly when a branch instruction needs to be processed with a 16-bit or higher value in a conventionally created PLC program. FIG. 3 illustrates a branch instruction having a 16-bit or higher value in a conventionally created PLC program. This is a diagram showing an operation actually performed when processing is required.

It is assumed that the total program size of the PLC operating system area is 0x8000 or more, and the user wants to execute all programs when any variable reaches the desired value at the start of the program.

If the user has written a PLC program using the PADT 10 to move from the position of the PLC operating system area “A00010” to the “A09000” over 16 bits by the branch instruction “BEQ”, the PLC 20 reads the branch instruction “ BEQ ”to move to the PLC operating system area“ A09000 ”(5) as shown in FIG. 2 to process PLC operation commands.

In practice, however, since the PLC 20 only supports up to 16 bits of branch instructions in the MPU, a value greater than “A08000” is treated as a negative number.

That is, as shown in FIG. 2, the PLC 20 does not move to the PLC operating system area “A09000”, and as shown in FIG. 3, “A09000” is treated as a negative number to move to the wrong address value (6). As a result, serious malfunction of the PLC 20 occurs.

In order to solve such a problem, an object of the present invention is to provide a processing method of extending a shift offset value of branch instructions having limited movement support of an MPU used in a PLC without changing a hardware specification itself. do.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention, which are not mentioned above, can be understood by the following description, and more clearly by the embodiments of the present invention. Also, it will be readily appreciated that the objects and advantages of the present invention may be realized by the means and combinations thereof indicated in the claims.

In order to achieve the above object, the branch instruction processing method of the PLC of the present invention, (A) when a PLC program using a branch instruction is created, generates PLC operation instructions through compilation, offset of the branch instruction (offset) Computing a value and storing it in a first register of the MPU, and generating a jump instruction processing function for performing a jump instruction, (B) PLC operation written in the operating system area when the run mode is executed using the PLC Executing the instructions sequentially; (C) storing the current PLC program position from which the jump instruction processing function is generated in the second register of the MPU; and (D) calling the jump instruction processing function and storing the instruction in the instruction address table. Branching to a second address, and (E) a current program position stored in the second register based on the called jump instruction processing function. The comprises the step of jumping to a value calculated by calculating the offset of the move as stored in the first register with the address value.

In addition, the step (B) is characterized in that to copy the jump instruction processing function to the end of the PLC operation instructions to be written to the operating system area.

The jump instruction processing function may store an address value branched to an instruction address table.

In addition, the step (C) is characterized in that to store the PLC program location in the second register of the MPU by performing a POP (POP) operation.

In addition, the step (D) includes the steps of calling a jump instruction processing function, checking an address of an instruction stored in a binary file in an instruction address table of the called jump instruction processing function, and branching to the identified address. Steps.

In addition, the address of the jump instruction processing function branched in the step (D) is included in the range supported by the branch instruction in the MPU.

The step (E) may further include adding a stored value of the first register and a value stored in the second register, storing the calculated shift position value in the second register, and storing the second register. And storing the position value to be stored in the stack in the stack, and moving to the address value stored in the stack.

According to the present invention as described above, the branch instruction processing method of the PLC of the present invention, when using a branch instruction that requires 16-bit or more processing in the MPU to be implemented to extend the movement offset values of the branch (branch) instructions without changing the MPU. It can be effective.

In addition, since it can be implemented by indirect compilation in the compile process, it is possible to extend the shift offset value of branch instructions of the unsupported MPU by modifying the compiler alone without modifying the operating system area of the PLC, which is efficient for maintenance.

In addition to the effects described above, the specific effects of the present invention will be described together with the following description of specifics for carrying out the invention.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view for explaining a process of driving a PLC program written by a user using a PADT in a conventional PLC.
FIG. 2 is a view showing an operation performed correctly when a branch instruction needs to be processed with a value of 16 bits or more in a conventional PLC program written by a user.
FIG. 3 is a view showing an operation actually performed when a branch instruction needs to be processed with a value of 16 bits or more in a conventionally created PLC program.
4 is a flowchart illustrating a branch instruction processing method of a PLC according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating writing PLC operation instructions compiled in FIG. 4 to an operating system area of a PLC. FIG.
FIG. 6 is a diagram illustrating internal command processing jumped to an offset value by a jump command processing function in FIG. 4; FIG.

The above objects, features, and advantages will be described in detail with reference to the accompanying drawings, whereby those skilled in the art to which the present invention pertains may easily implement the technical idea of the present invention. In describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to indicate the same or similar components.

Hereinafter, a branch instruction processing method of a PLC according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a flowchart illustrating a branch instruction processing method of a PLC according to an embodiment of the present invention.

Referring to FIG. 4, first, a user writes a PLC program using branch instructions as a combination of instructions of an MPU using a PADT (S10). In this case, a branch means a branch, which means that several branches from the repository are made available to each use. In other words, when using one remote repository, the version of several source codes may be different. The function to prevent this is branch. Branch instructions are commands that enable you to use these branches and perform jump-like instructions. The branch instructions that are written include inserts, operations, and conditional statements.

The PADT 100 generates PLC operation instructions by compiling processing according to each operation based on a PLC program written by a user in the compiler (S20). In this case, when the compiled instruction is a branch instruction, an offset value as much as being moved from the current program position is calculated, and the calculated offset value of the PADT 100 is the first register ER0 of the MPU. ). The PADT 100 generates a jump instruction processing function that performs a jump instruction.

The generated jump instruction processing function stores an address value branched to the instruction address table. Therefore, the PLC 200 sequentially executes PLC operation instructions written in the operating system area, and when a jump instruction processing function is issued, branches to the code block in which the actual instruction code is located. In this case, the instruction stored in the binary file in the instruction address table is used. Branch to the address of.

Subsequently, the PADT 10 writes the compiled PLC operation instructions to the operating system area of the PLC, and copies the generated jump instruction processing function to the end of the PLC operation instruction (S30).

FIG. 5 is a diagram illustrating writing PLC operation instructions compiled in FIG. 4 to an operating system area of a PLC.

As shown in FIG. 5, the compiled PLC operating instructions are written to the operating system area of the PLC (210), and the generated jump instruction processing function is copied to the end of the PLC operating instruction (220). In this case, the calculated offset value (#xx) among the compiled PLC operating instructions written in the operating system area is stored in the first register ER0 of the MPU, and the jump instruction processing function JUMP BRA_JMP is jumped. It is a command (201).

When the PLC 20 proceeds to the run mode, the PLC 20 sequentially executes PLC operation instructions written in the operating system area, and drives and processes the PLC instructions provided by the MPU (S90).

Then, the PLC 200 sequentially executes PLC operation instructions, and when a jump instruction processing function comes out (S40), performs a pop operation on the current PLC program position from which the jump instruction processing function came out and performs a second register (ER1) of the MPU. In step S50).

Subsequently, the PLC 200 calls the jump instruction processing function BRA_JUM and checks the address of the instruction stored in the binary file in the instruction address table. And branched to the confirmed address (S60). In this case, the address of the branched jump instruction processing function BRA_JUM is included in 16 bits in which branch instructions are supported in the MPU. That is, as shown in FIG. 5, when the program location stored before the jump instruction processing function call is “A00000”, the maximum branchable address is “A32000”.

The called jump instruction processing function calculates an offset as much as the current program position and moves to jump to the value. That is, the stored value of the first register ER0 and the value stored in the second register ER1 are added to each other and stored in the second register ER1 (S70). In this case, the first register ER0 stores the offset value calculated during the compilation process, and the second register ER1 stores the position of the PLC program before the jump instruction processing function is called.

As such, as the offset value and the position of the PLC program are added, the result value has a moving offset value as much as the branch instruction is moved. As the offset value according to the result value is branched by the jump instruction, the offset value is not limited by the moving range (16 bits) according to the performance of the MPU.

This is because, due to the limitation of the movement range in the MPU, the absolute address cannot be processed beyond the constraint range. By using the jump function, the absolute address is changed to a relative address, so that the offset value has a position beyond the movement range supported by the MPU. Movement processing becomes possible.

Therefore, the PLC 200 stores the calculated movement position value on the stack and moves to the address value stored on the stack (S80).

FIG. 6 is a diagram illustrating internal command processing jumped to an offset value by a jump command processing function in FIG. 4.

Subsequently, the PLC 20 sequentially executes PLC operation instructions written in the operating system area, drives and processes the PLC instructions provided by the MPU (S90).

In this way, when using branch instructions that require more than 16-bit processing in the MPU, the shift offset values of the branch instructions are changed to relative addresses without changing the MPU, thereby extending them to offset values having positions beyond the movement range supported by the MPU. It can be implemented to work.

In addition, since it can be implemented by indirect compilation in the compile process, it is possible to extend the shift offset value of branch instructions of the unsupported MPU by modifying the compiler alone without modifying the operating system area of the PLC, which is efficient for maintenance.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited by.

100: PADT 200: PLC

Claims (7)

(A) When a PLC program using a branch instruction is created, PLC operation instructions are generated by compiling, the offset value of the branch instruction is calculated, stored in the first register of the MPU, and a jump for performing a jump instruction. Generating an instruction processing function;
(B) sequentially executing PLC operation commands written in the operating system area when the system is in a run mode using the PLC;
(C) storing the current PLC program position from which the jump instruction processing function is output in the second register of the MPU;
(D) calling a jump instruction processing function to branch to an address stored in the instruction address table; And
(E) calculating a current program position stored in the second register and a moving offset offset stored in the first register based on the called jump instruction processing function, and jumping the calculated value to an address value;
How to handle branch instruction of PLC.
According to claim 1,
Step (B) is
The branch instruction processing method of a PLC, characterized in that for copying the jump instruction processing function to the end of the PLC operation instructions written in the operating system area.
According to claim 1,
The jump instruction processing function is a branch instruction processing method of a PLC, characterized in that for storing the address value branched to the instruction address table.
The method of claim 1,
Step (C) is a branch instruction processing method of a PLC, characterized in that to perform a POP operation to store the PLC program location in the second register of the MPU.
According to claim 1,
Step (D) is
Calling a jump instruction processing function,
Checking an address of an instruction stored in a binary file from an instruction address table of the called jump instruction processing function;
A branch instruction processing method of a PLC comprising the step of branching to the confirmed address.
The method of claim 5,
The branch instruction processing method of the PLC, wherein the address of the jump instruction processing function branched in the step (D) is included in a range supported by the branch instruction in the MPU.
According to claim 1,
Step (E) is
Adding the stored value of the first register with the value stored in the second register;
Storing the calculated shift position value in the second register;
Storing a shift position value stored in the second register on a stack;
A branch instruction processing method of a PLC comprising moving to an address value stored in the stack.

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