KR20190106622A - Multilayered capacitor - Google Patents

Abstract

Provided is a multilayered capacitor. An active area of the lower part of a capacitor body bonded to a substrate and a solder allows an overlapped area of an internal electrode to be relatively small and the overlapped area deviation of the active area is little so the piezoelectric deformation of the capacitor body is reduced to improve acoustic noises.

Description

Multilayer Capacitors {MULTILAYERED CAPACITOR}

The present invention relates to a multilayer capacitor.

In recent years, electronic devices have become more silent, and acoustic noise generated by multilayer capacitors (MLCCs) has become prominent.

The dielectric material of the multilayer capacitor is piezoelectric and deforms in synchronization with the applied voltage.

When the period of the applied voltage is in the audible frequency band, the displacement becomes a vibration and is transmitted to the substrate through the solder, and the substrate vibration is heard as sound. This is acoustic noise and has become a problem for electronic devices.

The acoustic noise problem may cause users to perceive acoustic noise as abnormal sounds when the operating environment of the device is quiet, or cause the device to malfunction. do.

In addition, apart from acoustic noise perceived by the human ear, piezoelectric vibration of a multilayer capacitor may cause malfunction in various sensors used in IT and industrial / electric fields when generated in a high frequency region of 20 kHz or more.

Domestic Publication No. 2015-0033302 Domestic Publication No. 2015-0019634

An object of the present invention is to provide an electronic component capable of reducing acoustic noise and high frequency vibration of 20 kHz or more in the audio frequency region below 20 kHz.

One aspect of the present invention includes an active region including a plurality of dielectric layers and a plurality of internal electrodes disposed with the dielectric layers interposed therebetween, the first and second surfaces opposing each other, and the first and second surfaces; A capacitor body including third and fourth surfaces connected to and opposed to each other, wherein one end of the plurality of internal electrodes is alternately exposed through the third and fourth surfaces; First and second external electrodes formed on third and fourth surfaces of the capacitor body and connected to internal electrodes exposed through the third and fourth surfaces of the capacitor body, respectively; Wherein the active region includes a first active region adjacent to a second surface of the capacitor body and a second active region adjacent to a first surface, which is a mounting surface of the capacitor body, and is internal to the second active region. The overlap area of the electrode is smaller than the overlap area of the internal electrode in the first active area, the overlap area deviation of the internal electrode in the first active area is 5% or less, and the overlap area deviation of the internal electrode in the second active area. Provides a multilayer capacitor having less than 5%.

Another aspect of the present invention includes an active region including a plurality of dielectric layers and a plurality of internal electrodes disposed with the dielectric layers interposed therebetween, the first and second surfaces opposing each other, and the first and second surfaces; A capacitor body including third and fourth surfaces connected to and opposed to each other, wherein one end of the plurality of internal electrodes is alternately exposed through the third and fourth surfaces; First and second external electrodes formed on third and fourth surfaces of the capacitor body and connected to internal electrodes exposed through third and fourth surfaces of the capacitor body, respectively; Wherein the active region includes a first active region adjacent to a second surface of the capacitor body and a second active region adjacent to a first surface, which is a mounting surface of the capacitor body, and includes an inside of the second active region. The length of the electrode may be less than the length of the internal electrode of the first active region, the length deviation of the internal electrode in the first active region is 5% or less, and the length deviation of the internal electrode in the second active region may be 5% or less. have.

In an embodiment, the thickness of the first active region may be 50% or more of the thickness of the entire active region.

In an embodiment, the overlap area of the internal electrodes of the second active region may be 25% or more of the overlap area of the internal electrodes of the first active region.

In an embodiment, the overlap area of the internal electrodes of the second active region may be 85% or less of the overlap area of the internal electrodes of the first active region.

In an embodiment, the second active region may further include a dummy electrode disposed to be spaced apart from the inner electrode and the adjacent outer electrode.

According to one embodiment of the present invention, it is possible to reduce acoustic noise and high frequency vibration of 20 kHz or more in the audible frequency region of less than 20 kHz of the multilayer capacitor.

1 is a perspective view schematically illustrating a stacked capacitor according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.
3 (a) to 3 (d) are cross-sectional views illustrating a capacitor body of a conventional multilayer capacitor and a multilayer capacitor according to three embodiments of the present invention.
4 (a) to 4 (d) are plan views illustrating overlap areas of internal electrodes applied to FIGS. 3 (a) to 3 (d), respectively.
5 (a) to 5 (h) show the displacement distribution of the pad and the displacement distribution of the printed circuit board when the multilayer capacitor of FIGS. 3 (a) to 3 (d) is mounted on the substrate. Each picture is shown.
FIG. 6 is a graph illustrating displacement of a substrate that varies with frequency in a conventional multilayer capacitor and a multilayer capacitor according to three embodiments of the present disclosure.
7 is a cross-sectional view illustrating a state in which the multilayer capacitor of FIG. 1 is mounted on a substrate.
8 is a cross-sectional view illustrating that vibration is transmitted when the multilayer capacitor of FIG. 1 is mounted on a substrate.
9 is a schematic cross-sectional view of a multilayer capacitor according to another exemplary embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

However, embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below.

Moreover, embodiment of this invention is provided in order to demonstrate this invention more completely to the person with average knowledge in the technical field.

Shape and size of the elements in the drawings may be exaggerated for more clear description.

In addition, the component with the same function within the range of the same idea shown by the figure of each embodiment is demonstrated using the same reference numeral.

In addition, the inclusion of any component throughout the specification means that it may further include other components, except to exclude other components unless specifically stated otherwise.

Hereinafter, when the direction of the capacitor body 110 is defined in order to clearly describe the embodiment of the present invention, X, Y, and Z shown in the drawings indicate the length direction, the width direction, and the thickness direction of the capacitor body 110, respectively. . In addition, in this embodiment, the Z direction can be used in the same concept as the lamination direction in which the dielectric layers are laminated.

1, 2, 3 (b), 4 (b), 5 (b), and 5 (f), a multilayer capacitor according to an embodiment of the present invention may include a capacitor body 110. And first and second external electrodes 131 and 132 formed at both ends of the capacitor body 110.

The capacitor body 110 is obtained by stacking a plurality of dielectric layers 111 in the Z direction and then firing the plurality of dielectric layers 111 and a plurality of internal electrodes alternately arranged in the Z direction with the plurality of dielectric layers 111 and the dielectric layers 111 interposed therebetween. do.

In this case, the dielectric layer 111 and the internal electrode may be stacked horizontally with respect to the first surface of the capacitor body 110, which will be described later.

In addition, the capacitor body 110 may include an active region including a plurality of internal electrodes stacked in the Z direction, and cover regions 112 and 113 disposed above and below the active region.

The cover regions 112 and 113 may refer to regions where the internal electrodes are not disposed.

At this time, each of the dielectric layers 111 adjacent to each other of the capacitor body 110 may be integrated to such an extent that it is impossible to identify a boundary.

The capacitor body 110 may be generally hexahedral in shape, but the present invention is not limited thereto.

In the present embodiment, for convenience of description, both surfaces of the capacitor body 110 facing each other in the Z direction are connected to the first and second surfaces 1 and 2 and the first and second surfaces 1 and 2. And opposite surfaces facing each other in the X direction to the third and fourth surfaces 3 and 4, connected to the first and second surfaces 1 and 2, and to the third and fourth surfaces 3 and 4, respectively. Both surfaces facing each other in the Y direction will be defined as fifth and sixth surfaces 5 and 6. In the present embodiment, the first surface 1 of the capacitor body 110 may be a mounting surface.

The dielectric layer 111 may include a ceramic material having a high dielectric constant, and may include, for example, BaTiO ₃ -based ceramic powder, but the present invention is not limited thereto.

In addition, a ceramic additive, an organic solvent, a plasticizer, a binder, a dispersant, and the like may be further added to the dielectric layer 111.

As the ceramic additive, for example, transition metal oxide or transition metal carbide, rare earth element, magnesium (Mg) or aluminum (Al) may be used.

The active region may include a first active region A2 positioned above the capacitor body 110 and a second active region A3 positioned below the capacitor body 110 in the Z direction. Can be.

The first active region A2 is adjacent to the second surface 2, which is the opposite surface of the capacitor body 110, and includes a plurality of first and second internal electrodes 121 and 122.

The first and second internal electrodes 121 and 122 are electrodes having different polarities, and are alternately disposed in the Z direction with the dielectric layer 111 interposed therebetween, and one end of each of the third and fourth surfaces of the capacitor body 110. Exposed through 3 and 4, the first and second external electrodes 131 and 132 may be electrically connected to each other.

The second active region A3 is adjacent to the first surface 1, which is a mounting surface of the capacitor body 110, and includes a plurality of third and fourth internal electrodes 123 and 124.

The third and fourth internal electrodes 123 and 124 are electrodes having different polarities, and are alternately disposed in the Z direction with the dielectric layer 111 interposed therebetween, and one end of the third and fourth internal electrodes 123 and 124 disposed on the third and fourth surfaces of the capacitor body 110. Exposed through 3 and 4, the first and second external electrodes 131 and 132 may be electrically connected to each other.

In addition, the overlap areas of the third and fourth internal electrodes 123 and 124 in the second active region A3 may correspond to the overlap areas of the first and second internal electrodes 121 and 122 of the first active region A2. Small compared to

In this case, the overlap area of the internal electrodes in the first active region A2 and the second active region A3 may be substantially the same regardless of the position.

In the present embodiment, the overlap area deviation of the first and second internal electrodes 121 and 122 in the first active region A2 may be 5% or less, and the third and fourth internal regions in the second active region A3. The overlap area deviation of the electrodes 123 and 124 may be 5% or less.

In addition, in order to make the overlap area of the second active area A3 smaller than the overlap area of the first active area A2, the third and fourth internal electrodes 123 and 124 of the second active area A3 are formed. The length may be shorter than the length of the first and second internal electrodes 121 and 122 in the first active region A2.

In this case, the length deviation of the first and second internal electrodes 121 and 122 in the first active region A2 may be 5% or less, and the third and fourth internal electrodes 123 and 123 in the second active region A3. The length deviation of 124) may be 5% or less.

Meanwhile, the first and second internal electrodes 121 and 122 and the third and fourth internal electrodes 123 and 124 are formed of a conductive metal, for example, a material such as nickel (Ni) or nickel (Ni) alloy. Although may be used, the present invention is not limited thereto.

According to the above configuration, when a predetermined voltage is applied to the first and second external electrodes 131 and 132, between the first and second internal electrodes 121 and 122 facing each other, and the third and fourth internal electrodes An electric charge accumulates between 123 and 124.

At this time, the capacitance of the multilayer capacitor 100 overlaps with each other along the Z direction and overlaps the area of the first and second internal electrodes 121 and 122 and the third and fourth internal electrodes 123 and 124. It will be proportional to the area.

Meanwhile, an overlap area of the third and fourth internal electrodes 123 and 124 in the second active region A3 is equal to an overlap area of the first and second internal electrodes 121 and 122 in the first active region A2. May be at least 25%.

If this ratio is less than 25%, there is a problem that the thickness of the second active region becomes too thick, so that the overall thickness of the multilayer capacitor is excessively increased.

More preferably, the overlap area of the third and fourth internal electrodes 123 and 124 in the second active region A3 is equal to that of the first and second internal electrodes 121 and 122 in the first active region A2. It may be up to 85% for the overlap area. If this ratio exceeds 85%, the amount of substrate vibration displacement reduction is less than 10%, which may result in insufficient acoustic noise improvement.

In addition, the thickness in the Z direction of the first active region A2 may be 50% or more of the thickness of the entire active region.

If the ratio is less than 50%, the second active region A3 needs to be increased to secure the same capacitance, thereby causing an increase in the overall thickness of the multilayer capacitor.

The first and second external electrodes 131 and 132 are formed on the third and fourth surfaces 3 and 4 in the X direction of the capacitor body 110, respectively, and are provided with voltages having different polarities. The exposed portions of the second internal electrodes 121 and 122 and the exposed portions of the third and fourth internal electrodes 123 and 124 may be connected and electrically connected, respectively.

Plating layers may be formed on the surfaces of the first and second external electrodes 131 and 132 as necessary.

For example, the first and second external electrodes 131 and 132 may include first and second conductive layers, first and second nickel (Ni) plating layers formed on the first and second conductive layers, and the first and second conductive layers. Each of the first and second tin (Sn) plating layers formed on the first and second plating layers may be included.

In addition, the first external electrode 131 may include a first connection part 131a and a first band part 131b.

The first connection portion 131a is a portion disposed on the third surface 3 of the capacitor body 110 and connected to the first and third external electrodes 121 and 123 and electrically connected thereto, and the first band portion 131b is provided. Is a portion extending from the first connection portion 131a to a part of the first surface 1 of the capacitor body 110.

In this case, the first band part 131b may be further extended to a part of the second surface 2 of the capacitor body 110 and a part of the fifth and sixth surfaces 5 and 6 as necessary for the purpose of improving the fixing strength. Can be.

The second external electrode 132 may include a second connection portion 132a and a second band portion 132b.

The second connecting portion 132a is a portion disposed on the fourth surface 4 of the capacitor body 110 and connected to the second and fourth external electrodes 122 and 124 to be electrically connected to the second band portion 132b. Is a portion extending from the second connection portion 132a to a part of the first surface 1 of the capacitor body 110.

At this time, the second band part 132b may be further extended to a part of the second surface 2 and the part of the fifth and sixth surfaces 5 and 6 of the capacitor body 110 when necessary for the purpose of improving the fixing strength. Can be.

Hereinafter, a difference between the structure of the internal electrode and the displacement distribution according to the comparative example and the first to third embodiments will be described with reference to FIGS. 3A to 5H.

At this time, the audible frequency is set to 2 to 9 kHz. In addition, in the drawings, Comparative Example, Example 1, Example 2, and Example 3 illustrate reducing the number of stacked internal electrodes for convenience.

3 (a), 4 (a), 5 (a), and 5 (e) do not have two active regions A1, and there are 200 first and second internal electrodes 121 in total. And (122), FIGS. 3 (b), 4 (b), 5 (b) and 5 (f) relate to Example 1, and FIGS. 3 (c) and 4 (c), FIG. 5 (c) and FIG. 5 (g) relate to Embodiment 2, and FIGS. 3 (d), 4 (d), 5 (d) and 5 (h) are Embodiment 3 It is about.

In the first embodiment, the capacitor body 110 includes a total of 210 internal electrodes, but the first and second internal electrodes 121 and 122 of the first active region A2 are 140 layers and the second active region A3 is formed. The third and fourth internal electrodes 123 and 124 are 70 layers.

In this case, the overlap area of the third and fourth internal electrodes 123 and 124 in the second active area A3 is equal to the overlap area of the first and second internal electrodes 121 and 122 in the first active area A1. 85%.

In Embodiment 2, the capacitor body 110 includes a total of 260 internal electrodes, but the first and second internal electrodes 121 and 122 of the first active region A4 have 180 layers and the second active region A5 includes The third and fourth internal electrodes 123 'and 124' are 80 layers.

In this case, the overlap areas of the third and fourth internal electrodes 123 ′ and 124 ′ in the second active region A5 overlap the first and second internal electrodes 121 and 122 in the first active region A4. It may be 25% of the area.

In the third embodiment, the capacitor body 110 includes a total of 290 internal electrodes, but the first and second internal electrodes 121 and 122 of the first active region A6 are 190 layers and the second active region A7 is formed. The third and fourth internal electrodes 123 ″ and 124 ″ are 100 layers.

In this case, the overlap areas of the third and fourth internal electrodes 123 ″ and 124 ″ in the second active region A7 overlap the first and second internal electrodes 121 and 122 in the first active region A6. It may be 10% of the area.

As shown in Fig. 7 and 8, the multilayer capacitor 100 of the present embodiment is a horizontal stacked type, when the voltage is applied, the capacitor body 110 expands and deforms in the Z direction and contracts in the X and Y directions. Deform behavior

More specifically, when the multilayer capacitor 100 is mounted on the substrate 210, the first and second electrodes 131 and 132 are bonded to the first and second external electrodes 131 and 132 due to expansion deformation in the Z direction of the capacitor body 110. The pads 221 and 222 may be displaced downward.

In addition, the shrinkage deformation in the X and Y directions of the capacitor body 110 is transferred to the first and second pads 221 and 222 through the solders 231 and 232 to lift the substrate 210 upward. On the ends of the first and second pads 221 and 222.

5 (a) to 5 (h) and FIG. 6, Embodiments 1 to 3 show an upper portion of the first and second pads 221 and 222 and a capacitor body 110 at the bottom of the stacked capacitor. In order to prevent the overlap of the internal electrodes on the third and fourth surfaces 3 and 4 of the C), the overlap area of the third and fourth internal electrodes of the second active region is reduced to mount the capacitor body 110. Piezoelectric deformation of the face and lower side can be reduced.

Thus, acoustic noise may be reduced by reducing vibration transmitted from the capacitor body 110 to the substrate 210 as compared with the comparative example.

On the other hand, since the first active region is located on the upper side of the capacitor body 110, the vibration generated here is difficult to transfer to the substrate 210.

Accordingly, as shown in FIG. 8, by increasing the number of stacked first and second internal electrodes 131 and 132 of the first active region by B1, the third and fourth internal electrodes 123 and 124 in the second active region. The reduced overlap areas B2 and B3 can be compensated for.

7 and 8 illustrate Embodiment 1 of the present invention by way of example, but the present invention is not limited thereto. For example, in Embodiments 2 and 3, only the numerical values may be different. The same effect occurs.

That is, in embodiments of the present invention, an overlap area of the third and fourth internal electrodes 123 and 124 in the second active region overlaps the first and second internal electrodes 121 and 122 of the first active region. Although smaller than the area, the capacitance of the same level as that of the comparative example can be secured by increasing the area of the first and second internal electrodes 121 and 122 in the first active region.

In addition, in Example 1, since the total number of internal electrodes is smaller than that of Example 2, the height of the multilayer capacitor may be relatively lower, but it is understood that Example 1 is more advantageous in terms of displacement distribution.

Table 1 below shows the displacement of the substrate at the corresponding resonance frequencies of the comparative example and the three embodiments in FIG. Here, the ratio (Ratio) represents the ratio of the substrate displacement of Examples 1 to 3 to the substrate displacement of the comparative example at each resonance frequency is reduced.

Resonant frequency Overlap area Substrate Displacement [m] Ratio (%) 4.3 kHz Comparative example 4.59E-11 - Example 1 4.21E-11 8.3 Example 2 1.94E-11 57.7 Example 3 1.74E-11 62.0 4.7 kHz Comparative example 8.94E-11 - Example 1 8.10E-11 9.4 Example 2 4.28E-11 52.1 Example 3 3.85E-11 56.9 7.1 kHz Comparative example 7.38E-11 - Example 1 6.75E-11 8.5 Example 2 3.71E-11 49.7 Example 3 3.34E-11 54.8

Referring to Table 1, when the overlap area of the third and fourth internal electrodes is 85% as in Example 1, the displacement reduction effect is less than 10% compared to the comparative example.

When the overlap area of the third and fourth internal electrodes is 25% as in Example 2, it can be seen that the displacement reduction effect is significantly increased compared to Example 1 to a little more than 50% compared to the comparative example.

And, as in Example 3, even if the overlap area of the third and fourth internal electrodes is greatly reduced to 10%, the displacement reduction effect is 62.0%, which is not significantly improved compared to Example 2.

Table 2 below shows a comparison of the total number of stacked layers of the internal electrodes of Examples 1 to 3 for the comparative example.

Internal electrode
Total laminations Floor
% Increase Comparative example 200 - Example 1 210 5 Example 2 260 30 Example 3 290 45

Referring to Table 2, when the overlap area of the third and fourth internal electrodes is 10% as in Example 3, the increase in the number of layers compared to the case where the overlap area of the third and fourth internal electrodes of Example 2 is 25% As this 15% increase, the overall thickness of the multilayer capacitor increases together.

Accordingly, the overlap area of the third and fourth internal electrodes, which can minimize the increase in the overall thickness of the multilayer capacitor while considering the substrate displacement reduction effect, is preferably 25% or more.

therefore. Referring to Table 1 and Table 2, the overlap area of the third and fourth internal electrodes of the second active region may be 25 to 85% of the overlap area of the first and second internal electrodes of the first active region.

9 is a schematic cross-sectional view of a multilayer capacitor according to another exemplary embodiment of the present invention.

Referring to FIG. 9, the stacked capacitor may include a plurality of first and second dummy electrodes 125 and 126 spaced apart from the third and fourth internal electrodes 123 and 124 in the second active region. .

In this case, the first dummy electrode 125 may be disposed to be spaced apart from the first external electrode 131, and may be disposed such that one end thereof is substantially coincident with the end of the second internal electrode 122 in a line in the Z direction. .

In addition, the second dummy electrode 126 may be disposed to be spaced apart from the second external electrode 132, and may be disposed such that one end thereof is substantially coincident with the end of the first internal electrode 121 in a line in the Z direction. .

Since the density of the first active region and the second active region is different from each other, the multilayer capacitor of the present embodiment may have a defect in which the lower portion of the capacitor body 110 is deformed into a jar shape during the compression firing process during the manufacturing of the multilayer capacitor. have.

According to the present embodiment, the first and second dummy electrodes 125 and 126 correct the density of the second active region to a level similar to that of the first active region, thereby deforming the capacitor body 110 in the compression firing process. It can play a role in restraining what is possible.

According to the structure of the multilayer capacitor of the present embodiment as described above, it is possible to effectively suppress the amount of vibration that the piezoelectric vibration of the multilayer capacitor is transmitted to the substrate at an audible frequency within 20 kHz of the multilayer capacitor.

Therefore, by reducing the high frequency vibration of the multilayer capacitor to prevent malfunction of sensors that may be a problem by the high frequency vibration of the multilayer capacitor of 20kHz or more in the IT or industrial / electronic field, and to prevent the accumulation of internal fatigue due to long-term vibration of the sensor Can be.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and variations can be made without departing from the technical matters of the present invention described in the claims. It will be obvious to those of ordinary skill in the field.

100: Stacked Capacitors
110: capacitor body
111: dielectric layer
112, 113: cover area
121 and 122: first and second internal electrodes
123 and 124: third and fourth internal electrodes
131 and 132: first and second external electrodes
131a and 132a: first and second connections
131b and 132b: first and second band portions
210: substrate
221. 222: First and second pads
231, 232: solder

Claims (9)

An active region including a plurality of dielectric layers and a plurality of internal electrodes disposed with the dielectric layers interposed therebetween; first and second surfaces facing each other and a third surface connected to and opposed to the first and second surfaces; And a capacitor body including a fourth surface, wherein one end of the plurality of internal electrodes is alternately exposed through the third and fourth surfaces; And
First and second external electrodes formed on third and fourth surfaces of the capacitor body and connected to internal electrodes exposed through third and fourth surfaces of the capacitor body, respectively; Including,
The active region includes a first active region adjacent to a second surface of the capacitor body and a second active region adjacent to a first surface, which is a mounting surface of the capacitor body,
The overlap area of the internal electrodes in the second active region is smaller than the overlap area of the internal electrodes in the first active region,
The overlapped area deviation of the internal electrodes in the first active region is 5% or less, and the overlap area deviation of the internal electrodes in the second active region is 5 or less.
The method of claim 1,
The overlapped capacitor of the inner electrode of the second active region is 25% or more of the overlap area of the inner electrode of the first active region.
The method of claim 1,
The overlapped capacitor of the inner electrode of the second active region is 85% or less of the overlap area of the inner electrode of the first active region.
The method of claim 1,
The multilayer capacitor has a thickness of at least 50% of a thickness of the entire active region.
The method of claim 1,
And a dummy electrode disposed in the second active region to be spaced apart from the inner electrode and the adjacent outer electrode.
An active region including a plurality of dielectric layers and a plurality of internal electrodes disposed with the dielectric layers interposed therebetween; first and second surfaces facing each other and a third surface connected to and opposed to the first and second surfaces; And a capacitor body including a fourth surface, wherein one end of the plurality of internal electrodes is alternately exposed through the third and fourth surfaces;
First and second external electrodes formed on third and fourth surfaces of the capacitor body and connected to internal electrodes exposed through third and fourth surfaces of the capacitor body, respectively; Including,
The active region includes a first active region adjacent to a second surface of the capacitor body and a second active region adjacent to a first surface, which is a mounting surface of the capacitor body,
The length of the inner electrode of the second active region is smaller than the length of the inner electrode of the first active region,
The length variation of the internal electrode in the first active region is 5% or less, and the length variation of the internal electrode in the second active region is 5% or less.
The method of claim 6,
The overlapped capacitor of the inner electrode of the second active region is 25% or more of the overlap area of the inner electrode of the first active region.
The method of claim 6,
The overlapped capacitor of the inner electrode of the second active region is 85% or less of the overlap area of the inner electrode of the first active region.
The method of claim 6,
And a dummy electrode disposed in the second active region to be spaced apart from the inner electrode and the adjacent outer electrode.

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