KR20190098794A - Multi-bit Multi-stage Binary Search Analog-to-Digital Converter - Google Patents

Abstract

The present invention relates to an analog-to-digital converter and, more specifically, to a multibit multistage binary search analog-to-digital converter. According to an embodiment of the present invention, the multibit multistage binary search analog-to-digital converter includes: a first stage comparator part including K first comparators receiving a clock signal, and comparing the input signal (VIN) to a reference voltage to output an output value; a second stage comparator part including M second comparators receiving a first triggering signal as a clock signal, and comparing the input signal to a reference voltage to output an output value; a decoder-switching part receiving the output value of each of the first comparators of the first stage comparator part, and selecting and providing a reference voltage for third comparators of a third stage comparator part based on the output value of the first comparators; and a third stage comparator part including O third comparators receiving the reference voltage from the decoder-switching part, receiving the second triggering signal as a clock signal, and comparing the input signal to the reference voltage to output an output value.

Description

Multi-bit Multi-stage Binary Search Analog-to-Digital Converter}

The present invention relates to an analog-to-digital converter, and more particularly to a multi-bit multi-stage binary search analog-to-digital converter.

Digital wireless communications technologies such as UWB and WPAN require low-power, high-speed analog to digital converters (ADCs) to convert RF / IF signals into digital formats for subsequent baseband processing. An analog-to-digital converter is a device that converts an analog signal into a digital signal, and is a device that receives and digitizes signals such as temperature, pressure, voice, video, and voltage that are continuously measured. To date, various types of analog to digital converters have been proposed. For example, flash type analog to digital converters (PIC), pipeline analog to digital converters (Pipeline ADCs), and successive approximation analog to digital converters (Successive Approximation Register ADCs) have been proposed, and are being used in applications suitable for each characteristic. .

Flash-type analog-to-digital converters operate relatively fast, but the area increases rapidly with precision. Pipeline analog-to-digital converters support fast operation and high precision, but power is consumed by the use of amplifiers at each stage. Serial approximation analog-to-digital converters (SAR ADCs) have a low power consumption of the circuit and have a simple circuit configuration, but operate relatively slowly.

Given latency and conversion speed, flash analog-to-digital converters (flash ADCs) are often the most desirable option. In general, flash analog-to-digital converters have the disadvantage of high power consumption and large area overhead. In contrast, SAR ADCs have low power consumption and occupy a small area. SAR ADCs, however, require multiple comparison cycles for one conversion, which limits the conversion rate. The structure of the comparator based binary search ADC is between the structures of the flash ADCs and SAR ADCs. Compared to flash ADCs (high speed, high power) and SAR ADCs (low speed, low power), binary search ADCs achieve a balance between operating speed and power consumption.

Figure 1 illustrates a conventional raw 5b asynchronous binary search ADC. The number in the comparator indicates the position of the reference voltage over the entire operating range of the reference voltage. The clock signal is input only to the first comparator 111. The first comparator 111 compares the input signal with the center reference voltage level, 1/2. In accordance with the determination of the first comparator 111, each comparator 121 (reference voltage 3/4) or comparator 122 (reference voltage 1/4) is activated. When the comparator 121 (reference voltage 3/4) is activated, it next activates each comparator 131 (reference voltage 7/8) or comparator 132 (reference voltage 5/8). The procedure repeats until the last bit is obtained.

2 illustrates a conventional decoder based asynchronous binary search ADC. 2 illustrates a structure in which a number of comparators is reduced, but a decoder and a switch are added, unlike FIG. 1. In FIG. 2, the number of comparators is smaller, so that calibration of the offsets becomes easier when there are offsets in the comparator than FIG. 1.

Similar to FIG. 1, the clock signal is input only to the first comparator 211. The output signal of the first comparator 211 is the start (trigger) signal of the comparators 221, 222 in the second stage. Once the first comparator 211 determines the output, one of the second-stage comparators starts a comparison between the input signal and the reference voltage level. In addition, the determination of the first comparator 211 is provided to the decoder & SW array 260 as a control signal, and the decoder & SW array 260 selects a reference voltage using the control signal to select the third-stage comparators 231 and 232. ) Provides a reference voltage. Decoder & SW array 260 serves as a reference voltage switching multiplexer. In the third stage there are four possible reference voltage levels (1/8, 3/8, 5/8, 7/8). If the output code of the first comparator 211 shows Vin> 1/2, then only 5/8 and 7/8 are possible reference voltages, since 1/8 and 3/8 are smaller than 1/2. The selected reference voltages, for example 5/8 and 7/8, are connected to third-stage comparators 231 and 232 via Decoder & SW array 260.

The comparison operation of the second-stage comparator and the switching of the reference voltages of the third-stage comparators occur simultaneously. The settling time of the switched reference voltage should be shorter than the comparison operation. When the comparison operation of the second stage is completed, the triggered third stage comparator starts its comparison operation. At this point, the reference voltage of the third-stage comparator has already stabilized. The accuracy of the comparison is guaranteed and no conversion time is wasted. The asynchronous binary search ADC of Figure 2 also avoids the requirement of a high frequency clock. The structure of the asynchronous binary search ADC reduces the complexity of the switching network, which increases exponentially in resolution, or reduces the number of comparators.

Binary search ADCs include sampling circuits such as Track and Hold Amplifier (THA) or Sample and Hold Amplifier (SHA) that hold a sampled input signal to repeat the comparison. Conventional n-bit binary search ADCs include 2n-1 comparators, with only n comparators active for one conversion period. In theory, only one comparator is active at any one moment of the comparison step. The THA of a conventional binary search ADC drives 2n-1 comparators. Although most comparators are inactive, blocking transistors still induce parasitic capacitance in THA. The asynchronous binary search ADC of Figure 2 requires a 2n-1 comparator, which simplifies the THA design. Although only 1b / successive Approximation Register (SAR) ADCs have only one comparator, the conversion speed of the SAR ADCs is limited by the comparator's recovery and setting of the digital-analog converter (DAC) limits.

In FIG. 2, the asynchronous binary search ADC may include passive THA (not shown) to maintain the sampled input signal. Passive THA provides the comparator with a high quality sample signal.

The first comparator 211 determines the selection of the third-stage reference voltage. The comparator of the first-stage and the second-stage together selects the reference voltage of the fourth-stage comparator. The input signal and the reference voltage can be differential voltages. A pair of reference voltages is selected from four pairs. Similarly, the reference voltage of the fifth-stage comparator is determined by the comparators from the first stage to the third stage. One pair of reference voltages is selected from eight pairs.

Since the comparators are activated in turn during the conversion period, a latch-based comparator without static power consumption is selected.

In the reset phase, both outputs of the comparator are forced to ground (logical 0). When the comparator is triggered, one output is at VDD (logic 1) and the other is grounded due to latch regeneration.

Table 1 below compares the characteristics of the conventional binary search ADCs shown in FIGS. 1 and 2 in terms of the number of comparators, active comparators, and bit delays.

Compare conventional binary search ADC Conventional Raw Binary Search ADC (Figure 1) Conventional decoder based binary search ADC (Figure 2) Area # of comp. 2 ^N -1 2N-1 Power # of active comp. N N Speed Bit latency N * T _CMP N * T _CMP + (N-2) * T _OR

Where N is the number of stages, T _CMP is the delay time of the comparator, and T _OR is the delay time of the OR gate.

As shown in Table 1, the decoder-based binary search ADC (Figure 2) has advantages in terms of physical area occupied by the ADC over the conventional raw binary search ADC (Figure 1), but the delay time is longer in terms of the bit delay of the ADC. The disadvantage is the complexity of the switching network, which increases exponentially with losing points and resolution (bits). Therefore, there is a need to develop a binary search ADC that reduces the physical area of the ADC and reduces the bit delay and complexity of the switching network.

Korean Patent Publication No. 10-1644999 "Low-Power Analog-to-Digital Converter Using Time Domain Multistage Interpolation Technique"

 SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a multi-bit multi-stage binary search analog-to-digital converter.

However, the object of the present invention is not limited to the above-mentioned object, and other objects not mentioned will be clearly understood by those skilled in the art from the following description.

A multi-bit multi-stage binary search analog-to-digital converter device according to an embodiment of the present invention includes K first comparators for receiving a clock signal and comparing an input signal V _IN with a reference voltage and outputting an output value. A first stage comparator; An AND gate section including L AND gates for receiving a plurality of output values of the comparators of the K first comparators and outputting a first triggering signal to a second stage comparator when the output values are all “1”; A second stage comparator comprising M second comparators for receiving the first triggering signal as a clock signal and comparing an input signal with a reference voltage and outputting an output value; OR including N OR gates receiving a plurality of output signals of the second comparators of the second comparator and outputting a second triggering signal to the third comparator when any one of the output values is "1". A gate portion; A decoder-switching unit receiving an output value of each first comparator of the first comparator and selecting and providing reference voltages of third comparators of the third comparator based on the output of the first comparator; And a third comparator for receiving a reference voltage from the decoder-switching unit, receiving the second triggering signal as a clock signal, and comparing the input signal with the received reference voltage and outputting an output value. Comparator unit; characterized in that comprises a.

Preferably, in order to operate as a 6-bit four-stage binary search analog-to-digital converter, a plurality of output values of the comparators of the O third comparators are input, and when the output values are all "1", the third triggering signal is output. The apparatus further includes two AND gate parts including L AND gates output to the fourth stage comparator, receives the third triggering signal as a clock signal, and compares an input signal with a reference voltage received from the decoder-switching part. And a fourth stage comparator including two fourth comparators for outputting an output value, wherein the decoder-switching unit is configured to compare the fourth stage based on the reference voltages of the third comparators of the third stage comparator. The reference voltage of the fourth comparators of the base is selected and provided to the fourth comparators of the fourth comparator.

As described above, the binary search ADC of the present invention has the effect of reducing the bit delay and reducing the complexity of the switching network while reducing the physical area of the conventional binary search ADC.

Figure 1 illustrates a conventional raw 5b asynchronous binary search ADC.
2 illustrates a conventional decoder based asynchronous binary search ADC.
Figure 3 illustrates the structure of a multi-bit multi-stage binary search analog-to-digital converter according to an embodiment of the present invention.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, the terms "comprise" or "consisting" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other It is to be understood that the present invention does not exclude the possibility of the presence or the addition of features, numbers, steps, operations, components, parts, or a combination thereof.

Figure 3 illustrates the structure of a multi-bit multi-stage binary search analog-to-digital converter according to an embodiment of the present invention.

The multi-bit multi-stage binary search analog-to-digital converter according to one embodiment of the present invention of FIG. 3 illustrates a 5-bit, three stage binary search ADC. As shown in FIG. 3, a plurality of comparators 311, 312 and 313 for the first stage, a plurality of AND gate portions 341 and 342 for selecting the comparator of the second stage, a plurality of comparators 321, 322, 323 and 324 for the second stage, A plurality of OR gate parts 351 and 352 for selecting a comparator in the third stage, a plurality of comparators 331, 332, 333, 334, 335 and 336 for the third stage, and a decoder & SW array 360 for setting a reference voltage of the comparator in the third stage. It is configured by.

Although not shown in FIG. 3, the V _IN input signal is simultaneously input to all comparators through a sampling circuit, such as a Track and Hold Amplifier (THA) or Sample and Hold Amplifier (SHA), which holds a sampled input signal. . As shown in FIG. 3, the plurality of comparators 311, 312, and 313 for the first stage have the same structure as the 2-bit flash ADC. Therefore, the clock signal V _CLK is input to the clock input terminals of all the comparators 311, 312, and 313 in the first stage. The output signals of all comparators 311, 312, 313 in the first stage are the start (trigger) signals of the comparators 321, 322, 323, 324 in the second stage. One of the second-stage comparators is triggered according to the output values of the output signals of all the comparators 311, 312, 313 of the first stage. Numbers (1/4, 1/2, 3/4) in the first stage comparators 311, 312, 313 and Numbers (1/8, 3/8, 5 / in the second stage comparators 321, 322, 323, 324 8, 7/8) represents the position of the reference voltage over the entire operating range of the reference voltage. The reference voltage of the comparator in the first and second stages is a predetermined fixed value.

Referring to the operation for triggering the comparators in the first stage,

If the input signal V _IN is greater than or equal to 3/4 of the entire operating range, the + output signal of the comparator 311 of the first stage is outputted with "1", and the clock input terminal of the comparator 321 of the second stage is enabled. It is input as a (drive) signal.

If the input signal V _IN is less than 3/4 of the entire operating range and is 1/2 or more, the negative side output signal of the comparator 311 of the first stage is outputted with “1” and the comparator 312 of the first stage. Output signal of " 1 " is outputted, output signals are inputted to AND gate portion 341, AND gate portion 341 outputs " 1 ", and output signal of AND gate portion 341 Is input to the clock input terminal of the comparator 322 in the second stage as an enable (drive) signal.

If the input signal V _IN is less than 1/2 of the entire operating range and is greater than 1/4, the output signal of the negative side of the comparator 312 of the second stage is outputted with “1”, and the comparator 313 of the first stage. Output signal of " 1 " is outputted, output signals are inputted to AND gate portion 341, AND gate portion 342 outputs " 1 ", and output signal of AND gate portion 342 Is input to the clock input terminal of the comparator 323 of the second stage as an enable (drive) signal.

If the input signal V _IN is less than 1/4 of the entire operating range, the negative output signal of the comparator 313 of the first stage is outputted with "1", and the clock input terminal of the comparator 324 of the second stage is enabled. It is input as a (drive) signal.

The output terminal outputs "1" of the + and-output signals of the comparators, but outputs a "high-Z" signal.

The comparator in the second stage selected according to the input signal is different. For example, when V _IN is 22/32 <V _IN <23/32, the first stage comparator 311 corresponds to the case where the input signal V _IN is less than 3/4 of the entire operating range and is more than 1/2. Output signal of " 1 " is outputted, output signal " 1 " of comparator 312 of the first stage is outputted, and output signals are inputted to AND gate portion 341. The unit 341 outputs "1", and the output signal of the AND gate unit 341 is input to the clock input terminal of the comparator 322 in the second stage as an enable (drive) signal, and in the second stage. Of the comparators that are present, comparator 322 starts a comparison between the input signal and the reference voltage level 5/8.

Referring to the operation of the triggered comparator among the comparators in the second stage,

If the input signal V _IN is greater than or equal to 7/8 of the entire operating range, the + output signal of the comparator 321 of the second stage is outputted with “1” and is input to the OR gate unit 351.

If the input signal V _IN is less than 7/8 of the entire operating range and is more than 5/8, the negative output signal of the comparator 321 of the second stage is outputted with “1” and is inputted to the OR gate unit 352. , The + output signal of the comparator 322 in the second stage is outputted to the OR gate unit 351.

If the input signal V _IN is less than 5/8 of the entire operating range and is more than 3/8, the negative output signal of the comparator 322 of the second stage is outputted with “1” and is input to the OR gate unit 352. , The + output signal of the comparator 323 of the second stage is outputted to the OR gate unit 351.

If the input signal V _IN is less than 3/8 of the entire operating range, and more than 1/8, the negative output signal of the comparator 323 of the second stage is outputted with “1” and is input to the OR gate unit 352. , The + output signal of the comparator 324 of the second stage is outputted to the OR gate unit 351.

If the input signal V _IN is less than 1/8 of the entire operating range, the negative output signal of the comparator 324 in the second stage is outputted with “1” and is input to the OR gate unit 352.

The OR gate units 351 and 352 that have received the output signals of the second stage comparators 321, 322, 323 and 324 have an output signal of the OR gate units 351 and 352 when one of the output signals is “1”. 331, 332, 333, 334, 335 and 336 are inputted as enable (drive) signals to the clock input terminals.

In order to explain the operation of the triggered comparator among the comparators in the third stage, the reference voltage setting is first described. The output signals of all the comparators 311, 312, 313 of the first stage are output to the decoder & SW array 360 to operate as a control signal for setting the reference voltages of the plurality of comparators 331, 332, 333, 334, 335, 336 for the third stage. Decoder & SW array 360 selects a reference voltage using a control signal to provide a reference voltage to third-stage comparators 331,332,333,334,335,336. Decoder & SW array 360 serves as a reference voltage switching multiplexer. There are 24 possible reference voltage levels for the six third stage comparators. Possible voltage references are 1 / 31-3 / 32, 5 / 32-7 / 32, 9 / 32-11 / 32, 13 / 32-15 / 32, 17 / 32-19 / 32, 21 / 32-23 / 32, 25 / 32-27 / 32, 29 / 32-31 / 32.

 As shown in Fig. 3, if the output code (signal) of the comparators 311, 312 shows 1/2 <Vin <3/4, only 17 / 32-19 / 32, 21 / 32-23 / 23 can reference voltage 1 / 31-3 / 32, 5 / 32-7 / 32, 9 / 32-11 / 32, 13 / 32-15 / 32 are smaller than 1/2, 25 / 32-27 / 32, 29 Because / 32-31 / 32 is bigger than 3/4.

If Vin> 3/4, only 25 / 32-27 / 32, 29 / 32-31 / 32 are the possible reference voltages,

Showing 1/4 <Vin <1/2, only 9 / 32-11 / 32, 13 / 32-15 / 32 are the possible reference voltages,

If Vin <1/4, only 1 / 31-3 / 32, 5 / 32-7 / 32 are possible reference voltages.

Selected reference voltages, for example 17 / 32-19 / 32, 21 / 32-23 / 23 reference voltages, are connected to six third-stage comparators 331,332,333,334,335,336 via Decoder & SW array 360. . That is, the reference voltages are received by the decoder & SW array 360 and provided to the comparators 331, 332, 333, 334, 335 and 336 according to the output signal of the first stage comparator.

The comparison operation of the second-stage comparator and the switching of the reference voltages of the third-stage comparators occur simultaneously. The settling time of the switched reference voltage should be shorter than the comparison operation. When the second-stage comparison operation is completed, the triggered third-stage comparator starts its comparison operation. At this point, the reference voltage of the third-stage comparator has already stabilized. The accuracy of the comparison is guaranteed and no conversion time is wasted.

Referring to the operation for triggering the comparators in the third stage,

When any one of the OR gate parts 351 and 352 (eg, 351) outputs "1", it is input as an enable (drive) signal to a clock input terminal of some of the comparators 331, 332, 333, 334, 335 and 336 of the third stage. The comparators 331, 332, 333 of some of the comparators in the third-stage compare between the input signal and the reference voltage levels 21 / 32-23 / 32 and if the input signal is greater than the reference voltage, " 1 " If it is less than the reference voltage, it outputs "1" at the output terminal.

Table 2 below compares the characteristics of the binary search ADC shown in FIG. 3 in terms of the number of comparators, active comparators, and bit delays.

Binary Search ADC Features of the Invention Binary Search ADC of the Invention (FIG. 3) # of comp. 2 ^{N, 1st + 1} + 2 ^{N, 3rd + 1} -3 # of active comp. 2 ^{N, 1st} + 2 ^{N, 3rd} -1 Bit latency 2-then-1 S * T _CMP + roundup {(S-1) / 2} * T _AND
+ rounddown {(S-1) / 2} * T _OR 1-then-2 S * T _CMP + roundup {(S-3) / 2} * T _AND
+ rounddown {(S-1) / 2} * T _OR

Where: S: number of stages, T _CMP : delay time of comparator, T _AND : delay time of AND gate, T _OR : delay time of OR gate, roundup {}: round up, rounddown {}: round down.

As shown in Table 2, the binary search ADC of the present invention has advantages in terms of the physical area occupied by the ADC over the conventional raw binary search ADC (FIG. 1), and the ADC over the conventional decoder-based binary search ADC (FIG. 2). In terms of bit delay, the delay time is short and the complexity of the switching network increases exponentially in resolution (bit count).

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

Claims (1)

In the multi-bit multi-stage binary search analog-to-digital converter,
A first stage comparator comprising a K first comparators for receiving a clock signal and comparing an input signal V _IN with a reference voltage and outputting an output value;
An AND gate section including L AND gates for receiving a plurality of output values of the comparators of the K first comparators and outputting a first triggering signal to a second stage comparator when the output values are all “1”;
A second stage comparator comprising M second comparators for receiving the first triggering signal as a clock signal and comparing an input signal with a reference voltage and outputting an output value;
OR including N OR gates receiving a plurality of output signals of the second comparators of the second comparator and outputting a second triggering signal to the third comparator when any one of the output values is "1". A gate portion;
A decoder-switching unit receiving an output value of each first comparator of the first comparator and selecting and providing reference voltages of third comparators of the third comparator based on the output of the first comparator; And
A third stage comparator including O third comparators for receiving a reference voltage from the decoder-switching unit, receiving the second triggering signal as a clock signal, and comparing the input signal with the received reference voltage and outputting an output value; Multi-bit multi-stage binary search analog-to-digital converter, characterized in that it comprises a base.

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