KR20190094141A - Display device and method for fabricating the same - Google Patents

Abstract

A display device includes a base layer including a first region and a second region, light emitting devices disposed on the first region of the base layer, an encapsulation layer sealing the light emitting devices, sensors disposed on the encapsulation layer, pads disposed on the second region of the base layer and arranged along a first direction, signal wires electrically connected to the sensors and the pads, respectively, and a sublayer disposed on the second region of the base layer, disposed between the sensors and the pads, and extended in the first direction. The sublayer includes a first layer and a second layer disposed on the first layer, and, in a planar view, the second layer does not overlap with the signal lines. It is possible to prevent detects generated in a line wiring patterning process.

Description

DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a display device and a method of manufacturing the same, and more particularly, to a display device and a method of manufacturing the same that improves a defect generated during the touch line wiring patterning process.

Various display devices for multimedia devices such as televisions, mobile phones, tablet computers, navigation devices, game machines, and the like are being developed. Input devices of the display devices include a keyboard or a mouse. Also, recently, display devices include a touch sensing unit as an input device.

The present invention relates to a display device and a method of manufacturing the same, and more particularly, to a display device and a method of manufacturing the same that improves a defect generated during the touch line wiring patterning process.

According to an exemplary embodiment, a display device includes a base layer including a first area and a second area, light emitting devices disposed on the first area of the base layer, an encapsulation layer sealing the light emitting devices, and the encapsulation device. Sensors disposed over the layer, pads disposed over the second area of the base layer and arranged along a first direction, signal wires electrically connected to the sensors and the pads, respectively, and the base layer A sublayer disposed over a second region, the sublayer disposed between the sensors and the pads, the sublayer extending in the first direction, the sublayer disposed on the first layer and the first layer; And a second layer, when viewed in plan view, non-overlapping with the signal lines.

One region of the second layer may be removed, and the signal lines may be disposed in the removed region.

The signal wires may extend in a second direction crossing the first direction.

Each of the sensors may be electrostatically coupled with other adjacent sensors.

The sensors may sense an external input in a capacitive manner.

The display device may further include a first capping pattern disposed on the second layer of the sub layer.

The display device may further include a first insulating layer covering the sensors, the signal lines, the sub layer, and the first capping pattern.

The apparatus may further include dummy wirings overlapping the signal wires and a second capping pattern overlapping the first capping pattern.

The dummy wires may be disposed under the signal wires, and the second capping pattern may be disposed under the first capping pattern.

The display device may further include a second insulating layer disposed between the dummy wires and the signal wires and between the second capping pattern and the first capping pattern.

The protrusion may further include a protrusion disposed on the second region of the base layer and surrounding at least a portion of the sensors, and at least a portion of the protrusion may be disposed between the sub layer and the sensors.

A display device according to an embodiment of the present invention includes a base layer and a light emitting device including a first area and a second area defined outside the first area, and are disposed on the first area of the base layer. An input sensing unit including an element layer, an encapsulation layer covering the element layer, electrodes disposed on the encapsulation layer, an insulating layer disposed on the encapsulation layer, and signal wires electrically connected to the electrodes, the second A sublayer disposed over an area, the first layer having a first thickness and a second area having a second thickness less than the first thickness and overlapping the signal wires, and the first area and the second area; And a capping pattern disposed on a boundary between regions, and the signal lines and the capping pattern may be covered by the insulating layer.

A display device according to an embodiment of the present invention includes a base layer including a first area and a second area defined outside the first area, and a light emitting device disposed on the first area of the base layer. An input sensing unit including a layer, an encapsulation layer covering the device layer, an insulating layer disposed on the encapsulation layer, electrodes disposed on the encapsulation layer, and signal wires electrically connected to the electrodes, and the second region. A sub-layer disposed on and including a first region having a first thickness and a second region having a second thickness less than the first thickness and overlapping the signal lines, wherein the signal lines are in a first direction The sub layer may extend along a second direction crossing the first direction.

The present invention forms a capping pattern at an inclined boundary on the bank, thereby preventing the organic material inside the bank from leaking due to the lack of a thickness of the photoresist layer formed on the boundary. It can be prevented from occurring.

1 is a perspective view illustrating a first operation of a display device according to an exemplary embodiment of the present invention.
2A is a perspective view illustrating a second operation of a display device according to an exemplary embodiment of the present invention.
2B is a perspective view according to a third operation of the display device according to an embodiment of the present invention.
2C is a cross-sectional view of a display device according to an exemplary embodiment of the present invention.
3A and 3B are perspective views of a display device according to an exemplary embodiment of the present invention.
4A is a cross-sectional view of a display module according to an exemplary embodiment of the present invention.
4B is a plan view of an organic light emitting display panel according to an exemplary embodiment of the present invention.
5 is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the present invention.
6A and 6B are partial cross-sectional views of an organic light emitting display panel according to an embodiment of the present invention.
7A to 7C are cross-sectional views of thin film encapsulation layers according to an exemplary embodiment.
8A is a cross-sectional view of a touch sensing unit according to an embodiment of the present invention.
8B to 8E are plan views of the touch sensing unit according to the embodiment of the present invention.
FIG. 8F is a partially enlarged view of the AA region of FIG. 8E.
9 is a cross-sectional view taken along the line AA ′ of FIG. 8E.
FIG. 10A is a cross-sectional view taken along the line BB ′ of FIG. 8E.
10B is a cross-sectional view of a bank BAK according to another embodiment of the present invention.
11 is a perspective view of a portion of the bank.
12A to 12G illustrate a process of forming a first capping pattern on a bank.
13A to 13C are plan views illustrating another embodiment of the present invention.
14 is a cross-sectional view for explaining another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the present specification, when a component (or region, layer, portion, etc.) is referred to as being on, "connected", or "coupled" to another component, it is directly connected / It may be combined or a third component may be arranged therebetween.

Like reference numerals refer to like elements. In addition, in the drawings, the thickness, ratio, and dimensions of the components are exaggerated for the effective description of the technical contents. "And / or" includes all one or more combinations that the associated configurations may define.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. Singular expressions include plural expressions unless the context clearly indicates otherwise.

Also, terms such as "below", "below", "above", and "above" are used to describe the association of the components shown in the drawings. The terms are described in a relative concept based on the directions indicated in the drawings.

The terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described on the specification, and one or more other features, numbers, steps It is to be understood that the present invention does not exclude, in advance, the possibility of the presence or addition of any operation, component, part, or combination thereof.

1 is a perspective view illustrating a first operation of a display device DD according to an exemplary embodiment of the present invention. 2A is a perspective view illustrating a second operation of the display device DD according to an exemplary embodiment of the present invention. 2B is a perspective view illustrating a third operation of the display device DD according to an exemplary embodiment of the present invention.

In the first operation mode, as illustrated in FIG. 1, the display surface IS on which the image IM is displayed is parallel to a surface defined by the first direction axis DR1 and the second direction axis DR2. The third direction axis DR3 indicates the normal direction of the display surface IS, that is, the thickness direction of the display device DD. The front (or top) and back (or bottom) surfaces of the members are separated by the third direction axis DR3. However, a direction indicated by the first to third direction axes DR1, DR2, and DR3 may be converted to another direction as a relative concept. Hereinafter, the first to third directions refer to the same reference numerals in the directions indicated by the first to third direction axes DR1, DR2, and DR3, respectively.

1, 2A, and 2B illustrate a foldable display as an example of the flexible display DD. However, the present invention may be a rollable display device or a banded display device that is rolled up, and is not particularly limited. In addition, although the flexible display device is illustrated in the present embodiment, the present invention is not limited thereto. The display device DD according to the present embodiment may be a flat rigid display device. The flexible display device DD according to the present invention may be used in large electronic devices such as a television, a monitor, and the like, as well as small and medium electronic devices such as a mobile phone, a tablet, a car navigation device, a game machine, a smart watch, and the like.

As illustrated in FIG. 1, the display surface IS of the flexible display device DD may include a plurality of regions. The flexible display device DD includes a display area DD-DA on which the image IM is displayed and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area DD-NDA is an area where no image is displayed. 1 illustrates a vase as an example of an image IM. For example, the display area DD-DA may have a rectangular shape. The non-display area DD-NDA may surround the display area DD-DA. However, the present invention is not limited thereto, and the shape of the display area DD-DA and the shape of the non-display area DD-NDA may be relatively designed.

As illustrated in FIGS. 1, 2A, and 2B, the display device DD may include a plurality of regions defined according to an operation type. The display device DD is configured to bend the bending area BA, the non-bending first non-bending area NBA1, and the second non-bending area NBA2 on the basis of the bending axis BX. It may include. As shown in FIG. 2A, the display device DD has an inner bending such that the display surface IS of the first non-bending area NBA1 and the display surface IS of the second non-bending area NBA2 face each other. -bending). As illustrated in FIG. 2B, the display device DD may be outer-bended so that the display surface IS is exposed to the outside.

In an exemplary embodiment, the display device DD may include a plurality of bending areas BA. In addition, the bending area BA may be defined to correspond to the form in which the user manipulates the display device DD. For example, unlike the FIGS. 2A and 2B, the bending area BA may be defined to be parallel to the first direction axis DR1 or may be defined in a diagonal direction. The area of the bending area BA is not fixed but may be determined according to the radius of curvature. In an embodiment of the present invention, the display device DD may be configured to repeat only the operation modes illustrated in FIGS. 1 and 2A.

2C is a cross-sectional view of the display device DD according to the exemplary embodiment of the present invention. 2 illustrates a cross section defined by the second direction axis DR2 and the third direction axis DR3.

As shown in Figure 2c, The display device DD includes a protective film PM, a display module DM, an optical member LM, a window WM, a first adhesive member AM1, a second adhesive member AM2, and a third adhesive member. (AM3). The display module DM is disposed between the protective film PM and the optical member LM. The optical member LM is disposed between the display module DM and the window WM. The first adhesive member AM1 couples the display module DM and the protective film PM, and the second adhesive member AM2 couples the display module DM and the optical member LM and the third adhesive member. AM3 couples the optical member LM and the window WM.

The protective film PM protects the display module DM. The protective film PM provides a first outer surface OS-L exposed to the outside, and provides an adhesive surface adhered to the first adhesive member AM1. The protective film PM prevents external moisture from penetrating the display module DM and absorbs external shocks.

The protective film PM may include a plastic film as a base substrate. Protective film (PM) is polyethersulfone (PES), polyacrylate, polyetherimide (PEI, polyetherimide), polyethylenenaphthalate (PEN, polyethylenenaphthalate), polyethylene terephthalate (PET, polyethyleneterephthalate), poly Phenylene sulfide (PPS), polyarylate (polyarylate), polyimide (PI, polyimide), polycarbonate (PC, polycarbonate), polyarylene ethersulfone (poly (arylene ethersulfone)) and combinations thereof It may include a plastic film including any one selected from the group consisting of.

The material constituting the protective film PM is not limited to plastic resins, and may include an organic / inorganic composite material. The protective film PM may include a porous organic layer and an inorganic material filled in pores of the organic layer. The protective film PM may further include a functional layer formed on the plastic film. The functional layer may include a resin layer. The functional layer may be formed by a coating method. In one embodiment of the present invention, the protective film PM may be omitted.

The window WM may comprise a plastic film. The window WM may have a multilayer structure. The window WM may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. The window WM may further include a bezel pattern. The multilayer structure may be formed through a continuous process or an adhesive process using an adhesive layer.

The optical member LM reduces the external light reflectance. The optical member LM may include at least a polarizing film. The optical member LM may further include a retardation film. In one embodiment of the present invention, the optical member LM may be omitted.

The display module DM may include an organic light emitting display panel DP and a touch sensing unit TS. The touch sensing unit TS is disposed directly on the organic light emitting display panel DP. As used herein, “directly disposed” means formed by a continuous process except for attaching using a separate adhesive layer.

The organic light emitting display panel DP generates an image IM (see FIG. 1) corresponding to the input image data. The organic light emitting display panel DP provides a first display panel surface BS1 -L and a second display panel surface BS1 -U facing each other in the thickness direction DR3. In the exemplary embodiment, the organic light emitting display panel DP has been described as an example, but the display panel is not limited thereto.

The touch sensing unit TS obtains coordinate information of an external input. The touch sensing unit TS may sense an external input in a capacitive manner.

Although not separately illustrated, the display module DM according to an exemplary embodiment may further include an antireflection layer. The antireflective layer may include a stacked structure of a color filter or a conductive layer / insulation layer / conductive layer. The antireflective layer may reduce external light reflectance by absorbing or canceling interference or polarizing light incident from the outside. The antireflection layer may replace the function of the optical member LM.

Each of the first adhesive member AM1, the second adhesive member AM2, and the third adhesive member AM3 may be an optically clear adhesive film (OCA) or an optically clear resin (OCR). Or an organic adhesive layer such as a pressure sensitive adhesive film (PSA). The organic adhesive layer may include an adhesive material such as polyurethane, polyacrylic, polyester, polyepoxy and polyvinyl acetate. As a result, the organic adhesive layer corresponds to one of the organic layers.

Although not separately illustrated, the display device DD may further include a frame structure supporting the functional layers in order to maintain the state illustrated in FIGS. 1, 2A, and 2B. The frame structure may comprise a joint structure or a hinge structure.

3A and 3B are perspective views of a display device DD-1 according to an exemplary embodiment of the present invention. FIG. 3A illustrates the display device DD-1 in an unfolded state and FIG. 3B illustrates the display device DD-1 in a bent state.

The display device DD-1 may include one bending area BA and one non-bending area NBA. The non-display area DD-NDA of the display device DD-1 may be bent. However, in an exemplary embodiment, the bending area of the display device DD-1 may be changed.

Unlike the display device DD illustrated in FIGS. 1, 2A, and 2B, the display device DD-1 according to the present exemplary embodiment may be fixed and operate in one form. The display device DD-1 may operate in a bent state as shown in FIG. 3B. The display device DD-1 may be fixed to a frame in a bent state, and the frame may be coupled to a housing of the electronic device.

The display device DD-1 according to the present exemplary embodiment may have the same cross-sectional structure as illustrated in FIG. 2C. However, the non-bending area NBA and the bending area BA may have different stacked structures. The non-bending area NBA may have the same cross-sectional structure as shown in FIG. 2C, and the bending area BA may have a different cross-sectional structure than that shown in FIG. 2C. The optical member LM and the window WM may not be disposed in the bending area BA. That is, the optical member LM and the window WM may be disposed only in the non-bending area NBA. The second adhesive member AM2 and the third adhesive member AM3 may also be unlocated in the bending area BA.

4A is a cross-sectional view of a display module DM according to an exemplary embodiment of the present invention. 4B is a plan view of an organic light emitting display panel DP according to an embodiment of the present invention. 5 is an equivalent circuit diagram of a pixel PX according to an exemplary embodiment of the present invention. 6A and 6B are partial cross-sectional views of an organic light emitting display panel DP according to an embodiment of the present invention.

As shown in FIG. 4A, the organic light emitting display panel DP includes a base layer SUB, a circuit layer DP-CL, an element layer DP-OLED, and a thin film encapsulation disposed on the base layer SUB. Layer TFE. The base layer SUB may include at least one plastic film. The base layer SUB is a flexible substrate and may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

The circuit layer DP-CL may include a plurality of insulating layers, a plurality of conductive layers, and a semiconductor layer. The plurality of conductive layers of the circuit layer DP-CL may constitute a control circuit of signal lines or pixels. The device layer DP-OLED includes organic light emitting diodes. The thin film encapsulation layer TFE includes an inorganic layer and an organic layer. The thin film encapsulation layer TFE may include at least two inorganic layers and an organic layer disposed therebetween. The inorganic layers protect the light emitting device layer (DP-OLED) from moisture / oxygen, and the organic layer protects the light emitting device layer (DP-OLED) from foreign matter such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, or the like. The organic layer may include an acrylic organic material, but is not limited thereto.

The touch sensing unit TS is disposed directly on the thin film encapsulation layer TFE. The touch sensing unit TS includes touch sensors and touch signal lines. The touch sensors and the touch signal lines may have a single layer or a multilayer structure.

The touch sensors and touch signal lines may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphene. The touch sensors and touch signal lines may comprise a metal layer, such as molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The touch sensors and the touch signal lines may have the same layer structure or different layer structures. Details of the touch sensing unit TS will be described later.

4B is a plan view of an organic light emitting display panel DP according to an embodiment of the present invention, and FIG. 5 is an equivalent circuit diagram of a pixel PX according to an embodiment of the present invention.

As shown in FIG. 4B, the organic light emitting display panel DP includes a display area DA and a non-display area NDA on a plane. The display area DA and the non-display area NDA of the organic light emitting display panel DP include the display area DD-DA and the non-display area DD-NDA of the display device DD (see FIG. 1). , See FIG. 1). The display area DA and the non-display area NDA of the organic light emitting display panel DP include the display area DD-DA and the non-display area DD-NDA of the display device DD (see FIG. 1). It is not necessarily the same as (see FIG. 1), it may be changed according to the structure / design of the organic light emitting display panel (DP).

The organic light emitting display panel DP includes a plurality of pixels PX. An area in which the plurality of pixels PX is disposed is defined as the display area DA. In the present embodiment, the non-display area NDA may be defined along the edge of the display area DA.

The organic light emitting display panel DP includes gate lines GL, data lines DL, light emitting lines EL, a control signal line SL-D, an initialization voltage line SL-Vint, and a voltage line. SL-VDD), a first pad PD1, and a power supply line E-VSS.

The gate lines GL are respectively connected to the corresponding pixels PX of the plurality of pixels PX, and the data lines DL are respectively connected to the corresponding pixels PX of the plurality of pixels PX. do. Each of the emission lines EL may be arranged in parallel with a corresponding gate line of the gate lines GL. The control signal line SL-D may provide control signals to the gate driving circuit GDC. The initialization voltage line SL-Vint may provide an initialization voltage to the plurality of pixels PX. The voltage line SL-VDD is connected to the plurality of pixels PX and may provide a first voltage to the plurality of pixels PX. The voltage line SL-VDD may include a plurality of lines extending in the first direction DR1 and a plurality of lines extending in the second direction DR2. The power supply line E-VSS may be disposed in the non-display area NDA to surround three side surfaces of the display area DA. A common voltage (eg, a second voltage) may be provided to the plurality of pixels PX of the power supply line E-VSS. The common voltage may be a voltage at a level lower than the first voltage.

A gate driving circuit GDC connected to the gate lines GL and the light emitting lines EL may be disposed on one side of the non-display area NDA. Some of the gate lines GL, the data lines DL, the light emitting lines EL, the control signal lines SL-D, the initialization voltage line SL-Vint, and the voltage lines are disposed on the same layer, Some are placed in different layers.

The first pad PD may be connected to the ends of the data lines DL, the control signal line SL-D, the initialization voltage line SL-Vint, and the voltage line SL-VDD.

FIG. 5 exemplarily illustrates an i-th pixel PXi connected to a k-th data line DLk among the plurality of data lines DL (refer to FIG. 4B).

The i-th pixel PXi includes an organic light emitting diode OLED and a pixel driving circuit for controlling the organic light emitting diode. The driving circuit may include seven thin film transistors T1 to T7 and one storage capacitor Cst.

The driving transistor controls the driving current supplied to the organic light emitting diode OLED. The output electrode of the second transistor T2 is electrically connected to the organic light emitting diode OLED. The output electrode of the second transistor T2 may be in direct contact with the anode of the organic light emitting diode OLED or may be connected via another transistor (in this embodiment, the sixth transistor T6).

The control electrode of the control transistor may receive a control signal. The control signal applied to the i th pixel PXi includes an i-1 th gate signal Si-1, an i th gate signal Si, an i + 1 th gate signal Si + 1, a data signal Dk, And an i-th emission control signal Ei. In an embodiment of the present invention, the control transistor may include a first transistor T1 and third to seventh transistors T3 to T7.

The first transistor T1 includes an input electrode connected to the k-th data line DLk, a control electrode connected to the i-th gate line GLi, and an output electrode connected to the output electrode of the second transistor T2. do. The first transistor T1 is turned on by the gate signal Si (hereinafter referred to as the i-th gate signal) applied to the i-th gate line GLi and the data signal Dk applied to the k-th data line DLk. To the storage capacitor Cst. 6A is a partial cross-sectional view of an organic light emitting display panel according to an embodiment of the present invention. 6B is a partial cross-sectional view of an organic light emitting display panel according to an exemplary embodiment of the present invention. Specifically, FIG. 6A illustrates a cross section of a portion corresponding to the first transistor T1 of the equivalent circuit illustrated in FIG. 5. FIG. 6B is a cross-sectional view of a portion corresponding to the second transistor T2, the sixth transistor T6, and the organic light emitting diode OLED of the equivalent circuit illustrated in FIG. 5.

6A and 6B, the circuit layer DP-CL is disposed on the base layer SUB. Although not separately illustrated, functional layers may be further disposed on one surface of the base layer SUB. The functional layers include at least either a barrier layer or a buffer layer.

The semiconductor pattern of the first transistor T1 (hereinafter referred to as the first semiconductor pattern) on the base layer SUB, the semiconductor pattern of the second transistor T2 (hereinafter referred to as the second semiconductor pattern), and the sixth transistor T6. ) Semiconductor pattern OSP6 (hereinafter referred to as a sixth semiconductor pattern) is disposed. The first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6 may be selected from amorphous silicon, polysilicon, and metal oxide semiconductors.

The first insulating layer 10 may be disposed on the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6. 6B and 6C, the first insulating layer 10 is provided as a layer covering the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6. However, the first insulating layer 10 may be provided as a pattern disposed corresponding to the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6.

The first insulating layer 10 may include a plurality of inorganic thin films. The plurality of inorganic thin films may include a silicon nitride layer, a silicon oxy nitride layer, and a silicon oxide layer.

On the first insulating layer 10, a control electrode GE1 (hereinafter referred to as first control electrode) of the first transistor T1, a control electrode GE2 (hereinafter referred to as a second control electrode) of the second transistor T2, and a sixth electrode The control electrode GE6 (hereinafter referred to as a sixth control electrode) of the transistor T6 is disposed. The first control electrode GE1, the second control electrode GE2, and the sixth control electrode GE6 may be manufactured according to the same photolithography process as the gate lines GL (see FIG. 5A).

The second insulating layer 20 covering the first control electrode GE1, the second control electrode GE2, and the sixth control electrode GE6 may be disposed on the first insulating layer 10. The second insulating layer 20 may provide a flat upper surface. The second insulating layer 20 may include an organic material and / or an inorganic material.

The input electrode SE1 of the first transistor T1 (hereinafter, referred to as a first input electrode), the output electrode DE1 (the first output electrode), and the input electrode of the second transistor T2 on the second insulating layer 20. SE2: second input electrode) and output electrode (DE2: second output electrode), input electrode of the sixth transistor T6 (SE6: next, sixth input electrode) and output electrode (DE6: sixth output electrode) ) Is placed.

The first input electrode SE1 and the first output electrode DE1 form a first through hole CH1 and a second through hole CH2 that pass through the first insulating layer 10 and the second insulating layer 20. The first semiconductor pattern OSP1 is connected to each other through the first semiconductor pattern OSP1. The second input electrode SE2 and the second output electrode DE2 form a third through hole CH3 and a fourth through hole CH4 that pass through the first insulating layer 10 and the second insulating layer 20. The second semiconductor pattern OSP2 is connected to each other through the second semiconductor pattern OSP2. The sixth input electrode SE6 and the sixth output electrode DE6 form the fifth through hole CH5 and the sixth through hole CH6 that pass through the first insulating layer 10 and the second insulating layer 20. The sixth semiconductor pattern OSP6 is connected to each other. Meanwhile, in another embodiment of the present invention, the first transistor T1, the second transistor T2, and the sixth transistor T6 may be modified to have a bottom gate structure.

The first input electrode SE1, the second input electrode SE2, the sixth input electrode SE6, the first output electrode DE1, the second output electrode DE2, and the second input electrode SE1 on the second insulating layer 20. The third insulating layer 30 covering the six output electrodes DE6 is disposed. The third insulating layer 30 includes an organic layer and / or an inorganic layer. In particular, the third insulating layer 30 may include an organic material to provide a flat surface.

Any one of the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 may be omitted according to the circuit structure of the pixel. Each of the second insulating layer 20 and the third insulating layer 30 may be defined as an interlayer insulating layer. The interlayer insulating layer is disposed between the conductive pattern disposed below and the conductive pattern disposed above the insulating layer to insulate the conductive patterns.

The pixel defining layer PDL and the organic light emitting diode OLED are disposed on the third insulating layer 30. The anode AE is disposed on the third insulating layer 30. The anode AE is connected to the sixth output electrode DE6 through the seventh through hole CH7 penetrating the third insulating layer 30. An opening OP is defined in the pixel defining layer PDL. The opening OP of the pixel defining layer PDL exposes at least a portion of the anode AE.

The pixel PX (shown in FIG. 4B) may be disposed in the pixel area on a plane. The pixel area may include a light emitting area PXA and a non-light emitting area NPXA adjacent to the light emitting area PXA. The non-light emitting area NPXA may surround the light emitting area PXA. In the present exemplary embodiment, the emission area PXA is defined to correspond to a partial area of the anode AE exposed by the opening OP.

The hole control layer HCL may be disposed in common in the light emitting area PXA and the non-light emitting area NPXA. Although not separately illustrated, a common layer such as the hole control layer HCL may be formed in common with the plurality of pixels PX (see FIG. 5A).

The organic light emitting layer EML is disposed on the hole control layer HCL. The organic light emitting layer EML may be disposed in a region corresponding to the opening OP. That is, the organic light emitting layer EML may be formed separately from each of the plurality of pixels PX. In the present exemplary embodiment, the patterned organic light emitting layer EML is illustrated as an example, but the organic light emitting layer EML may be commonly disposed on the plurality of pixels PX. In this case, the organic light emitting layer EML may generate white light. In addition, the organic light emitting layer (EML) may have a multilayer structure.

The electronic control layer ECL is disposed on the organic light emitting layer EML. Although not separately illustrated, the electronic control layer ECL may be formed in common with the plurality of pixels PX (see FIG. 4B).

The cathode CE is disposed on the electronic control layer ECL. The cathode CE is commonly disposed in the plurality of pixels PX.

The thin film encapsulation layer TFE is disposed on the cathode CE. The thin film encapsulation layer TFE is commonly disposed in the plurality of pixels PX. The thin film encapsulation layer TFE includes at least one inorganic layer and at least one organic layer. The thin film encapsulation layer TFE may include a plurality of inorganic layers and a plurality of organic layers that are alternately stacked. In one embodiment of the present invention, the thin film encapsulation layer TFE may directly cover the cathode CE.

7A to 7C are cross-sectional views of thin film encapsulation layers TFE1, TFE2, and TFE3 according to an embodiment of the present invention. Hereinafter, the thin film encapsulation layers TFE1, TFE2, and TFE3 according to one embodiment of the present invention will be described with reference to FIGS. 7A to 7C.

As shown in FIG. 7A, the thin film encapsulation layer TFE1 may include n inorganic thin films IOL1 to IOLn including the first inorganic thin film IOL1 contacting the cathode CE (see FIG. 6A). .

The first inorganic thin film IOL1 may be defined as a lower inorganic thin film, and inorganic thin films other than the first inorganic thin film IOL1 among the n inorganic thin films IOL1 to IOLn may be defined as upper inorganic thin films.

The thin film encapsulation layer TFE1 includes n-1 organic thin films OL1 to OLn-1, and the n-1 organic thin films OL1 to OLn-1 are n inorganic thin films IOL1 to IOLn. It can be arranged alternately with. The n-1 organic thin films OL1 to OLn-1 may have a larger thickness than the n inorganic thin films IOL1 to IOLn on average.

Each of the n inorganic thin films IOL1 to IOLn may be a single layer including one material, or may have a plurality of layers each including a different material. Each of the n-1 organic thin films OL1 to OLn-1 may be formed by depositing organic monomers. The organic monomers may include acrylic monomers. In one embodiment of the present invention, the thin film encapsulation layer TFE1 may further include an nth organic thin film.

As shown in FIGS. 7B and 7C, the inorganic thin films included in each of the thin film encapsulation layers TFE2 and TFE3 may have the same or different inorganic materials and may have the same or different thicknesses. The organic thin films included in each of the thin film encapsulation layers TFE2 and TFE3 may have the same or different organic materials and may have the same or different thicknesses.

As shown in FIG. 7B, the thin film encapsulation layer TFE2 is sequentially stacked with the first inorganic thin film IOL1, the first organic thin film OL1, the second inorganic thin film IOL2, and the second organic thin film OL2. , And the third inorganic thin film IOL3.

The first inorganic thin film IOL1 may have a two-layer structure. The first sub layer S1 and the second sub layer S2 may include different inorganic materials.

As illustrated in FIG. 7C, the thin film encapsulation layer TFE3 may include a first inorganic thin film IOL10, a first organic thin film OL1, and a second inorganic thin film IOL20 that are sequentially stacked. The first inorganic thin film IOL10 may have a two-layer structure. The first sub layer S10 and the second sub layer S20 may include different inorganic materials. The first organic thin film OL1 may be an organic layer including a polymer, and the second inorganic thin film IOL20 may have a two-layer structure. The second inorganic thin film IOL20 may include a first sublayer S100 and a second sublayer S200 deposited in different deposition environments. The first sublayer S100 may be deposited under low power conditions, and the second sublayer S200 may be deposited under high power conditions. The first sublayer S100 and the second sublayer S200 may include the same inorganic material.

8A is a cross-sectional view of a touch sensing unit TS according to an embodiment of the present invention. 8B to 8E are plan views of the touch sensing unit TS according to the embodiment of the present invention.

As shown in FIG. 8A, the touch sensing unit TS includes a lower insulating layer TS-LIL, an intermediate insulating layer TS-MIL, a first conductive layer TS-CL1, and an upper insulating layer TS-HIL. ) And a second conductive layer TS-CL2. The lower insulating layer TS-LIL is disposed directly on the encapsulation layer TFE. The first conductive layer TS-CL1 is directly disposed on the lower insulating layer TS-LIL. However, the present invention is not limited thereto, and another inorganic layer (eg, a buffer layer) may be further disposed between the first conductive layer TS-CL1 and the lower insulating layer TS-LIL.

Each of the first conductive layer TS-CL1 and the second conductive layer TS-CL2 may have a single layer structure or may have a multilayer structure stacked along the third direction axis DR3. The multilayer conductive layer may include at least two of the transparent conductive layers and the metal layers. The conductive layer of the multilayer structure may include metal layers including different metals. The transparent conductive layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphene. The metal layer may comprise molybdenum, silver, titanium, copper, aluminum, and alloys thereof.

Each of the first conductive layer TS-CL1 and the second conductive layer TS-CL2 includes a plurality of patterns. Hereinafter, the first conductive layer TS-CL1 includes the first conductive patterns, and the second conductive layer TS-CL2 includes the second conductive patterns. Each of the first conductive patterns and the second conductive patterns may include touch electrodes and touch signal lines.

Each of the lower insulating layer TS-LIL, the intermediate insulating layer TS-MIL, and the upper insulating layer TS-HIL may include an inorganic material or an organic material. The inorganic material may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The organic material includes at least one of acrylic resin, methacryl resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin siloxane resin, polyimide resin, polyamide resin and perylene resin. can do.

Each of the lower insulating layer TS-LIL, the intermediate insulating layer TS-MIL, and the upper insulating layer TS-HIL may have a single layer or a multilayer structure. Each of the lower insulating layer TS-LIL, the intermediate insulating layer TS-MIL, and the upper insulating layer TS-HIL may have at least one of an inorganic layer and an organic layer. The inorganic layer and the organic layer may be formed by chemical vapor deposition.

The intermediate insulating layer TS-MIL is sufficient to insulate the first conductive layer TS-CL1 and the second conductive layer TS-CL2, and the shape thereof is not limited. The shape of the intermediate insulating layer TS-MIL may be changed according to the shapes of the first conductive patterns and the second conductive patterns. The intermediate insulating layer TS-MIL may cover the thin film encapsulation layer TFE as a whole or may include a plurality of insulating patterns. It is sufficient that the plurality of insulating patterns overlap the first connection parts CP1 or the second connection parts CP2 which will be described later.

In the present exemplary embodiment, the two-layer touch sensing unit is illustrated as an example, but is not limited thereto. The single layer touch sensing unit includes a conductive layer and an insulating layer covering the conductive layer. The conductive layer includes touch sensors and touch signal lines connected to the touch sensors. The tomography type touch sensing unit may acquire coordinate information by a self-cap method.

As shown in FIG. 8B, the touch sensing unit TS may include first touch signals connected to the first touch electrodes TE1-1 to TE1-5 and the first touch electrodes TE1-1 to TE1-5. Lines TL1, second touch electrodes TE2-1 to TE2-4, and second touch signal lines TL2 and first connected to the second touch electrodes TE2-1 to TE2-4. The second pad PD2 may be connected to the touch signal lines TL1 and the second touch signal lines TL2. 8B exemplarily illustrates a touch sensing unit TS including five first touch electrodes TE1-1 to TE1-5 and four second touch electrodes TE2-1 to TE2-4. However, it is not limited thereto.

Each of the first touch electrodes TE1-1 to TE1-5 may have a mesh shape in which a plurality of touch openings are defined. Each of the first touch electrodes TE1-1 to TE1-5 includes a plurality of first touch sensor parts SP1 and a plurality of first connection parts CP1. The first touch sensor parts SP1 are arranged along the second direction DR2. Each of the first connection parts CP1 connects two adjacent first touch sensor parts SP1 to which the first touch sensor parts SP1 are adjacent. Although not illustrated in detail, the first touch signal lines TL1 may also have a mesh shape.

The second touch electrodes TE2-1 to TE2-4 insulate and cross the first touch electrodes TE1-1 to TE1-5. Each of the second touch electrodes TE2-1 to TE2-4 may have a mesh shape in which a plurality of touch openings are defined. Each of the second touch electrodes TE2-1 to TE2-4 includes a plurality of second touch sensor parts SP2 and a plurality of second connection parts CP2. The second touch sensor parts SP2 are arranged along the first direction DR1. Each of the second connection parts CP2 connects two second touch sensor parts SP2 adjacent to each other. The second touch signal lines TL2 may also have a mesh shape.

The first touch electrodes TE1-1 to TE1-5 and the second touch electrodes TE2-1 to TE2-4 are electrostatically coupled. As touch sensing signals are applied to the first touch electrodes TE1-1 to TE1-5, capacitors are formed between the first touch sensor parts SP1 and the second touch sensor parts SP2.

The plurality of first touch sensor parts SP1, the plurality of first connection parts CP1, the first touch signal lines TL1, the plurality of second touch sensor parts SP2, and the plurality of second connection parts ( CP2 and some of the second touch signal lines TL2 are formed by patterning the first conductive layer TS-CL1 shown in FIG. 8A, and others are formed by patterning the second conductive layer TS shown in FIG. 8A. -CL2) can be formed by patterning.

In order to electrically connect the conductive patterns disposed on the other layer, a contact hole penetrating the intermediate insulating layer TS-MIL shown in FIG. 8A may be formed. Hereinafter, the touch sensing unit TS according to an embodiment will be described with reference to FIGS. 8C to 8E.

As illustrated in FIG. 8C, first conductive patterns are disposed on the lower insulating layer TS-LIL. The first conductive patterns may include bridge patterns CP1. Bridge patterns CP1 are directly disposed on the lower insulating layer TS-LIL. The bridge patterns CP1 correspond to the second connection parts CP2 shown in FIG. 8B.

As shown in FIG. 8D, an intermediate insulating layer TS-MIL covering the bridge patterns CP1 is disposed on the lower insulating layer TS-LIL. In the intermediate insulating layer TS-MIL, touch contact holes TCH that partially expose the bridge patterns CP1 are defined. Touch contact holes TCH may be formed by a photolithography process.

As shown in FIG. 8E, second conductive patterns are disposed on the first touch insulating layer TS-IL1. The second conductive patterns include a plurality of first touch sensor parts SP1, a plurality of first connection parts CP1, first touch signal lines TL1, a plurality of second touch sensor parts SP2, and a second. The touch signal lines TL2 may be included. Although not separately illustrated, an upper insulating layer TS-HIL covering the second conductive patterns is disposed on the intermediate insulating layer TS-MIL.

In another embodiment of the present invention, the first conductive patterns may include first touch electrodes TE1-1 to TE1-5 and first touch signal lines TL1. The second conductive patterns may include second touch electrodes TE2-1 to TE2-4 and second touch signal lines TL2. In this case, the contact holes CH are not defined in the first touch insulating layer TS-IL1.

Also, in one embodiment of the present invention, the first conductive patterns and the second conductive patterns may be interchanged. In other words, the second conductive patterns may include bridge patterns CP1.

FIG. 8F is a partially enlarged view of the AA region of FIG. 8E.

As shown in FIG. 8F, the first touch sensor unit SP1 overlaps the non-light emitting area NPXA. The first touch sensor part SP1 may include a plurality of first extension parts SP1 -A and a fifth direction extending in a fifth direction DR5 crossing the first direction DR1 and the second direction DR2. The plurality of second extensions SP1-B extend in the sixth direction DR6 crossing the DR5. The plurality of first extensions SP1 -A and the plurality of second extensions SP1 -B may be defined by mesh lines. The line width of the mesh line may be several microns.

The plurality of first extensions SP1 -A and the plurality of second extensions SP1 -B are connected to each other to form a plurality of touch openings TS-OP. In other words, the first touch sensor unit SP1 has a mesh shape having a plurality of touch openings TS-OP. Although the touch openings TS-OP correspond to the emission areas PXA in one-to-one correspondence, the touch openings TS-OP are not limited thereto. One touch opening TS-OP may correspond to two or more light emitting regions PXA.

The size of the light emitting regions PXA may vary. For example, the sizes of the light emitting regions PXA providing the blue light and the light emitting regions PXA providing the red light may be different among the light emitting regions PXA. Therefore, the sizes of the touch openings TS-OP may also vary. In FIG. 8F, the light emitting regions PXA vary in size, but the present invention is not limited thereto. The size of the emission regions PXA may be the same, and the sizes of the touch openings TS-OP may also be the same.

Since the information about the first touch sensor unit SP1 may be applied to the second touch sensor unit SP2, the description of the second touch sensor unit SP2 will be omitted.

The touch sensing unit has been described above, and the dam and the bank will be described with reference to FIGS. 8B and 8E.

8B and 8E, the dam DAM is disposed on a non-display area (hereinafter referred to as a peripheral area) of the base layer SUB (hereinafter referred to as a substrate). In more detail, the dam DAM may have a closed loop shape on a plane and surround the display area. However, the shape of the dam DAM is not limited thereto and may be modified in various shapes. The dam DAM may be plural. For example, a plurality of dams DAM surrounding the display area and spaced apart from each other may be disposed in the peripheral area NDA.

The bank BAK is disposed in the peripheral area NDA of the substrate SUB adjacent to the dam DAM. The bank BAK is disposed between the second pad PD2 and the dam DAM. In more detail, the bank BAK may have a bar shape on a plane, but is not limited thereto and may be variously modified.

The first touch signal lines TL1, TL1 and the second touch signal lines TL2, TL2 extend to be disposed on the dam DAM and the bank BAK and are connected to the second pad PD2. The dam DAM and the bank BAK will be described in detail with reference to FIGS. 9 to 11.

9 is a cross-sectional view taken along the line AA ′ of FIG. 8E. FIG. 10A is a cross-sectional view taken along the line BB ′ of FIG. 8E. 10B is a cross-sectional view of a bank BAK according to another embodiment of the present invention. FIG. 11 is a perspective view of a portion of the bank BAK. Referring to FIGS. 9 through 11, the dam DAM may include an upper portion DAMU and a lower portion DAMD. The upper portion DAMU is disposed on the lower portion DAMD. In more detail, the upper portion DAMU may be disposed in contact with the upper surface of the lower portion DAMD. The lower portion DAMD may be formed by the same process as the third insulating layer 30 (see FIG. 6A). That is, the lower portion DAMD may be disposed on the same layer as the third insulating layer 30. The lower portion DAMD may be an organic layer and / or an inorganic layer. In particular, the lower portion DAMD may comprise an organic material to provide a flat surface.

The upper portion DAMU may be formed by the same process as the pixel defining layer PDL. That is, the upper portion DAMU may be disposed on the same layer as the pixel defining layer PDL. The upper portion DAMU may comprise an organic material. For example, the upper portion DAMU may include an organic material such as polyimide.

The dam DAM may have a combination of a lower portion DAMD and an upper portion DAMU in a protruding shape on a cross section. The dam DAM may function to control the flow of the organic thin film material formed inside the encapsulation layer TFE. For example, when the encapsulation layer TFE illustrated in FIG. 9 is the encapsulation layer TFE3 illustrated in FIG. 7C, the dam DAM may control the flow of monomers of the first organic thin film OL1. The movement of the first organic thin film OL1 in the first direction DR1 may be controlled by the dam DAM. Therefore, the first inorganic thin film IOL10 of the encapsulation layer TFE may be directly disposed on the dam DAM, and the second inorganic thin film IOL20 may be directly disposed on the first inorganic thin film IOL.

The bank BAK may be disposed at a predetermined distance from the dam DAM in the first direction DR1. The bank BAK includes a first bank part BANK1, a boundary BOR, and a second bank part BANK2. The boundary BOR is disposed between the first bank part BANK1 and the second bank part BANK2.

The first bank part BANK1 may include an upper part BU and a lower part BD. The upper portion BU is disposed on the lower portion BD. In more detail, the upper portion BU may be disposed in contact with the upper surface of the lower portion BD. The lower portion BD may be formed by the same process as the third insulating layer 30 (see FIG. 6A). That is, the lower part BD may be disposed on the same layer as the third insulating layer 30. The lower portion BD may be an organic layer and / or an inorganic layer. In particular, the lower portion BD may comprise an organic material to provide a flat surface.

The upper portion BU may be formed by the same process as the pixel defining layer PDL. The upper portion BU may be disposed on the same layer as the pixel defining layer PDL. The upper portion BU may include a portion corresponding to the pixel defining layer PDL and a spacer SPC. The spacer SPC may be formed at the same time as a portion corresponding to the pixel defining layer PDL. In an example, the spacer SPC may be disposed on the pixel defining layer PDL. That is, the first bank BANK1 may have a height greater than that of the dam DAM. The upper portion BU may include an organic material. For example, the upper portion BU may include an organic material such as polyimide.

 The boundary BOR may also include an upper portion BRU and a lower portion BRD, similarly to the first bank portion BANK1. The rest of the description is the same as that of the first bank part BANK1 and will be omitted.

The second bank part BANK2 may be formed by the same process as the third insulating layer 30. That is, the second bank part BANK2 may be disposed on the same layer as the third insulating layer 30. The second bank part BANK2 may be an organic layer and / or an inorganic layer.

The boundary BOR may be provided in plurality. The second bank part BANK2 may be disposed between two adjacent boundary parts BOR among the boundary parts BOR. The height of the second bank part BANK2 may be smaller than the height of the first bank part BANK1 and the boundary BOR.

As a result, the lower part BD of the first bank part BANK1, the lower part BRD of the boundary BOR, and the second bank part BANK2 may be integrally formed.

As the second bank part BANK2 and the boundary BOR are formed, the bank BAK is formed by the scratches generated by the mask in the process of supporting the mask used to form the encapsulation layer TFE. BAK) It is possible to prevent a poor patterning of the touch signal line generated on the upper surface.

12A to 12G illustrate a process of forming the first capping pattern CAP1 on the bank BAK.

As shown in FIG. 12A, a lower insulating layer TS-LIL may be formed on the bank BAK. The lower insulating layer TS-LIL may be formed on the bank BAK through a deposition process.

As shown in FIG. 12B, an intermediate insulating layer TS-MIL may be formed on the lower insulating layer TS-LIL through a deposition process.

As illustrated in FIG. 12C, a conductive layer CODL to be formed of the first capping pattern CAP1 and touch signal lines TL1 and TL2, which will be described later, may be formed on the intermediate insulating layer TS-MIL. The conductive layer CODL may be formed on the intermediate insulating layer TS-MIL through a deposition process. The conductive layer CODL may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphene. The conductive layer CODL may include a metal layer such as molybdenum, silver, titanium, copper, aluminum, or an alloy thereof.

Referring to FIG. 12D, a photoresist layer PRE may be formed on the conductive layer CODL, except for portions in which the first capping pattern CAP1 and the touch signal lines TL1 and TL2 are to be formed. This can be exposed.

Referring to FIG. 12E, an etching process may be performed on the conductive layer CODL corresponding to the exposed portion ELA. For example, the conductive layer CODL corresponding to the exposed portion ELA may be etched through a dry etching process.

Referring to FIG. 12F, after the etching process is performed, the photoresist layer PRE may be removed through a strip process. The photoresist layer PRE may be removed to form a first capping pattern CAP1 between the intermediate insulating layer TS-MIL and the upper insulating layer TS-HIL corresponding to the boundary BOR. The first touch signal lines TL1 and the second touch signal lines TL2 may be formed between the middle insulating layer TS-MIL and the upper insulating layer TS-HIL corresponding to the bank part BANK2. have.

10A, 11, and 12F, the intermediate insulating layer TS-MIL and the upper insulating layer TS-HIL are covered to cover the first capping pattern CAP1 and the touch signal lines TL1 and TL2. Can be formed on. The upper insulating layer TS-HIL may be formed on the intermediate insulating layer TS-MIL through a deposition process.

As the first capping pattern CAP1 is formed corresponding to the boundary portion BOR, the organic material inside the bank BAK leaks due to insufficient thickness of the photoresist layer PRE formed on the boundary portion BOR. It is possible to prevent the occurrence of a phenomenon such as film lifting as a result.

In addition, as illustrated in FIG. 10B, the first capping pattern CAP1 ′ is disposed between the intermediate insulating layer TS-MIL and the upper insulating layer TS-HIL corresponding to the first bank part BANK1 and the boundary BOR. The first capping pattern CAP1 is not limited thereto and may be modified in various shapes. For example, in the exemplary embodiment of the present invention, the touch signal lines TL1 and TL2 and the first capping pattern CAP1 are formed on the intermediate insulating layer TS-MIL. The signal lines TL1 and TL2 may also be formed on the lower insulating layer TS-LIL. In this case, the first capping pattern CAP1 may include the lower insulating layer TS-LIL and the intermediate insulating layer TS. -MIL) may be formed.

13A to 13C are plan views illustrating another embodiment of the present invention. 14 is a cross-sectional view for explaining another embodiment of the present invention.

As shown in FIG. 13A, dummy lines DUL may be disposed on the lower insulating layer TS-LIL. The dummy lines DUL may overlap the touch signal lines TL1 and TL2 shown in FIG. 8E. Each of the dummy lines DUL may be connected in parallel with each of the touch signal lines TL1 and TL2 described above to increase the sensing sensitivity of the touch by reducing the resistance of the line through which the signal is transmitted.

Since the method of forming the dummy lines DUL is the same as the method of forming the touch signal lines TL1 and TL2 described above, a description thereof will be omitted.

As illustrated in FIG. 13B, dummy contact holes DCH exposing the touch signal lines TL1 and TL2 may be defined in the intermediate insulating layer TS-MIL. The dummy contact holes DCH may be formed by a photolithography process. Each of the dummy lines DUL of FIG. 13A may be connected in parallel with each of the touch signal lines TL1 and TL2 by the dummy contact holes DCH.

As shown in FIG. 13C, since the dummy lines DUL overlap the touch signal lines TL1 and TL2, after the first touch signal lines TL1 and the second touch signal lines TL2 are formed. It may not be shown on the plane. Each of the dummy lines DUL may be connected to the second pad PD2 'to which the corresponding touch signal lines TL1 and TL2 are connected.

Referring to FIG. 14, a second capping pattern CAP2 may be disposed between the lower insulating layer TS-LIL and the intermediate insulating layer TS-MIL corresponding to the boundary portion BOR, and the second bank portion ( The dummy lines DUL may be disposed between the lower insulating layer TS-LIL and the intermediate insulating layer TS-MIL corresponding to BANK2. The second capping pattern CAP2 and the dummy lines DUL may be formed by the same process, and the forming process may be the same as that of forming the first capping pattern CAP1 and the touch signal lines TL1 and TL2. Omit the bar.

By forming the second capping pattern CAP2, the above-described poor phenomenon such as lifting of the film can be prevented.

Although the dummy lines DUL are described as being disposed on the lower insulating layer TS-LIL and the intermediate insulating layer TS-MIL, they may be variously modified. For example, the touch signal lines TL1 and TL2 may be disposed on the lower insulating layer TS-LIL and the intermediate insulating layer TS-MIL, and the dummy lines DUL may be the intermediate insulating layer TS. -MIL and the upper insulating layer (TS-HIL) may be disposed.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art or those skilled in the art without departing from the spirit and scope of the invention described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the scope thereof.

Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

TS-LIL: Lower insulation layer BAK: Bank
TS-MIL: intermediate insulation layer BANK2: second bank portion
TS-HIL: Upper insulation layer CAP1: First capping pattern

Claims (13)

A base layer including a first region and a second region;
Light emitting devices disposed on the first region of the base layer;
An encapsulation layer sealing the light emitting elements;
Sensors disposed on the encapsulation layer;
Pads disposed on the second region of the base layer and arranged along a first direction;
Signal wires electrically connected to the sensors and the pads, respectively; And
A sublayer disposed on the second region of the base layer, disposed between the sensors and the pads, and extending in the first direction;
The sub layer includes a first layer and a second layer disposed on the first layer, and when viewed in plan view, the second layer is non-overlapping with the signal lines. According to claim 1,
The display device of claim 1, wherein one area of the second layer is removed and the signal lines are removed. The display device of claim 1, wherein the signal lines extend in a second direction crossing the first direction. According to claim 1,
And each of the sensors is electrostatically coupled to other adjacent sensors. According to claim 1,
The sensors detect an external input in a capacitive manner. According to claim 1,
And a first capping pattern disposed on the second layer of the sub layer. The method of claim 6,
And a first insulating layer covering the sensors, the signal lines, the sub layer, and the first capping pattern. The method of claim 6,
Dummy wires overlapping the signal wires; And
And a second capping pattern overlapping the first capping pattern. The method of claim 8,
The dummy wires are disposed under the signal wires, and the second capping pattern is disposed under the first capping pattern. The method of claim 9,
And a second insulating layer disposed between the dummy lines and the signal lines and between the second capping pattern and the first capping pattern. According to claim 1,
And a protrusion disposed on the second area of the base layer and surrounding at least a portion of the sensors, wherein at least a portion of the protrusion is disposed between the sub layer and the sensors. A base layer including a first region and a second region defined outside of the first region;
An element layer including light emitting elements and disposed on the first region of the base layer;
An encapsulation layer covering the device layer;
An input sensing unit including electrodes disposed on the encapsulation layer, an insulating layer disposed on the encapsulation layer, and signal wires electrically connected to the electrodes;
A sublayer disposed over the second region and including a first region having a first thickness and a second region having a second thickness smaller than the first thickness and overlapping the signal lines; And
And a capping pattern disposed on a boundary between the first region and the second region, wherein the signal lines and the capping pattern are covered by the insulating layer. A base layer including a first region and a second region defined outside of the first region;
An element layer including light emitting elements disposed on the first region of the base layer;
An encapsulation layer covering the device layer;
An input sensing unit including an insulating layer disposed on the encapsulation layer, electrodes disposed on the encapsulation layer, and signal wires electrically connected to the electrodes; And
A sublayer disposed over the second region and including a first region having a first thickness and a second region having a second thickness less than the first thickness and overlapping the signal lines;
The signal lines extend in a first direction, and the sub layer extends in a second direction crossing the first direction.

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