KR20190091251A - method of manufacturing printed circuit board for dial switch - Google Patents

Abstract

According to an embodiment of the present invention, a method of manufacturing a printed circuit board for a dial switch, in a method of manufacturing a printed circuit board for a dial switch in which a dial knob is in contact with one surface, includes: a one-side circuit forming step of forming a first circuit pattern in which conductor circuits are spaced apart at intervals on one surface of the base substrate opposite to the dial knob; a both-side circuit stacking step of stacking a dummy layer on the first circuit pattern and stacking a second circuit pattern on the other surface of the base substrate; a one-side polishing step of maintaining the second circuit pattern and polishing and removing the dummy layer, to expose the first circuit pattern; and a plating step of forming a plating layer for electrical connection on the conductor of the first circuit pattern and the second circuit pattern. It is possible to smoothly manufacture the surface of the printed circuit board which is in contact with the dial knob.

Description

Method of manufacturing printed circuit board for dial switch

The present invention relates to a method for manufacturing a printed circuit board for a dial switch, and more particularly, to smoothly manufacture a surface of a printed circuit board that is in contact with the dial knob so that the operation precision and operation degree are improved when the dial switch is rotated. The present invention relates to a method for manufacturing a printed circuit board for a dial switch.

The dial switch allows the user to rotate the dial knob 1 so that the mechanical and electronic devices can be controlled to a desired value. In general, a panel part 2 in which characters are displayed as shown in FIGS. The panel unit 2 is rotatably provided in the dial knob 1 to be rotated by the user by hand, and the printed circuit board 3 receiving the generated signal according to the rotation of the dial knob 1 and sending it to an external control system. And a rotating shaft 4 provided on the printed circuit board 3 to rotate the dial knob 1.

Here, the digital dial switch has an encoder installed on the rotating shaft, and reads the degree of rotation of the dial knob 1 from the encoder and sends it to the controller, so that the user can send an accurate signal close to the desired signal to the controller. It is more expensive than analog because it requires additional encoder.

In the analog dial switch, as shown in FIGS. 1 and 2, a resistor 6 is provided at the dial knob 1, and a resistor 6 of the dial knob 1 is provided at one side of the printed circuit board 3. A conductor circuit 7 in contact with is provided.

In the case of the analog system, when the user rotates the dial knob 1, the conductor circuit 7 of the printed circuit board 3 reads a resistance value which is changed according to the degree of rotation of the dial knob 1, and the user desires a signal. Since it is sent to the external control system through the wire (5), there is an advantage that the manufacturing cost is cheap because there is no need for the encoder on the rotating shaft, it is still used in military products or mass production that requires a reduction in manufacturing cost.

As shown in FIG. 2, a typical printed circuit board 3 used for an analog dial switch has a conductor circuit 7 of the printed circuit board 3 having a thickness of about 60 μm from the surface of the printed circuit board 3. Protruding to the height (l) to form the irregularities with the step of the surface of the printed circuit board (3).

Therefore, in the case of the analog system in which the contact between the conductor circuit 7 of the printed circuit board 3 and the resistance of the dial knob 1 directly occurs, the surface of the printed circuit board 3 and the unevenness of the conductor circuit 7 are generated. Due to the step difference, the operation precision is lowered, irregular operation feeling due to the step is also generated.

Therefore, in the case of the analog method, a method of manufacturing a printed circuit board for a dial switch that can improve operation accuracy and generate a certain feeling of operation by eliminating or minimizing a step between the surface of the conductor circuit 7 and the printed circuit board 3 is minimized. This is necessary.

The problem to be solved by the present invention is to provide a method of manufacturing a printed circuit board for a dial switch that can smoothly manufacture the surface of the printed circuit board in contact with the dial knob so that the operation accuracy and operation degree when the dial switch is rotated. It is.

The objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a method for manufacturing a dial switch printed circuit board according to an embodiment of the present invention, wherein the dial knob is in contact with one surface of the dial switch printed circuit board. A one side circuit forming step of forming a first circuit pattern in which conductor circuits are disposed on one surface of a substrate to form a spaced interval; Stacking a dummy layer on the first circuit pattern and stacking a second circuit pattern on the other surface of the base substrate; A surface polishing step of exposing the first circuit pattern by maintaining the second circuit pattern and polishing and removing the dummy layer; And a plating step of forming a plating layer for electrical connection on the conductor circuit and the second circuit pattern of the first circuit pattern. It includes.

Further, in the double-sided circuit lamination step, a prepreg is filled in the separation interval formed by the conductor circuit of the first circuit pattern, and in the one-side polishing step, the height of the conductor circuit is formed lower than the height of the prepreg. Can be.

In addition, the resistor unit provided in the dial knob may contact the plating layer of the first circuit pattern.

In addition, an electric wire may be connected to the plating layer of the second circuit pattern.

The double-sided circuit laminating step may include a prepreg stacking step of stacking prepregs on the other surface of the base substrate and at a spaced interval formed by the conductor circuit of the first circuit pattern; Copper foil lamination step of laminating the copper foil on both sides of the prepreg; A pressurized heating step of pressurizing and heating the copper foil laminated on both surfaces; A via hole forming step of forming a via hole penetrating the copper foil stacked on both surfaces; An electroless copper plating layer forming step of forming an electroless copper plating layer on the copper foil and the via hole; A second surface circuit forming step of processing the electroless copper plating layer formed on the other surface of the base substrate into an electric circuit and maintaining the electroless copper plating layer stacked on the first circuit pattern; And forming an electrolytic copper plating layer in electrical communication with the first circuit pattern and the electric circuit, thereby forming the second circuit pattern on the other surface of the base substrate and forming the dummy layer on the first circuit pattern. Copper plating layer forming step; It may include.

In the polishing of the one surface, the dummy layer may be polished to expose the conductor circuit of the first circuit pattern and the prepreg filled in the separation interval.

In addition, in the one-side polishing step, the height of the conductor circuit of the first circuit pattern may be lower than the height of the prepreg filled in the separation interval.

In addition, a height difference between the height of the conductor circuit and the prepreg may be 5.03 μm to 8.06 μm.

In addition, the plating layer in the plating step, the nickel plating layer laminated to a height of 5μm ~ 8μm on the conductor circuit of the first circuit pattern; And a gold plating layer laminated on the nickel plating layer at a height of 0.03 μm to 0.06 μm. It may include.

In addition, the dummy layer may include the prepreg, the copper foil, the electroless copper plating layer, and the electrolytic copper plating layer.

Specific details of other embodiments are included in the detailed description and the drawings.

According to the manufacturing method of the printed circuit board for dial switch according to an embodiment of the present invention, the plating layer formed on the surface of the conductor circuit of the first circuit pattern forms the same plane as the adjacent prepreg to form a smooth surface without step As a result, the surface of one surface of the printed circuit board in contact with the dial knob can be manufactured smoothly.

In addition, the printed circuit board manufactured according to the manufacturing method of the dial switch printed circuit board according to the embodiment of the present invention, since the surface of one surface is formed smoothly does not cause irregularities, the contact with one surface of the printed circuit board When the dial knob is rotated, the operation precision can be improved and a certain feeling of operation can be generated.

The effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a front view of a general dial switch.
2 is a sectional view of an analog dial switch according to the prior art.
Figure 3 is a flow chart of a manufacturing method of a printed circuit board for a dial switch according to an embodiment of the present invention.
4 is a diagram illustrating a dial switch printed circuit board manufactured according to a procedure of a method of manufacturing a dial switch printed circuit board according to an embodiment of the present invention.
5 is a perspective view of an analog dial switch using a printed circuit board for dial switch according to an embodiment of the present invention.
6 is a cross-sectional view of an analog dial switch using a printed circuit board for dial switch according to an embodiment of the present invention.
7 is a flowchart of a double-sided circuit lamination step according to an embodiment of the present invention.
8 is a diagram illustrating a printed circuit board for a dial switch manufactured according to the order of a double-sided circuit lamination step according to an embodiment of the present invention.
9 is a cross-sectional view of a dial switch printed circuit board manufactured according to a method of manufacturing a dial switch printed circuit board according to an exemplary embodiment of the present invention.

In describing the present invention, when it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Even if the terms are the same, if the displayed portions are different, it is to be noted that the reference numerals do not match.

The terms to be described below are terms set in consideration of functions in the present invention, and may be changed according to the intention or custom of an operator such as an experimenter and a measurer, and the definitions thereof should be made based on the contents throughout the present specification.

In this specification, terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. A singular expression includes a plural expression unless the context clearly indicates otherwise.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

In addition, when a part is said to "include" a certain component, this means that it may further include other components, except to exclude other components unless otherwise stated.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

Figure 3 is a flow chart of a manufacturing method of a dial switch printed circuit board according to an embodiment of the present invention, Figure 4 is manufactured in accordance with the order of the manufacturing method of a printed circuit board for a dial switch according to an embodiment of the present invention FIG. 5 is a diagram illustrating a dial switch printed circuit board, FIG. 5 is a perspective view of a dial switch using a dial switch printed circuit board according to an embodiment of the present invention, and FIG. 6 is a dial according to an embodiment of the present invention. A cross-sectional view of a dial switch using a printed circuit board for switches.

3 to 6, a method for manufacturing a printed circuit board for a dial switch according to an embodiment of the present invention includes a dial in the method for manufacturing a printed circuit board for dial switches in which the dial knob 1 is in contact with one surface thereof. One-side circuit forming step (S10) of forming a first circuit pattern 20 in which the conductor circuit 21 is formed by forming a spaced gap 23 on one surface of the base substrate 10 opposite to the knob 1. The double-sided circuit lamination step S20 of stacking the dummy layer d on the first circuit pattern 20 and the second circuit pattern 50 on the other surface of the base substrate 10, and the second circuit pattern 50 is present. And polishing the dummy layer d to expose the first circuit pattern 20 (S30), and the plating layer 80 for electrical connection to the first circuit pattern 20 and the second circuit pattern 50. Plating step (S50) to form a.

In one surface circuit forming step (S10), the first circuit pattern 20 is formed on the base substrate 10. Here, the first circuit pattern 20 includes a space 23 formed by the conductor circuit 21 and the conductor circuit 21.

First, the base substrate 10 is a copper clad laminate (CCL) in which copper foil is laminated on both sides of the base surface, and the base surface may be made of paper and phenol, glass fiber and epoxy, polyamide, or a known material. . In the present invention, the base surface is a material in which a woven glass fiber and an epoxy are mixed, and a material generally referred to as FR-4 is used, but the material of the base substrate 10 is not limited thereto.

The first circuit pattern 20 is formed on one surface of the printed circuit board opposite to the dial knob 1. As shown in FIG. 6, the first circuit pattern 20 is disposed on the dial knob 1 side, and is formed on a surface of the dial knob 1 that is in contact with the resistor portion 6.

The conductor circuit 21 of the first circuit pattern 20 is arranged to form a spaced interval 23. The conductor circuit 21 is a copper foil laminated on the base substrate 10 processed into an electric circuit through a plurality of processes, and constitutes an electric circuit of a printed circuit board. The first circuit pattern 20 may be formed by a known method of manufacturing a printed circuit board.

For example, the first circuit pattern 20 according to an embodiment of the present invention corresponds to an electric circuit through a dry film (D / F) coating, a dry film exposure, and a dry film developing process on a copper foil surface. After forming the copper foil, it may be formed through an etching process and a dry film removal process of etching the copper foil that does not constitute an electrical circuit.

FIG. 4A illustrates that the first circuit pattern 20 is formed on one surface of the base substrate 10. In the first circuit pattern 20 of FIG. 4A, a solder resist (S / R) 70 for preventing oxidation is not applied to the conductor circuit 21, and the surface of the conductor circuit 21 is not applied. An oxide film 30 may be formed in the film.

In the double-sided circuit lamination step S20, the dummy layer d is stacked on the first circuit pattern 20, and the second circuit pattern 50 is laminated on the other surface of the base substrate 10. Here, the prepreg 40 is filled in the spaced interval 23 formed by the conductor circuit 21 of the first circuit pattern 20. This will be described later.

The prepreg 40 is a material in which at least one of epoxy or phenol resin is impregnated into glass fiber, and is used for stacking a plurality of circuit patterns when manufacturing a multilayer board (MLB). In the present invention, the prepreg 40 may be implemented in the form of a resin or sheet applicable to the embodiment. The prepreg 40 is pressed and heated within a predetermined temperature and pressure range to cure.

The dummy layer d is stacked on the first circuit pattern 20. In the present invention, the dummy layer d is defined as a layer stacked on the prepreg 40 filled in the conductor circuit 21 and the separation gap 23 of the first circuit pattern 20.

The dummy layer d is a secondary layer formed while the process of forming the second circuit pattern 50 on the other surface of the base substrate 10 while the first circuit pattern 20 is formed. The dummy layer d may have a base for forming the second circuit pattern 50 and electrically communicating the first circuit pattern 20 and the second circuit pattern 50 in a state where the first circuit pattern 20 is formed. It is formed in the process of processing both sides of the substrate 10.

As shown in FIG. 4B, the dummy layer d according to the exemplary embodiment of the present invention includes the oxide film 30, the prepreg 40, the copper foil 51, and the electroless layer formed on the surface of the conductor circuit 21. The copper plating layer 61 and the electrolytic copper plating layer 63 may be included. The dummy layer d is not processed into an additional circuit pattern. The dummy layer d is removed in one side polishing step S30 described later.

The second circuit pattern 50 is stacked on the other surface of the base substrate 10. The second circuit pattern S50 may include a copper foil 51, an electroless copper plating layer 61, and an electrolytic copper plating layer 63 constituting an electric circuit. The second circuit pattern 50 is in electrical communication with the first circuit pattern 20 through the via hole v. The manufacturing process of the second circuit pattern 50 will be described later.

The second circuit pattern 50 is a surface in which a plurality of wires 5 are connected through the plating layer 80 in the printed circuit board for dial switch of the present invention, and the dial knob 1 is not in contact with each other. 4B, the second circuit pattern 50 is stacked on the other surface of the base substrate 10.

In one surface polishing step S30, the second circuit pattern 50 is left and the dummy layer d is polished to expose the first circuit pattern 20.

In one polishing step (S30), the dummy layer (d) is polished and removed. In this case, the polishing processing method may be performed by sand paper polishing, turning polishing or a known polishing processing method or a combination thereof.

In general, laser processing or router processing may cause damage to the circuit pattern by transferring a heat load or a mechanical load to the first circuit pattern 20, but the polishing process may be performed relative to the first circuit pattern 20. Since the load is not transmitted, the first circuit pattern 20 may be protected when the dummy layer d is removed, and the prepreg filled in the conductor circuit 21 and the separation gap 23 of the first circuit pattern 20 may be protected. The surface of 40 can be made as smooth as possible.

In one surface polishing step (S30), since the dummy layer (d) is polished and removed, the first circuit pattern 20 is exposed to the outside. In this case, the prepreg 40 filled in the conductor circuit 21 and the separation interval 23 of the first circuit pattern 20 is exposed.

According to one embodiment of the present invention, the height h2 of the conductor circuit 21 may be formed lower than the height h1 of the prepreg 40 in one surface polishing step S30. In this case, during the polishing process, the conductor circuit 21 is further polished and processed to a lower height than the prepreg 40.

In FIG. 4C, the dummy layer d is removed. 4 (c) shows that the conductor circuit 21 is formed slightly lower than the height of the prepreg 40, according to one embodiment of the invention. This will be described later with reference to FIG. 9.

In one surface polishing step S30, the second circuit pattern 50 is present. The second circuit pattern 50 is connected to a plurality of wires 5 for the electrical connection. In the second circuit pattern 50, the plating layer 80 for electrical connection is formed through the solder resist processing step S40 and the plating step S50 described later.

In the solder resist processing step (S40), after applying a solder resist (S / R) 70 to the polished printed circuit board, only the electrical connection portion is exposed and developed to be exposed.

When the solder resist of the electrical connection is developed and removed, a portion of the conductor circuit 21 and the second circuit pattern 50 of the first circuit pattern 20 for the electrical connection may be exposed. 4 (c) shows that the solder resist 70 is processed on the printed circuit board.

In the plating step S50, the plating layer 80 for electrical connection is formed on the first circuit pattern 20 and the second circuit pattern 50. In the plating step (S50), the plating layer 80 on the exposed portion for the electrical connection of the conductor circuit 21 and the second circuit pattern 50 of the first circuit pattern 20 exposed through the solder resist processing step (S40). ).

In this case, in the state where the height of the conductor circuit 21 of the first circuit pattern 20 is slightly lower than the height of the prepreg 40 according to one embodiment of the present invention, the plating layer 80 is a conductor circuit. Filled by the height difference of the height of the 21 and the prepreg (40).

Accordingly, since the height difference between the conductor circuit 21 and the prepreg 40 on which the plating layer 80 is formed is eliminated, the plating layer 80 formed on the surface of the conductor circuit 21 is coplanar with the adjacent prepreg 40. To form a smooth surface without a step between the conductor circuit 21 and the prepreg 40, and finally, the surface of one surface of the printed circuit board facing the dial knob 1 is smoothly manufactured. . 4 (d) shows a printed circuit board on which a plating layer 80 is formed to have a smooth surface.

In the routing step S60, the edge of the printed circuit board is cut into the designed shape. 4 (e) shows a printed circuit board manufactured according to an embodiment of the present invention in which the rim is circularly processed.

5 and 6 illustrate that a printed circuit board for a dial switch manufactured according to an embodiment of the present invention is used for an analog dial switch.

The analog dial switch has a structure in which the resistance part 6 of the dial knob 1 is in direct contact with one surface of a printed circuit board to generate a control signal, as described above in the related art. In the plating layer 80 of the first circuit pattern 20 according to the exemplary embodiment of the present invention, the resistor unit 6 provided on the dial knob 1 is in contact with the plating layer 80 of the second circuit pattern 50. One or more wires 5 are connected to the outside.

The dial knob 1 of the dial switch is coupled to the rotating shaft 4 disposed through the printed circuit board. The dial knob 1 is provided with a resistor 6 for contacting the plating layer 80 of the first circuit pattern 20 to generate a control signal.

Here, when the dial knob 1 in contact with the plating layer 80 of the first circuit pattern 20 is rotated about the rotation shaft 4, there is no step between the conductor circuit 21 and the prepreg 40. Since a smooth surface is rotated in close contact with one surface of the printed circuit board, there is no problem that the operation accuracy is lowered when a step is generated, and a constant feeling of operation occurs.

7 is a flowchart of a double-sided circuit lamination step (S20) according to an embodiment of the present invention, Figure 8 is a dial switch for printing manufactured in the order of the double-sided circuit lamination step (S20) according to an embodiment of the present invention 9 is a diagram illustrating a circuit board, and FIG. 9 is a cross-sectional view of a dial switch printed circuit board manufactured according to a method of manufacturing a dial switch printed circuit board, according to an exemplary embodiment.

A method of manufacturing a printed circuit board for a dial switch according to embodiments of the present invention will be described in more detail with reference to FIGS. 7 to 9. The following description mainly focuses on the differences from the above-described components, and replaces the above description unless otherwise specified.

In the double-sided circuit lamination step (S20) according to the exemplary embodiment of the present invention, the prepreg 40 is formed on the other surface of the base substrate 10 and the spaced gap 23 formed by the conductor circuit 21 of the first circuit pattern 20. ) Prepreg lamination step (S21) of laminating, copper foil lamination step (S22) of laminating copper foil 51 on both sides of the prepreg 40, pressurized heating step of pressing and heating the copper foil 51 laminated on both sides (S23), a via hole forming step of forming a via hole (v) penetrating through the copper foils 51 stacked on both surfaces, and an electroless copper plating layer 61 forming an electroless copper plating layer 61 on the copper foil 51 and the via hole (v). In the step of forming the copper plating layer (S25), the electroless copper plating layer 61 formed on the other surface of the base substrate 10 is processed into an electric circuit and the electroless copper plating layer 61 laminated on the first circuit pattern 20 is The other surface circuit forming step (S26) to be maintained and the electrolytic copper plating layer 63 which electrically connects the first circuit pattern 20 and the electric circuit are formed to form the base substrate 10. The other surface to a second circuit pattern including a copper plated layer forming step (S27) of forming the electrolyte 50 to form a first circuit pattern to dummy layer (d) on a 20 in.

The prepreg stacking step S21 may be performed on one or more of the separation interval 23 formed by the conductor circuit 21 of the first circuit pattern 20, the surface of the conductor circuit 21, or the other surface of the base substrate 10. The step of applying the legs 40 and laminating.

The prepreg 40 is stacked on the other surface of the first circuit pattern 20 and the base substrate 10 in the process of machining both sides of the base substrate 10 to form the second circuit pattern 50 as described above. do. In this process, the prepreg 40 is applied to both the surface of the conductor circuit 21 of the first circuit pattern 20 and the spaced gap 23 formed by the conductor circuit 21. FIG. 8A illustrates that the prepreg 40 is stacked on the other surface of the first circuit pattern 20 and the base substrate 10.

Copper foil lamination step (S22) is a step of laminating the copper foil 51 on both sides of the prepreg (40). The copper foil 51 is laminated on both the first circuit pattern 20 and the other surface side of the base substrate 10. In order to pressurize and harden the prepreg 40 stacked on both surfaces in the pressure heating step S23 to be described later, the copper foil 51 is laminated on both surfaces of the base substrate 10.

The copper foil 51 disposed on the other surface of the base substrate 10 is processed into the second circuit pattern 50. FIG. 8B shows that copper foils 51 are laminated on both surfaces of the prepreg 40. In addition, the copper foil 51 laminated on the first circuit pattern 20 forms the above-described dummy layer d.

Pressurized heating step (S23) is a step of pressing and heating the copper foil 51 laminated on both sides based on the base substrate 10. In the pressure heating step (S23), the copper foil 51 is pressurized and heated for 150 ~ 200 ℃, 20 ~ 25kg / cm ² , 1 ~ 2 hours.

When the copper foil 51 is pressurized and heated, the prepreg 40 is hardened so that it may have a certain strength. 8 (c) shows that the copper foil 51 is pressurized and heated according to the pressurized heating step S23.

The via hole forming step S24 is a step of forming a via hole v passing through the copper foil 51 stacked on both surfaces. The via hole v is formed through the printed circuit board to electrically connect the first circuit pattern 20 and the second circuit pattern 50. 8 (d), a via hole v is formed.

Electroless copper plating layer forming step (S25) is a step of forming an electroless copper plating layer 61 in the copper foil 51 and the via hole (v).

The electroless copper plating layer 61 is a seed layer for electrically connecting the first circuit pattern 20 and the second circuit pattern 50. The copper foil 51 and the via hole (v) stacked on both surfaces are laminated. Is formed. When the electrolytic copper plating layer 63 is formed on the electroless copper plating layer 61, it is electrically connected. The electroless copper plating layer 61 may be performed by a known chemical copper plating process. FIG. 8E shows that the electroless copper plating layer 61 is formed.

In the other surface circuit forming step S26, the electroless copper plating layer 61 formed on the other surface of the base substrate 10 is processed into an electrical circuit, and the electroless copper plating layer 61 stacked on the first circuit pattern 20 is formed. It is a step of honor.

As described above, the dummy layer d of the first circuit pattern 20 is polished and removed, and is not processed into a separate electric circuit. Therefore, the copper plating layer 80 stacked on the first circuit pattern 20 is left as it is.

In the other surface circuit forming step (S26), only the electroless copper plating layer 61 formed on the other surface of the base substrate 10 is processed into an electric circuit. Since the electroless copper plating layer 61 is processed into an electric circuit, a detailed description thereof will be omitted.

Electrolytic copper plating layer forming step (S27) is a step of forming an electrolytic copper plating layer 63 in electrical communication between the first circuit pattern 20 and the electrical circuit on the other surface of the base substrate 10. Since the electrolytic copper plating layer 63 may be implemented by a known electrolytic copper plating method, detailed description thereof will be omitted.

A dummy layer d is formed on the first circuit pattern 20 that has undergone the electrolytic copper plating layer forming step S27. The dummy layer d is removed in one surface polishing step S30 without forming an additional electric circuit as described above.

As described above, the dummy layer d includes the oxide film 30, the prepreg 40, the copper foil 51, and the electroless copper plating layer 61 formed on the surface of the conductor circuit 21 of the first circuit pattern 20. Or it may include one or more of the electrolytic copper plating layer (63).

The second circuit pattern 50 is formed on the other surface of the base substrate 10 on which the electrolytic copper plating layer 63 is formed. In the second circuit pattern 50, a plurality of wires 5 may be connected through the plating layer 80. In FIG. 8F, the second circuit pattern 50 and the dummy layer d which are finally formed through the electrolytic copper plating layer forming step S27 are disclosed.

After the above-described step, the surface polishing step S30 is performed.

In one surface polishing step (S30), as described above, the prepreg filled in the spaced interval 23 of the conductor circuit 21 and the conductor circuit 21 of the first circuit pattern 20 by polishing the dummy layer d may be 40). The polishing processing method may be carried out by sand paper polishing, turning polishing or a known polishing processing method or a combination thereof as described above.

Here, as shown in FIG. 9, the height h2 of the conductor circuit 21 of the first circuit pattern 20 is lower than the height h1 of the prepreg 40 filled in the separation space 23. Can be formed. In this case, as described above, the conductive circuit 21 is selectively further polished at the time of polishing, and processed to a lower height than the prepreg 40.

In this case, the difference h3 of the height h2 of the conductor circuit 21 and the height h1 of the prepreg 40 may be 5.03 μm to 8.06 μm. As described above, when the dummy layer d is polished and removed in the one-side polishing step S30, the conductor circuit 21 is polished more than the prepreg 40 so as to have a very fine height difference h3.

When the height difference is less than 5.03 μm, when the plating layer 80 is formed on the surface of the conductor circuit 21, the surface of the plating layer 80 is higher than the surface of the prepreg 40 of the first circuit pattern 20. If the step is formed, the step may occur, and if the thickness is greater than 8.06 μm, the plating layer 80 formed on the surface of the conductor circuit 21 may be formed lower than the surface of the prepreg 40 to cause the reverse step of the recessed state. Will be.

In this state, the plating step S50 is performed through the solder resist processing step S40.

In the plating step S50, the plating layer 80 is stacked on the conductor circuit 21 of the first circuit pattern 20 at a height h4 of 5 μm to 8 μm, and on the nickel plating layer 81. And a gold plating layer 83 laminated at a height h5 of 0.03 μm to 0.06 μm.

That is, in the plating step S50, the plating layer 80 is applied to the surface of the conductor circuit 21 by 5.03 μm to 8.06 μm, which is a difference between the height of the conductor circuit 21 and the prepreg 40 generated in one surface polishing step S30. Form.

The nickel plating layer 81 according to the embodiment of the present invention is formed by stacking nickel on the surface of the conductor circuit 21 at a height of 5 μm to 8 μm. If the nickel plated layer 81 is formed to be less than 5μm, the nickel plated layer may not be sufficiently formed on the surface of the copper circuit conductor 21, and if the nickel plated layer 81 is formed to be more than 8μm, cracks or bubbles may occur inside the nickel plated layer. Can be.

The gold plating layer 83 is formed by laminating gold on the nickel plating layer 81 at a height of 0.03 µm to 0.06 µm. If the gold plating layer 83 is formed to less than 0.03μm, the gold plating layer may not be sufficiently formed on the surface of the nickel plating layer 81 and may be peeled off. Can be.

Accordingly, in the present invention, the final height and the prepreg formed by the conductor circuit 21 and the plating layer 80 are compared with those of the conventional printed circuit board, in which a 60 μm high step is generated between the conductor circuit and the surface of the printed circuit board. Since the height of the 40 is formed to be the same, and the surface of the first circuit pattern 20 in contact with the dial knob 1 is formed smoothly without a step, the operation precision is improved and the operation feeling is improved.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

The scope of the present invention is indicated by the scope of the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and the equivalent concept are included in the scope of the present invention. Should be interpreted.

10: base substrate 21: conductor circuit
20: first circuit pattern 30: prepreg
80: plating layer

Claims (3)

In the manufacturing method of a printed circuit board for a dial switch, the dial knob is in contact with one surface,
A one side circuit forming step of forming a first circuit pattern in which conductor circuits are disposed on one surface of the base substrate opposite to the dial knob with a spaced interval therebetween;
Stacking a dummy layer on the first circuit pattern and stacking a second circuit pattern on the other surface of the base substrate;
A surface polishing step of exposing the first circuit pattern by maintaining the second circuit pattern and polishing and removing the dummy layer; And
A plating step of forming a plating layer for electrical connection on the conductor circuit and the second circuit pattern of the first circuit pattern; Including,
The double-sided circuit lamination step,
A prepreg stacking step of stacking prepregs on a spaced interval formed by the conductor circuit of the first circuit pattern and the other surface of the base substrate;
Copper foil lamination step of laminating the copper foil on both sides of the prepreg;
A pressurized heating step of pressurizing and heating the copper foil laminated on both surfaces;
A via hole forming step of forming a via hole penetrating the copper foil stacked on both surfaces;
An electroless copper plating layer forming step of forming an electroless copper plating layer on the copper foil and the via hole;
A second surface circuit forming step of processing the electroless copper plating layer formed on the other surface of the base substrate into an electric circuit and maintaining the electroless copper plating layer stacked on the first circuit pattern; And
An electrolytic copper plating layer is formed to electrically connect the first circuit pattern and the electric circuit, thereby forming the second circuit pattern on the other surface of the base substrate and forming the dummy layer on the first circuit pattern. Plating layer forming step; Including;
The one-step polishing step is to polish the dummy layer to expose the prepreg filled in the conductor circuit of the first circuit pattern and the spacing interval, and the height of the conductor circuit of the first circuit pattern is filled in the spacing interval. Is formed lower than the height of the legs,
The pressurized heating step is a method of manufacturing a printed circuit board for a dial switch for heating copper foil laminated on both sides based on the base substrate to 150 ~ 200 ℃.
The method of claim 1,
The method of manufacturing a printed circuit board for a dial switch, wherein the plating part of the first circuit pattern is in contact with a resistor provided in the dial knob.
The method of claim 2,
The method of manufacturing a printed circuit board for dial switch to which a wire is connected to the plating layer of the second circuit pattern.

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