KR20190088934A - Thin-film transistor substrate and method of manufacturing the same - Google Patents

Abstract

Disclosed in the present invention is a thin film transistor substrate which comprises: a base substrate; an active pattern placed on the base substrate and including a source area, a drain area, and a channel placed between the source area and the drain area; a gate insulation pattern placed on the active pattern; a gate electrode placed on the gate insulation pattern and overlapping the channel; and a light-shielding pattern placed between the base substrate and the active pattern and having a larger area than the active pattern. Therefore, the thin film transistor substrate can be used in a display device and an electronic device such as a liquid crystal display device, an organic EL display device, a circuit substrate, and semiconductor device.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a thin film transistor substrate,

The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and more particularly, to a thin film transistor substrate and a method of manufacturing the same, which can prevent reliability from being deteriorated by external light.

Generally, a thin film transistor for driving a pixel in a display device includes a gate electrode, a source electrode, a drain electrode, and a channel layer forming a channel between the source electrode and the drain electrode. The channel layer includes a semiconductor layer including amorphous silicon, poly silicon or an oxide semiconductor.

The gate electrode overlaps with the channel layer and may be formed under or over the channel layer.

However, the amorphous silicon, polycrystalline silicon, or oxide semiconductor constituting the channel layer may be deteriorated in electric characteristics due to external light. Therefore, the thin film transistor may include a light shielding layer in order to prevent the reliability of the switching element from deteriorating.

A thin film transistor substrate according to an embodiment of the present invention includes a base substrate, an active pattern disposed on the base substrate, the active pattern including a source region, a drain region, and a channel disposed between the source region and the drain region, A gate insulating pattern, a gate electrode disposed on the gate insulating pattern, a gate electrode overlapping the channel, and a light shielding pattern disposed between the base substrate and the active pattern and having a larger area than the active pattern.

In one embodiment, the source region, the drain region, and the channel are located in the same layer.

In one embodiment, the device further comprises a gate line electrically connected to the gate electrode, wherein the gate electrode extends from the gate line.

In one embodiment, the shielding pattern may include a first portion extending in a first direction and overlapping at least a part of the gate line, a second portion protruding from the first portion in a second direction intersecting with the first direction, A second portion overlapping the gate electrode, and a third portion protruding from the second portion in the first direction and overlapping the active pattern.

In one embodiment, the shielding pattern overlaps the entire gate electrode and the entire active pattern.

In one embodiment, the shielding pattern may include a region extending in a first direction and overlapping with the active pattern, and a second region extending from the first portion in a second direction intersecting with the first direction, .

In one embodiment, the gate electrode includes a region that does not overlap with the channel, and the shielding pattern also overlaps with the region where the channel does not overlap with the gate electrode.

In one embodiment, the thin film transistor substrate further comprises a buffer pattern disposed between the light shielding pattern and the active pattern, the buffer pattern comprising silicon oxide or silicon nitride.

In one embodiment, the light emitting device further includes a buffer layer disposed between the base substrate and the light shielding pattern.

In one embodiment, the thin film transistor substrate further comprises a data line electrically connected to the source region and a data insulation layer covering the data line, wherein the light blocking pattern is disposed on the data insulation layer.

In one embodiment, the shielding pattern comprises a silicon-germanium alloy, germanium or titanium oxide.

In one embodiment, the thickness of the light shielding pattern is 100 ANGSTROM to 2,000 ANGSTROM.

In one embodiment, the active pattern comprises a metal oxide, wherein the metal oxide is selected from the group consisting of zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO) TiO), indium-gallium-zinc oxide (IGZO) or indium-zinc-tin oxide (IZTO).

A thin film transistor substrate according to an embodiment of the present invention includes a base substrate, an active pattern disposed on the base substrate, the active pattern including a source region, a drain region, and a channel disposed between the source region and the drain region, A gate insulating pattern disposed on the gate insulating pattern, a gate electrode overlapping the channel, and a shielding pattern disposed between the base substrate and the active pattern, the shielding pattern including a silicon-germanium alloy.

In one embodiment, the shielding pattern has a multilayer structure including a silicon-germanium alloy layer and a germanium layer.

According to the method of manufacturing a thin film transistor substrate according to an embodiment of the present invention, a light shielding layer is formed on a base substrate. A semiconductor layer is formed on the light-shielding layer. The semiconductor layer is patterned to form a semiconductor pattern. A gate insulating layer and a gate metal layer are sequentially formed on the semiconductor pattern. The gate metal layer is patterned to form a gate electrode. The gate insulating layer is patterned to form a gate insulating pattern. The gate electrode and the semiconductor pattern are used as a mask, and the light shielding layer is patterned to form a light shielding pattern having a larger area than the semiconductor pattern.

In one embodiment, after forming the gate insulating pattern, the exposed semiconductor pattern is subjected to plasma treatment to form a source region and a drain region.

In one embodiment, before forming the light-shielding layer, a data line is formed on the base substrate, and a data insulating layer is formed covering the data line.

In one embodiment, a buffer layer is formed on the light-shielding layer before forming the semiconductor layer.

In one embodiment, a buffer layer is formed on the base substrate before forming the light shielding layer.

According to the embodiment of the present invention, in the thin film transistor substrate having the top gate structure, the light shielding pattern is formed by using the semiconductor pattern and the gate electrode as a mask to form the light shielding pattern without increasing the mask and substantially without decreasing the opening ratio. And the area of the shielding pattern can be increased to prevent or reduce the inflow of the leakage light.

According to the embodiment of the present invention, the reliability of the thin film transistor can be increased by using the light-shielding layer including the silicon-germanium alloy.

1 is a plan view of a thin film transistor substrate according to an embodiment of the present invention.
2 is a cross-sectional view taken along line II 'of FIG.
FIGS. 3, 4, 6 to 9, 12, and 13 are cross-sectional views illustrating the method of manufacturing the thin film transistor substrate shown in FIGS. 1 and 2. FIG.
5 is a graph showing transmittance and absorbance of a light-shielding layer including a silicon-germanium alloy with respect to wavelength.
FIGS. 10 and 11 are plan views illustrating a light shielding pattern of a thin film transistor substrate according to an embodiment of the present invention.
14 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
FIGS. 15 to 19 are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate shown in FIG.
20 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
FIGS. 21 to 26 are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate shown in FIG. 20. FIG.
27 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
28 to 33 are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate shown in FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

Thin film transistor substrate

1 is a plan view of a thin film transistor substrate according to an embodiment of the present invention. 2 is a cross-sectional view taken along line I-I 'of FIG.

Referring to FIGS. 1 and 2, the thin film transistor substrate 100 includes a base substrate 100, a gate line GL, a data line DL, an active pattern 120, and a light shielding pattern 140.

The gate line GL extends in a first direction D1 on a plan view and the data line DL extends in a second direction D2. The first direction D1 and the second direction D2 intersect with each other. For example, the first direction D1 and the second direction D2 may be substantially perpendicular to each other.

The gate line GL is electrically connected to the gate electrode GE. For example, the gate electrode GE may protrude from the gate line GL in the second direction D2.

The active pattern 120 includes a channel 122, a source region 124, and a drain region 126. The channel region 122, the source region 124 and the drain region 126 are formed from the same layer and are successively arranged in the same layer, and between the source region 124 and the drain region 126, Channel 122 is located.

The channel 122 overlaps the gate electrode GE. Specifically, the gate electrode GE is disposed on the channel 122, and a gate insulating pattern 160 is disposed between the gate electrode GE and the channel 122. The gate electrode GE may cover the entire channel 122.

In an embodiment of the invention, the area of the gate electrode (GE) may be equal to or greater than the area of the channel (122). When the area of the gate electrode GE is wider than the area of the channel 122, the gate electrode GE is not overlapped with the channel 122, but a region protruding in the second direction D2 from the channel 122 and / RTI > may include an area protruding in a direction opposite to the second direction (D2) than the channel (122) without overlapping the channel (122). That is, there may be a region that does not overlap the channel 122 above and / or below the gate electrode with respect to the second direction.

In an embodiment of the present invention, the thin film transistor substrate 100 further includes a pixel electrode PE electrically connected to the drain region 126.

The data line DL is formed on the base substrate 110 and is electrically connected to the source region 124. For example, the data line DL and the source region 124 may be electrically connected through the connection electrode 130. A data insulating layer 115 is formed on the base substrate 110 on which the data lines DL are formed to cover the data lines DL.

The channel 122, the source region 124, the drain region 126, and the gate electrode GE constitute a thin film transistor. When the gate signal is transmitted to the gate electrode GE through the gate line GL, the channel 122 becomes conductive, so that the data signal provided from the data line DL is electrically connected to the connection electrode The source region 124, the channel 122, and the drain region 126 of the pixel electrode PE.

The thin film transistor substrate 100 includes a passivation layer 170 covering the thin film transistor and the data insulating layer 115 and an organic insulating layer 180 covering the passivation layer 170. The pixel electrode PE and the connection electrode 130 are formed on the organic insulating layer 180.

In an embodiment of the invention, the data lines DL are formed directly on the base substrate 110, while in other embodiments, the data lines DL may be formed on the passivation layer 170.

The connection electrode 130 is connected to the data line DL through a first contact hole CH1 formed through the organic insulation layer 180, the passivation layer 170, and the data insulation layer 115. [ And is connected to the source region 124 through a second contact hole CH2 formed through the organic insulating layer 180 and the passivation layer 170. [ The pixel electrode PE is connected to the drain region 126 through a third contact hole CH3 formed through the organic insulating layer 180 and the passivation layer 170. [

The light blocking pattern 140 is disposed below the channel 122. The shielding pattern 140 covers a bottom surface of the channel 122 to prevent external light from entering the channel 122 from the bottom of the TFT substrate 100. The light blocking pattern 140 overlaps the entire active pattern 120 including the channel 122 and overlaps the entire gate electrode GE. That is, when there is a region of the gate electrode GE that does not overlap with the channel 122, the shielding pattern 140 overlaps the channel 122, and at the same time, the gate electrode GE that does not overlap with the channel 122 Overlap. Therefore, the light shielding pattern 120 may have a larger area than the active pattern 120 in a plan view. A buffer pattern 150 is disposed between the shielding pattern 140 and the active pattern 120 and the shielding pattern 140 is formed on the data insulating layer 115. [

In another embodiment, a buffer layer may be additionally formed between the base substrate 110 and the light shielding pattern 140. In this case, the data line DL may be formed directly on the base substrate 110, or may be formed on the buffer layer.

FIGS. 3 to 8, FIGS. 10 and 11 are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate shown in FIGS. 1 and 2. FIG.

Referring to FIG. 3, a data line DL is formed on a base substrate 110. As the base substrate 110, a glass substrate, a quartz substrate, a silicon substrate, a plastic substrate, or the like can be used.

In order to form the data line DL, a data metal layer is formed on the base substrate 110, and the data metal layer is etched through a photolithography process.

For example, the data line DL may include copper, silver, chromium, molybdenum, aluminum, titanium, manganese, aluminum, or an alloy thereof, and may include a plurality of metal layers including a single- Layer structure. For example, the data line DL may include a copper layer and a titanium layer formed on top and / or bottom of the copper layer.

In another embodiment, the data line DL may comprise a metal layer and an oxide layer formed on top and / or below the metal layer. In detail, the data line DL may include a copper layer and an oxide layer formed on the upper and / or lower portions of the copper layer. For example, the oxide layer may be formed of indium zinc oxide (IZO), indium tin oxide (ITO), gallium zinc oxide (GZO), zinc aluminum oxide (ZAO) And may include one or more.

4, a data insulating layer 115, a light shielding layer 240, a buffer layer 250, and a semiconductor layer 220 are sequentially formed on the base substrate 110 on which the data lines DL are formed .

The data insulating layer 115 covers the data lines DL and may include silicon nitride, silicon oxide, and the like.

The light shielding layer 240 is formed on the data insulating layer 115. Since the semiconductor layer 220 is exposed to the etchant in a process subsequent to the step of etching the light shielding layer 240, the light shielding layer 240 includes a material having etching selectivity with respect to the semiconductor layer 220 .

For example, the light-shielding layer 240 may include at least one of a metal, an alloy, an insulating inorganic material, and an organic material. Preferably, the light-shielding layer 240 may include at least one of a silicon-germanium alloy, germanium, and titanium oxide, and more preferably, the light-shielding layer 24 includes a silicon-germanium alloy.

In an embodiment of the invention, the channel may comprise an oxide semiconductor. The oxide semiconductor is particularly vulnerable to ultraviolet rays having a wavelength of about 450 nm or less, and the silicon-germanium alloy is excellent in ultraviolet light shielding ability. Therefore, when the thin film transistor substrate is used in a display device, ultraviolet rays generated by a light source or the like can be effectively blocked to protect the channel.

Germanium alloy may have an amorphous state when the light-shielding layer 24 includes the silicon-germanium alloy, and the light-shielding layer 240 may be made of a silicon-germanium alloy Layer structure or a multi-layer structure including a silicon-germanium alloy layer and a germanium layer. The germanium layer may be disposed above or below the silicon-germanium alloy layer.

The thickness of the light shielding layer 240 may be about 100 Å to about 2,000 Å. When the thickness of the light shielding layer 240 is less than 100 angstroms, the light shielding ability may be lowered and the electrical characteristics of the channel may be deteriorated. When the thickness of the light shielding layer 240 exceeds 2,000 angstroms, It is possible to delay the signal by forming a capacitance with the source region 124 or the drain region 126.

More preferably, the thickness of the light-shielding layer 240 may be about 600 Å to about 2,000 Å. When the thickness of the light shielding layer 240 is 600 ANGSTROM or more, it may have a high optical density.

5 is a graph showing transmittance and absorbance of a light-shielding layer including a silicon-germanium alloy with respect to wavelength. 5, (1) has a single layer structure of a silicon-germanium alloy layer having a thickness of about 300 angstroms, (2) has a double layer structure of a silicon-germanium alloy layer having a thickness of about 100 angstroms and a germanium layer having a thickness of about 300 angstroms, (3) has a single layer structure of a silicon-germanium alloy layer having a thickness of about 500 ANGSTROM, (4) has a double layer structure of a silicon-germanium alloy layer having a thickness of about 300 ANGSTROM and a germanium layer having a thickness of about 300 ANGSTROM, (6) has a bilayer structure of a silicon-germanium alloy layer having a thickness of about 500 ANGSTROM and a germanium layer having a thickness of about 300 ANGSTROM, and (7) a layer having a thickness of about 700 ANGSTROM Layer structure of a silicon-germanium alloy layer and a germanium layer of a thickness of about 300 angstroms.

Referring to FIG. 5, it can be seen that the light-shielding layer having a bilayer structure of the silicon-germanium alloy layer and the germanium layer has lower transmittance and higher absorbance than the light-shielding layer having the single-layer structure of the silicon-germanium alloy layer . When the thickness of the light shielding layer is about 600 angstroms or more, the light transmittance is about 1% or less for light of 450 nm or less. When the thickness of the light shielding layer is about 1,000 angstroms or more, And an absorbance of 4 or more can be maintained.

Therefore, the thin film transistor substrate according to the embodiment of the present invention can increase the reliability of the thin film transistor by using the light-shielding layer including the silicon-germanium alloy.

The buffer layer 250 is formed on the light shielding layer 240 and may include an insulating oxide such as silicon oxide, aluminum oxide, hafnium oxide, or yttrium oxide.

The semiconductor layer 220 is formed on the buffer layer 250. The semiconductor layer 220 may include polycrystalline silicon, an oxide semiconductor, or the like, but may include an oxide semiconductor in an embodiment of the present invention.

The oxide semiconductor may be a metal oxide semiconductor, for example, the oxide semiconductor may include one or a combination of oxides of zinc, indium, gallium, tin, titanium, and phosphorus. Specifically, the oxide semiconductor may be at least one selected from the group consisting of zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium- , Indium-zinc-tin oxide (IZTO).

The data insulating layer 115, the light shielding layer 240, the buffer layer 250 and the semiconductor layer 220 may be formed by a chemical vapor deposition (CVD) method, a plasma enhanced chemical vapor deposition, PECVD), a solution coating method, a sputtering method, or the like.

Referring to FIG. 6, the semiconductor layer 220 is patterned to form a semiconductor pattern 222. Specifically, a photoresist pattern PR is formed on the semiconductor layer 220, and the semiconductor layer 220 is etched using the photoresist pattern PR as a mask.

Referring to FIG. 7, a gate insulating layer 260 and a gate metal layer 290 are formed on the semiconductor pattern 222 and the buffer layer 250.

The gate insulating layer 260 covers the semiconductor pattern 222 and may include silicon nitride, silicon oxide, or the like.

The gate metal layer 290 may be formed on the gate insulating layer 260 and may include at least one of copper, silver, chromium, molybdenum, aluminum, titanium, manganese, aluminum, Layer structure including a plurality of metal layers including different materials. For example, the gate metal layer 290 may comprise a copper layer and a titanium layer formed on top and / or below the copper layer.

In another embodiment, the gate metal layer 290 may comprise a metal layer and an oxide layer formed on top and / or below the metal layer. Specifically, the gate metal layer 290 may include a copper layer and an oxide layer formed on upper and / or lower portions of the copper layer. The oxide layer may include indium zinc oxide, indium tin oxide, gallium zinc oxide, zinc aluminum oxide, and the like.

8, the gate metal layer 290 and the gate insulating layer 260 are patterned to form a gate electrode GE, a gate line GL, and a gate insulating pattern 160. Referring to FIG.

First, the gate metal layer 290 is patterned to form the gate electrode GE and the gate line GL. Next, the gate insulating layer 260 is patterned by using the gate electrode GE and the gate line GL as a mask to form a gate insulating pattern 160. Next, as shown in FIG. Therefore, the gate insulating pattern 160 has substantially the same shape as the gate electrode GE and the gate line GL on a plan view.

The semiconductor pattern 222 is exposed in the process of patterning the gate insulation layer 260. Since the gate insulation layer 260 includes a material different from the semiconductor pattern 222 and has etching selectivity , The semiconductor pattern 222 is not etched.

The gate insulating layer 260 and the buffer layer 250 may include a similar material so that the buffer layer 250 is etched together with the gate insulating layer 260. [ . The buffer layer 250 located under the semiconductor pattern 222 is left to form the buffer pattern 150. The buffer layer 250 is formed on the buffer layer 250. The buffer layer 250 is formed on the buffer layer 250,

Referring to FIG. 9, the light shielding layer 240 is etched using the gate electrode 160 and the semiconductor pattern 222 as a mask to form a light shielding pattern 140. Thus, the data insulating layer 115 is exposed.

10 is a plan view illustrating a light shielding pattern of a thin film transistor substrate according to an embodiment of the present invention.

10, the shielding pattern 140 includes a first portion 142 that overlaps at least a portion of the gate line GL, a second portion 142 that extends from the first portion 142, And a third portion 146 extending from the second portion 144 and overlapping the semiconductor pattern 222. The second portion 144 includes a second portion 144,

For example, the first portion 142 extends along the first direction D1, the second portion 144 extends along the second direction D2, and the third portion 146 Extend along the first direction D1. In the plan view, the edge of the second portion 144 substantially coincides with the edge of the gate electrode GE, and the edge of the third portion 146 substantially coincides with the edge of the semiconductor pattern 222 do. The length W1 of the light shielding pattern 140 overlapping the semiconductor pattern 222 in the first direction is substantially equal to the length of the semiconductor pattern 222 in the first direction, The length W2 in the second direction of the shielding pattern 140 overlapping the gate electrode GE is substantially equal to the length of the gate electrode GE in the second direction.

10, the shielding pattern 140 may overlap all of the gate lines GL, but the present invention is not limited thereto, and may be a part of the gate lines GL adjacent to the gate electrodes GE, Can only be overlapped. The gate line GL is formed from a metal layer, so that the light reflectance is high. Therefore, when light is incident on the lower surface of the gate line GL, reflected light enters the channel 122, which may affect the electrical characteristics of the thin film transistor. In the embodiment of the present invention, the light shielding pattern 140 overlaps at least a part of the gate line GL, thereby improving the reliability of the thin film transistor.

The buffer pattern 150 has substantially the same shape as the light-shielding pattern 140 on a plan view.

In an embodiment of the present invention, the light shielding pattern 140 overlapping the semiconductor pattern 222 and the gate electrode GE has a cross shape as a whole. However, the shape of the light-shielding pattern 140 may vary depending on the shape and arrangement of the semiconductor pattern 222 and the gate electrode GE, and may be, for example, a T shape, a square shape, It is possible.

In another embodiment, the shielding pattern may overlap the gate electrode GE and the semiconductor pattern 222 without overlapping the gate line GL. 11, the shielding pattern 141 includes a first portion 143 which overlaps with the gate electrode GE and a second portion 143 which protrudes from the first portion 143 in the first direction D1, And a second portion 145 overlapping the second portion. The edge of the second portion 145 is substantially aligned with the edge of the semiconductor pattern 222. The edge of the first portion 143 is substantially coincident with the edge of the gate electrode GE, . The length W1 in the first direction of the shielding pattern 141 overlapping the semiconductor pattern 222 is substantially equal to the length of the semiconductor pattern 222 in the first direction, The length W2 in the second direction of the shielding pattern 141 overlapping with the gate electrode GE is substantially equal to the length of the gate electrode GE in the second direction.

If a separate mask is used to form the light shielding pattern 140, the manufacturing cost of the thin film transistor substrate can be increased, and the aperture ratio of the pixel in the display device can be lowered. The light shielding layer 240 may be patterned using the gate electrode GE, the gate line GL and the semiconductor pattern 222 as a mask so that the light shielding pattern 140 ), And does not substantially reduce the aperture ratio. Also, the light shielding pattern 140 has a larger area than the semiconductor pattern 222, thereby increasing the light shielding performance.

Referring again to FIG. 9, a channel 122, a source region 124, and a drain region 126 are formed from the semiconductor pattern 222. Specifically, the semiconductor pattern 222 exposed without being covered by the gate electrode GE and the gate insulating pattern 160 is converted into a source region 124 and a drain region 126.

For example, to form the source region 124 and the drain region 126, the exposed semiconductor pattern 222 may be plasma treated. For example, hydrogen (H2), helium (He), phosphine (PH3), ammonia (NH3), silane (SiH4), methane (CH4), acetylene (C2H2), diborane (B2H6) (PT) such as germane (GeH4), hydrogen selenide (H2Se), hydrogen sulfide (H2S), argon (Ar), nitrogen (N2), nitrogen oxide (N2O), fluoroform (CHF3) Pattern 222 as shown in FIG. Accordingly, at least a part of the semiconductor material constituting the exposed semiconductor pattern 222 subjected to reduction treatment can be reduced to be converted into a metallic conductor. The semiconductor pattern 222 thus formed forms the source region 124 and the drain region 126 and the portion covered by the gate electrode GE and the gate insulating pattern 160 remains, (122).

Alternatively, in order to form the source region 124 and the drain region 126, the semiconductor pattern 222 may be heat-treated in an atmosphere of a reducing gas, or an ion implantation process may be performed.

The source region 124 and the drain region 126 are formed after patterning the light shielding layer 240. In another embodiment of the present invention, the light shielding layer 240 is formed before patterning .

12, a passivation layer 170 is formed to cover the gate electrode GE, the source region 124, the drain region 126, and the data insulating layer 115, and the passivation layer The organic insulating layer 180 is formed.

The passivation layer 170 may include silicon nitride, silicon oxide, or the like. The organic insulating layer 180 may be formed by planarizing a surface of the thin film transistor substrate and spin-coating a photoresist composition on the passivation layer 170.

Referring to FIG. 13, the data insulating layer 115, the passivation layer 170, and the organic insulating layer 180 are patterned to form contact holes.

A first contact hole CH1 exposing the data line DL is formed by patterning the data insulating layer 115, the passivation layer 170 and the organic insulating layer 180, A second contact hole CH2 exposing a portion of the source region 124 and a third contact hole 142 exposing a portion of the drain region 126 by patterning the layer 170 and the organic insulating layer 180, (CH3).

Specifically, the organic insulating layer 180 may be patterned by exposing the organic insulating layer 180, applying a developing solution to the organic insulating layer 180, and removing the non-exposed region or the exposed region, Using the patterned organic insulating layer 180 as a mask, the exposed passivation layer 170 and the data insulating layer 115 are etched to form the first to third contact holes CH1, CH2, and CH3 .

Next, a transparent conductive layer is formed on the organic insulating layer 180. The transparent conductive layer may include indium zinc oxide, indium tin oxide, and the like.

The transparent conductive layer is patterned to form the connection electrode 130 and the pixel electrode PE shown in FIG. The connection electrode 130 contacts the data line DL through the first contact hole CH1 and contacts the source region 124 through the second contact hole CH2. The pixel electrode PE contacts the drain region 124 through the third contact hole CH3.

According to an embodiment of the present invention, after the semiconductor pattern 222 is formed, the gate electrode GE is formed, and the light-shielding pattern 140 (FIG. 1) is formed using the semiconductor pattern 222 and the gate electrode GE as masks. The light shielding pattern 140 can be formed without increasing the mask and substantially without decreasing the aperture ratio. Also, the light shielding pattern 140 has a larger area than the semiconductor pattern 222, thereby preventing or reducing the inflow of the leakage light.

The thin film transistor substrate according to the embodiment of the present invention can be used as an array substrate of a liquid crystal display. However, the present invention is not limited to this, and can be used in other display devices such as organic EL display devices, circuit boards having thin film transistors, and electronic devices such as semiconductor devices. And may be varied depending on the use thereof without departing from the spirit and scope of the invention.

14 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. Specifically, Fig. 14 shows the same cross section as the thin film transistor substrate shown in Fig.

Referring to FIG. 14, the thin film transistor substrate 300 includes a base substrate 310, a gate line, a data line DL, an active pattern 320, and a light shielding pattern 340.

The active pattern 320 includes a channel 322, a source region 324, and a drain region 326. The channel 322, the source region 324 and the drain region 326 are formed from the same layer and are successively arranged over the same layer, and between the source region 324 and the drain region 326, Channel 322 is located. The drain region 326 is electrically connected to the pixel electrode PE and a gate insulation pattern 360 is disposed between the gate electrode GE and the channel 322.

The data line DL is formed on the base substrate 310 and is electrically connected to the source region 324. The data insulating layer 315 covers the data line DL and the base substrate 310. [

In an embodiment of the invention, the data line DL is formed directly on the base substrate 310, but in other embodiments, the data line DL may be formed on the passivation layer 370.

The passivation layer 370 covers the gate electrode GE, the active pattern 320 and the data insulating layer 315 and the organic insulating layer 380 covers the passivation layer 370. The pixel electrode PE and the connection electrode 330 are formed on the organic insulating layer 380. The connection electrode 330 is connected to the data line DL through the first contact hole CH1 and is connected to the source region 324 through the second contact hole CH2. The pixel electrode PE is connected to the drain region 326 through a third contact hole CH3.

A light blocking pattern 140 is disposed below the channel 322. The light shielding pattern 140 overlaps the entire active pattern 320 including the channel 322 and the entire gate electrode GE. Therefore, the light shielding pattern 320 has a larger area than the active pattern 320 in a plan view.

In an embodiment of the invention, the thin film transistor substrate does not include the buffer pattern 150 shown in FIG. Therefore, the light blocking pattern 320 and the active pattern 320 can be in contact with each other.

In another embodiment, a buffer layer may be additionally formed between the base substrate 310 and the light shielding pattern 340. In this case, the data line DL may be formed directly on the base substrate 310, or may be formed on the buffer layer.

The thin film transistor substrate 300 is substantially the same as the thin film transistor substrate 100 shown in FIGS. 1 and 2 except that it does not include the buffer pattern 150. Therefore, overlapping detailed description will be omitted.

FIGS. 15 to 19 are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate shown in FIG.

Referring to FIG. 14, a data line DL is formed on a base substrate 310. For example, a data metal layer is formed on the base substrate 310, and the data metal layer is etched through a photolithography process to form the data lines DL.

A data insulating layer 315, a light shielding layer 440 and a semiconductor layer 420 are sequentially formed on the base substrate 310 after the data lines DL are formed.

Referring to FIG. 15, the semiconductor layer 420 is patterned to form a semiconductor pattern 422. Specifically, a photoresist pattern PR is formed on the semiconductor layer 420, and the semiconductor layer 420 is etched using the photoresist pattern PR as a mask.

Referring to FIG. 16, a gate insulating layer 460 and a gate metal layer 490 are formed on the semiconductor pattern 422 and the light shielding layer 440.

Referring to FIG. 17, the gate metal layer 490 and the gate insulating layer 460 are patterned to form a gate electrode GE, a gate line, and a gate insulating pattern 360. First, the gate metal layer 490 is patterned to form a gate electrode GE and a gate line. Next, a gate insulating pattern 360 is formed by patterning the gate insulating layer 460 using the gate electrode GE and the gate line as masks. Accordingly, the light shielding layer 440 under the gate insulating layer 460 is exposed.

Referring to FIG. 18, the light shielding layer 440 is etched using the gate electrode 360 and the semiconductor pattern 422 as masks to form a light shielding pattern 340. Therefore, the light shielding pattern 340 substantially overlaps the entire gate electrode 360 and the entire semiconductor pattern 422. Specifically, the light shielding pattern 340 may have the same shape as the light shielding pattern shown in FIG.

A channel 322, a source region 324 and a drain region 326 are formed from the semiconductor pattern 422. Specifically, a source region 324 and a drain region 326 are formed by applying a plasma gas (PT) or the like to the semiconductor pattern 422 exposed without being covered by the gate electrode GE and the gate insulating pattern 360, . The portion covered by the gate electrode GE and the gate insulator pattern 360 forms a channel 322.

The step of applying the plasma gas to the exposed semiconductor pattern 422 may be performed after or before the patterning of the light shielding layer 440.

Next, a passivation layer covering the gate electrode GE, the source region 324, the drain region 326, and the data insulating layer 315 is formed, and an organic insulating layer is formed on the passivation layer .

Next, the data insulating layer 315, the passivation layer, and the organic insulating layer are patterned to form contact holes. Next, a transparent conductive layer is formed on the organic insulating layer, and the transparent conductive layer is patterned to form the connection electrode 330 and the pixel electrode PE shown in FIG.

20 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. Specifically, FIG. 20 shows the same cross section as the thin film transistor substrate shown in FIG.

20, a thin film transistor substrate 500 includes a base substrate 510, a gate line, a data line DL, an active pattern 520, and a light shielding pattern 540. Referring to FIG.

The active pattern 520 includes a channel 522, a source region 524, and a drain region 526. The channel 522, the source region 524 and the drain region 526 are formed from the same layer and are successively arranged such that the channel 522 is formed between the source region 524 and the drain region 526, ). The drain region 526 is electrically connected to the pixel electrode PE and a gate insulation pattern 560 is disposed between the gate electrode GE and the channel 522.

A passivation layer 570 covers the gate electrode GE, the active pattern 520 and the base substrate 510 and an organic insulating layer 580 covers the passivation layer 570. The pixel electrode PE and the connection electrode 530 are formed on the organic insulating layer 580. The connection electrode 530 is connected to the data line DL through the first contact hole CH1 and is connected to the source region 524 through the second contact hole CH2. The pixel electrode PE is connected to the drain region 526 through a third contact hole CH3.

The data line DL is formed on the passivation layer 570 and is electrically connected to the source region 524.

A light blocking pattern 540 is disposed below the channel 522. The light blocking pattern 540 overlaps the entire active pattern 520 including the channel 522 and also overlaps a part of the gate electrode GE that does not overlap with the active pattern 520. [ Therefore, the light shielding pattern 520 has a larger area than the active pattern 520 in a plan view.

In an embodiment of the invention, the thin film transistor substrate 500 does not include the buffer pattern 150 and the data insulating layer 115 shown in FIG. Therefore, the light blocking pattern 520 and the base substrate 510 can be in contact with each other.

1 and 2 except that the thin film transistor substrate 500 does not include the buffer pattern 150 and the data insulating layer 115 and the data line DL is formed on the passivation layer 570. [ And is substantially the same as the thin film transistor substrate 100 shown in the figure. Therefore, overlapping detailed description will be omitted.

FIGS. 21 to 26 are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate shown in FIG. 20. FIG.

Referring to FIG. 21, a light shielding layer 640 and a semiconductor layer 620 are sequentially formed on a base substrate 510.

Referring to FIG. 22, the semiconductor layer 620 is patterned to form a semiconductor pattern 622. Specifically, a photoresist pattern PR is formed on the semiconductor layer 620, and the semiconductor layer 620 is etched using the photoresist pattern PR as a mask.

Referring to FIG. 23, a gate insulating layer 660 and a gate metal layer 690 are formed on the semiconductor pattern 622 and the light shielding layer 640.

Referring to FIG. 24, the gate metal layer 690 and the gate insulating layer 660 are patterned to form a gate electrode GE, a gate line, and a gate insulating pattern 560. First, the gate metal layer 690 is patterned to form a gate electrode GE and a gate line. Next, a gate insulating pattern 560 is formed by patterning the gate insulating layer 660 using the gate electrode GE and the gate line as a mask. Accordingly, the light shielding layer 640 under the gate insulating layer 660 is exposed.

25, a light shielding pattern 540 is formed by etching the light shielding layer 640 using the gate electrode 560 and the semiconductor pattern 622 as a mask. Therefore, the light shielding pattern 540 substantially overlaps the entire gate electrode 560 and the entire semiconductor pattern 622. Specifically, the light shielding pattern may have the same shape as the light shielding pattern shown in FIG.

A channel region 522, a source region 524, and a drain region 526 are formed from the semiconductor pattern 622. Specifically, a source region 524 and a drain region 526 are formed by applying a plasma gas (PT) or the like to the semiconductor pattern 622 that is exposed without being covered by the gate electrode GE and the gate insulating pattern 560, . The portion covered by the gate electrode GE and the gate insulator pattern 560 forms a channel 522.

The step of applying the plasma gas to the exposed semiconductor pattern 622 may be performed after or before the patterning of the light shielding layer 640.

Referring to FIG. 26, a passivation layer 570 is formed to cover the gate electrode GE, the source region 524, the drain region 526, and the base substrate 510. A data metal layer is formed on the passivation layer 570, and the data metal layer is patterned to form a data line DL.

Next, an organic insulating layer covering the data line DL and the passivation layer 570 is formed, and the passivation layer 570 and the organic insulating layer are patterned to form contact holes. In an embodiment of the present invention, an organic insulating layer is formed directly on the data line DL. In another embodiment, a data insulating layer made of silicon oxide, silicon nitride, or the like is formed, and then an organic insulating layer is formed on the data insulating layer .

Next, a transparent conductive layer is formed on the organic insulating layer, and the transparent conductive layer is patterned to form the connection electrode 530 and the pixel electrode PE shown in FIG.

27 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. Specifically, Fig. 27 shows the same cross section as the thin film transistor substrate shown in Fig.

Referring to FIG. 27, the thin film transistor substrate 700 includes a base substrate 710, a gate line, a data line DL, an active pattern 720, a buffer pattern 750, and a light shielding pattern 740.

The active pattern 720 includes a channel 722, a source region 724, and a drain region 726. The channel 722, the source region 724 and the drain region 726 are formed from the same layer and are successively arranged such that the channel 722 is formed between the source region 724 and the drain region 726, ). The drain region 726 is electrically connected to the pixel electrode PE and a gate insulation pattern 760 is disposed between the gate electrode GE and the channel 722.

A passivation layer 770 covers the gate electrode GE, the active pattern 720 and the base substrate 710 and an organic insulating layer 780 covers the passivation layer 770. The pixel electrode PE and the connection electrode 730 are formed on the organic insulating layer 780. The connection electrode 730 is connected to the data line DL through the first contact hole CH1 and is connected to the source region 724 through the second contact hole CH2. The pixel electrode PE is connected to the drain region 726 through a third contact hole CH3.

The data line DL is formed on the passivation layer 770 and is electrically connected to the source region 724.

A light blocking pattern 740 is disposed under the channel 722. The light blocking pattern 740 overlaps the entire active pattern 720 including the channel 722 and also overlaps a portion of the gate electrode GE that does not overlap with the active pattern 720. [ Therefore, the light-shielding pattern 720 has an area larger than the active pattern 720 in a plan view.

A buffer pattern 750 is disposed between the light-shielding pattern 740 and the active pattern 720. The buffer pattern 750 may have substantially the same shape as the light blocking pattern 740.

In an embodiment of the invention, the thin film transistor substrate 700 does not include the data insulating layer 115 shown in FIG. Therefore, the light blocking pattern 720 and the base substrate 710 can be in contact with each other.

1 and 2 except that the thin film transistor substrate 700 does not include the data insulating layer 115 and the data line DL is formed on the passivation layer 770. [ ). Therefore, overlapping detailed description will be omitted.

28 to 33 are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate shown in FIG.

28, a light shielding layer 840, a buffer layer 850, and a semiconductor layer 820 are sequentially formed on a base substrate 710.

Referring to FIG. 29, the semiconductor layer 820 is patterned to form a semiconductor pattern 822. Specifically, a photoresist pattern PR is formed on the semiconductor layer 820, and the semiconductor layer 820 is etched using the photoresist pattern PR as a mask.

Referring to FIG. 30, a gate insulating layer 860 and a gate metal layer 890 are formed on the semiconductor pattern 822 and the buffer layer 850.

Referring to FIG. 31, the gate metal layer 890 and the gate insulating layer 860 are patterned to form a gate electrode GE, a gate line, and a gate insulating pattern 760. First, the gate metal layer 890 is patterned to form a gate electrode GE and a gate line. Next, the gate insulating layer 860 is patterned by using the gate electrode GE and the gate line as masks to form a gate insulating pattern 760. Next, as shown in FIG. Thus, the buffer layer 850 under the gate insulating layer 860 is exposed.

32, the buffer layer 850 and the light shielding layer 840 are etched using the gate electrode 760 and the semiconductor pattern 822 as masks to form a buffer pattern 750 and a light shielding pattern 740 ). Therefore, the buffer pattern 750 and the light shielding pattern 740 substantially overlap with the entire gate electrode 760 and the entire semiconductor pattern 822. Specifically, the light shielding pattern 740 may have the same shape as the light shielding pattern shown in FIG.

A channel 722, a source region 724, and a drain region 726 are formed from the semiconductor pattern 822. Specifically, a source region 724 and a drain region 726 are formed by applying a plasma gas (PT) or the like to the semiconductor pattern 822 that is exposed without being covered by the gate electrode GE and the gate insulating pattern 760, . The portion covered by the gate electrode GE and the gate insulating pattern 760 forms a channel 722.

The step of applying the plasma gas to the exposed semiconductor pattern 822 may be performed after or before the patterning of the light shielding layer 840.

Referring to FIG. 33, a passivation layer 770 covering the gate electrode GE, the source region 724, the drain region 726, and the base substrate 710 is formed. A data metal layer is formed on the passivation layer 770, and the data metal layer is patterned to form a data line DL.

Next, an organic insulating layer covering the data line DL and the passivation layer 770 is formed, and the passivation layer 770 and the organic insulating layer are patterned to form contact holes.

Next, a transparent conductive layer is formed on the organic insulating layer, and the transparent conductive layer is patterned to form the connection electrode 730 and the pixel electrode PE shown in FIG.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible.

The thin film transistor substrate and the method of manufacturing the thin film transistor substrate according to the embodiments of the present invention can be used for a liquid crystal display, an organic EL display, a circuit board having a thin film transistor, a display device such as a semiconductor device, and an electronic device.

100, 300, 500, 700: thin film transistor substrate
110, 310, 510, 710: base substrate
GL: gate line DL: data line
GE: gate electrode PE: pixel electrode
120, 320, 520, 720: active pattern
140, 340, 540, 740: Shading pattern
130, 330, 530, 730:
115, 315: data insulating layer 150, 750: buffer pattern
160, 360, 560, 760: Gate insulation pattern
CH1, CH2, CH3: contact hole
170, 370, 570, 770: passivation layer
180, 380, 580, 780: organic insulating layer

Claims (8)

A base substrate;
An active pattern disposed on the base substrate and including a source region, a drain region, and a channel disposed between the source region and the drain region;
A gate insulating pattern disposed on the active pattern;
A gate electrode disposed on the gate insulating pattern and overlapping the channel;
And a shielding pattern disposed between the base substrate and the active pattern, the shielding pattern including a silicon-germanium alloy. The thin film transistor substrate according to claim 1, wherein the thickness of the light shielding pattern ranges from 100 Å to 2,000 Å. The thin film transistor substrate according to claim 2, wherein the shielding pattern has a multilayer structure including a silicon-germanium alloy layer and a germanium layer. Forming a light-shielding layer on the base substrate;
Forming a semiconductor layer on the light-shielding layer;
Forming a semiconductor pattern by patterning the semiconductor layer;
Sequentially forming a gate insulating layer and a gate metal layer on the semiconductor pattern;
Patterning the gate metal layer to form a gate electrode;
Forming a gate insulating pattern by patterning the gate insulating layer; And
And forming a light shielding pattern having a larger area than the semiconductor pattern by patterning the light shielding layer using the gate electrode and the semiconductor pattern as a mask. 5. The method of claim 4, further comprising forming a source region and a drain region by plasma-treating the exposed semiconductor pattern after forming the gate insulating pattern. 6. The light-emitting device according to claim 5, wherein before forming the light-
Forming a data line on the base substrate; And
And forming a data insulation layer covering the data lines. ≪ Desc / Clms Page number 21 > 6. The method of claim 5, further comprising forming a buffer layer on the light-shielding layer before forming the semiconductor layer. 6. The method of claim 5, further comprising forming a buffer layer on the base substrate before forming the light shielding layer.

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