KR102105005B1 - Thin-film transistor substrate and method of manufacturing the same - Google Patents

Abstract

The disclosed thin film transistor substrate includes a base substrate, an active pattern including a source region, a drain region, and a channel disposed between the source region and the drain region, a gate insulating pattern disposed on the active pattern, and It is disposed on the gate insulating pattern, and is disposed between the gate electrode overlapping the channel and the base substrate and the active pattern, and includes a light blocking pattern having a larger area than the active pattern.

Description

THIN-FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

The present invention relates to a thin film transistor substrate and a method for manufacturing the same, and more particularly, to a thin film transistor substrate and a method for manufacturing the same, which can prevent a decrease in reliability by external light.

In general, a thin film transistor for driving a pixel in a display device includes a gate electrode, a source electrode, a drain electrode, and a channel layer forming a channel between the source electrode and the drain electrode. The channel layer includes a semiconductor layer including amorphous silicon, polysilicon, or oxide semiconductor.

The gate electrode overlaps the channel layer and may be formed under or over the channel layer.

However, the electrical properties of the amorphous silicon, polycrystalline silicon, or oxide semiconductor constituting the channel layer may be reduced by external light. Therefore, in order to prevent a decrease in reliability of the switching element, the thin film transistor may include a light blocking layer.

A thin film transistor substrate according to an embodiment of the present invention is disposed on a base substrate, an active pattern including a source region, a drain region, and a channel disposed between the source region and the drain region, and disposed on the active pattern It includes a gate insulating pattern, a gate electrode disposed on the gate insulating pattern, overlapping the channel, and disposed between the base substrate and the active pattern, and has a light blocking pattern having a larger area than the active pattern.

In one embodiment, the source region, the drain region and the channel are on the same layer.

In one embodiment, the gate electrode further includes a gate line electrically connected to the gate electrode, and the gate electrode extends from the gate line.

In one embodiment, the light blocking pattern extends in a first direction, and protrudes in a second direction that intersects the first direction from a first part overlapping at least a portion of the gate line and the first part. A second portion overlapping the gate electrode and a third portion protruding from the second portion and overlapping the active pattern are included.

In one embodiment, the light blocking pattern overlaps the entire gate electrode and the entire active pattern.

In one embodiment, the light blocking pattern extends in a first direction, and protrudes in a second direction crossing the first direction from an area overlapping the active pattern and the first portion, overlapping the gate electrode It includes the area.

In one embodiment, the gate electrode includes a region that does not overlap the channel, and the light blocking pattern overlaps a region where the gate electrode and the channel do not overlap.

In one embodiment, the thin film transistor substrate further includes a buffer pattern disposed between the light blocking pattern and the active pattern, and the buffer pattern includes silicon oxide or silicon nitride.

In one embodiment, a buffer layer disposed between the base substrate and the light blocking pattern is further included.

In one embodiment, the thin film transistor substrate further includes a data line electrically connected to the source region and a data insulating layer covering the data line, and the light blocking pattern is disposed on the data insulating layer.

In one embodiment, the light blocking pattern includes a silicon-germanium alloy, germanium or titanium oxide.

In one embodiment, the thickness of the light blocking pattern is 100Å to 2,000Å.

In one embodiment, the active pattern includes a metal oxide, and the metal oxide is zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide ( TiO), indium-gallium-zinc oxide (IGZO) or indium-zinc-tin oxide (IZTO).

A thin film transistor substrate according to an embodiment of the present invention is disposed on a base substrate, an active pattern including a source region, a drain region, and a channel disposed between the source region and the drain region, and disposed on the active pattern A gate insulating pattern, a gate electrode disposed on the gate insulating pattern, overlapping the channel, and disposed between the base substrate and the active pattern, and a light blocking pattern including a silicon-germanium alloy.

In one embodiment, the light blocking pattern has a multilayer structure including a silicon-germanium alloy layer and a germanium layer.

According to a method of manufacturing a thin film transistor substrate according to an embodiment of the present invention, a light blocking layer is formed on a base substrate. A semiconductor layer is formed on the light blocking layer. The semiconductor layer is patterned to form a semiconductor pattern. A gate insulating layer and a gate metal layer are sequentially formed on the semiconductor pattern. The gate metal layer is patterned to form a gate electrode. The gate insulating layer is patterned to form a gate insulating pattern. The gate electrode and the semiconductor pattern are used as a mask, and the light blocking layer is patterned to form a light blocking pattern having a larger area than the semiconductor pattern.

In one embodiment, after the gate insulating pattern is formed, the exposed semiconductor pattern is plasma processed to form a source region and a drain region.

In one embodiment, before forming the light blocking layer, a data line is formed on the base substrate, and a data insulating layer covering the data line is formed.

In one embodiment, before forming the semiconductor layer, a buffer layer is formed on the light blocking layer.

In one embodiment, before forming the light blocking layer, a buffer layer is formed on the base substrate.

According to an embodiment of the present invention, in a thin film transistor substrate having a top gate structure, a light shielding pattern is formed by using a semiconductor pattern and a gate electrode as a mask, thereby forming the light shielding pattern without increasing the mask and substantially without reducing the aperture ratio. It is possible to increase the area of the light blocking pattern, thereby preventing or reducing the inflow of leakage light.

According to an embodiment of the invention, by using a light-shielding layer comprising a silicon-germanium alloy, it is possible to increase the reliability of the thin film transistor.

1 is a plan view of a thin film transistor substrate according to an embodiment of the present invention.
2 is a cross-sectional view taken along line II ′ of FIG. 1.
3, 4, 6 to 9, 12 and 13 are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIGS. 1 and 2.
5 is a graph showing transmittance and absorbance of a light-shielding layer containing a silicon-germanium alloy with respect to wavelength.
10 and 11 are plan views illustrating a light blocking pattern of a thin film transistor substrate according to an embodiment of the present invention.
14 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
15 to 19 are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 14.
20 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
21 to 26 are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 20.
27 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
28 to 33 are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 27.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Thin film transistor substrate

1 is a plan view of a thin film transistor substrate according to an embodiment of the present invention. 2 is a cross-sectional view taken along line I-I 'of FIG. 1.

1 and 2, the thin film transistor substrate 100 includes a base substrate 100, a gate line GL, a data line DL, an active pattern 120, and a light blocking pattern 140.

The gate line GL extends in a first direction D1 on a plan view, and the data line DL extends in a second direction D2. The first direction D1 and the second direction D2 intersect each other. For example, the first direction D1 and the second direction D2 may be substantially perpendicular to each other.

The gate line GL is electrically connected to the gate electrode GE. For example, the gate electrode GE may protrude from the gate line GL in the second direction D2.

The active pattern 120 includes a channel 122, a source region 124 and a drain region 126. The channel 122, the source region 124, and the drain region 126 are formed from the same layer, are successively arranged in the same layer, and between the source region 124 and the drain region 126, Channel 122 is located.

The channel 122 overlaps the gate electrode GE. Specifically, the gate electrode GE is disposed on the channel 122, and a gate insulating pattern 160 is disposed between the gate electrode GE and the channel 122. The gate electrode GE may cover the entire channel 122.

In an embodiment of the invention, the area of the gate electrode GE may be equal to or larger than the area of the channel 122. When the area of the gate electrode GE is larger than the area of the channel 122, the gate electrode GE does not overlap the channel 122 and protrudes in the second direction D2 more than the channel 122 and / Or may include an area protruding in the reverse direction of the second direction D2 more than the channel 122 without overlapping the channel 122. That is, there may be a region that does not overlap the channel 122 above and / or below the gate electrode based on the second direction.

In an embodiment of the invention, the thin film transistor substrate 100 further includes a pixel electrode PE electrically connected to the drain region 126.

The data line DL is formed on the base substrate 110 and is electrically connected to the source region 124. For example, the data line DL and the source region 124 may be electrically connected through a connection electrode 130. A data insulating layer 115 is formed on the base substrate 110 on which the data line DL is formed to cover the data line DL.

The channel 122, the source region 124, the drain region 126 and the gate electrode GE constitute a thin film transistor. When a gate signal is transmitted to the gate electrode GE through the gate line GL, the channel 122 becomes conductive, and accordingly, a data signal provided from the data line DL is connected to the connection electrode. 130, the source region 124, the channel 122 and the drain region 126 are transferred to the pixel electrode PE.

The thin film transistor substrate 100 includes a passivation layer 170 covering the thin film transistor and the data insulating layer 115 and an organic insulating layer 180 covering the passivation layer 170. The pixel electrode PE and the connection electrode 130 are formed on the organic insulating layer 180.

In an embodiment of the invention, the data line DL is formed directly on the base substrate 110, but in another embodiment, the data line DL may be formed on the passivation layer 170.

The connection electrode 130 is connected to the data line DL through a first contact hole CH1 formed through the organic insulating layer 180, the passivation layer 170, and the data insulating layer 115. It is connected to the source region 124 through a second contact hole CH2 formed through the organic insulating layer 180 and the passivation layer 170. The pixel electrode PE is connected to the drain region 126 through a third contact hole CH3 formed through the organic insulating layer 180 and the passivation layer 170.

The light blocking pattern 140 is disposed under the channel 122. The light blocking pattern 140 covers the lower surface of the channel 122 to prevent external light from entering the channel 122 from the bottom of the thin film transistor substrate 100. The light blocking pattern 140 overlaps the entire active pattern 120 including the channel 122 and overlaps the entire gate electrode GE. That is, if there is an area in the gate electrode GE that does not overlap the channel 122, the light blocking pattern 140 overlaps the channel 122 and also the gate electrode GE that does not overlap the channel 122. Overlap. Therefore, the light blocking pattern 120 may have a larger area than the active pattern 120 on a plan view. In an embodiment of the invention, a buffer pattern 150 is disposed between the light blocking pattern 140 and the active pattern 120, and the light blocking pattern 140 is formed on the data insulating layer 115.

In another embodiment, a buffer layer may be additionally formed between the base substrate 110 and the light blocking pattern 140. In this case, the data line DL may be directly formed on the base substrate 110 or may be formed on the buffer layer.

3 to 8, 10 and 11 are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIGS. 1 and 2.

Referring to FIG. 3, first, a data line DL is formed on the base substrate 110. A glass substrate, a quartz substrate, a silicon substrate, a plastic substrate, etc. may be used as the base substrate 110.

To form the data line DL, a data metal layer is formed on the base substrate 110 and the data metal layer is etched through a photolithography process.

For example, the data line DL may include copper, silver, chromium, molybdenum, aluminum, titanium, manganese, aluminum, or alloys thereof, and may include a single layer structure or a plurality of metal layers including different materials. It may have a multi-layer structure including. For example, the data line DL may include a copper layer and a titanium layer formed on and / or below the copper layer.

In another embodiment, the data line DL may include a metal layer and an oxide layer formed on and / or below the metal layer. Specifically, the data line DL may include a copper layer and an oxide layer formed on and / or below the copper layer. For example, the oxide layer is of indium zinc oxide (IZO), indium tin oxide (ITO), gallium zinc oxide (GZO), zinc aluminum oxide (zinc aluminium oxide, ZAO) It may include one or more.

Referring to FIG. 4, a data insulating layer 115, a light blocking layer 240, a buffer layer 250 and a semiconductor layer 220 are sequentially formed on the base substrate 110 on which the data line DL is formed. .

The data insulating layer 115 covers the data line DL and may include silicon nitride, silicon oxide, or the like.

The light blocking layer 240 is formed on the data insulating layer 115. In the subsequent process of etching the light blocking layer 240, since the semiconductor layer 220 is exposed to an etchant, the light blocking layer 240 includes a material having an etch selectivity with respect to the semiconductor layer 220 It is preferred.

For example, the light blocking layer 240 may include one or more of metal, alloy, insulating inorganic material, and organic material. Preferably, the light-shielding layer 240 may include one or more of a silicon-germanium alloy, germanium, titanium oxide, and more preferably, the light-shielding layer 24 includes a silicon-germanium alloy.

In an embodiment of the invention, the channel may include an oxide semiconductor. The oxide semiconductor is particularly vulnerable to ultraviolet light having a wavelength of about 450 nm or less, and the silicon-germanium alloy has excellent light blocking ability of ultraviolet light. Therefore, when the thin film transistor substrate is used in a display device, ultraviolet rays generated by a light source or the like can be effectively blocked to protect a channel.

In an embodiment of the invention, when the light-shielding layer 24 includes the silicon-germanium alloy, the silicon-germanium alloy may have an amorphous state, and the light-shielding layer 240 may be made of a silicon-germanium alloy. It may have a single-layer structure or a multi-layer structure including a silicon-germanium alloy layer and a germanium layer. The germanium layer may be disposed above or below the silicon-germanium alloy layer.

The light blocking layer 240 may have a thickness of about 100 mm 2 to about 2,000 mm 2. When the thickness of the light-shielding layer 240 is less than 100 Å, the light-shielding ability may be lowered and the electrical characteristics of the channel may be reduced. When the thickness of the light-shielding layer 240 exceeds 2,000 ,, the active pattern 120 The signal may be delayed by forming a capacitance with the source region 124 or the drain region 126.

More preferably, the thickness of the light blocking layer 240 may be about 600 mm 2 to about 2,000 mm 2. When the thickness of the light shielding layer 240 is 600 MPa or more, it may have a high optical density.

5 is a graph showing transmittance and absorbance of a light-shielding layer containing a silicon-germanium alloy with respect to wavelength. In FIG. 5, (1) has a single layer structure of a silicon-germanium alloy layer having a thickness of about 300 mm 2, and (2) has a double layer structure of a silicon-germanium alloy layer with a thickness of about 100 mm 2 and a germanium layer with a thickness of about 300 mm 2, (3) has a single layer structure of a silicon-germanium alloy layer with a thickness of about 500 ,, (4) has a double layer structure of a silicon-germanium alloy layer with a thickness of about 300 과 and a germanium layer with a thickness of about 300 Å, (5) It has a single-layer structure of a silicon-germanium alloy layer of about 700 Å thickness, (6) has a double-layer structure of a silicon-germanium alloy layer of about 500 두께 thickness and a germanium layer of about 300 두께 thickness, and (7) has a thickness of about 700 Å. It has a double layer structure of a silicon-germanium alloy layer and a germanium layer having a thickness of about 300 mm 2.

Referring to FIG. 5, it can be seen that compared to the light-blocking layer having a single-layer structure of a silicon-germanium alloy layer, the light-blocking layer having a double-layer structure of a silicon-germanium alloy layer and a germanium layer has lower light transmittance and high absorbance. . In addition, when the thickness of the light-shielding layer is about 600 Å or more, it has a transmittance of about 1% or less with respect to light of 450 nm or less. And 4 or more absorbance.

Therefore, the thin film transistor substrate according to an embodiment of the present invention can increase the reliability of the thin film transistor by using a light blocking layer including a silicon-germanium alloy.

The buffer layer 250 is formed on the light blocking layer 240 and may include insulating oxides such as silicon oxide, aluminum oxide, hafnium oxide, and yttrium oxide.

The semiconductor layer 220 is formed on the buffer layer 250. The semiconductor layer 220 may include polycrystalline silicon, an oxide semiconductor, or the like, but in an embodiment of the present invention, an oxide semiconductor.

The oxide semiconductor may be a metal oxide semiconductor, for example, the oxide semiconductor may include one or a combination of oxides of zinc, indium, gallium, tin, titanium, and phosphorus. Specifically, the oxide semiconductor is zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-gallium-zinc oxide (IGZO) , Indium-zinc-tin oxide (IZTO).

The data insulating layer 115, the light blocking layer 240, the buffer layer 250, and the semiconductor layer 220 are chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (CVD), depending on the material. vapor deposition, PECVD), solution coating, sputtering, or the like.

Referring to FIG. 6, the semiconductor layer 220 is patterned to form a semiconductor pattern 222. Specifically, a photoresist pattern PR is formed on the semiconductor layer 220, and the semiconductor layer 220 is etched using the photoresist pattern PR as a mask.

Referring to FIG. 7, a gate insulating layer 260 and a gate metal layer 290 are formed on the semiconductor pattern 222 and the buffer layer 250.

The gate insulating layer 260 covers the semiconductor pattern 222 and may include silicon nitride, silicon oxide, or the like.

The gate metal layer 290 is formed on the gate insulating layer 260, and may include one or more of copper, silver, chromium, molybdenum, aluminum, titanium, manganese, aluminum, or alloys thereof. It may have a multi-layer structure including a plurality of metal layers containing different materials. For example, the gate metal layer 290 may include a copper layer and a titanium layer formed on and / or below the copper layer.

In another embodiment, the gate metal layer 290 may include a metal layer and an oxide layer formed on and / or below the metal layer. Specifically, the gate metal layer 290 may include a copper layer and an oxide layer formed on and / or below the copper layer. The oxide layer may include indium zinc oxide, indium tin oxide, gallium zinc oxide, zinc aluminum oxide, and the like.

Referring to FIG. 8, the gate metal layer 290 and the gate insulating layer 260 are patterned to form a gate electrode GE, a gate line GL, and a gate insulating pattern 160.

First, the gate metal layer 290 is patterned to form the gate electrode GE and the gate line GL. Next, the gate insulating layer 260 is patterned using the gate electrode GE and the gate line GL as a mask to form a gate insulating pattern 160. Accordingly, the gate insulating pattern 160 has substantially the same shape as the gate electrode GE and the gate line GL in a plan view.

In the process of patterning the gate insulating layer 260, the semiconductor pattern 222 is exposed, but the gate insulating layer 260 includes a different material from the semiconductor pattern 222, and thus has etch selectivity. , The semiconductor pattern 222 is not etched.

In an embodiment of the invention, the gate insulating layer 260 and the buffer layer 250 may include similar materials, and accordingly, the buffer layer 250 is also etched in the process of etching the gate insulating layer 260. Can be. Accordingly, the light blocking layer 240 positioned under the buffer layer 250 is exposed, and the buffer layer 250 positioned under the semiconductor pattern 222 remains to form the buffer pattern 150.

Referring to FIG. 9, the light blocking layer 240 is etched using the gate electrode 160 and the semiconductor pattern 222 as a mask to form a light blocking pattern 140. Accordingly, the data insulating layer 115 is exposed.

10 is a plan view illustrating a light blocking pattern of a thin film transistor substrate according to an embodiment of the present invention.

Referring to FIG. 10, the light blocking pattern 140 extends from the first portion 142 and the first portion 142 overlapping at least a portion of the gate line GL, and the gate electrode GE and It includes a second portion 144 overlapping and a third portion 146 extending from the second portion 144 and overlapping the semiconductor pattern 222.

For example, the first portion 142 extends along the first direction D1, the second portion 144 extends along the second direction D2, and the third portion 146 ) Extends along the first direction D1. In plan view, the edge of the second portion 144 substantially coincides with the edge of the gate electrode GE, and the edge of the third portion 146 substantially coincides with the edge of the semiconductor pattern 222. do. Accordingly, the length W1 of the first direction of the light blocking pattern 140 overlapping the semiconductor pattern 222 is substantially the same as the length of the semiconductor pattern 222 in the first direction, and the gate electrode GE The length W2 in the second direction of the light blocking pattern 140 overlapping with is substantially the same as the length in the second direction of the gate electrode GE.

As illustrated in FIG. 10, the light blocking pattern 140 may overlap with all of the gate line GL, but is not limited thereto, and among the gate lines GL, a portion adjacent to the gate electrode GE and Can only be nested. The gate line GL is formed from a metal layer and has high light reflectance. Therefore, when light is incident on the lower surface of the gate line GL, reflected light enters the channel 122, thereby affecting the electrical characteristics of the thin film transistor. In an embodiment of the invention, the light blocking pattern 140 overlaps at least a portion of the gate line GL, thereby improving reliability of the thin film transistor.

The buffer pattern 150 has substantially the same shape as the light blocking pattern 140 on a plan view.

In an embodiment of the invention, the semiconductor pattern 222 and the light blocking pattern 140 overlapping the gate electrode GE have a cross shape as a whole. However, the shape of the light blocking pattern 140 may vary depending on the shape and arrangement of the semiconductor pattern 222 and the gate electrode GE, and may have, for example, a T-shape, a square shape, or a rectangular shape. It might be.

In another embodiment, the light blocking pattern may not overlap the gate line GL, but may overlap the gate electrode GE and the semiconductor pattern 222. Referring to FIG. 11, the light blocking pattern 141 protrudes in the first direction D1 from the first portion 143 and the first portion 143 overlapping the gate electrode GE, and the semiconductor pattern ( 222) and the second portion 145 overlapping. Thus, on a plan view, the edge of the first portion 143 substantially coincides with the edge of the gate electrode GE, and the edge of the second portion 145 is substantially the edge of the semiconductor pattern 222. Matches. Therefore, the length W1 of the first direction of the light blocking pattern 141 overlapping the semiconductor pattern 222 is substantially the same as the length of the semiconductor pattern 222 in the first direction, and the gate electrode GE The length W2 in the second direction of the light blocking pattern 141 overlapping with is substantially the same as the length in the second direction of the gate electrode GE.

When a separate mask is used to form the light blocking pattern 140, manufacturing cost of a thin film transistor substrate may be increased, and an aperture ratio of a pixel in a display device may be reduced. In an embodiment of the invention, the light blocking layer 240 is patterned using the gate electrode GE, the gate line GL and the semiconductor pattern 222 as a mask, so that the light blocking pattern 140 without a separate mask ), And does not substantially decrease the aperture ratio. In addition, the light blocking pattern 140 may have a larger area than the semiconductor pattern 222, thereby increasing light blocking performance.

Referring to FIG. 9 again, a channel 122, a source region 124 and a drain region 126 are formed from the semiconductor pattern 222. Specifically, the semiconductor pattern 222 exposed without being covered by the gate electrode GE and the gate insulating pattern 160 is converted into a source region 124 and a drain region 126.

For example, when the semiconductor pattern 222 includes a metal oxide, the exposed semiconductor pattern 222 may be plasma treated to form the source region 124 and the drain region 126. For example, hydrogen (H2), helium (He), phosphine (PH3), ammonia (NH3), silane (SiH4), methane (CH4), acetylene (C2H2), diborane (B2H6), carbon dioxide (CO2) , Plasma exposed to plasma gas (PT) such as germane (GeH4), hydrogen selenide (H2Se), hydrogen sulfide (H2S), argon (Ar), nitrogen (N2), nitrogen oxide (N2O), fluorform (CHF3), etc. It can be applied to the pattern 222. Accordingly, at least a portion of the semiconductor material constituting the reduced-treated exposed semiconductor pattern 222 may be reduced and converted into a metallic conductor. Accordingly, the reduced semiconductor pattern 222 forms the source region 124 and the drain region 126, and a portion covered by the gate electrode GE and the gate insulating pattern 160 remains and the channel (122) is formed.

Alternatively, in order to form the source region 124 and the drain region 126, the semiconductor pattern 222 may be heat treated in an atmosphere of a reducing gas or an ion implantation process may be performed.

In an embodiment of the invention, the source region 124 and the drain region 126 are performed after the light blocking layer 240 is patterned, but in other embodiments, the light blocking layer 240 is patterned. It may be.

Referring to FIG. 12, a passivation layer 170 covering the gate electrode GE, the source region 124, the drain region 126, and the data insulating layer 115 is formed, and the passivation layer ( An organic insulating layer 180 is formed on the 170).

The passivation layer 170 may include silicon nitride, silicon oxide, or the like. The organic insulating layer 180 may be formed by flattening the surface of the thin film transistor substrate and spin coating a photoresist composition on the passivation layer 170.

Referring to FIG. 13, contact holes are formed by patterning the data insulating layer 115, the passivation layer 170, and the organic insulating layer 180.

Specifically, the data insulating layer 115, the passivation layer 170 and the organic insulating layer 180 are patterned to form a first contact hole CH1 exposing the data line DL, and the passivation A second contact hole CH2 exposing a portion of the source region 124 and a third contact hole exposing a portion of the drain region 126 by patterning the layer 170 and the organic insulating layer 180 (CH3).

Specifically, after exposing the organic insulating layer 180, the organic insulating layer 180 may be patterned by removing a non-exposed region or an exposed region by applying a developer to the organic insulating layer 180, and the The exposed passivation layer 170 and the data insulating layer 115 are etched using the patterned organic insulating layer 180 as a mask to form the first to third contact holes CH1, CH2, and CH3. You can.

Next, a transparent conductive layer is formed on the organic insulating layer 180. The transparent conductive layer may include indium zinc oxide, indium tin oxide, and the like.

The transparent conductive layer is patterned to form the connection electrode 130 and the pixel electrode PE shown in FIG. 2. The connection electrode 130 contacts the data line DL through the first contact hole CH1 and contacts the source region 124 through the second contact hole CH2. The pixel electrode PE contacts the drain region 124 through the third contact hole CH3.

According to an embodiment of the invention, after the semiconductor pattern 222 is formed, the gate electrode GE is formed, and the light blocking pattern 140 is formed using the semiconductor pattern 222 and the gate electrode GE as masks. By forming), the light blocking pattern 140 can be formed without increasing the mask and substantially without reducing the aperture ratio. In addition, the light blocking pattern 140 may have a larger area than the semiconductor pattern 222 to prevent or reduce the inflow of leakage light.

The thin film transistor substrate according to the embodiment of the described invention may be used as an array substrate of a liquid crystal display device. However, the present invention is not limited to this, and other display devices such as organic EL display devices, circuit boards having thin film transistors, and electronic devices such as semiconductor devices can also be used, and specific configurations of the present invention described in claims It can be changed according to its use without departing from the spirit and scope.

14 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. Specifically, FIG. 14 shows the same cross-section as the thin film transistor substrate shown in FIG. 2.

Referring to FIG. 14, the thin film transistor substrate 300 includes a base substrate 310, a gate line, a data line DL, an active pattern 320, and a light blocking pattern 340.

The active pattern 320 includes a channel 322, a source region 324 and a drain region 326. The channel 322, the source region 324, and the drain region 326 are formed from the same layer, and are successively arranged on the same layer, and between the source region 324 and the drain region 326 Channel 322 is located. The drain region 326 is electrically connected to the pixel electrode PE, and a gate insulating pattern 360 is disposed between the gate electrode GE and the channel 322.

The data line DL is formed on the base substrate 310 and is electrically connected to the source region 324. The data insulating layer 315 covers the data line DL and the base substrate 310.

In an embodiment of the invention, the data line DL is formed directly on the base substrate 310, but in another embodiment, the data line DL may be formed on the passivation layer 370.

The passivation layer 370 covers the gate electrode GE, the active pattern 320 and the data insulating layer 315, and the organic insulating layer 380 covers the passivation layer 370. The pixel electrode PE and the connection electrode 330 are formed on the organic insulating layer 380. The connection electrode 330 is connected to the data line DL through a first contact hole CH1 and is connected to the source region 324 through a second contact hole CH2. The pixel electrode PE is connected to the drain region 326 through a third contact hole CH3.

The light blocking pattern 140 is disposed under the channel 322. The light blocking pattern 140 overlaps the entire active pattern 320 including the channel 322 and the entire gate electrode GE. Therefore, the light blocking pattern 320 has a larger area than the active pattern 320 on a plan view.

In an embodiment of the invention, the thin film transistor substrate does not include the buffer pattern 150 shown in FIG. 2. Therefore, the light blocking pattern 320 and the active pattern 320 may contact each other.

In another embodiment, a buffer layer may be additionally formed between the base substrate 310 and the light blocking pattern 340. In this case, the data line DL may be directly formed on the base substrate 310 or may be formed on the buffer layer.

The thin film transistor substrate 300 is substantially the same as the thin film transistor substrate 100 shown in FIGS. 1 and 2 except that the buffer pattern 150 is not included. Therefore, a detailed description of overlapping will be omitted.

15 to 19 are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 14.

Referring to FIG. 14, first, a data line DL is formed on the base substrate 310. For example, a data metal layer is formed on the base substrate 310 and the data metal layer is etched through a photolithography process to form the data line DL.

After the data line DL is formed, the data insulating layer 315, the light blocking layer 440, and the semiconductor layer 420 are sequentially formed on the base substrate 310.

Referring to FIG. 15, the semiconductor layer 420 is patterned to form a semiconductor pattern 422. Specifically, a photoresist pattern PR is formed on the semiconductor layer 420, and the semiconductor layer 420 is etched using the photoresist pattern PR as a mask.

Referring to FIG. 16, a gate insulating layer 460 and a gate metal layer 490 are formed on the semiconductor pattern 422 and the light blocking layer 440.

Referring to FIG. 17, the gate metal layer 490 and the gate insulating layer 460 are patterned to form a gate electrode GE, a gate line, and a gate insulating pattern 360. First, the gate metal layer 490 is patterned to form a gate electrode GE and a gate line. Next, the gate insulating layer 460 is patterned using the gate electrode GE and the gate line as a mask to form a gate insulating pattern 360. Accordingly, the light blocking layer 440 under the gate insulating layer 460 is exposed.

Referring to FIG. 18, the light blocking layer 440 is etched using the gate electrode 360 and the semiconductor pattern 422 as a mask to form a light blocking pattern 340. Therefore, the light blocking pattern 340 substantially overlaps the entire gate electrode 360 and the entire semiconductor pattern 422. Specifically, the light blocking pattern 340 may have the same shape as the light blocking pattern illustrated in FIG. 10.

A channel 322, a source region 324 and a drain region 326 are formed from the semiconductor pattern 422. Specifically, plasma gas PT or the like is applied to the exposed semiconductor pattern 422 that is not covered by the gate electrode GE and the gate insulating pattern 360, and the source region 324 and the drain region 326 are applied. Convert to The portion covered by the gate electrode GE and the gate insulating pattern 360 forms a channel 322.

The step of applying plasma gas to the exposed semiconductor pattern 422 may be performed after or before patterning the light blocking layer 440.

Next, a passivation layer covering the gate electrode GE, the source region 324, the drain region 326, and the data insulating layer 315 is formed, and an organic insulating layer is formed on the passivation layer. .

Next, the data insulating layer 315, the passivation layer, and the organic insulating layer are patterned to form contact holes. Next, a transparent conductive layer is formed on the organic insulating layer, and the transparent conductive layer is patterned to form a connection electrode 330 and a pixel electrode PE illustrated in FIG. 14.

20 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. Specifically, FIG. 20 shows the same cross-section as the thin film transistor substrate shown in FIG. 2.

Referring to FIG. 20, the thin film transistor substrate 500 includes a base substrate 510, a gate line, a data line DL, an active pattern 520, and a light blocking pattern 540.

The active pattern 520 includes a channel 522, a source region 524 and a drain region 526. The channel 522, the source region 524, and the drain region 526 are formed from the same layer, are arranged in series, and the channel 522 is between the source region 524 and the drain region 526. ) Is located. The drain region 526 is electrically connected to the pixel electrode PE, and a gate insulating pattern 560 is disposed between the gate electrode GE and the channel 522.

The passivation layer 570 covers the gate electrode GE, the active pattern 520 and the base substrate 510, and the organic insulating layer 580 covers the passivation layer 570. The pixel electrode PE and the connection electrode 530 are formed on the organic insulating layer 580. The connection electrode 530 is connected to the data line DL through a first contact hole CH1 and is connected to the source region 524 through a second contact hole CH2. The pixel electrode PE is connected to the drain region 526 through a third contact hole CH3.

The data line DL is formed on the passivation layer 570 and is electrically connected to the source region 524.

The light blocking pattern 540 is disposed under the channel 522. The light blocking pattern 540 overlaps the entire active pattern 520 including the channel 522, and a portion of the gate electrode GE that does not overlap the active pattern 520. Therefore, the light blocking pattern 520 has a larger area than the active pattern 520 on a plan view.

In an embodiment of the invention, the thin film transistor substrate 500 does not include the buffer pattern 150 and the data insulating layer 115 shown in FIG. 2. Therefore, the light blocking pattern 520 and the base substrate 510 may contact each other.

1 and 2 except that the thin film transistor substrate 500 does not include the buffer pattern 150 and the data insulating layer 115, and the data line DL is formed on the passivation layer 570. It is substantially the same as the thin film transistor substrate 100 shown. Therefore, a detailed description of overlapping will be omitted.

21 to 26 are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 20.

Referring to FIG. 21, a light blocking layer 640 and a semiconductor layer 620 are sequentially formed on the base substrate 510.

Referring to FIG. 22, the semiconductor layer 620 is patterned to form a semiconductor pattern 622. Specifically, a photoresist pattern PR is formed on the semiconductor layer 620, and the semiconductor layer 620 is etched using the photoresist pattern PR as a mask.

23, a gate insulating layer 660 and a gate metal layer 690 are formed on the semiconductor pattern 622 and the light blocking layer 640.

Referring to FIG. 24, the gate metal layer 690 and the gate insulating layer 660 are patterned to form a gate electrode GE, a gate line, and a gate insulating pattern 560. First, the gate metal layer 690 is patterned to form a gate electrode GE and a gate line. Next, the gate insulating layer 660 is patterned using the gate electrode GE and the gate line as a mask to form a gate insulating pattern 560. Accordingly, the light blocking layer 640 under the gate insulating layer 660 is exposed.

Referring to FIG. 25, the light blocking layer 640 is etched using the gate electrode 560 and the semiconductor pattern 622 as a mask to form a light blocking pattern 540. Therefore, the light blocking pattern 540 substantially overlaps the entire gate electrode 560 and the entire semiconductor pattern 622. Specifically, the light blocking pattern may have the same shape as the light blocking pattern illustrated in FIG. 10.

A channel 522, a source region 524 and a drain region 526 are formed from the semiconductor pattern 622. Specifically, plasma gas PT or the like is applied to the exposed semiconductor pattern 622 that is not covered by the gate electrode GE and the gate insulating pattern 560, so that the source region 524 and the drain region 526 are applied. Convert to The portion covered by the gate electrode GE and the gate insulating pattern 560 forms a channel 522.

The step of applying a plasma gas to the exposed semiconductor pattern 622 may be performed after or before patterning the light blocking layer 640.

Referring to FIG. 26, a passivation layer 570 covering the gate electrode GE, the source region 524, the drain region 526 and the base substrate 510 is formed. A data metal layer is formed on the passivation layer 570, and the data metal layer is patterned to form a data line DL.

Next, an organic insulating layer covering the data line DL and the passivation layer 570 is formed, and contact holes are formed by patterning the passivation layer 570 and the organic insulating layer. In an embodiment of the invention, an organic insulating layer is directly formed on the data line DL, but in another embodiment, after forming a data insulating layer made of silicon oxide, silicon nitride, or the like, an organic insulating layer is formed on the data insulating layer. You can.

Next, a transparent conductive layer is formed on the organic insulating layer, and the transparent conductive layer is patterned to form a connection electrode 530 and a pixel electrode PE shown in FIG. 20.

27 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. Specifically, FIG. 27 shows the same cross-section as the thin film transistor substrate shown in FIG. 2.

Referring to FIG. 27, the thin film transistor substrate 700 includes a base substrate 710, a gate line, a data line DL, an active pattern 720, a buffer pattern 750 and a light blocking pattern 740.

The active pattern 720 includes a channel 722, a source region 724 and a drain region 726. The channel 722, the source region 724 and the drain region 726 are formed from the same layer, and are arranged continuously, and the channel 722 between the source region 724 and the drain region 726 is formed. ) Is located. The drain region 726 is electrically connected to the pixel electrode PE, and a gate insulating pattern 760 is disposed between the gate electrode GE and the channel 722.

The passivation layer 770 covers the gate electrode GE, the active pattern 720 and the base substrate 710, and the organic insulating layer 780 covers the passivation layer 770. The pixel electrode PE and the connection electrode 730 are formed on the organic insulating layer 780. The connection electrode 730 is connected to the data line DL through a first contact hole CH1 and is connected to the source region 724 through a second contact hole CH2. The pixel electrode PE is connected to the drain region 726 through a third contact hole CH3.

The data line DL is formed on the passivation layer 770 and is electrically connected to the source region 724.

A light blocking pattern 740 is disposed under the channel 722. The light blocking pattern 740 overlaps the entire active pattern 720 including the channel 722, and overlaps a portion of the gate electrode GE not overlapping the active pattern 720. Therefore, the light blocking pattern 720 has a larger area than the active pattern 720 on a plan view.

A buffer pattern 750 is disposed between the light blocking pattern 740 and the active pattern 720. The buffer pattern 750 may have substantially the same shape as the light blocking pattern 740.

In an embodiment of the invention, the thin film transistor substrate 700 does not include the data insulating layer 115 shown in FIG. 2. Therefore, the light blocking pattern 720 and the base substrate 710 may contact each other.

The thin film transistor substrate 700 does not include the data insulating layer 115, except that the data line DL is formed on the passivation layer 770, the thin film transistor substrate 100 shown in FIGS. 1 and 2 ). Therefore, a detailed description of overlapping will be omitted.

28 to 33 are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 27.

Referring to FIG. 28, a light blocking layer 840, a buffer layer 850 and a semiconductor layer 820 are sequentially formed on the base substrate 710.

Referring to FIG. 29, the semiconductor layer 820 is patterned to form a semiconductor pattern 822. Specifically, a photoresist pattern PR is formed on the semiconductor layer 820, and the semiconductor layer 820 is etched using the photoresist pattern PR as a mask.

Referring to FIG. 30, a gate insulating layer 860 and a gate metal layer 890 are formed on the semiconductor pattern 822 and the buffer layer 850.

Referring to FIG. 31, the gate metal layer 890 and the gate insulating layer 860 are patterned to form a gate electrode GE, a gate line, and a gate insulating pattern 760. First, the gate metal layer 890 is patterned to form a gate electrode GE and a gate line. Next, the gate insulating layer 860 is patterned using the gate electrode GE and the gate line as a mask to form a gate insulating pattern 760. Accordingly, the buffer layer 850 under the gate insulating layer 860 is exposed.

Referring to FIG. 32, the buffer layer 850 and the light blocking layer 840 are etched using the gate electrode 760 and the semiconductor pattern 822 as masks, so that the buffer pattern 750 and the light blocking pattern 740 are etched. ). Accordingly, the buffer pattern 750 and the light blocking pattern 740 substantially overlap the entire gate electrode 760 and the semiconductor pattern 822. Specifically, the light blocking pattern 740 may have the same shape as the light blocking pattern illustrated in FIG. 10.

A channel 722, a source region 724 and a drain region 726 are formed from the semiconductor pattern 822. Specifically, plasma gas PT or the like is applied to the exposed semiconductor pattern 822 that is not covered by the gate electrode GE and the gate insulating pattern 760, and the source region 724 and the drain region 726 are applied. Convert to The portion covered by the gate electrode GE and the gate insulating pattern 760 forms a channel 722.

The step of applying a plasma gas to the exposed semiconductor pattern 822 may be performed after or before patterning the light blocking layer 840.

Referring to FIG. 33, a passivation layer 770 covering the gate electrode GE, the source region 724, the drain region 726 and the base substrate 710 is formed. A data metal layer is formed on the passivation layer 770, and the data metal layer is patterned to form a data line DL.

Next, an organic insulating layer covering the data line DL and the passivation layer 770 is formed, and contact holes are formed by patterning the passivation layer 770 and the organic insulating layer.

Next, a transparent conductive layer is formed on the organic insulating layer, and the transparent conductive layer is patterned to form a connection electrode 730 and a pixel electrode PE shown in FIG. 27.

Although described with reference to the above embodiments, those skilled in the art understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. Will be able to.

The method of manufacturing a thin film transistor substrate and a thin film transistor substrate according to embodiments of the present invention can be used in display devices and electronic devices such as liquid crystal display devices, organic EL display devices, circuit boards having thin film transistors, and semiconductor devices.

100, 300, 500, 700: thin film transistor substrate
110, 310, 510, 710: base substrate
GL: Gate line DL: Data line
GE: Gate electrode PE: Pixel electrode
120, 320, 520, 720: active pattern
140, 340, 540, 740: shading pattern
130, 330, 530, 730: connecting electrode
115, 315: data insulating layer 150, 750: buffer pattern
160, 360, 560, 760: gate insulation pattern
CH1, CH2, CH3: Contact hole
170, 370, 570, 770: passivation layer
180, 380, 580, 780: organic insulating layer

Claims (8)

delete delete delete Forming a light shielding layer on the base substrate;
Forming a semiconductor layer on the light blocking layer;
Patterning the semiconductor layer to form a semiconductor pattern;
Sequentially forming a gate insulating layer and a gate metal layer on the semiconductor pattern;
Forming a gate electrode by patterning the gate metal layer;
Patterning the gate insulating layer to form a gate insulating pattern; And
And using the gate electrode and the semiconductor pattern as a mask, and patterning the light blocking layer to form a light blocking pattern having a larger area than the semiconductor pattern. The method of claim 4, further comprising forming a source region and a drain region by plasma processing the exposed semiconductor pattern after forming the gate insulation pattern, wherein the semiconductor pattern comprises metal oxide. Method for manufacturing a thin film transistor substrate. According to claim 5, Before forming the light-shielding layer,
Forming a data line on the base substrate; And
And forming a data insulating layer covering the data line. The method of claim 5, further comprising forming a buffer layer on the light blocking layer before forming the semiconductor layer. The method of claim 5, further comprising forming a buffer layer on the base substrate before forming the light blocking layer.

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