KR20190078031A - Multi-layered electronic component - Google Patents

Abstract

The present invention relates to a multilayer electronic component. The multilayer electronic component comprises: a multilayer capacitor including a capacitor body having first and second external electrodes formed on both ends thereof; an encapsulation unit encapsulating the multilayer capacitor so that lower surfaces of the first and second external electrodes are exposed; an electrode connection chip including a chip body which is made of alumina and has first and second external terminals formed on both ends thereof to correspond to the first and second external electrodes, and disposed below the multilayer capacitor; and first and second conductive connecting portions containing 90 parts by weight of at least one among copper (Cu), silver (Ag), nickel (Ni), palladium (Pd), and platinum (Pt) or alloys thereof with respect to 100 parts by weight thereof, and disposed to connect the first and second external electrodes to the first and second external terminals, respectively. Thus, moisture resistance reliability can be improved.

Description

[0001] MULTI-LAYERED ELECTRONIC COMPONENT [0002]

The present invention relates to a multilayer electronic component.

A multilayer capacitor, which is one of the multilayer chip electronic components, is widely used as a display device such as a liquid crystal display (LCD) and a plasma display panel (PDP), a computer, a personal digital assistant (PDA) It is a chip type capacitor which is mounted on circuit boards of various electronic products such as mobile phones and plays a role of charging or discharging electricity.

Such a multi-layered ceramic capacitor (MLCC) can be used as a component of various electronic devices because of its small size, high capacity, and ease of mounting.

The stacked capacitor may have a structure in which a plurality of dielectric layers and internal electrodes of different polarities are alternately stacked between the dielectric layers.

In recent years, with the tendency of ultra-high capacity and miniaturization of electronic components, such a stacked capacitor has a tendency of becoming smaller in size, increasing the number of stacked internal electrodes and approaching the distance between internal electrodes, The reliability of the capacitor is significantly degraded.

Particularly, in the process of plating the external electrodes of the multilayer capacitor, a plating liquid or other water permeates into a portion where the density of the external electrode is low, and the moisture resistance reliability of the multilayer capacitor deteriorates frequently.

Korean Patent Laid-Open Publication No. 2016-0085547 Korean Patent Laid-Open Publication No. 2016-0055424

It is an object of the present invention to provide a multilayer electronic component capable of improving moisture resistance reliability of a multilayer capacitor.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a stacked capacitor including a capacitor body having first and second external electrodes formed on both ends thereof; An encapsulating unit for encapsulating the stacked capacitor so that the lower surfaces of the first and second external electrodes are exposed; An electrode connecting chip disposed on the lower side of the multilayer capacitor, the multilayer capacitor comprising: a chip body made of alumina and having first and second external terminals formed on both ends so as to correspond to the first and second external electrodes; And at least one of copper (Cu), silver (Ag), nickel (Ni), palladium (Pd) and platinum (Pt) or an alloy thereof in an amount of 90 parts by weight or more based on 100 parts by weight of the total And first and second conductive connection parts arranged to connect the second external electrode and the first and second external terminals, respectively; And a plurality of electronic components.

In one embodiment of the present invention, the encapsulation may include at least one of parylene, epoxy, and silicone.

In one embodiment of the present invention, the first and second external electrodes of the multilayer capacitor include first and second connection portions formed on both sides of the capacitor body in the longitudinal direction thereof, and first and second connection portions, And may include first and second band portions extending to a portion of both sides of the body in the thickness direction and a portion of both sides in the width direction.

In an embodiment of the present invention, the first and second external terminals of the electrode connection chip include third and fourth connecting portions formed on both sides in the length direction of the chip body, and third and fourth connecting portions A nickel plating layer formed on a surface of the first and second external terminals and a nickel plating layer formed on a surface of the first and second external terminals, And a tin plating layer formed on the surface of the tin plating layer.

In one embodiment of the present invention, the capacitor body includes a dielectric layer and first and second internal electrodes alternately arranged with the dielectric layer interposed therebetween, one end of each of which is exposed through both surfaces in the longitudinal direction of the capacitor body .

In one embodiment of the present invention, the chip body may include third and fourth internal electrodes, one end of each of which is exposed through both sides in the longitudinal direction of the chip body.

According to an embodiment of the present invention, an electrode connecting chip made of alumina is disposed so as to be electrically connected to a lower portion of the stacked capacitor by a conductive connecting portion. The stacked capacitor is sealed with a sealing portion so that the lower surface of the external electrode is exposed, Forming the plating layer only on the external terminals of the chip has the effect of improving the moisture resistance reliability of the multilayer capacitor without deteriorating the electrical connectivity.

1 is a perspective view showing a multilayer electronic component according to an embodiment of the present invention.
Fig. 2 is an exploded perspective view showing the laminated electronic component of Fig. 1 separated into a laminated capacitor and an electrode connecting chip.
3 is a front view of Fig.
4 is a perspective view showing a part of the stacked type capacitor among the stacked electronic components of FIG.
5 (a) and 5 (b) are plan views showing the structure of the first and second internal electrodes of the stacked capacitor of FIG.
Fig. 6 is a perspective view showing a part of the electrode connection chip of the multilayer electronic component of Fig. 1 cut away. Fig.
7 (a) and 7 (b) are plan views showing structures of third and fourth internal electrodes of the electrode connection chip of Fig. 6;

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below.

Further, the embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art.

The shape and size of elements in the drawings may be exaggerated for clarity.

In the drawings, like reference numerals are used to designate like elements that are functionally equivalent to the same reference numerals in the drawings.

In order to clearly illustrate the embodiment of the present invention, when the directions of the respective components are defined, X, Y, and Z shown in the drawings indicate the longitudinal direction, the width direction, and the thickness direction, respectively. Here, the thickness direction can be used in the same concept as the lamination direction in which the dielectric layers are laminated in the lamination type capacitor.

Stacked electronic component

FIG. 1 is a perspective view showing a multilayer electronic component according to an embodiment of the present invention, FIG. 2 is an exploded perspective view showing the multilayer electronic component of FIG. 1 separated by a multilayer capacitor and an electrode connecting chip, Fig.

1 to 3, a multilayer electronic device according to an embodiment of the present invention includes a stacked capacitor 100, an encapsulation unit 140, an electrode connection chip 200, and first and second conductive connection units 151 , 152).

The stacked capacitor 100 includes first and second external electrodes 131 and 132 formed at both ends of the capacitor body 110 and the capacitor body 110 in the X direction.

The electrode connecting chip 200 is connected to the lower surface of the multilayer capacitor 100 in the mounting direction and is provided at both ends of the chip body 210 and the chip body 210 in the X direction. And first and second external terminals 231 and 232 serving as terminals for mounting on the substrate so as to correspond to the second external electrodes 131 and 132 and to be connected to each other.

The encapsulant 140 is formed to encapsulate the remaining portion of the stacked capacitor 100 except the lower surface thereof.

That is, a portion of the lower surface of the capacitor body 110 and the lower surface of the capacitor body 110 of the first and second external electrodes 131 and 132 of the stacked capacitor 100 is not covered by the sealing portion 140 It becomes an open state.

Also, the sealing portion 140 may be formed of a material having at least one of parylene, epoxy, and silicone, which is preferably a stretchable material.

The parylene has an excellent insulating property and chemical resistance, and has an advantage that a sealing portion 140 can be formed by making the thickness of a thin film uniform by CVD (Chemical Vapor Deposition) method.

In this embodiment, the thickness of the sealing portion 140 may be 1 占 퐉 or more. If the thickness of the sealing portion 140 is less than 1 占 퐉, there is a problem that the insulating property of the insulating film is insufficient in the plating process and is plated or destroyed by an external force.

The sealing portion 140 prevents a short between the first and second external electrodes 131 and 132 of the stacked capacitor 100 and prevents the plating solution from penetrating into the stacked capacitor 100 during the plating process, It is possible to prevent defects of the stacked capacitor 100 caused by the capacitor.

At least one of copper (Cu), silver (Ag), nickel (Ni), palladium (Pd), and platinum (Pt) or a mixture thereof is added to 100 parts by weight of the total of the first and second conductive connecting portions 151 and 152 Of the alloy may be contained in an amount of 90 parts by weight or more.

When the content of at least one of copper (Cu), silver (Ag), nickel (Ni), palladium (Pd) and platinum (Pt) or an alloy thereof is less than 90 parts by weight based on 100 parts by weight of the total 100 parts by weight, The ESR of the product may rise.

The first and second conductive connection portions 151 and 152 are disposed on the upper surfaces of the first and second external terminals 231 and 232 of the chip 200 for electrode connection, And the second external electrodes 131 and 132, respectively.

That is, the first and second conductive connection portions 151 and 152 are interposed between the upper surfaces of the first and second external terminals 231 and 232 and the lower surfaces of the first and second external electrodes 131 and 132, respectively The laminated capacitor 100 and the alumina chip 200 are mechanically joined together with the first and second conductive connection portions 151 and 152 being electrically connected to each other.

As described above, only the stacked capacitor is encapsulated in the encapsulation unit, the chip for electrode connection is not coated with the encapsulation unit, and only the external terminals of the electrode connection chip connected to the substrate by lead are plated, The penetration of the plating liquid into the stacked capacitor can be prevented.

In the case of the multilayer electronic component of the present embodiment, the electrode connecting chip 200 arranged close to the mounting surface relieves the stress or vibration due to the piezoelectricity of the multilayer capacitor 100 by the elastic force of the chip body 210 An effect of reducing acoustic noise generated in the substrate when mounted on the substrate can be expected.

Stacked capacitor

FIG. 4 is a perspective view showing a part of the multilayered capacitor among the multilayered electronic components of FIG. 1, and FIGS. 5 (a) and 5 (b) show the structure of the first and second internal electrodes of the multilayered capacitor of FIG. FIG.

4 to 5 (b), a stacked capacitor 100 according to the present embodiment includes a capacitor body 110, a plurality of first and second inner electrodes 121 and 122, 2 external electrodes 131 and 132, respectively.

The capacitor body 110 is formed by laminating a plurality of dielectric layers 111 and then firing the capacitor body 110. The shape and dimensions of the capacitor body 110 and the number of stacked layers of the dielectric layer 111 are not limited to those shown in this embodiment .

In the present embodiment, for convenience of explanation, both sides of the capacitor body 110 facing each other in the Z direction are referred to as first and second surfaces 1 and 2, and both surfaces facing each other in the X direction are referred to as third and fourth The surfaces 3 and 4 are defined by the fifth and sixth surfaces 5 and 6 facing each other in the Y direction, and the first surface 1 may be a surface facing the mounting direction.

A plurality of dielectric layers 111 forming the capacitor body 110 are in a sintered state and the boundaries between the adjacent dielectric layers 111 are such that it is difficult to confirm without using a scanning electron microscope (SEM) Can be integrated.

The dielectric layer 111 may include a ceramic powder having a high dielectric constant, for example, a barium titanate (BaTiO ₃ ) -based or a strontium titanate (SrTiO ₃ ) -based powder, but the present invention is not limited thereto.

The capacitor body 110 includes an active region in which the first and second internal electrodes 121 and 122 are alternately stacked in the Z direction with a dielectric layer 111 serving as a portion contributing to capacity formation of the capacitor interposed therebetween, And upper and lower covers 112 and 113 respectively formed on the upper and lower surfaces of the upper and lower marginal portions.

The upper and lower covers 112 and 113 may have the same material and configuration as the dielectric layer 111 except that they do not include internal electrodes.

The upper and lower covers 112 and 113 may be formed by laminating a single dielectric layer or two or more dielectric layers on the upper and lower surfaces of the active region in the Z direction, respectively. Basically, the first and second It is possible to prevent the internal electrodes 121 and 122 from being damaged.

The first and second internal electrodes 121 and 122 are electrodes having different polarities. A conductive paste containing a conductive metal is printed on the dielectric layer 111 to have a predetermined thickness, and one end of the conductive paste is connected to the capacitor body 110 , And may be electrically insulated from each other by the dielectric layer 111 disposed in the middle.

The first and second internal electrodes 121 and 122 are electrically connected to the first and second external electrodes 131 and 132 through the third and fourth faces 3 and 4 of the capacitor body 110, To be electrically connected to each other.

When a voltage is applied to the first and second external electrodes 131 and 132, charges are accumulated between the first and second internal electrodes 121 and 122 opposing each other. At this time, the capacitance of the stacked capacitor 100 Is proportional to the area of the first and second internal electrodes 121 and 122 overlapping each other in the active region.

The conductive metal included in the conductive paste forming the first and second internal electrodes 121 and 122 may be nickel (Ni), copper (Cu), palladium (Pd), or an alloy thereof. But is not limited thereto.

The conductive paste may be printed by a screen printing method or a gravure printing method, but the present invention is not limited thereto.

The first and second external electrodes 131 and 132 may be formed of a conductive paste including a conductive metal such as nickel (Ni), copper (Cu), palladium (Pd) Gold (Au), or an alloy thereof, but the present invention is not limited thereto.

The first and second external electrodes 131 and 132 may include first and second connecting portions 131a and 132a and first and second band portions 131b and 132b, respectively.

The first and second connection portions 131a and 132a are formed on the third and fourth surfaces 3 and 4 of the capacitor body 110 and are respectively connected to the first and second internal electrodes 121 and 122 .

The first and second band portions 131b and 132b are portions extending from the first and second connection portions 131a and 132a to a portion of the first surface 1 of the capacitor body 110.

The first and second band portions 131b and 132b may be formed by a part of the second surface 2 of the capacitor body 110 and a part of the fifth and sixth surfaces 5 and 6 Respectively.

Chip for electrode connection

FIG. 6 is a perspective view showing a part of the chip for electrode connection among the stacked electronic components of FIG. 1, and FIGS. 7 (a) and 7 (b) Fig.

6 and 7 (b), an electrode connection chip 200 according to the present embodiment includes a chip body 210, a plurality of third and fourth internal electrodes 221 and 222, And second external electrodes 231 and 232.

The chip body 210 may be made of alumina (Al 2 O 3), and the shape and dimensions of the chip body 210 are not limited to those shown in the present embodiment.

When the chip body 210 is made of alumina, the alumina has a higher strength than the ceramic and the dielectric, which constitute the capacitor body 110. Therefore, when the chip body 210 is disposed below the stacked capacitor 100 in the stacked type electronic part, The vibration displacement can be suppressed and absorbed and the acoustic noise can be reduced during mounting on the substrate.

In this embodiment, both sides facing each other in the Z direction of the chip body 210 are referred to as the seventh and eighth sides 7 and 8, and both sides facing each other in the X direction are referred to as the ninth and tenth sides The faces 9 and 10 are defined by the eleventh and twelfth faces 11 and 12 facing each other in the Y direction, and the seventh face 7 may be a face facing the mounting direction.

The third and fourth internal electrodes 221 and 222 are electrodes having different polarities so that one end is alternately exposed along the Z direction through the ninth and tenth surfaces 9 and 10 of the chip body 210 And can be electrically isolated from one another by the alumina material disposed in the middle.

The third and fourth internal electrodes 221 and 222 are electrically connected to the first and second external terminals 231 and 232 through the ninth and tenth surfaces 9 and 10 of the chip body 210, To be electrically connected to each other.

The conductive metal included in the conductive paste forming the third and fourth internal electrodes 221 and 222 may be nickel (Ni), copper (Cu), palladium (Pd), or an alloy thereof. But is not limited thereto.

In the present embodiment, the third and fourth internal electrodes 221 and 222 may shorten the current path of the multilayer electronic component to lower the equivalent series resistance (ESR) of the product .

The first and second external terminals 231 and 232 may be formed of a conductive paste containing a conductive metal such as nickel (Ni), copper (Cu), palladium (Pd), gold (Au) Or an alloy thereof, and the present invention is not limited thereto.

At this time, the first and second external terminals 231 and 232 may further include a plating layer on the surface thereof.

The plating layer may be a nickel (Ni) plating layer and a tin (sn) plating layer formed on the nickel plating layer.

The first and second external terminals 231 and 232 may include third and fourth connecting portions 231a and 232a and third and fourth band portions 231b and 232b, respectively.

The third and fourth connecting portions 231a and 232a are portions formed on the ninth and tenth surfaces 9 and 10 of the chip body 210 and connected to the third and fourth internal electrodes 221 and 222, respectively .

The third and fourth band portions 231b and 232b are portions extending from the third and fourth connecting portions 231a and 232a to a portion of the seventh face 7 of the chip body 210.

At this time, the third and fourth band portions 231b and 232b may be formed in a part of the eighth surface 8 of the chip body 210 and a part of the eleventh and twelfth surfaces 11 and 12 Respectively.

When manufacturing a laminated capacitor, the process in which water or other liquid penetrates into the inside of the laminated capacitor is a plating process.

Therefore, in order to improve moisture resistance, it is necessary to seal the surface of the stacked capacitor so as to omit the plating process or to protect the stacked capacitor from the plating solution when manufacturing the stacked capacitor.

However, since the multilayer capacitor is a component finally mounted on the substrate by soldering, it is difficult to omit the step of forming the plating layer on the external electrode. When the surface of the multilayer capacitor is entirely sealed and then plated, the external electrode is not plated This plating process becomes meaningless.

In this embodiment, the capacitor body of the multilayer capacitor is coated with the sealing portion before the plating process, and only the electrode connection chip used for soldering connection with the substrate is left without being sealed with the sealing portion so as to be plated.

Therefore, the solder can be mounted on the substrate through the electrode connection chip, so that the electrical connection is not deteriorated, and the capacitor body of the stacked capacitor is sealed through the sealing part, thereby preventing the humidity resistance caused by the plating solution and other moisture.

The surface of the first and second external electrodes 131 and 132 is coated with a plating solution by a plating process so that the surfaces of the first and second external electrodes 131 and 132 are plated The solder is prevented from rising on the first and second external electrodes 131 and 132 of the stacked capacitor 100 even if the amount of solder is large when the substrate is mounted on the substrate, 1 and the second external electrodes 131 and 132, it is possible to further improve the effect of reducing the acoustic noise.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. It will be obvious to those of ordinary skill in the art.

100: stacked capacitor
110: Capacitor body
111: dielectric layer
121 and 122: first and second inner electrodes
131, 132: first and second outer electrodes
140:
151, 152: first and second conductive connection portions
200: Chip for electrode connection
210: Chip body
221, 222: third and fourth inner electrodes
231, 232: first and second external terminals

Claims (6)

A stacked capacitor including a capacitor body having first and second external electrodes formed on both ends thereof;
An encapsulating unit for encapsulating the stacked capacitor so that the lower surfaces of the first and second external electrodes are exposed;
An electrode connecting chip disposed on the lower side of the multilayer capacitor, the multilayer capacitor comprising: a chip body made of alumina and having first and second external terminals formed on both ends so as to correspond to the first and second external electrodes; And
Wherein at least one of copper (Cu), silver (Ag), nickel (Ni), palladium (Pd) and platinum (Pt) or an alloy thereof is contained in an amount of 90 parts by weight or more, First and second conductive connection portions arranged to connect the second external electrode and the first and second external terminals, respectively; Wherein the electronic device is a multilayer electronic device.
The method according to claim 1,
Wherein the encapsulation portion comprises at least one of parylene, epoxy, and silicone.
The method according to claim 1,
The first and second external electrodes of the multilayer capacitor include first and second connection portions formed on both surfaces of the capacitor body in the longitudinal direction thereof and first and second connection portions formed on both sides of the capacitor body in the thickness direction of the capacitor body And first and second band portions each extending to a portion of both sides in the width direction.
The method according to claim 1,
Wherein the first and second external terminals of the electrode connection chip include third and fourth connecting portions formed on both sides of the chip body in the longitudinal direction thereof and second and fourth connecting portions formed on both sides in the thickness direction of the chip body at the third and fourth connecting portions, And third and fourth connecting portions extending to a portion of both sides in the width direction,
A nickel plating layer formed on the surfaces of the first and second external terminals, and a tin plating layer formed on the surface of the nickel plating layer.
The method according to claim 1,
Wherein the capacitor body includes a dielectric layer and first and second internal electrodes which are alternately arranged with the dielectric layer interposed therebetween, and one end thereof is exposed through both longitudinal sides of the capacitor body, respectively.
The method according to claim 1,
Wherein the chip body includes third and fourth internal electrodes, one end of each of which is exposed through both sides in the longitudinal direction of the chip body, respectively.

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