KR20190066205A - Display Device - Google Patents

Abstract

The present invention relates to a display device capable of increasing an opening ratio of a sub-pixel and preventing light leakage. According to an embodiment of the present invention, the display device comprises a first sub-pixel located on a substrate. The first sub-pixel includes: a first gate line located on the substrate; a first data line crossing the first gate line; a light emitting region arranged in parallel with the first data line and including an organic light emitting diode; and a circuit region arranged in parallel with the light emitting region, arranged to be in neighborhood with the first data line with the light emitting region interposed therebetween, and including a plurality of thin film transistors and capacitors.

Description

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device capable of improving the aperture ratio of a subpixel and preventing light leakage.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. The display field has rapidly changed to a thin, light, and large-area flat panel display device (FPD) that replaces bulky cathode ray tubes (CRTs). The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and an electrophoretic display device : ED).

Among these organic electroluminescent display devices, self-luminous elements emit self-luminous elements, which have the advantage of high response speed and high luminous efficiency, brightness and viewing angle. In particular, the organic light emitting display device can be formed on a flexible flexible substrate, and can be driven at a lower voltage than a plasma display panel or an inorganic electroluminescence (EL) display, and the power consumption is relatively low It has the advantage of excellent color.

In the organic light emitting diode display, three subpixels of red, green, and blue form one unit pixel, or four subpixels constitute one unit pixel by adding white. The organic light emitting display device is designed to improve the display quality by increasing the aperture ratio of each subpixel. At this time, since the light emitting regions of the respective subpixels are disposed adjacent to each other, a light leakage occurs in which light of adjacent subpixels is emitted through the other subpixels.

The present invention provides a display device capable of improving the aperture ratio of sub-pixels and preventing light leakage.

According to an aspect of the present invention, there is provided a display device including a first sub-pixel positioned on a substrate, a first gate line positioned on the substrate, A first data line intersecting with the first gate line, a light emitting region arranged in parallel with the first data line and including an organic light emitting diode, and a second light emitting region arranged in parallel with the light emitting region, And a circuit region disposed adjacent to the data line and including a plurality of thin film transistors and a capacitor.

And a second sub-pixel adjacent to the first sub-pixel, wherein the second sub-pixel includes a second data line intersecting the first gate line, an organic light emitting diode disposed in parallel with the second data line, And a circuit region disposed in parallel with the light emitting region and disposed adjacent to the second data line with the light emitting region interposed therebetween, the circuit region including a plurality of thin film transistors and a capacitor.

The circuit region of the first subpixel and the circuit region of the second subpixel are arranged side by side and are adjacent to each other.

And a first power line that is aligned with the first data line on the outer side of the first data line and is shared by the first sub pixel and the second sub pixel, respectively.

And a sensing line shared on the outer side of the second data line with the first subpixel and the second subpixel, respectively.

And a third subpixel and a fourth subpixel that are symmetrical to the first and second subpixels with respect to the sensing line, and the sensing line is shared by the third subpixel and the fourth subpixel .

The third subpixel includes a third data line adjacent to the sensing line and the fourth subpixel includes a fourth data line on the outside of the fourth subpixel in parallel with the third data line.

And a second power line which is arranged outside the fourth data line and is shared by the fourth data line and is shared by the third subpixel and the fourth subpixel, respectively.

A second gate line disposed below the first through fourth subpixels, and fifth through eighth subpixels connected to the second gate line and having the same structure as the first through fourth subpixels, respectively .

The first subpixel and the fifth subpixel emit the same color, and the color filters of the first subpixel and the fifth subpixel are connected in series.

A display device according to an embodiment of the present invention includes circuit regions disposed between neighboring subpixels by disposing a circuit region apart from a data line with a light emitting region of the subpixel interposed therebetween. Therefore, it is possible to prevent light leakage between adjacent sub-pixels from occurring.

In addition, the display device according to an embodiment of the present invention continuously forms the color filter of the sub-pixels emitting the same color in the adjacent sub-pixels, thereby improving the aperture ratio of the sub-pixels and facilitating the manufacturing process of the color filter .

In addition, the display device according to an embodiment of the present invention can reduce parasitic capacitors that may occur between the first electrode and the gate line by forming the gate line adjacent to the first electrode of each subpixel as a light blocking layer.

1 is a schematic block diagram of an organic light emitting diode display.
2 is a schematic circuit configuration diagram of a subpixel.
3 is a detailed circuit diagram of a subpixel.
4 is a sectional view of a display panel;
Figure 5 schematically illustrates a planar layout of subpixels according to the present invention;
6 illustrates a planar layout of a subpixel of the present invention.
7 is a cross-sectional view taken along the cutting line A-A 'in Fig. 6;
8 is a simplified plan view layout of subpixels in accordance with an embodiment of the present invention.
Figure 9 illustrates a detailed layout of subpixels according to an embodiment of the present invention.
10 is a sectional view taken along the cutting line B-B 'in Fig. 9;
11 is a sectional view taken along the cutting line C-C 'in Fig. 9;

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, a detailed description of known technologies or configurations related to the present invention will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured. In addition, the component names used in the following description may be selected in consideration of easiness of specification, and may be different from the parts names of actual products.

A display device according to the present invention is a display device in which a display element is formed on a glass substrate or a flexible substrate. As an example of the display device, an organic light emitting display device, a liquid crystal display device, an electrophoretic display device, or the like can be used. In the present invention, an organic light emitting display device will be described as an example. The organic light emitting diode display includes an organic layer between the first electrode, which is an anode, and the second electrode, which is a cathode. Therefore, the holes supplied from the first electrode and the electrons supplied from the second electrode are combined in the organic layer to form excitons, which are hole-electron pairs, and the excitons emit light by energy generated when the excitons return to the ground state Emitting display device.

FIG. 1 is a schematic block diagram of an organic light emitting display device, FIG. 2 is a schematic circuit configuration diagram of a subpixel, FIG. 3 is a detailed circuit configuration diagram of a subpixel, and FIG.

1, the OLED display includes an image processor 110, a timing controller 120, a data driver 130, a scan driver 140, and a display panel 150.

The image processing unit 110 outputs a data enable signal DE together with a data signal DATA supplied from the outside. The image processing unit 110 may output at least one of a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of explanation.

The timing controller 120 receives a data signal DATA from a video processor 110 in addition to a data enable signal DE or a driving signal including a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal. The timing controller 120 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 130, .

The data driver 130 samples and latches the data signal DATA supplied from the timing controller 120 in response to the data timing control signal DDC supplied from the timing controller 120 and converts the sampled data signal into a gamma reference voltage . The data driver 130 outputs the data signal DATA through the data lines DL1 to DLn. The data driver 130 may be formed in the form of an IC (Integrated Circuit).

The scan driver 140 outputs a scan signal in response to the gate timing control signal GDC supplied from the timing controller 120. The scan driver 140 outputs a scan signal through the gate lines GL1 to GLm. The scan driver 140 is formed in the form of an integrated circuit (IC) or a gate-in-panel (GATE) panel in the display panel 150.

The display panel 150 displays an image corresponding to the data signal DATA and the scan signal supplied from the data driver 130 and the scan driver 140. The display panel 150 includes sub-pixels SP that operate to display an image.

The subpixels SP include a red subpixel, a green subpixel, and a blue subpixel or a white subpixel, a red subpixel, a green subpixel, and a blue subpixel. The subpixels SP may have one or more different emission areas depending on the emission characteristics.

As shown in FIG. 2, one sub-pixel includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode OLED.

The switching transistor SW is operated so that a data signal supplied through the first data line DL1 is stored as a data voltage in the capacitor Cst in response to a scan signal supplied through the first gate line GL1. The driving transistor DR operates so that the driving current flows between the power supply line EVDD (high potential voltage) and the cathode power supply line EVSS (low potential voltage) in accordance with the data voltage stored in the capacitor Cst. The organic light emitting diode OLED operates to emit light in accordance with the driving current generated by the driving transistor DR.

The compensation circuit CC is a circuit added in the sub-pixel to compensate the threshold voltage of the driving transistor DR and the like. The compensation circuit CC is composed of one or more transistors. The configuration of the compensation circuit (CC) varies greatly according to the external compensation method. An example of the compensation circuit (CC) is as follows.

As shown in Fig. 3, the compensation circuit CC includes a sensing transistor ST and a sensing line VREF (or a reference line). The sensing transistor ST is connected between the source electrode of the driving transistor DR and the anode electrode of the organic light emitting diode OLED (hereinafter referred to as a sensing node). The sensing transistor ST supplies the initialization voltage (or sensing voltage) transmitted through the sensing line VREF to the sensing node of the driving transistor DR or the voltage of the sensing node VREF Or to sense the current.

A drain electrode of the switching transistor SW is connected to the first data line DL1, and a source electrode of the switching transistor SW is connected to a gate electrode of the driving transistor DR. In the driving transistor DR, a drain electrode is connected to the power supply line EVDD and a source electrode is connected to the anode electrode of the organic light emitting diode OLED. In the capacitor Cst, the upper electrode is connected to the gate electrode of the driving transistor DR, and the lower electrode is connected to the anode electrode of the organic light emitting diode OLED. In the organic light emitting diode OLED, an anode electrode is connected to the source electrode of the driving transistor DR and a cathode electrode is connected to the second power supply line EVSS. In the sensing transistor ST, a drain electrode is connected to the sensing line VREF, and a source electrode is connected to the anode electrode of the organic light emitting diode OLED, which is a sensing node, and the source electrode of the driving transistor DR.

The operating time of the sensing transistor ST may be similar to, or the same as, or different from that of the switching transistor SW depending on the external compensation algorithm (or the configuration of the compensation circuit). For example, the gate electrode of the switching transistor SW may be connected to the first gate line GL1, and the gate electrode of the sensing transistor ST may be coupled to the second gate line GL2. In this case, a scan signal (Scan) is transmitted to the first gate line (GL1) and a sensing signal (Sense) is transmitted to the second gate line (GL2). As another example, the first gate line GL1 connected to the gate electrode of the switching transistor SW and the second gate line GL2 connected to the gate electrode of the sensing transistor ST may be connected in common.

The sensing line VREF may be connected to the data driver. In this case, the data driver can sense the sensing node of the subpixel during the non-display period of the real time image, or the N frame (N is an integer of 1 or more) and generate the sensing result. On the other hand, the switching transistor SW and the sensing transistor ST can be turned on at the same time. In this case, the sensing operation through the sensing line (VREF) and the data output operation for outputting the data signal are separated (separated) based on the time division system of the data driver.

In addition, the object to be compensated according to the sensing result may be a digital data signal, an analog data signal, gamma, or the like. The compensation circuit for generating the compensation signal (or the compensation voltage) based on the sensing result may be implemented in the interior of the data driver, in the timing controller, or in a separate circuit.

The light blocking layer LS may be disposed only below the channel region of the driving transistor DR or may be disposed not only below the channel region of the driving transistor DR but also below the channel region of the switching transistor SW and the sensing transistor ST. The light blocking layer LS may be used merely for blocking external light, or the light blocking layer LS may be connected to other electrodes or lines and used as an electrode constituting a capacitor or the like. Therefore, the light blocking layer LS is selected as a multi-layered metal layer having a light shielding property.

3, a sub-pixel of a 3T (Capacitor) structure including a switching transistor SW, a driving transistor DR, a capacitor Cst, an organic light emitting diode OLED, and a sensing transistor ST However, if the compensation circuit CC is added, it may be composed of 3T2C, 4T2C, 5T1C, 6T2C, and the like.

As shown in FIG. 4, subpixels are formed on the display area AA of the substrate (or thin film transistor substrate) SUB1 based on the circuit described in FIG. The subpixels formed on the display area AA are sealed by a protective film (or protective substrate) SUB2. NA not otherwise described means non-display area. The substrate SUB1 may be made of glass or a material having ductility.

The subpixels are arranged horizontally or vertically in the order of red (R), white (W), blue (B) and green (G) on the display area AA. The subpixels are red (R), white (W), blue (B), and green (G) However, the arrangement order of the subpixels can be variously changed depending on the light emitting material, the light emitting area, the structure (or structure) of the compensation circuit, and the like. Also, the subpixels may be red (R), blue (B), and green (G) as one pixel (P).

5 is a schematic diagram illustrating a planar layout of subpixels according to the present invention.

4 and 5, a first sub-pixel SPn1 to a fourth sub-pixel SPn4 having a light emitting area EMA and a circuit area DRA are formed on the display area AA of the substrate SUB1, . An organic light emitting diode (light emitting element) is formed in the light emitting region EMA and a circuit including a switching, sensing and driving transistor for driving the organic light emitting diode is formed in the circuit region DRA. The first subpixel SPn1 to the fourth subpixel SPn4 are turned on in response to the operation of switching and driving transistors located in the circuit region DRA so that the organic light emitting diode located in the light emitting region EMA emits light do. WA "positioned between the first subpixel SPn1 to the fourth subpixel SPn4 is a wiring region and includes the power supply line EVDD, the sensing line VREF, the first to fourth data lines DL1- DL4 are disposed. The first and second gate lines GL1 and GL2 are disposed across the first to fourth subpixels SPn1 to SPn4.

The electrodes constituting the thin film transistor as well as the wirings such as the power supply line EVDD, the sensing line VREF and the first to fourth data lines DL1 to DL4 are located on different layers but are connected to each other through the contact holes And are electrically connected due to the contact. The sensing line VREF is connected to each sensing transistor (not shown) of the first to fourth sub-pixels SPn1 to SPn4 through a sensing connection line VREFC. The power supply line EVDD is connected to each driving transistor (not shown) of the first to fourth sub-pixels SPn1 to SPn4 through a power supply connection line EVDDC. The first and second gate lines GL1 and GL2 are connected to respective sensing and switching transistors (not shown) of the first to fourth sub-pixels SPn1 to SPn4.

FIG. 6 is a plan view of a subpixel of the present invention, and FIG. 7 is a cross-sectional view taken along the cutting line A-A 'of FIG.

Referring to FIG. 6, the OLED display of the present invention includes first to fourth sub-pixels GL1 and GL2 intersecting first and second gate lines GL1 and GL2 and first to fourth data lines DL1 to DL4, SPn1 to SPn4) are defined. Specifically, the first to fourth sub-pixels SPn1 to SPn4 connected to the first to fourth data lines DL1 to DL4 are commonly connected to the sensing line VREF. The sensing line VREF is directly connected to the second and third subpixels SPn2 and SPn3 and is connected to the first and fourth subpixels SPn1 and SPn4 through a sensing connection line VREFC. A power supply line EVDD is disposed on both edges of the first to fourth subpixels SPn1 to SPn4 and first and fourth subpixels SPn1 and SPn4 adjacent to the power supply line EVDD are directly connected to each other. 2 and the third sub-pixels SPn2 and SPn3 are connected through a power supply connection line EVDDC.

The first electrode ANO of the organic light emitting diode OLED is disposed in the emission region EMA of each subpixel and the driving transistor DR, the capacitor Cst, and the sensing transistor ST are connected to the circuit region DRA. And a switching transistor SW are disposed. For example, the sensing transistor ST is composed of a gate electrode 240, a drain electrode 250D, a source electrode 250S, and a semiconductor layer 220. [ The sensing line VREF is connected to each sensing transistor ST of the first to fourth sub-pixels SPn1 to SPn4 through a sensing connection line VREFC. The power supply line EVDD is connected to each driving transistor DR of the first to fourth sub-pixels SPn1 to SPn4 through a power supply connection line EVDDC. The first and second gate lines GL1 and GL2 are connected to the respective sensing and switching transistors ST and SW of the first to fourth sub-pixels SPn1 to SPn4.

Reference is made to the cross section of the boundary between the first and second subpixels SPn1 and SPn2 shown in FIG. The first subpixel SPn1 may be a red subpixel and the second subpixel SPn2 may be a white subpixel.

A first buffer layer BUF1, a second buffer layer BUF2, a gate insulating film GI and an interlayer insulating film ILD are sequentially arranged on a substrate SUB and a first data line DL1 and a second data line DL2 are sequentially formed thereon, The line DL2 is arranged. A passivation film PAS is disposed on the first and second data lines DL1 and DL2 and a red color filter CF is disposed in the first subpixel SPn1 region. The overcoat layer OC is disposed on the red color filter CF and the first electrode ANO is disposed on the overcoat layer OC respectively in the first and second subpixels SPn1 and SPn2. On the first electrode ANO, a bank layer BNK defining the light emitting region of each subpixel is disposed.

The first sub-pixel SPn1 is provided with a red color filter CF to emit red light through a red color filter CF. The second sub-pixel SPn2 does not have a color filter, and emits white light as it is. When the red color filter CF of the first subpixel SPn1 partially invades the second subpixel SPn2 region, the red color filter CF) is partially transmitted and becomes reddish. Therefore, display quality is degraded due to light leakage between adjacent sub-pixels.

In the following, a display device for preventing light leakage between the sub-pixels and improving the aperture ratio is disclosed.

<Examples>

FIG. 8 is a simplified plan view of a subpixel according to an exemplary embodiment of the present invention. FIG. 9 is a detailed plan view of a subpixel according to an exemplary embodiment of the present invention. Sectional view taken along the perforated line B-B ', and FIG. 11 is a sectional view taken along the perforated line C-C' shown in FIG.

8 and 9, a first subpixel SPn1 to an eighth subpixel SPn8 having a light emitting region E and a circuit region D are disposed on a substrate SUB1. An organic light emitting diode (light emitting element) is formed in the light emitting region E and a circuit including a switching, sensing, and driving transistor for driving the organic light emitting diode is formed in the circuit region D. The first subpixel SPn1 to the eighth subpixel SPn8 correspond to the operations of the switching and driving transistors located in the circuit region D so that the organic light emitting diode located in the light emitting region E emits light do. The first and second power supply lines EVDD1 and EVDD2, the sensing line VREF and the first to fourth data lines DL1 to DL4 are arranged in the first to eighth subpixels SPn1 to SPn8. do. The first gate line GL1 is arranged across the first subpixel SPn1 to the fourth subpixel SPn4 and the second gate line GL2 is arranged across the fifth subpixel SPn5 to the eighth subpixel SPn5 SPn8.

The electrodes constituting the thin film transistor as well as the wirings such as the power supply line EVDD, the sensing line VREF and the first to fourth data lines DL1 to DL4 are located on different layers, but a contact hole Lt; RTI ID = 0.0 &gt; through &lt; / RTI &gt; The sensing line VREF is connected to each sensing transistor (not shown) of the first to eighth sub-pixels SPn1 to SPn8. The first power supply line EVDD1 is connected to each driving transistor (not shown) of the first, second, fifth and sixth subpixels SPn1, SPn2, SPn5 and SPn6. The second power supply line EVDD2 is connected to each driving transistor (not shown) of the third, fourth, seventh and eighth subpixels SPn3, SPn4, SPn7, SPn8. The first gate line GL1 is connected to each sensing and switching transistor (not shown) of the first to fourth subpixels SPn1 to SPn4 and the second gate line GL2 is connected to the fifth to eighth subpixels SPn5 to SPn8) and a switching transistor (not shown).

Each of the subpixels SPn1 to SPn8 of the present invention has the light emitting region E and the circuit region D arranged in parallel with the first data line DL1. Specifically, the circuit region D1 of the first subpixel SPn1 is disposed in parallel with the light emitting region E1 and is disposed adjacent to the first data line DL1 with the light emitting region E1 interposed therebetween. The circuit region D2 of the second subpixel SPn2 is disposed adjacent to the light emitting region E2 and adjacent to the second data line DL2 with the light emitting region E2 therebetween. The circuit region D1 of the first subpixel SPn1 and the circuit region D2 of the second subpixel SPn2 are arranged side by side and disposed adjacent to each other. The circuit region D3 of the third subpixel SPn3 is disposed in parallel to the light emitting region E3 and is disposed adjacent to the third data line DL3 with the light emitting region E3 interposed therebetween. The circuit region D4 of the fourth subpixel SPn4 is disposed adjacent to the light emitting region E4 and adjacent to the fourth data line DL4 with the light emitting region E4 therebetween. The circuit region D3 of the third subpixel SPn3 and the circuit region D4 of the fourth subpixel SPn4 are arranged side by side and disposed adjacent to each other.

And the fifth to eighth sub-pixels SPn5 to SPn8 are positioned with the second gate line GL2 therebetween. The circuit region D5 of the fifth subpixel SPn5 is disposed adjacent to the light emitting region E5 and adjacent to the first data line DL1 with the light emitting region E5 therebetween. The circuit region D6 of the sixth subpixel SPn6 is disposed adjacent to the light emitting region E6 and adjacent to the second data line DL2 with the light emitting region E6 interposed therebetween. The circuit region D5 of the fifth subpixel SPn5 and the circuit region D6 of the sixth subpixel SPn6 are arranged side by side and disposed adjacent to each other. The circuit region D7 of the seventh subpixel SPn7 is disposed adjacent to the light emitting region E7 and adjacent to the third data line DL3 with the light emitting region E7 interposed therebetween. The circuit region D8 of the eighth subpixel SPn8 is disposed adjacent to the light emitting region E8 and adjacent to the fourth data line DL4 with the light emitting region E8 interposed therebetween. The circuit region D7 of the seventh subpixel SPn7 and the circuit region D8 of the eighth subpixel SPn8 are arranged side by side and disposed adjacent to each other.

On the other hand, a first power line EVDD1 connected to the first data line DL1 and connected to the first and second subpixels SPn1 and SPn2 is connected to the outside of the first data line DL1, . A second power line EVDD2 is arranged outside the fourth data line DL4 and aligned with the fourth data line DL4 and shared by the third subpixel SPn3 and the fourth subpixel SPn4 do. A sensing line shared between the first to fourth subpixels SPn1 is disposed between the second data line DL2 and the second data line DL2 and between the third data line DL3 and the third data line DL3. The third subpixel SPn3 and the fourth subpixel SPn4 are symmetrical to the first subpixel SPn1 and the second subpixel SPn2 with respect to the sensing line VREF. The third subpixel SPn3 includes a third data line DL3 adjacent to the sensing line VREF and the fourth subpixel SPn4 includes a third data line DL3 on the outside of the fourth subpixel SPn4. And a fourth data line DL4 in parallel with the data lines DL1 and DL2. Although not described, the fifth to eighth sub-pixels SPn5 to SPn8 are configured in the same manner as the first to fourth sub-pixels SPn1 to SPn4 described above.

The structure of the first subpixel SPn1 will be described with reference to FIG. 9 with reference to FIG. The first subpixel SPn1 is defined by intersecting the first and second gate lines GL1 and GL2 and the first data line DL1. The first sub-pixel SPn1 includes a driving transistor DR, a sensing transistor ST, a switching transistor SW, a capacitor Cst, and an organic light emitting diode OLED.

A first electrode ANO of the organic light emitting diode OLED is disposed in the light emitting region E1 and a driving transistor DR, a capacitor Cst, a sensing transistor ST, SW) are disposed. For example, the switching transistor SW is composed of a first gate line GL1, a drain electrode 250D, a source electrode 250S, and a semiconductor layer 220. [ The sensing transistor ST also functions as a source electrode 240S connected to the sensing connection line VREFC extending from the sensing line VREF, the first gate line GL1 and the semiconductor layer 230 serving as drain electrodes . The driving transistor DR is composed of a semiconductor layer 230, a gate electrode 260, a source electrode 270S connected to a power supply connection line EVDDC extending from the first power supply line EVDD, and a drain electrode 270D do. The capacitor Cst is composed of a capacitor lower electrode LCst, a capacitor middle electrode MCst, and a first electrode ANO. The first electrode ANO is connected to the drain electrode 270D of the driving transistor DR through the via hole VIA.

On the other hand, in Fig. 6 described above, the emission regions of the respective subpixels are arranged adjacent to each other in the direction in which the gate lines extend. Therefore, light leakage may occur between adjacent sub-pixels. On the other hand, as shown in FIG. 8, in the present invention, the light emitting area E1 / circuit area D1 / second sub-pixel SPn2 of the first sub-pixel SPn1 in the extended direction of the first gate line GL1, A light emitting region E2 is arranged. Since two circuit regions D1 and D2 are disposed between the light emitting region E1 of the first subpixel SPn1 and the light emitting region E2 of the second subpixel SPn2, (D1, D2).

10, on the substrate SUB1 of the first and second subpixels SPn1 and SPn2, a capacitor lower electrode LCst, a capacitor center electrode MCst, and a first electrode ANO And a capacitor Cst including a capacitor Cst. A passivation film PAS is disposed on the capacitor center electrode MCst and a red color filter RCF is disposed on the passivation film PAS. An overcoat layer OC is positioned on a red color filter (RCF), and first electrodes (ANO) of each subpixel are disposed on the overcoat layer (OC). Further, a bank layer BNK for partitioning the light emitting region of each subpixel is located.

8, two circuit regions D1 and D2 are formed between the light emitting region E1 of the first subpixel SPn1 and the light emitting region E2 of the second subpixel SPn2, The capacitor Cst of the pixel SPn1 and the capacitor Cst of the second subpixel SPn2 are disposed to prevent light leakage between adjacent subpixels.

And the red color filter RCF of the first subpixel SPn1 may have a margin that can be further applied to the region where the capacitor Cst of the second subpixel SPn2 is disposed. The two circuit regions D1 and D2 exist between the light emitting region E1 of the first subpixel SPn1 and the light emitting region E2 of the second subpixel SPn2, BNK) can have a wider margin.

7 and FIG. 10, only two data lines are present between the subpixels in FIG. 7, so that a space between the subpixels is narrow and light leakage may occur. 10, since the capacitors Cst are arranged between the first subpixel SPn1 and the second subpixel SPn2, the interval between the first and second subpixels SPn1 and SPn2 is significantly widened It can prevent light leakage. In addition, as the interval between the first and second subpixels SPn1 and SPn2 becomes wider, the red color filter RCF can have a margin that can be further formed toward the second subpixel SPn2, . As the interval between the first and second subpixels SPn1 and SPn2 becomes wider, the bank layer BNK may have a margin, and the margin of the first electrode ANO of the first subpixel SPn1 It becomes wider. As the margins of the red color filter (RCF), the bank layer (BNK), and the first electrode (ANO) are widened, the design becomes free and the aperture ratio can be improved and the process can be facilitated.

Referring again to FIG. 8, the third subpixel SPn3 and the fourth subpixel SPn4 are arranged in the same manner as the first subpixel SPn1 and the second subpixel SPn2, Can be prevented. A sensing line VREF, a second data line DL2 and a third data line DL3 are arranged between the second subpixel SPn2 and the third subpixel SPn3 to form the second subpixel SPn2, Emitting region E2 of the third sub-pixel SPn3 and the light-emitting region E3 of the third sub-pixel SPn3.

On the other hand, the color filters of the present invention are formed consecutively in the extending direction of the data lines, unlike the case of Fig. Specifically, the first subpixel SPn1 and the fifth subpixel SPn5 of the present invention are arranged in the extending direction of the first data line DL1 and emit the same red color to each other. The second subpixel SPn2 and the sixth subpixel SPn6 also emit the same white color. The third subpixel SPn3 and the seventh subpixel SPn7 also emit the same blue color. The fourth subpixel SPn4 and the eighth subpixel SPn8 also emit the same green.

The light emitting region of the subpixel shown in FIG. 6 has a light emitting region that emits a color different from that of the circuit regions, so that the color filter can only be patterned into an island shape. However, since the light emitting region of the subpixel emitting the same color in the extending direction of the first data line DL1 is disposed, the color filter can be continuously formed in the extending direction of the first data line DL1 have. For example, a red color filter (RCF) is formed continuously in the first subpixel SPn1 and the fifth subpixel SPn5. The blue color filter BCF is formed continuously in the third subpixel SPn3 and the seventh subpixel SPn7. The green color filter GCF is formed continuously in the fourth subpixel SPn4 and the eighth subpixel SPn8. As described above, when the color filter is formed continuously, the aperture ratio of the subpixel can be improved.

For example, referring to FIG. 11, which is a cross-sectional view taken along a perforated line C-C 'of FIG. 9, a first gate line GL1 is disposed between subpixels arranged in the extending direction of the first data line. The first gate line GL1 is disposed on the first buffer layer BUF1. The second buffer layer BUF2, the gate insulating film GI, the interlayer insulating film ILD, the passivation film PAS, the red color filter RCF and the overcoat layer OC are sequentially arranged on the first gate line GL1 do. The first electrodes ANO of each subpixel are disposed on the overcoat layer OC. A red color filter (RCF) is formed continuously in adjacent subpixels.

Here, since the first electrodes ANO of the respective subpixels are arranged very close to the first gate line GL1, parasitic capacitors may be generated. However, in the present invention, the first gate line GL1 is formed of a light blocking layer material that is the conductive material closest to the substrate, thereby minimizing parasitic capacitors that may occur in the first electrode ANO and the first gate line GL1 .

As described above, in the display device according to the embodiment of the present invention, circuit regions are arranged between adjacent subpixels by disposing a circuit region apart from a data line with a light emitting region of the subpixel interposed therebetween. Therefore, it is possible to prevent light leakage between adjacent sub-pixels from occurring.

In addition, the display device according to an embodiment of the present invention continuously forms the color filter of the sub-pixels emitting the same color in the adjacent sub-pixels, thereby improving the aperture ratio of the sub-pixels and facilitating the manufacturing process of the color filter .

In addition, the display device according to an embodiment of the present invention can reduce parasitic capacitors that may occur between the first electrode and the gate line by forming the gate line adjacent to the first electrode of each subpixel as a light blocking layer.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

GL1 to GL2: first and second gate lines DL1 to DL4: first to fourth data lines
VREF: sensing lines EVDD1 to EVDD2: first and second power lines
SPn1 to SPn8: first to eighth sub-pixels E1 to E8:
D1 to D8: circuit area

Claims (10)

A first sub-pixel located on a substrate,
The first sub-
A first gate line positioned on the substrate;
A first data line crossing the first gate line;
A light emitting region disposed in parallel with the first data line and including an organic light emitting diode; And
And a circuit region disposed in parallel with the light emitting region and disposed adjacent to the first data line with the light emitting region interposed therebetween, the circuit region including a plurality of thin film transistors and a capacitor. The method according to claim 1,
A second sub-pixel adjacent to the first sub-pixel,
The second sub-
A second data line crossing the first gate line;
A light emitting region arranged in parallel with the second data line and including an organic light emitting diode; And
And a circuit region disposed in parallel to the light emitting region and disposed adjacent to the second data line with the light emitting region therebetween, the circuit region including a plurality of thin film transistors and a capacitor. 3. The method of claim 2,
And the circuit region of the first subpixel and the circuit region of the second subpixel are arranged in parallel to each other and adjacent to each other. The method of claim 3,
And a first power line that is parallel to the first data line and is shared by the first sub-pixel and the second sub-pixel, respectively, outside the first data line. 5. The method of claim 4,
And a sensing line shared on the outer side of the second data line with the first sub pixel and the second sub pixel, respectively. 6. The method of claim 5,
And a third subpixel and a fourth subpixel symmetrical to the first and second subpixels with respect to the sensing line, the sensing line being connected to the third subpixel and the fourth subpixel Display device. The method according to claim 6,
The third subpixel includes a third data line adjacent to the sensing line, and the fourth subpixel includes a fourth data line on the outer side of the fourth subpixel, the fourth data line being parallel to the third data line. . 8. The method of claim 7,
And a second power line that is arranged outside the fourth data line and is in parallel with the fourth data line and is shared by the third subpixel and the fourth subpixel, respectively. 9. The method of claim 8,
A second gate line disposed below the first through fourth subpixels; And
And fifth to eighth sub-pixels connected to the second gate line and having the same structure as the first to fourth sub-pixels, respectively. 9. The method of claim 8,
The first subpixel and the fifth subpixel emit the same color, and the color filters of the first subpixel and the fifth subpixel are connected in series.

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