KR20190060505A - Pi/4-dqpsk decoder and decoding method therefor - Google Patents

Abstract

The present invention relates to a decoder of a PI/4 differential quadrature phase shift keying (PI/4 D-QPSK) demodulator comprising: a fast Fourier transformer for receiving input of a signal and performing fast Fourier transformation on the signal; and a phase locked loop for fixing and outputting a phase on an IQ plane by using an output from the fast Fourier transformer, wherein the phase locked loop includes a second phase rotator for selecting an odd-numbered signal or an even-numbered signal among alternately input signals, rotating a phase of the selected signal by 45 degrees in a first direction on the IQ plane, and outputting the unselected signals as it is.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a PI quadrature phase shift keying decoder and a decoding method thereof.

More particularly, the present invention relates to a quadrature pi-phase quadrature phase shift keying decoder and a decoding method thereof. More particularly, the present invention relates to a quadrature- Pi difference quadrature phase shift keying decoder and a decoding method therefor.

Generally, in an encoder of a signal transmitter for quadrature phase shift keying (PI / 4 differential quadrature phase shift keying, PI / 4 D-QPSK), the output complex of a frequency interleaver, The signal undergoes differential modulation. Specifically, the PI / 4 D-QPSK can be expressed by the following equation (1).

In Equation (1), Z is an input of an Inverse Fast Fourier Transform (IFFT), l is a sequence of input signals, y is a mapping result of QPSK, and k is a position of a subcarrier.

(1), Z _{l, k} is a value obtained by rotating Z _{l - 1, k} by y _{l, k} . That is, the multiplication of (1) is the multiplication of the complex operator. In this way, it can be seen that the point displayed in the constellation expressed by the I axis and the Q axis when PI / 4 D-QPSK is performed is the same as in Fig.

Referring to FIG. 1, eight points are displayed in an ellipse on the IQ plane. It is characterized by PI / 4 D-QPSK and is plotted at one point of 0, π / 2, π, 3π / 2 at one time and one of π / 4, 3π / 4, 5π / 4, Point of view. This process is repeated continuously. It should not be judged by 8 phase shift keying.

In a quadrature pyro-quadrature phase shift keying receiver, information is obtained with a difference of two signals, and the signal error of the current phase is susceptible to the error of the signal of the previous phase.

Korean Patent Laid-Open Publication No. 1995-0016104: Differential Quadrature Phase Shift Keying Demodulator (Published June 17, 1995).

An object of the present invention is to solve the technical problems as described above, and an object of the present invention is to provide a quadrature pyramid orthogonalizer capable of improving the signal reception performance by strongly responding to a signal error in a previous stage, And to provide a phase shift keying decoder and a decoding method therefor.

The decoder of the quadrature pyramidal quadrature phase shift keying demodulator of the present invention comprises: a fast Fourier transformer for receiving and fast Fourier transforming a signal; And a phase locked loop unit for fixing and outputting a phase on an IQ plane using an output from the FFT unit, wherein the phase locked loop unit selects an odd-numbered signal among the alternately input signals, And a second phase rotator for selecting a signal and rotating the phase of the selected signal by 45 degrees in the first direction on the IQ plane and outputting the unselected signal as it is.

In addition, the decoder of the present invention includes: a mobile device for moving the output of the second phase rotator to a designated position on the IQ plane; And a fifth phase rotator for rotating the phase of the selected signal among the signals output from the mobile device in a second direction, wherein the first direction and the second direction are opposite to each other.

The decoder of the present invention further includes: a delay unit for delaying the output of the fifth phase rotator; And a multiplier for multiplying the output of the delay unit by a complex conjugate of the output of the phase locked loop unit and outputting the multiplication result.

Preferably, the phase-locked loop unit rotates the output from the second phase rotator located at three different quadrants in one quadrant on the IQ plane at an angle of 90 °, 180 °, or 270 ° A third phase rotator for moving the third phase rotator; A fourth phase rotator for rotating the output of the third phase rotator by 45 degrees in a first direction or a second direction; And a phase error extractor for extracting a phase value whose output of the fourth phase rotator is out of the Q axis or the I axis as an error value, wherein the first direction and the second direction are opposite to each other.

The phase locked loop may further include: a numerical control oscillator for calculating a cumulative average of error values output from the phase error extractor; And a first phase rotator for adjusting the phase of the output of the FFT unit using the output of the numerically controlled oscillator.

In summary, the decoder of the quadrant pi-phase quadrature phase shift keying demodulator of the present invention comprises: a fast Fourier transformer for receiving and fast Fourier transforming a signal; A phase locked loop unit for fixing and outputting a phase on an IQ plane by using an output from the fast Fourier transformer; And a phase correcting unit for receiving a signal from the phase locked loop unit and correcting and outputting the phase signal, wherein the phase locked loop unit receives a signal located on the IQ plane as a positive I axis, a negative I axis, Axis or positive Q-axis to extract an error value as a phase value deviating from the positive or negative I-axis or Q-axis deviated from the axis, adjusts the phase and outputs the error value , The phase correcting unit may select an odd-numbered signal or an even-numbered signal among the alternately inputted signals, rotate the phase of the selected signal by 45 degrees in the first direction, or output the signal that is not selected as it is , The error is corrected by moving to a designated position on the IQ plane, wherein the first direction and the second direction are opposite to each other.

A quadrature-phase quadrature phase shift keying demodulator for decoding a quadrature phase shift keying demodulator according to the present invention comprises: (a) receiving a signal and performing fast Fourier transform; And (b) fixing and outputting a phase on the IQ plane using the output from the step (a), wherein (b) comprises: (b-1) Selecting an even signal or selecting an even signal, and rotating the selected signal by 45 degrees in a first direction on the IQ plane, and outputting the unselected signal as it is.

In addition, the decoding method of the present invention may further include: (c) moving the output of the step (b-1) to a designated position on the IQ plane; And rotating the phase of the selected signal among the signals output from the step (c) in a second direction, wherein the first direction and the second direction are opposite to each other.

Preferably, the decoding method of the present invention further comprises: (e) delaying the output of step (d); And (f) multiplying the output of the step (e) by the complex conjugate of the output of the step (a) and outputting the result.

The step (b) includes the steps of: (b-2) outputting the output from the step (b-1) located in three different quadrants in one quadrant on the IQ plane at 90 °, 180 °, By an angle of < / RTI > (b-3) rotating the output of the step (b-2) by 45 degrees in the first direction or the second direction; (b-4) extracting an output value of the output of the step (b-3) as an error value out of the Q axis or the I axis; (b-5) calculating a cumulative average of the error values output from the step (b-4); And (b-6) adjusting the phase of the output of step (a) using the output of step (b-5).

According to the quadrature pi quadrature phase shift keying decoder and decoding method thereof of the present invention, the signal error of the current stage can be robustly corrected to the error of the signal of the previous stage, thereby improving the signal reception performance.

FIG. 1 is a configuration diagram of quadrant pi-phase quadrature phase shift keying; FIG.
2 is a configuration diagram of a conventional differential quadrature phase shift keying decoder;
3 is a configuration diagram of a differential quadrature phase shift keying decoder according to a preferred embodiment of the present invention.
4 is an explanatory view of the operation of the phase locked loop unit of the present invention.
5 is an explanatory view of the operation of the phase correction section of the present invention.
6 is a simulation result of the bit error rate of the conventional decoder and the decoder of the present invention.

Hereinafter, a quad-Pitch differential quadrature phase shift keying decoder and a decoding method thereof according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be understood that the following embodiments of the present invention are only for embodying the present invention and do not limit or limit the scope of the present invention. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.

First, FIG. 2 shows a configuration diagram of a conventional quadrature py inter-quadrature phase shift keying decoder 100. The decoder 100 constitutes a part of a differential quadrature phase shift keying demodulator.

2, the conventional decoder 100 includes a fast Fourier transformer 110, a delay 120, a multiplier 130, and an error corrector 140. [

The fast Fourier transformer 110 performs a fast Fourier transform on a signal. The delay 120 delays the output of the fast Fourier transformer 110 and outputs the delayed output. The multiplier 130 multiplies the output of the delay unit 120 by the complex conjugate of the output of the fast Fourier transformer 110 and outputs the result. The error corrector 140 performs a Forward Error Correction for correcting an error using the output of the multiplier 130. [

FIG. 3 shows a configuration diagram of a Quad-Pie differential quadrature phase shift keying decoder 200 according to a preferred embodiment of the present invention.

The decoder 200 constitutes a part of a differential quadrature phase shift keying demodulator.

3, the decoder 200 of the present invention includes a fast Fourier transformer 210, a phase locked loop (PLL) 250, a phase corrector 260, 220, a multiplier 230, and an error corrector 240.

The decoder 200 of the present invention can be implemented by a processor such as a DSP (Digital Signal Process).

The fast Fourier transformer 210 receives a signal and performs fast Fourier transform. In addition, the phase lock loop unit 250 uses the output from the fast Fourier transformer 210 to fix and output the phase on the IQ plane. The phase correcting unit 260 receives the signal from the phase lock loop unit 250, corrects the phase, and outputs the corrected signal.

The delay unit 220 delays the output of the phase correction unit 260 and outputs the delayed output. The multiplier 230 multiplies the output of the delay unit 220 by the complex conjugate of the output of the phase lock loop unit 250 and outputs the result.

Specifically, the multiplier 230 can calculate the complex conjugate by the following equation (2).

Z is Z _{l l -} a value obtained by rotating the ₁ y _l, Z _{l, k} is the output of the current _stage, Z _{l - 1, k} may be referred to as the output of the previous stage. In addition, y _l can be expressed as I _l + jQ _l . Where I is the in-phase signal and Q is the quadrature phase signal.

The error corrector 240 performs a Forward Error Correction to correct the error using the output of the multiplier 230. [

Hereinafter, the phase locked loop unit 250 will be described in detail.

The phase locked loop unit 250 includes a first phase rotator 251, a second phase rotator 252, a third phase rotator 253, a fourth phase rotator 254, a phase error extractor 255, And includes an oscillator 256.

The second phase rotator 252 selects an odd-numbered signal (Odd Symbol) or an even-numbered signal (Even Symbol) among the alternately inputted signals and outputs the phase of the selected signal on the IQ plane, The signal is rotated by 45 degrees in one direction, and the unselected signal is output as it is.

The third phase rotator 253 rotates the output from the second phase rotator 252 located in the other three quadrants in one quadrant on the IQ plane at an angle of 90 °, 180 °, or 270 ° To move by. The rotation direction of the third phase rotator 253 is preferably the first direction.

The fourth phase rotator 254 rotates the output of the third phase rotator 253 by 45 degrees in the first direction or the second direction. Here, the first direction and the second direction are opposite to each other.

The phase error extractor 255 serves to extract, as an error value, a phase value whose output of the fourth phase rotator 254 is out of the Q axis or the I axis. The numerical control oscillator 256 also calculates a cumulative average of the error values output from the phase error extractor 255.

In addition, the first phase rotator 251 serves to adjust the phase of the fast Fourier transformer 210 using the output of the numerical control oscillator 256.

4 is an operation explanatory diagram of the phase locked loop unit 250 of the present invention.

The second phase rotator 252 selects odd-numbered signals among the alternately inputted signals, rotates the phases of the selected odd-numbered signals clockwise by 45 degrees, and outputs the unselected even-numbered signals as they are.

Next, the third phase rotator 253 rotates the output from the second phase rotator 252 located in the other three quadrants in one quadrant on the IQ plane at an angle of 90 degrees, 180 degrees, or 270 degrees As shown in Fig. Specifically, a symbol located in the second quadrant on the IQ plane is rotated 90 ° clockwise, a symbol located in the third quadrant is rotated 180 ° clockwise, and a symbol located in quadrant 4 is rotated 270 ° clockwise to move to the first quadrant.

In addition, the fourth phase rotator 254 rotates the output of the third phase rotator 253 clockwise or counterclockwise by 45 degrees. In FIG. 4, when the fourth phase rotator 254 rotates clockwise, i. E. It rotates in the positive I axis direction, the symbols are located near the positive I axis. However, in FIG. 4, the symbols are located near the positive Q-axis by the rotation of the fourth phase rotator 254 in the counterclockwise direction, that is, the positive Q-axis direction. The phase error extractor 255 extracts the phase value out of the Q axis as the error value by the output of the fourth phase rotator 254.

In summary, the phase-locked loop unit 250 of the present invention rotates a signal located on the IQ plane toward one of positive I-axis, negative I-axis, positive Q-axis, or negative Q-axis Axis direction, a phase value deviating from the positive or negative I-axis or Q-axis deviated from the axis is extracted as an error value, and the phase is adjusted and outputted.

The phase corrector 260 preferably includes a mobile device 261 and a fifth phase rotator 262.

The mobile device 261 serves to move the output of the second phase rotator 252 to a designated position on the IQ plane. The position designated here is preferably located on the I axis or the Q axis, or on a line that forms 45 degrees with the I axis or the Q axis. The designated position is a position rotated by 45 degrees in the first direction from the phase when the corresponding signal has no error.

The fifth phase rotator 262 serves to rotate the phase of the selected signal among the signals output from the mobile device 261 in the second direction. That is, the fifth phase rotator 262 moves to the position of the signal when there is no phase error.

5 is an operation explanatory diagram of the phase correction section 260 of the present invention.

The mobile device 261 moves to the designated position on the line that forms 45 degrees with the I axis or the Q axis. In addition, it can be seen that the fifth phase rotator 262 rotates the selected odd-numbered signal counter-clockwise by 45 degrees while leaving the unselected even-numbered signal intact.

In summary, the phase corrector 260 of the present invention selects the odd-numbered signal or the even-numbered signal among the alternately input signals and rotates the phase of the selected signal by 45 degrees in the first direction, The signal which is not output as it is, serves to correct the error by moving the output signal to the designated position on the IQ plane.

A decoding method of a quadrature pyramidal quadrature phase shift keying demodulator according to a preferred embodiment of the present invention will now be described.

The quadrature pyramidal quadrature phase shift keying demodulator decoding method according to the preferred embodiment of the present invention utilizes the decoder 200 of the present invention described above and therefore all the features of the decoder 200 described above Of course.

The decoding method of the present invention includes a step (S10) of receiving a signal and performing a fast Fourier transform and a step (S20) of fixing the phase on the IQ plane of the input signal using the output from step S10 and outputting it.

Specifically, in step S20, an odd-numbered signal is selected or an even-numbered signal is alternately selected, and the phase of the selected signal is rotated by 45 degrees in the first direction on the IQ plane. By rotating the output from the step (b-1) located at the other three quadrants in one quadrant on the IQ plane at an angle of 90 °, 180 °, or 270 °, (S23) of rotating the output of step S12 by 45 degrees in the first direction or the second direction (S23), extracting a phase value whose output in step S13 is out of the Q axis or I axis as an error value S24), a step (S25) of calculating a cumulative average of the error values output from the step S24, and a step (S26) of adjusting the phase of the output of the step S10 using the output of the step S25. In addition, the first direction and the second direction are opposite to each other.

The decoding method of the present invention further includes a step S30 of moving the output of step S21 to a designated position on the IQ plane, a step S40 of rotating the phase of the selected signal among the signals output from step S30, (S50) of delaying the output of step S40 and a step (S60) of multiplying the output of step S50 by the complex conjugate of the output of step S10 and outputting the result.

6 shows a simulation result of the bit error rate of the conventional decoder 100 and the decoder 200 of the present invention.

In FIG. 6, the X-axis represents the signal-to-noise ratio (SNR) and the Y-axis represents the bit error rate (BER).

As can be seen from FIG. 6, according to the present invention, the bit error rate is improved and the reception performance is improved.

As described above, according to the quadrature Pi-phase quadrature phase shift keying decoder 200 of the present invention and the decoding method thereof, the signal error of the current stage is robust to the error of the signal of the previous stage, .

100, 200: Decoder
110, 210: Fast Fourier transformer 120, 220: Delay
130, 230: multiplier 140, 240: error corrector
250: phase lock loop unit 260: phase correction unit
251: first phase rotator 252: second phase rotator
253: Third phase rotator 254: Fourth phase rotator
255: phase error extractor 256: numerically controlled oscillator
261: Mobile machine 262: Fifth phase rotator

Claims (14)

A decoder of a Quadrature Pi differential quadrature phase shift keying demodulator,
A fast Fourier transformer for performing a fast Fourier transform on a signal; And
And a phase locked loop unit for fixing and outputting a phase on an IQ plane by using an output from the fast Fourier transformer,
The phase locked loop unit includes:
A second phase rotator for selecting an odd-numbered signal among the alternately inputted signals or selecting an even-numbered signal, rotating the phase of the selected signal by 45 degrees in the first direction on the IQ plane, and outputting the unselected signal as it is And a decoder. The method according to claim 1,
The decoder includes:
A mobile device for moving the output of the second phase rotator to a designated position on the IQ plane; And
And a fifth phase rotator for rotating the phase of the selected signal among the signals output from the mobile device in a second direction,
Wherein the first direction and the second direction are opposite to each other. 3. The method of claim 2,
The decoder includes:
A delay for delaying the output of the fifth phase rotator; And
And a multiplier for multiplying the output of the delay unit by a complex conjugate of the output of the phase locked loop unit and outputting the result. 4. The method according to any one of claims 1 to 3,
The phase locked loop unit includes:
A third phase rotator for moving the output from the second phase rotator located in the other three quadrants in one quadrant on the IQ plane by rotating at an angle of 90 °, 180 °, or 270 °;
A fourth phase rotator for rotating the output of the third phase rotator by 45 degrees in a first direction or a second direction; And
And a phase error extractor for extracting a phase value of the output of the fourth phase rotator out of the Q axis or the I axis as an error value,
Wherein the first direction and the second direction are opposite to each other. 5. The method of claim 4,
The phase locked loop unit includes:
A numerical control oscillator for calculating a cumulative average of error values output from the phase error extractor; And
And a first phase rotator for adjusting the phase of the output of the fast Fourier transformer using the output of the numerically controlled oscillator. A decoder of a Quadrature Pi differential quadrature phase shift keying demodulator,
A fast Fourier transformer for performing a fast Fourier transform on a signal;
A phase locked loop unit for fixing and outputting a phase on an IQ plane by using an output from the fast Fourier transformer; And
And a phase corrector for receiving a signal from the phase locked loop and correcting the phase and outputting the corrected phase. The method according to claim 6,
The phase locked loop unit includes:
By moving the signal located on the IQ plane toward one of the positive I-axis, negative I-axis, positive Q-axis, or negative Q-axis, a positive or negative I- Extracts a phase value deviated from the Q axis as an error value, adjusts the phase, and outputs the error. 8. The method of claim 7,
Wherein:
A signal that is selected by selecting an odd-numbered signal or an even-numbered signal among the alternately input signals and rotating the phase of the selected signal by 45 degrees in a first direction or outputting an unselected signal as it is, To correct the error,
Wherein the first direction and the second direction are opposite to each other. 9. The method according to any one of claims 6 to 8,
The decoder includes:
A delay for delaying an output signal from the phase corrector; And
And a multiplier for multiplying the output of the delay unit by a complex conjugate of the output of the phase locked loop unit and outputting the result. A method for decoding a Quadrature Pi differential quadrature phase shift keying demodulator,
(a) receiving and fast Fourier transforming a signal; And
(b) fixing the phase on the IQ plane using the output from the step (a), and outputting the fixed phase,
The step (b)
(b-1) selecting an odd-numbered signal among the alternately inputted signals or selecting an even-numbered signal, rotating the phase of the selected signal by 45 ° in the first direction on the IQ plane, and outputting the unselected signal as it is The decoding method comprising the steps of: 11. The method of claim 10,
The decoding method includes:
(c) moving the output of the step (b-1) to a designated position on the IQ plane; And
(d) rotating the phase of the selected signal among the signals output from the step (c) in a second direction,
Wherein the first direction and the second direction are opposite to each other. 12. The method of claim 11,
The decoding method includes:
(e) delaying the output of step (d); And
(f) multiplying the output of step (e) by the complex conjugate of the output of step (a) and outputting the result. 12. The method according to any one of claims 10 to 11,
The step (b)
(b-2) shifting the output from the step (b-1) located at the other three quadrants in one quadrant on the IQ plane by rotating at an angle of 90 °, 180 °, or 270 ° step;
(b-3) rotating the output of the step (b-2) by 45 degrees in the first direction or the second direction; And
(b-4) extracting, as an error value, a phase value whose output of the step (b-3) is out of the Q axis or the I axis,
Wherein the first direction and the second direction are opposite to each other. 14. The method of claim 13,
The step (b)
(b-5) calculating a cumulative average of the error values output from the step (b-4); And
(b-6) adjusting the phase of the output of step (a) using the output of step (b-5).

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