KR20190058245A - Operation method of signal receiver, pulse width controller, and electric device including the same - Google Patents

Abstract

According to an embodiment of the present invention, provided is an operating method of a signal receiver, which comprises the following steps: sequentially receiving zeroth and first bits through one signal line; and adjusting any one width from a first high section or and a first low section of the first signal corresponding to the first bit based on values of the zeroth and first bits when the values of the zeroth and first bits are equal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an operation method of a signal receiver, a pulse width controller, and an electronic device including the same.

The present invention relates to electronic devices, and more particularly, to a method of operating a signal receiver, a pulse width controller, and an electronic device including the same.

Electronic devices exchange information by transmitting an electrical signal to an external device (e.g., a memory controller) through a signal line. As one example, the semiconductor memory device transfers data to the memory controller in synchronization with the data strobe signal. In this case, depending on the characteristics of the lines between the memory device and the memory controller, distortion may occur in each signal. As a result, there is a problem that the data transmission speed is lowered or the data reliability is lowered.

It is an object of the present invention to provide a method of operating a signal receiver, a pulse width controller, and an electronic device including the same, by adjusting the pulse width of a data signal corresponding to a current data bit based on previous data bits have.

The method of operating a signal receiver according to an embodiment of the present invention includes sequentially receiving the 0th and 1st bits through one signal line, and when the values of the 0th and 1st bits are the same, And adjusting the width of either the first high period and the first low period of the first signal corresponding to the first bit based on the values of the first bits.

A pulse width controller according to an embodiment of the present invention includes a sampler configured to sample an output signal and output a zero feedback signal, a first delay configured to delay the zero feedback signal to output a first feedback signal, 0 and a pulse width adjuster configured to adjust the width of either the high or low section of the output signal if the values of the first and second feedback signals are equal to each other.

An electronic device according to an embodiment of the present invention includes a delay signal generator for sequentially receiving signals corresponding to the 0th and 2nd bits and for delaying the signals to generate a plurality of delay signals, And a pulse width modulation decision feedback equalizer configured to adjust either the high or low duration of the output signal based on the plurality of delay signals if the bits are equal or the first and second bits are equal .

A signal transmitter according to an embodiment of the present invention includes a delay signal generator configured to receive a signal for the zeroth and second bits and to generate a plurality of delay signals by delaying the signal, A pulse width adjuster configured to adjust either the width of either the high or low section of the output signal if the same or the first and second bits are equal and output the adjusted output signal to an external device via a data line, .

According to an embodiment of the present invention, the electronic device can adjust the pulse width of the data signal corresponding to the current data bit based on the previous data bits. Accordingly, a method of operation of a signal receiver with improved reliability, a pulse width controller, and an electronic device including them are provided.

1A and 1B are block diagrams showing a memory system according to an embodiment of the present invention.
FIGS. 2A and 2B are timing diagrams showing data signals according to various data patterns.
3 is a flow chart showing the operation of the pulse width controller of FIG.
FIGS. 4A and 4B are views for explaining the operation method of FIG. 3 in more detail.
5 is a block diagram illustrating an exemplary hardware configuration of the pulse width controller of FIG.
FIG. 6 is a block diagram illustrating the PWC-DFE of FIG. 5 in more detail.
FIG. 7 is a circuit diagram illustrating the pulse width controller of FIG. 6; FIG.
8 is a timing chart for explaining the operation of the pulse width adjuster of FIG.
FIG. 9 is a block diagram illustrating an exemplary pulse width adjuster of FIG. 6;
10 is a timing chart for explaining the operation of the pulse width adjuster of FIG.
11 is a block diagram showing the configuration of a pulse width controller according to an embodiment of the present invention.
12 is a timing chart for explaining the operation of the pulse width controller of FIG.
13 is a block diagram showing a pulse width controller according to an embodiment of the present invention.
14 is an exemplary illustration of the zeroth pulse width adjuster of Fig.
15 is a timing chart for explaining the operation of the pulse width adjuster of FIG.
16A and 16B are block diagrams illustrating a memory system in accordance with an embodiment of the present invention.
17 is a block diagram illustrating an exemplary pulse width controller of FIG. 16;
18 is a timing chart for explaining the operation of the pulse width controller.
19A to 19C are block diagrams showing electronic devices having a pulse width controller (PWC) according to the present invention.
20 is a block diagram illustrating an exemplary electronic system in which a transmitter and a receiver with a pulse width controller according to the present invention are reflected.

In the following, embodiments of the present invention will be described in detail and in detail so that those skilled in the art can easily carry out the present invention.

The terms " unit, " " module, " or the like, or functional blocks shown in the figures may be implemented in the form of a software configuration, a hardware configuration, or a combination thereof. Hereinafter, in order to clearly explain the technical idea of the present invention, detailed description of the overlapping components will be omitted.

1A and 1B are block diagrams showing a memory system according to an embodiment of the present invention. Referring to FIG. 1A, a memory system 10 may include a memory device 11 and a memory controller 12. The memory device 11 may be a dynamic random access memory (DRAM), but the scope of the present invention is not limited thereto, and the memory device 11 may be a volatile memory device or a nonvolatile memory device.

The memory device 11 may store the data (DATA) or transmit the stored data (DATA) to the memory controller 12 under the control of the memory controller 12. For example, the memory device 11 may transmit the data (DATA) to the memory controller 12 in response to the command CMD and the address ADDR from the memory controller 12. [ At this time, the memory controller 12 can provide the data (DATA) to the memory controller 12 in synchronization with the data strobe signal provided through the data strobe line DQS. Illustratively, between the memory device 11 and the memory controller 12, the data DATA can be transmitted and received via the plurality of data lines DQ and the data strobe lines DQS.

The memory controller 12 can receive data (DATA) from the memory device 11 via the data lines DQ. For example, the memory controller 12 may identify the data (DATA) received via the data lines DQ based on the signal of the data strobe line DQS.

For example, the memory device 11 and the memory controller 12 may communicate based on a double data rate (DDR) interface, but the scope of the present invention is not limited thereto, (PCI), an Advanced Technology Attachment (ATA), a Serial ATA (SATA), a PATA (Parallel) (ATA), a small computer small interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a mobile industry processor interface (MIPI), a nonvolatile memory- And may communicate based on at least one of the various interfaces.

The memory controller 12 may include a pulse width controller 100. The pulse width controller 100 may be configured to adjust the pulse width corresponding to the current data bit based on the data received from the memory device 11. [ For example, the pulse width controller 100 may adjust the pulse width corresponding to the current data bit based on the received data pattern. Or the pulse width controller 100 may adjust the pulse width corresponding to the current data bit based on whether the previously received data bits have changed. The operation method and structure of the pulse-width controller 100 according to the present invention will be described in more detail with reference to the following drawings.

Referring to FIG. 1B, the memory system 10 'may include a memory device 11' and a memory controller 12 '. 1B, the pulse width controller 100 'is included in the memory device 11', and is connected to the current data bit based on the data received by the memory device 11 ' May be configured to adjust the corresponding pulse width. Other components are similar to those of FIG. 1A, so a detailed description thereof will be omitted.

As described above, the pulse width controller 100 may adjust the pulse width corresponding to the current data bit based on the previous data bits. Thus, at the receiving end of the memory controller 12, an effective margin for identifying the data bit can be sufficiently secured. Therefore, data can be normally received from the memory device 11 in the memory controller 12 supporting the high-speed interface, and the reliability of the memory controller 12 is improved.

Hereinafter, for convenience of description, embodiments of the present invention will be described with reference to a pulse width controller 100 (i.e., the embodiment of FIG. 1A) applied to the memory controller 12. FIG. Illustratively, the configurations of the memory device 11 and the memory controller 12 described above are for illustrating the exemplary embodiments of the present invention, and the scope of the present invention is not limited thereto. For example, the pulse width controller 100 according to the present invention may be applied to a signal transmitter, a signal receiver, or various electronic devices (e.g., a memory device) configured to transmit and receive various information via a signal line. In addition, the pulse width controller 100 according to the present invention can be used to receive or transmit various signals as well as data lines or data signals.

FIGS. 2A and 2B are timing diagrams showing data signals according to various data patterns. Hereinafter, embodiments of the present invention will be described with reference to a data signal or a data pattern received via one data line DQ in order to clearly illustrate the technical concept of the present invention.

It is also assumed that the data bit of " 1 " indicates a data signal of logic high and the data bit of " 0 " indicates a data signal of logic low. The data pattern DP means a combination of data bits sequentially received through one data line DQ. However, the scope of the present invention is not limited thereto.

Referring to Figures 1, 2A, and 2B, the memory controller 12 may receive various data patterns DP1-DP8 from the memory device 11. [ For example, as shown in FIGS. 2A and 2B, the memory controller 12 may receive the first to eighth data patterns DP1 to DP8 from the memory device 11. The first to fourth data patterns DP1 to DP4 may indicate patterns of 1101, 0101, 1001 and 0001 respectively and the fifth to eighth data patterns DP5 to DP8 May denote patterns of "0010", "1010", "0110", and "1110", respectively.

Illustratively, the timing diagrams shown in FIGS. 2A and 2B show data signals corresponding to the third and fourth bits of the first to eighth data patterns DP1 to DP8. That is, a data signal rising from " 0 " data bit to the " 1 " data bit of the first to fourth data patterns DP1 to DP4 is shown in FIG. 2A, and the fifth to eighth data patterns DP5 to DP8 Quot; 1 " data bit to a " 0 " data bit in Fig.

As shown in FIG. 2A, in each of the first to fourth data patterns DP1 to DP4, the data signal may rise at each of the first to fourth time points t1 to t4. As shown in FIG. 2B, in each of the fifth to eighth data patterns DP5 to DP8, the data signal may be lowered at each of the fifth to eighth time points t5 to t8.

That is, the rising and falling points of the data signal may be different from each other depending on the data pattern (or the previous data bit). Due to the difference between the rising point and the falling point, the effective margin for each data bit may not be ensured. Accordingly, the memory controller 12 may not normally receive data.

The pulse width controller 100 according to the embodiment of the present invention adjusts the pulse width of a data signal corresponding to a current data bit based on a data pattern (or previous data bits), as shown in FIGS. 2A and 2B . For example, in each of the first to fourth data patterns DP1 to DP4, the pulse width controller 100 controls the pulse width controller 100 so that the data signal corresponding to the current data bit or the data signal corresponding to the current data bit The pulse width of the data signal corresponding to the next data bit can be adjusted. Or the fifth to eighth data patterns DP5 to DP8, the data signal corresponding to the current data bit or the data signal corresponding to the next data bit, such that the data signal falls at the sixth time point t6, The width can be adjusted.

Illustratively, the second time point t2 indicates the rising time point of the data signal corresponding to the second data pattern DP2, 0101, and the sixth time point t6 indicates the rising point of the data signal corresponding to the sixth data pattern DP6, It may indicate a falling time point of the data signal. In other words, the pulse width controller 100 can adjust the pulse width of the data signal based on the rising and falling points of the data signal according to the specific data pattern. Illustratively, a particular data pattern may indicate a pattern (i.e., 0101 or 1010) in which the data bits are changed for each period.

3 is a flow chart illustrating the operation of the pulse width controller 100 of FIG. Hereinafter, for convenience of explanation, terms of a data pattern or a state of a data bit are used. The " state of the data bit " indicates whether or not the specific data bit and the previous data bit have changed. That is, if the state of the first data bit indicates a transition state, the immediately preceding data bit (i.e., the previous data bit) of the first data bit and the first data bit will be different from each other. If the state of the first data bit indicates a non-transition state, the immediately preceding data bit (i.e., the previous data bit) of the first data bit and the first data bit will be equal to each other. In other words, the change state of the data bits indicates whether the data bits are changed between adjacent (temporally) data bits.

Hereinafter, for convenience of explanation, it is assumed that the pulse width controller 100 sequentially receives the four data bits included in the data pattern and adjusts the pulse width for the third data bit among the four data bits do. In other words, according to the operation method described below, the pulse width controller 100 can control the pulse width of the data signal between the third data bit and the fourth data bit.

The above-described terms and assumptions are for the purpose of illustrating embodiments of the present invention easily, and the scope of the present invention is not limited thereto.

1 and 3, in step S110, the pulse width controller 100 may receive a data pattern. For example, the pulse width controller 100 may receive various data patterns (e.g., first through eighth data patterns DP1 through DP8). Or the pulse width controller 100 may sequentially receive a plurality of data bits.

In step S120, the pulse width controller 100 may determine a change state of each data bit based on the received data pattern. For example, when the pulse width controller 100 receives the second data pattern DP2 (i.e., 0101) (see FIG. 2A), since the adjacent data bits all change, the received second data pattern DP2 ) May be all transition states.

On the other hand, when the pulse width controller 100 receives the third data pattern DP3 (i.e., 1001), since the second and third bits are " 0 ", the state of the third data bit is non- State (non-transition state).

In step S130, the pulse width controller 100 can determine whether a non-changing state exists. In other words, the pulse width controller 100 can determine that adjacent data in the received data pattern has the same value of bits.

If there is a data bit in the non-changing state, the pulse width controller 100 can determine whether the data bit in the non-changing state is " 1 " or " 0 " in step S140.

If the data in the non-change state is a bit " 1 ", in step S150, the pulse width controller 100 may increase the interval corresponding to the data bit " 0 ". For example, when the pulse width controller 100 receives the seventh data pattern (DP7, i.e., 0110), the second data bit and the third data bit adjacent thereto are equal to " 1 " The data bit of " 1 " In this case, the pulse width controller 100 can increase the pulse width of the section corresponding to the data bit " 0 " (i.e., the low section) or increase the pulse width of the section corresponding to the data bit & The pulse width can be reduced. In this case, as shown in the seventh data pattern DP7 of FIG. 2B, the time point of falling from the third data bit to the fourth data bit may be aligned to the sixth point of time t6.

If the data in the non-change state is a bit " 0 ", in step S150, the pulse width controller 100 can increase the interval corresponding to the data bit " 1 ". For example, when the pulse width controller 100 receives the third data pattern DP3, 1001, since the second data bit and the third data bit adjacent thereto are equal to " 0 ", the non- The bit will be " 0 ". In this case, the pulse width controller 100 can increase the pulse width of the interval (i.e., the high interval) corresponding to the data bit " 1 " or increase the pulse width of the interval (i.e., the low interval) The pulse width can be reduced. In this case, as shown in the third data pattern DP3 of FIG. 2A, the time point of falling from the third data bit to the fourth data bit may be aligned to the second time point t2.

If there is no data bit in the non-changing state, the pulse width controller 100 may not perform the pulse width control operation. For example, when the pulse width controller 100 receives the second data pattern DP2, 0101, since each data bit of the second data pattern DP2 has a different value from the adjacent data bit, The bits will all have a change state. In this case, the pulse width controller 100 may not perform a separate pulse width control operation.

As described above, the pulse width controller 100 according to the embodiment of the present invention can determine, for received data bits, whether there are data bits having the same value among adjacent data bits. If there are data bits having the same value among adjacent data bits, the high or low interval at the current time can be increased or the low interval or the high interval can be decreased based on the value of the data bit .

For example, the pulse width controller 100 according to the embodiment of the present invention can adjust the change width of the high period or the low period, which increases according to the number of data bits having the same value among adjacent data bits.

FIGS. 4A and 4B are views for explaining the operation method of FIG. 3 in more detail. 4A, an embodiment of the data patterns DP1 to DP4 in which the current data bit D [n] is " 0 " is described and referring to FIG. 4B, the current data bits D [n ]) Is " 1 ". In each of the data patterns DP1 to DP8, the current data bit D [n] indicates the third data bit.

For convenience of explanation, the pulse width control operation at the point X [n] will be described. The point X [n] may point to a point changing from the current data bit D [n] to the next data bit D [n + 1]. That is, the pulse width controller 100 can increase / decrease the pulse width of the high section or the low section at the point X [n].

4A and 4B, the pulse width controller 100 may receive the first to eighth data patterns DP1 to DP8. The data signal may have a signal level corresponding to a data bit of each of the data patterns DP1 to DP4.

Illustratively, the second data pattern DP2 or the sixth data pattern DP6 may have an ideal signal level in each data bit interval. For example, the second data pattern DP2 and the sixth data pattern DP6 may include periodically repeated data bits. That is, the interval of the first and second data bits D [n-1] and D [n-2], the current data bit D [n] (I.e., a high level or a low level) in each of the plurality of memory cells.

On the other hand, the other data patterns DP1, DP3, DP4, DP5, DP7, and DP8 may have a data signal having a phase that precedes or lags behind the second and sixth data patterns DP2 and DP6 .

For example, in the case of the first data pattern DP1, at the point X [n], the pulse width may be reduced by the first time ta1. In other words, in the case of the first data pattern DP1, the data signal may rise earlier than the X [n] point by the first time ta1. On the other hand, in the case of the third data pattern DP3, the pulse width may be increased by the second time ta2 at the point X [n]. In other words, in the case of the third data pattern DP3, the data signal may rise after the second time ta2 after the point X [n]. In the case of the fourth data pattern DP4, at the point X [n], the pulse width may increase by the third time ta3. In other words, in the case of the fourth data pattern DP4, the data signal may rise after the third time ta3 after the point X [n].

The pulse width controller 100 according to the present invention increases / decreases the pulse width of the low section / high section by the first time ta1 in the case of the first data pattern DP1, The pulse width of the high section / low section is increased / decreased by the second time ta2 and the pulse width of the high section / the low section is decreased by the third time ta3 in the case of the fourth data pattern DP4 / RTI >

For example, in the case of the first data pattern (DP1, 1101), the first and second data bits are the same as " 1 ". That is, the first data pattern DP1 includes a data bit in a non-changing state having a data bit of " 1 ". In this case, as described with reference to Fig. 3, the pulse width controller 100 increases the pulse width (i.e., the width of the row section) corresponding to the data bit " 0 " .

In the case of the third data pattern DP3, 1001, the second and third data bits are the same as " 0 ". That is, the third data pattern DP3 includes a data bit in a non-changing state having a data bit of " 0 ". In this case, as described with reference to Fig. 3, the pulse width controller 100 increases (at X [n]) the pulse width corresponding to the data bit " 1 " .

In the case of the fourth data pattern DP4, 0001, the first, second and third data bits are the same as " 0 ". That is, the fourth data pattern DP4 includes data bits in a non-changing state having data bits of " 0 ". In this case, as described with reference to Fig. 3, the pulse width controller 100 increases (at X [n]) the pulse width corresponding to the data bit " 1 " .

Illustratively, the third and fourth data patterns DP3 and DP4 include data bits in the non-changing state having data bits of " 0 ", but the pulse width adjustments may be different. For example, in the third data pattern DP3, there is one non-changing data bit having a data bit of " 0 ", and in the fourth data pattern DP4, - There are two data bits in the change state.

That is, the third and fourth data patterns DP3 and DP4 include non-changing data bits having data bits of " 0 ", but the number of data bits in the non- have. The pulse width controller 100 according to the present invention can adjust the pulse width adjustment amount based on the number of data bits of the non-change ecology. Illustratively, as the number of data bits of the non-changing ecology increases, the pulse width adjustment amount may increase.

The fifth to eighth data patterns DP5 to DP8 differ only in the values of the data bits from the first to fourth data patterns DP1 to DP4, and the operation principle is the same, so a detailed description thereof will be omitted.

In each data pattern, the state of each of the data bits is determined by the current data bit D [n] and the first and second previous data bits D [n-1], D [n-2] As shown in FIG. For example, the pulse width adjuster 100 may compare the logical product of the current data bit D [n] and the first and second previous data bits D [n-1], D [n-2] 1), the first pull-up bit Xpu [n-1], the second pull-up bit Xpu [n-1] Xpu [n-2]), and a first pull-down bit Xpd [n-2].

The first pull-up bit Xpu [n-1] is a logical OR calculated value of the current data bit D [n] and the first previous data bit D [n-1] The full-down bit Xpd [n-1] is a logical AND of the current data bit D [n] and the first previous data bit D [n-1] - the up bit Xpu [n-2] is a value obtained by ORing the first previous data bit D [n-1] and the second previous data bit D [n-2] 2 full-down bit Xpd [n-2] is a logical product of the first previous data bit D [n-1] and the second previous data bit D [n-2] to be. The calculation values according to each of the data patterns DP1 to DP8 are as shown in Figs. 4A and 4B, and a detailed description thereof will be omitted.

The pulse width controller 100 may increase the row interval based on the first and second pull-down bits Xpd [n-1], Xpd [n-2]. For example, as shown in Figs. 4A and 4B, the first full-down bit Xpd [n-1] for the first, seventh, and eighth data patterns DP1, DP7, At least one of the second pull-down bits Xpd [n-2] may be " 1 ", and the first full-down bits (DP2, DP3, DP4, DP5, DP6) Xpd [n-1]) and the second pull-down bit Xpd [n-2] may be " 0 ". In this case, for the first, seventh, and eighth data patterns DP1, DP7, and DP8, the pulse width controller 100 outputs the data signal corresponding to the low level (that is, The pulse width of the pulse signal can be increased.

On the other hand, the pulse width controller 100 may increase the high period based on the first and second pull-up bits Xpu [n-1], Xpu [n-2]. For example, the first full-up bit (Xpu [n-1]) for the third, fourth and fifth data patterns DP3, DP4, DP5, as shown in Figures 4A and 4B, At least one of the second pull-up bits Xpu [n-2] may be "0" and the first full-up bits (DP1, Xpu [n-1] and the second pull-up bit Xpu [n-2] may all be " 1 ". In this case, the pulse width controller 100 generates a data signal corresponding to the high level (that is, a high level), for the third, fourth, and fifth data patterns DP3, DP4, The pulse width of the pulse signal can be increased.

As discussed above, the pulse width controller 100 may adjust the pulse width at a particular point (e.g., X [n]) based on the data pattern (i.e., the current data bit and the previous data bits). Thus, since the effective margin for data identification in the memory controller 12 is increased, a memory controller having improved reliability is provided.

4A and 4B illustrate operation principles of the pulse width adjusting operation according to the technical idea of the present invention, and the scope of the present invention is not limited thereto. The embodiments according to the present invention can be variously modified without departing from the technical idea of the present invention.

Illustratively, in the embodiments described above, the current data bit D [n], the two previous data bits D [n-1], D [n] D [n-2]), but the scope of the present invention is not limited thereto. The pulse width controller 100 sets the current data bit and the k previous data bits D [n] to D [nk] (where k is an integer) to adjust the pulse width at the current time point X [n] ) Can be used.

5 is a block diagram illustrating an exemplary hardware configuration of the pulse width controller 100 of FIG. For the sake of brevity, the components that are unnecessary for explaining the structure and operation of the pulse-width controller 100 are omitted. 1 and 5, the pulse-width controller 100 includes a plurality of delay signal generators 110-1 to 110-n, a plurality of pulse width control decision feedback equalizers 120-1 to 120- (PWC-DFE), control logic 130, and a delay circuit 140. In one embodiment,

The plurality of delay signal generators 110-1 to 110-n each receive data (DATA) from the memory device 11 through a plurality of data lines DQ1 to DQn and receive the received data (DATA) A plurality of delay signals can be output based on the received signal.

Each of the plurality of PWC-DFEs 120-1 through 120-n receives a plurality of delay signals from each of the plurality of delay signal generators 110-1 through 110-n, It is possible to output a plurality of output signals Yout1 to Youtn.

The control logic 130 may control the plurality of delay signal generators 110-1 to 110-n and the plurality of PWC-DFEs 120-1 to 120-n. For example, the control logic 130 may provide delay coefficients for generating a plurality of delay signals to a plurality of delay signal generators 110-1 through 110-n, and may include a plurality of PWC-DFEs 120 -1 to < RTI ID = 0.0 > 120-n. ≪ / RTI >

Illustratively, each of the plurality of delay signal generators 110-1 through 110-n may generate a plurality of delay signals based on delay coefficients from the control logic 130, and may include a plurality of PWC-DFEs 120-1 through 120-n may adjust the pulse width of the data signal corresponding to the current data bit based on the adjustment coefficients from the control logic 130 and the previous data bits.

The delay circuit 140 may be configured to delay the signal received via the data strobe line DQS. Each of the plurality of PWC-DFEs 120-1 to 120-n can output the output signals Yout1 to Youtn based on the delay signal from the delay circuit 140. [

Illustratively, the pulse width control operation described with reference to Figs. 2 to 4B through a plurality of delay signal generators 110-1 to 110-n and a plurality of PWC-DFEs 120-1 to 120- Can be performed. A more detailed configuration and operation method will be described in more detail with reference to the following drawings.

FIG. 6 is a block diagram illustrating the PWC-DFE of FIG. 5 in more detail. Hereinafter, for convenience of description, an embodiment of the present invention will be described based on one data line DQ, one delay signal generator 110, and one PWC-DFE 120. [ However, the scope of the present invention is not limited thereto, and each of the plurality of delay signal generators, the plurality of PWC-DFEs may operate based on the embodiments described below.

The pulse width controller 100 may include a delay signal generator 110, a PWC-DFE 120, and control logic 130. The delay signal generator 110 receives the data pattern DP0 through the data line DQ and delays the data signal according to the received data pattern DP0 to generate a plurality of delay signals S (t0) to S (tn)). Illustratively, the plurality of delay signals S (t0) to S (tn) may each be a delayed signal based on a delay coefficient Cd from the control logic 130. [

The PWC-DFE 120 may include a Pulse Width Adjuster 121, a sampler 122, and a plurality of delayers 123-1 through 123-m. The sampler 122 may be configured to sample the final output signal Yout from the pulse width adjuster 121. [ The zero-order feedback signal Y [0] sampled by the sampler 122 may be provided to the first delay 123-1. The first to m-th delayers 123-1 to 123-m are connected in series to each other and delay the output of the previous stage to output the first to m-th feedback signals Y [1] to Y [m] Can be output. The 0th to mth feedback signals Y [0] to Y [m] from the sampler 122 and the first to mth delay units 123-1 to 123-m are input to the pulse width adjuster 121, . ≪ / RTI >

The pulse width adjuster 121 may output the final output signal Yout based on the 0th to mth feedback signals Y [0] to Y [m]. For example, the pulse width adjuster 121 may adjust the pulse width from the 0th to mth feedback signals Y [0] to Y [m], the adjustment coefficients Cp, (T) to S (tn), as described above. The final output signal Yout may point to a data signal whose pulse width is adjusted as described above.

As a more detailed example, the 0th feedback signal Y [0] is a signal corresponding to the current data bit D [n] and the first feedback signal Y [1] [n-1]) and the second feedback signal Y [2] may be a signal corresponding to the second previous data bit D [n-2]. The pulse width adjuster 121 may adjust the pulse width as described above based on the 0th to mth signals Y [0] to Y [m]. At this time, the pulse width adjuster 121 combines (or adds signals) the plurality of delay signals S (t0) to S (tn) using the adjustment coefficients Cp to generate the final output signal Yout Can be adjusted. The structure of the pulse width controller 121 will be described in more detail with reference to Fig.

Illustratively, the size and number of delay coefficients Cd and adjustment coefficients Cp may be varied according to the implementation of the pulse width adjuster 121. In addition, the number of delays of the PWC-DFE 120 may be variously modified according to the implementation of the PWC-DFE 120. [ For example, when the PWC-DFE 120 is implemented in a one-tap configuration, the PWC-DFE 120 may include only the first delay 123-1 and the PWC- - tapped structure, the PWC-DFE 120 may include only the first and second delays 123-1 and 123-2. When the PWE-DFE 120 is implemented in an m-tap structure, the PWC-DFE 120 may include first through m-th delayers 123-1 and 123-m.

FIG. 7 is a circuit diagram illustrating the pulse width regulator 121 of FIG. 6 as an example. 8 is a timing chart for explaining the operation of the pulse width adjuster 121 of FIG. For the sake of brevity, it is assumed that the delay signal generator 110 outputs three delay signals S (t0), S (t1), S (t2). The circuit diagram of the pulse width adjuster 121 shown in FIG. 7 is illustrative, and the present invention is not limited thereto. The pulse width adjuster 121 may further include other components such as an output buffer circuit and the like.

In addition, the embodiment of Fig. 8 is described based on the specific data pattern DP0 of " 00010 ". 8, the data bits of the specific data pattern DP0 are D [n-3] = 0, D [n-2] = 0, And D [n + 1] = 0.

7, a pulse width controller 121 having an m-tap structure is shown in FIG. 7. For convenience of explanation, the operation of the pulse width controller 121 will be described based on the 2-TAP structure. However, the scope of the present invention is not limited thereto, and the pulse width adjuster 121 may include a plurality of pull-up units PU and a plurality of pull-down units PD as shown in FIG. 1-TAP structure or a plurality of tap structures.

7 and 8, the pulse width controller 121 may include inversion circuits INV1 to INV3, a pull-up driver (PUD), and a pull-down driver (PDD). The inverting circuits INV1 to INV3 may be configured to receive the 0th to 2nd delay signals S (t0), S (t1), and S (t2), respectively.

Illustratively, the zeroth delay signal S (t0) may be a signal comprising only the delay by the data line DQ or the internal circuit, without any deliberate delay. In the specific data pattern DP0, the zero delayed signal S (t0) may be a signal having a high level at a portion (e.g., tb1) of the D [n] interval as shown in Fig. As shown in Fig. 8, the first delay signal S (t1) may be a signal having a phase earlier than the zero delay signal S (t0) by a first time ta1). As shown in Fig. 8, the second delay signal S (t2) may be a signal having a phase delayed by a second time ta2 in comparison with the zero delayed signal S (t0).

Illustratively, each of the zeroth to second delay signals S (t0), S (t1), S (t2)) is generated by the delay signal generator 110-1 based on the delay coefficient Cd Lt; / RTI > The phase of the first and second delay signals S (t1), S (t2) may be determined by the delay coefficient Cd of the control logic 130. [ Illustratively, when the delay signal generator 110 generates three delay signals S (t0), S (t1), S (t2), the phase difference between the respective delay signals is given by the following equation 1 < / RTI >

Ta1 denotes the delay time of the first delay signal S (t1), ta2 denotes the delay time of the second delay signal S (t2), tb1 denotes the delay time of the zero delay signal (t S (t0)), and T indicates one period of the data signal. As described above, control logic 130 may generate delay coefficients Cd to satisfy equation (1).

7, the pull-up driver PUD and the pull-down driver PDD receive the signals from the inversion circuits INV1 to INV3 and the 0th to mth feedback signals Y [0] To Y [m]) of the final output signal Yout.

For example, the pull-up driver (PUD) may output the final output signal (Y [m]) based on the signals from the inversion circuits INV1 to INV3 and the 0- The voltage of the output node connected to the node Yout may be increased. That is, the pulse width in the high period can be increased by the operation of the pull-up driver (PUD).

The pull-down driver PDD outputs the final output signal Yout and the output signal Yout based on the signals from the inversion circuits INV1 to INV3 and the 0th to mth feedback signals Y [0] to Y [m] The voltage at the connected output node can be lowered. That is, the operation of the pull-down driver (PDD) can increase the pulse width of the low period.

As a more detailed example, the pull-up driver PUD may include a plurality of pull-up units PU0 through PUm2, and the pull-down driver PDD may include a plurality of pull- PDm2). Each of the plurality of pull-up units PU0 to PUm2 can output a high level signal when all the input signals are " 0 ". Each of the plurality of pull-down units PD0 to PDm2 can output a low level signal when the input signals are all " 1 ".

For example, as shown in FIG. 8, the 0th to 2nd feedback signals Y [0], Y [1], Y [2] [n-1], D [n-2], and D [n-3]. That is, at the point X [n-1], the zeroth to second feedback signals Y [0], Y [1], Y [2] In this case, referring to the pull-up driver of the 2-TAP structure, since the inputs of the pull-up units PU11 and PU21 are all " 0 & (PU11, PU21) will output a high level signal. That is, at the point X [n-1], the final output signal Yout can be made high level by the pull-up driver PUD. In other words, in the first period tpost, the high-level final output signal Yout can be generated by the pull-up driver PUD. In other words, at the point X [n-1], since the data bits in the non-changing state have a value of " 0 ", the high- can do.

Illustratively, the 0th to 2nd feedback signals Y [0], Y [1], Y [2] may be changed in synchronization with the clock signal CK. Illustratively, the clock signal CK may be a data strobe signal DQS.

Thereafter, until the point X [n] is reached, the final output signal Yout can be maintained at a high level by the pull-up driver PUD. For example, at the point X [n], the zeroth to second feedback signals Y [0], Y [1], Y [2] D [n-2]. That is, at the point X [n], the 0th to 2nd feedback signals Y [0], Y [1], Y [2] have values of "1", "0" . In this case, since the inputs (Y [1], Y [2], and the inverted second delay signal) of the pull-up unit PU22 are all "0" (PU22) will output a high level signal. That is, at the point X [n], the final output signal Yout may be at a high level. In other words, at the point X [n], since the data bits in the non-changing state have a value of " 0 ", the pull-up driver PUD can increase the high section by the second section tpre have.

As a result, the final output signal Yout is compensated for by the time tpost at the point X [n-1] and compensated for by the time tpre at the point X [n], compared with the zero delayed signal S . This means that a high-level pulse of the tpost time and the tpre time is added to or added to the output signal Yout at the X [n-1] point and the X [n] point.

Illustratively, the output signals from the plurality of pull-up units PU0 to PUm2 and the plurality of pull-down units PD0 to PDm2 respectively correspond to the corresponding adjustment coefficients Cpu0 to Cpum2, Cpd0 to Cpdm2 And may be provided as a final output signal Yout. Illustratively, the adjustment coefficients corresponding to the plurality of pull-up units PU0 to PUm2 and the plurality of pull-down units PD0 to PDm2 may have different values. Illustratively, each of the corresponding adjustment coefficients Cpu0-Cpum2, Cpd0-Cpdm2 may be provided by the control logic 130 and may be set through an initialization operation or pre-set via manufacturer firmware.

As described above, the pulse width controller 100 according to the present invention can increase / decrease the pulse width of the high period or the low period at the current point based on the value of the previous data bits. Thus, since the effective margin for identifying data can be increased, a memory controller with improved reliability is provided.

FIG. 9 is a block diagram illustrating an exemplary pulse width adjuster of FIG. 6; 10 is a timing chart for explaining the operation of the pulse width adjuster of FIG. For the sake of brevity, duplicate descriptions of the components described above are omitted. Also, for the sake of brevity, the embodiments of Figs. 9 and 10 will be described based on the data pattern DP0 of " 00010 "

9 and 10, the pulse width adjuster 121 'may include a plurality of inverting circuits, a pull-up driver (PUD), and a pull-down driver (PDD). Unlike the pulse width adjuster 120 'of FIG. 7, the pulse width adjuster 121' of FIG. 9 can receive the seven delay signals S (t0) to S (t6).

For example, the delay signal generator 110 may generate a plurality of delay signals S (t0) to S (t6) based on a delay coefficient Cd from the control logic 130. [ Each of the plurality of delay signals S (t0) to S (t6) may be delayed signals having a phase earlier or later than the zero delayed signal S (t0) by a predetermined time. For example, as shown in Fig. 10, the second and fourth delay signals S (t2) and S (t4) are compared with the zero delay signal S (t0) 2 > times ta1, ta2. The sixth delay signal S (t6) may have a phase that is delayed by the third time ta3 in comparison with the zero delay signal S (t0). Although not shown in the figure, other delay signals may also have a phase that is ahead of or behind the predetermined delay time compared to the zero delay signal S (t0). The phase of each delayed signal may be set by the delay coefficient Cd from the control logic 130. [

Similarly, the pull-up driver (PUD) and the pull-down driver (PDD) receive the signals from the plurality of inverting circuits and the zeroth to second feedback signals Y [0] ]), The level of the final output signal Yout can be adjusted. For example, the pull-up driver PUD includes a plurality of pull-up units PU0 to PU22, and each of the plurality of pull-up units PU0 to PU22 includes a pull- , It is possible to output a signal of a high level. The pull-down driver (PUD) includes a plurality of pull-down units (PD0 to PD22), and each of the pull-down units (PD0 to PD22) Can be output. The operation of the pull-up driver (PUD) and the pull-down driver (PDD) has been described above, and a detailed description thereof will be omitted.

Illustratively, the output signals of the pull-up unit PU0 of the pull-up driver PUD and the pull-down unit PU0 of the pull-down driver PDD of FIG. The output signals of the other pull-up units PU11 to PU22 of the pull-up driver PUD and the other pull-down units PD11 to PD22 of the pull-down driver PDD can be amplified 2 < / RTI > adjustment factor Cp2. At this time, the magnitude of the second adjustment coefficient Cp2 may be set to be very large in comparison with the magnitude of the first adjustment coefficient Cp1. (I. E., Cp2 > Cp1). This is to increase the strength of pull-up units and pull-down units operating by delay signals to achieve correct compensation.

10, the final output signal Yout is supplied to the pull-up driver (PUD) during the first period tpost at X [n-1] and during the second period tpre at X [n] ). ≪ / RTI > In other words, during the first period tpost, the second and fourth delay signals S (t2) and S (t4) and the 0th to 2nd feedback signals Y [0] to Y [2] The pull-up driver PUD can output a signal of a high level and the sixth delay signal S (t6) and the 0th to the second feedback signals Y [0] during the second period tpre, To Y [2]), the pull-up driver PUD can output a signal of a high level. That is, at the point X [n-1], the previous data bits D [n-1], D [n-2], D [n- (D [n-1], D [n-2], and D [n-2]) are the same since the previous data bits D [n-1] -3] is equal to "0"), the pulse width of the high section at each point is increased.

Although not shown in the figure, the pulse width modulation scheme for other data patterns can be performed similarly to the operation method described with reference to FIGS. 6 to 10. FIG. For example, with reference to FIGS. 6 to 10, a configuration in which the pulse width of the high section (i.e., the section corresponding to the data bit " 1 ") is adjusted is described. However, , And the data bit " 0 "). In this case, the level of the final output signal Yout can be adjusted by the pull-down driver PDD.

11 is a block diagram showing the configuration of a pulse width controller 200 according to an embodiment of the present invention. Illustratively, the pulse width controller 100 described with reference to Figures 1 to 10 shows a data receiving end of a full rate structure (i.e., a single data rate (SDR)). On the other hand, the pulse width controller 200 of FIG. 11 shows a data receiving end of a half-rate structure (that is, a double data rate (DDR)). That is, the pulse width controller 100 described with reference to FIGS. 1 to 10 receives or identifies one data bit per period of the clock signal CK (or data strobe signal DQS) 11 pulse width controller 200 may receive or identify one data bit per half cycle of clock signal CK (or data strobe signal DQS).

11, the pulse width controller 200 includes a delay signal generator 210, first and second pulse width adjusters 221 and 222, and first to fourth flip / flops FF1 to FF4. . ≪ / RTI > The first and second pulse width adjusters 221 and 222 and the first to fourth flip / flops FF1 to FF4 may constitute the PWC-DFE as described above.

The delay signal generator 210 receives a specific data pattern DP0 through the data line DQ and outputs a plurality of delay signals S (t0) to S (tn) based on the received signal have. Since the delay signal generator 210 has been described above, a detailed description thereof will be omitted.

The first flip-flop FF1 receives the second final output signal Yout2 from the second pulse width controller 222 and outputs the first feedback signal Y [1] in response to the clock signal CK . The second flip-flop FF2 receives the first final output signal Yout1 from the first pulse width regulator 221 and outputs the second feedback signal Y [2] in response to the inverted clock signal CKB can do. The third flip-flop FF3 receives the first feedback signal Y [1] from the first flip-flop FF1 and outputs the third feedback signal Y [3] in response to the inverted clock signal CKB Can be output. The fourth flip-flop FF4 receives the second feedback signal Y [2] from the second flip-flop FF2 and outputs the fourth feedback signal Y [4] in response to the clock signal CK can do.

The first and second pulse width regulators 221 and 222 output the delay signals S (t0) to S (tn) from the delay signal generator 210 and the first to fourth feedback signals Y The first and second final output signals Yout1 and Yout2 may be output based on the output signals [1] to Y [4], respectively. Illustratively, the configuration of the first and second pulse width modulators 221 and 222 may have a similar structure to the pulse width modulators described with reference to FIG. 7 or FIG. Illustratively, the first and second pulse width modulators 221 and 222 may be implemented in a 2-TAP architecture.

That is, each of the first and second pulse width adjusters 221 and 222 includes a pull-up driver (PUD) and a pull-down driver (PDD) The driver PDD may adjust the level of the first and second final output signals Yout1, Yout2 based on the input signals.

Illustratively, each of the first and second pulse width adjusters 221 and 222 is configured to output data one cycle before the present time based on the first and second feedback signals Y [1] and Y [2] (I.e., change information) of the data bits before the current point in time and based on the third and fourth feedback signals Y [3], Y [4] , Change information) can be obtained. Illustratively, each of the first and second pulse width modulators 221 and 222 uses first and second feedback signals delayed by a predetermined time (e.g., 1/2 period) The state of the data bits (i.e., change information) can be obtained.

12 is a timing chart for explaining the operation of the pulse width controller 200 of FIG. For the sake of brevity and ease of illustration, the delay in actual operation (e.g., the setup time of the flip-flop, etc.) in each circuit is not accurately reflected in the timing diagram. However, the scope of the present invention is not limited thereto, and some signals may include delays depending on the internal circuit configuration.

For the sake of convenience of explanation, the second pulse width adjuster 222 is a pulse width adjuster that operates based on the plurality of delay signals S (t0) to S (t6), as described with reference to Fig. 9 It is assumed to be a regulator. The embodiment of Fig. 12 is also described with reference to the second final output Yout2 of the second pulse width adjuster 222. [ However, the scope of the present invention is not limited thereto.

Referring to Figs. 11 and 12, the pulse width controller 200 may receive a data pattern of " 00010 ". That is, D [n-3] = 0, D [n-2] = 0, D [n-1] = 0, D [n] = 1, and D [n + 1] = 0. Similar to that described with reference to Figs. 9 and 10, can receive the 0th to 6th delay signals S (t0) to S (t6). The first, third and fifth delay signals S (t1), S (t3) and S (t5) are omitted in FIG. 12 because they are unnecessary to explain the operation of the second pulse width adjuster 222. Also, since the 0th to 6th delay signals S (t0) to S (t6)) have been described with reference to FIGS. 9 and 10, a detailed description thereof will be omitted.

2], D [n-1], D [n-2], and D [n-1] , And D [n-3]. At the point X [n], the first to fourth feedback signals Y [1] to Y [4] are D [n], D [n-1], D [n-2] D [n-1]. Similarly, the second pulse width adjuster 222 outputs the first to fourth feedback signals Y [1] to Y [4] at X [n-1] The pulse width of the second final output signal Yout2 can be adjusted.

Illustratively, the second final output signal Yout2 may be a signal delayed by the control delay time tc. The control delay time tc may be the delay time generated by the pulse width adjuster 222. [ Illustratively, the control delay time tc can be determined to satisfy equation (2).

Referring to Equation (2), tff indicates the delay time due to the flip-flop, tc indicates the delay time generated by the pulse width adjuster 222, T indicates one cycle of the second output signal Yout2, It indicates 1/2 of the period of the signal.

Illustratively, the pulse width controller 200 generates the first and second feedback signals Y [1], Y [2] to determine the state of the first previous data bit at X [n-1] ) And may use the third and fourth feedback signals Y [3], Y [4] to determine the state of the second previous data bit. For example, at the X [n-1] point, the pulse width controller 200 sets D [n-2] and D [n-1] the first and second feedback signals Y [1], Y [2] that are [n-1] can be used and to determine the state of the second previous data bit D [n-2] It is possible to use the third and fourth feedback signals Y [3], Y [4] each of which is D [n-2] and D [n-3]. Illustratively, each of the first to fourth feedback signals Y [1] to Y [4] is a signal delayed by a predetermined time tff in comparison with the clock signal CK and the inverted clock signal CKB have. The predetermined time tff may be a delay time generated by the flip-flops FF1 to FF4.

Illustratively, at a point X [n], the first and second feedback signals Y [1], Y [2] are delayed by a predetermined delay time td in order to determine the state of the second previous data bit. The first and second delayed feedback signals Y [1] _d and Y [2] _d delayed by a predetermined amount may be used. For example, at the X [n] point, the pulse width controller 200 determines D [n-2] and D [n-1] -1] and the second delayed feedback signals Y [1] _d and Y [2] _d, which are the first and second delayed feedback signals. The first and second delayed feedback signals Y [1] _d and Y [2] _d may include various signal delays such as a delay by a separate delay circuit, a delay by internal wiring, and the like.

12, the second pulse width controller 222 receives the first to fourth feedback signals Y [1] to Y [4] and the plurality of delay signals S (t0) to S t6) to output the second final output signal Yout2. As shown in Fig. 12, the second final output signal Yout2 can be increased or compensated for the high section at X [n-1] and X [n], respectively. The operation of the second pulse width adjuster 222 is similar to that of the pulse width controller described with reference to FIGS. 9 and 10, so that detailed description thereof will be omitted.

13 is a block diagram showing a pulse width controller 300 according to an embodiment of the present invention. 14 is an exemplary diagram illustrating the zeroth pulse width adjuster 320 of FIG. For the sake of brevity, a detailed description of the redundant components is omitted.

13 and 14, the pulse width controller 300 includes a delay signal generator 310, zeroth to second pulse width modulators 320 to 322, first and second multiplexers MUX1 and MUX2, And first and second flip-flops FF1 and FF2.

The delay signal generator 310 may receive the data pattern DP0 from the data line DQ and output a plurality of delay signals S (t0) to S (tn). Since the delay signal generator 310 has been described above, a detailed description thereof will be omitted.

The 0th to 2nd pulse width modulators 320 to 322 each receive a plurality of delay signals S (t0) to S (tn) (Y0 to Y2).

For example, as shown in FIG. 14, the zero pulse width adjuster 320 may include a pull-up driver (PUD) and a pull-down driver (PDD). As described above, the pull-up driver (PUD) may include pull-up units (PU), and each of the pull-up units (PU) Can be output. The pull-down units PD may include pull-down units PD and each of the pull-down units PD may output a low level signal when the input signal is " 1 & have.

The output signals of the pull-up unit PD0 of the pull-up driver PUD and the pull-down driver PDD of the pull-up driver PUD can be amplified with the first adjustment coefficient Cp1, The output signals of the pull-up unit PU1 of the up driver PUD and the pull-down unit PD2 of the pull-down driver PDD can be amplified to the second adjustment coefficient Cp2. The second adjustment coefficient Cp2 may be very large compared to the first adjustment coefficient Cp1. Illustratively, the first and second pulse width modulators 321 and 322 may also have a similar structure to the zero pulse width modulator 320 of FIG.

The ground voltage VSS and the power supply voltage VDD are applied to the 0th and first input terminals Z [0], Z [1] of the 0th pulse width controller 320 and the first pulse width adjuster The ground voltage VSS is applied to the zeroth and first input terminals Z [0], Z [1] of the first pulse width adjuster 322 and the zeroth and first input terminals Z [0], Z [1]).

In this case, the zeroth intermediate signal Y0 from the zero pulse width adjuster 320 may be the same as the output signal in the data pattern in which the previous data bits are " 01 " or " 10 ". The first intermediate signal Y1 of the first pulse width adjuster 321 may be the same as the output signal in the data pattern in which the previous data bits are " 00 ". The second intermediate signal Y2 of the second pulse width adjuster 322 may be the same as the output signal in the data pattern in which the previous data bits are " 11 ". The operation method of the 0 < th > to 2 < th > pulse width adjusters 320 to 322 is similar to the operation method of the pulse width adjuster described with reference to Figs. 1 to 12, and therefore a detailed description thereof will be omitted.

The first flip-flop FF1 receives the first final output signal Yout1 and can output the first feedback signal Y [1] in response to the clock signal CK. The second flip-flop FF2 can receive the second final output signal Yout2 and output the second feedback signal Y [2] in response to the inverted clock signal CKB.

The first and second MUXs MUX1 and MUX2 receive one of the 0th to 2nd intermediate signals Y0 to Y2 based on the first and second feedback signals Y [1] and Y [2] May be selected and output as the first and second final output signals Yout1 and Yout2. For example, if the first and second feedback signals Y [1], Y [2] indicate a data bit of "10" or "01", the first and second MUXs MUX1, Of the 0th to the 2nd intermediate signals Y0 to Y2 and the first and second feedback signals Y [1], Y [2] The first and second MUXs MUX1 and MUX2 select the first intermediate signal Y1 among the 0th to the 2nd intermediate signals Y0 to Y2, The first and second MUXs MUX1 and MUX2 receive the 0th to 2nd intermediate signals Y0 to Y2 when the signals Y [1] and Y [2] The second intermediate signal Y2 can be selected.

As described above, the pulse width controller 300 generates a plurality of intermediate signals whose pulse widths are adjusted for a specific data pattern, selects one of the plurality of intermediate signals based on the value of previous data bits, And output as an output signal.

15 is a timing chart for explaining the operation of the pulse width controller 300 of FIG. Referring to Fig. 15, an embodiment of the first final output signal Yout1 in the data pattern of " 1101 " is described. For the sake of brevity, the delay times for the components of pulse width adjuster 300 are excluded in FIG. However, the scope of the present invention is not limited thereto.

Referring to FIGS. 13 and 15, the delay signal generator 310 may generate the 0th and first delay signals S (t0), S (t1). The zero delayed signal S (t0) may have a low level in a part of D [n] and the first delayed signal S 1 > (ta1).

As described above, the zeroth intermediate signal Y0 may be the same as the zeroth delay signal S (t0). This is because the 0th intermediate signal Y0 is a signal for the case where the previous data bits are " 01 " or " 10 " The first intermediate signal Y1 may have a data pulse whose row section is reduced, as shown in FIG. This is because the first intermediate signal Y1 is a signal in which the pulse width adjustment is reflected on the basis that the previous data bits are " 00 ". The second intermediate signal Y2 may include a data pulse having a low level in an interval of D [n], as shown in Fig. This is because the second intermediate signal Y2 is a signal in which the adjustment of the pulse width is reflected on the basis that the previous data bits are " 11 ".

That is, at the point X [n-1], since the previous data bits are " 11 ", the second intermediate signal Y2 can be selected as the first final output signal Yout1. Illustratively, at a particular time instant ts, the zeroth intermediate signal Y0 may be selected as the first output signal Yout1. For example, at a specific time point ts, the first feedback signal Y [1] may be changed from D [n-2] to D [n]. In this case, the first and second feedback signals Y [1], Y [2] input to the first MUX MUX1 are D [n-2] / D [n- ] / D [n-1].

In this case, at a specific time point ts, the signal output from the first MUX MUX1 may be changed to the 0th intermediate signal Y0, but the first final output signal Yout1 may be output normally. This is because the previous data bits are " 10 " or " 01 " based on the X [n] point and no separate pulse width compensation is required. That is, the pulse width controller 300 of the present invention can normally output the final output signal even if the feedback signal is changed in a specific data period.

16A and 16B are block diagrams illustrating a memory system in accordance with an embodiment of the present invention. Referring to FIG. 16A, the memory system 40 may include a memory device 41 and a memory controller 42. The memory controller 42 can transmit the command CMD and the address ADDR to the memory device 41. [ The memory controller 42 can transfer the data DATA to the memory device 41 through the data line DQ and the data strobe line DQS.

Illustratively, the memory controller 42 may include a pulse width controller 400. For example, the pulse width controllers 100, 200, 300 of Figures 1-15 are configured to control the pulse width of the received data signal at the receiving end of the memory controller. On the other hand, the pulse width controller 400 of FIG. 16 can transmit the data signal having the adjusted pulse width to the memory device 41 by adjusting the pulse width of the data signal in advance at the transmitting end of the memory controller 42. If the data signal can not be normally full-swung according to the load of the data line DQ, the effective margin can be secured by transmitting the data signal by adjusting the pulse width in advance.

Referring to FIG. 16B, the memory system 40 'may include a memory device 41' and a memory controller 42 '. Since the memory controller 41 'and the memory device 42' have been described above, a detailed description thereof will be omitted.

Illustratively, the memory device 42 'may include a pulse width controller 400'. The pulse width controller 400 'may transmit the data signal having the adjusted pulse width to the memory controller 42' through the data line DQ by adjusting the pulse width of the data signal in advance.

That is, as shown in FIGS. 16A and 16B, the memory device 41 'or the memory controller 42 may be configured to pre-adjust the pulse width of the data signal and to transmit the data signal with the adjusted pulse width have.

17 is a block diagram illustrating an exemplary pulse width controller 400 of FIG. 18 is a timing chart for explaining the operation of the pulse width controller 400. FIG. For the sake of brevity, embodiments will be described with reference to the pulse width controller 400, but the scope of the present invention is not limited thereto. Referring to FIGS. 17 and 18, the pulse width controller 400 may include a delay signal generator 410 and a pulse width controller 420.

The delay signal generator 410 may output a plurality of delay signals S (t1) to S (t5) based on the input data signal S (t0). For example, the delay signal generator 410 may include first through fifth delays 411 through 412. Each of the first to fifth delay units 411 to 415 may delay the input signal by a predetermined time.

The first delay 411 may delay the input signal S (t0) by a first time and output the first delay signal S (t1). Illustratively, the first delay signal S (t1) may correspond to the input data D [n]. The second delay 412 can output the second delay signal S (t2) by delaying the first delay signal S (t1) by a second time. That is, the input signal S (t0) , The first and second delay signals S (t1) and S (t2) may have timings as shown in Fig.

The third delay 413 can output the third delay signal S (t3) by delaying the first delay signal S (t1) corresponding to the input data D [n] by 0.5 period . The fourth delay 414 may delay the third delay signal S (t3) by one period to output the fourth delay signal S (t4). The fifth delay 415 can output the fifth delay signal S (t5) by delaying the fourth delay signal S (t4) by one period. That is, the third to fifth delay signals S (t3) to S (t5) may have the timing as shown in Fig.

Illustratively, when the input data has a data pattern of " 00010 ", the input signal S (t0) and the first to fifth delay signals S (t1) to S And may have a waveform as shown.

The pulse width controller 420 receives the input signal S (t0) and the first to fifth delay signals S (t1) to S (t5), and supplies the data line DQ based on the received signals. The pulse width of the signal of FIG. For example, when the input data has a data pattern of " 00010 ", the pulse width adjuster 420 determines that the signal of the data line DQ, which corresponds to the bit of " 1 & The pulse width can be adjusted to have the pulse width.

Thus, a signal margin can be ensured according to the RC load of the data line DQ. For example, in the case where the pulse width adjustment is not performed, the signal according to the RC load may have a waveform like the dotted line in Fig. In this case, the valid margin may be the first time T1. On the other hand, when the pulse width is adjusted by the pulse width controller 400 according to the embodiment of the present invention, the signal according to the RC load may have the waveform as shown by the solid line in FIG. 18, And may be a second time T2 longer than one hour T1. That is, by adjusting the pulse width corresponding to the data bits currently to be provided based on the data bits previously transmitted to the memory device, the signal margin can be secured.

19A to 19C are block diagrams showing electronic devices having a pulse width controller (PWC) according to the present invention. For the sake of brevity, a detailed description of the components described above is omitted.

Referring to FIG. 19A, system 1000 may include first and second devices 1100, 1200. Each of the first and second devices 1100 and 1200 may be an apparatus for exchanging information signals such as a data signal, an electric signal, an analog signal, or a digital signal in the system 1000. Illustratively, each of the first and second devices 1100 and 1200 may be an information processing device such as a signal transmitter, a signal receiver, an IP block, an electronic module, an electronic circuit, or the like.

The first and second devices 1100, 1200 may each include pulse width controllers 1110, 1210. The pulse width controllers 1110 and 1210 may be the pulse width controllers described with reference to FIGS. 1 to 15, respectively. That is, the pulse width controllers 1110 and 1210 may be configured to adjust the pulse width of the signal received from the first and second devices 1100 and 1200. [

19B, the system 2000 may include first and second devices 2100 and 2200, and the first and second devices 2100 and 2200 may each include pulse width controllers (2110, 2210). The pulse width controllers 2110 and 2210 may be the pulse width controllers described with reference to Figures 16A-18. That is, each of the first and second devices 2100 and 2200 may be configured to pre-adjust the pulse width of the signal to transmit a signal having the adjusted pulse width.

19C, system 3000 includes first and second devices 3100 and 3200 and first device 3100 includes first and second pulse width controllers 3110 and 3120 ). The first pulse width controller 3110 may be the pulse width controller described with reference to Figures 16A-18 and the second pulse width controller 3120 may be the pulse width controller described with reference to Figures 1-15. have. That is, the first device 3100 may pre-adjust the pulse width of the signal to transmit a signal having the adjusted pulse width, or may be configured to adjust the pulse width at the current point based on previous bit values of the received signal .

20 is a block diagram illustrating an exemplary electronic system in which a transmitter and a receiver with a pulse width controller according to the present invention are reflected. 20, by way of example, the electronic system 1000 may be in the form of a portable communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a smart phone, or a wearable device, A workstation, a notebook computer, or the like.

The electronic system 4000 may include an application processor 4100 (or central processing unit), a display 4220, and an image sensor 4230. The application processor 4100 may include a DigRF master 4110, a Display Serial Interface (DSI) host 4120, a CSI (Camera Serial Interface) host 4130, and a physical layer 4140.

The DSI host 4120 can communicate with the DSI device 4225 of the display 4220 via the DSI. Illustratively, a DSI host 4120 may be implemented with an optical serializer (SER). By way of example, an optical deserializer (DES) may be implemented in the DSI device 4225. The CSI host 4130 may communicate with the CSI device 4235 of the image sensor 4230 via the CSI. Illustratively, optical deserializer (DES) may be implemented in CSI host 4130. As an example, an optical serializer (SER) may be implemented in the CSI device 4235.

The electronic system 4000 may further include a Radio Frequency (RF) chip 4240 in communication with the application processor 4100. The RF chip 4240 may include a physical layer 4242, a DigRF slave 4244, and an antenna 4246. Illustratively, the physical layer 4242 of the RF chip 4240 and the physical layer 4140 of the application processor 4100 may exchange data with each other by a MIPI DigRF interface.

The electronic system 4000 may further include a working memory 4250 and an embedded / card storage 4255. The working memory 4250 and the embedded / card storage 4255 may store data provided by the application processor 4100. [ Working memory 4250 and embedded / card storage 4255 may provide stored data to application processor 4100. [

Working memory 4250 may temporarily store data to be processed or processed by application processor 4100. [ The working memory 4250 may include volatile memory such as SRAM, DRAM, SDRAM, or the like, or non-volatile memory such as flash memory, PRAM, MRAM, ReRAM, FRAM, The embedded / card storage 4255 can store data regardless of whether or not the power is supplied.

The electronic system 4000 can communicate with an external system through a World Interoperability for Microwave Access (WIMAX) 1260, a Wireless Local Area Network (WLAN) 4262, an Ultra Wideband (UWB)

The electronic system 4000 may further include a speaker 1270 and a microphone 1275 for processing voice information. Illustratively, electronic system 1000 may further include a Global Positioning System (GPS) device 1280 for processing location information. The electronic system 4000 may further include a bridge chip 4290 for managing connections with peripheral devices.

By way of example, each of the components of the electronic system 4000 described above, or each of the components included in the components, may be configured to adjust the pulse width of the received signal using the pulse width controller in accordance with the present invention, The width can be adjusted in advance and the signal having the adjusted pulse width can be transmitted.

The above description is specific embodiments for carrying out the present invention. The present invention will also include embodiments that are not only described in the above-described embodiments, but also can be simply modified or changed easily. In addition, the present invention will also include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the following claims.

Claims (20)

A method of operating a signal receiver,
Sequentially receiving the zeroth and first bits through one signal line; And
A first high-level portion and a first low-level portion of the first signal corresponding to the first bit, based on the values of the zeroth and first bits, when the values of the zeroth and first bits are equal to each other, The method comprising the steps of: The method according to claim 1,
If the value of the zeroth and first bits is a logic high and the first row interval of the first signal is increased and the value of the zeroth and first bits is a logic low, Wherein the width of the first high section is increased. The method according to claim 1,
Further receiving the second bits sequentially after receiving the zeroth and first bits; And
And adjusting the width of one of the second high period and the second low period of the second signal corresponding to the second bit based on the values of the zeroth and first bits when the zeroth and first bits are identical And adjusting the width of either the second high interval and the second row interval of the second signal based on the values of the first and second bits if the first and second bits are equal ≪ / RTI > The method of claim 3,
If the value of the zeroth and first bits is a logic high or the value of the first and second bits is a logic high then the width of the second row of the second signal is increased,
Wherein the width of the second high period of the second signal is increased if the values of the zeroth and first bits are logic low or if the values of the first and second bits are logic low. The method of claim 3,
Wherein if the zeroth and second bits are all the same, the width of either the second high period and the second low period of the second signal is increased by a first time,
Wherein when either one of the zeroth and second bits is different from the other bits, a width of either the second high period and the second low period of the second signal is shorter than the first time Lt; / RTI > The method of claim 3,
Wherein if the zeroth and first bits are different and the first and second bits are different, the widths of the second high interval and the second row interval of the second signal are unadjusted. A sampler configured to sample an output signal and output a zero-th feedback signal;
A first delay configured to delay the zero-th feedback signal and output a first feedback signal; And
And a pulse width adjuster configured to adjust the width of either the high or low range of the output signal if the values of the zeroth and first feedback signals are equal to each other. 8. The method of claim 7,
And a delay signal generator configured to receive a signal for a plurality of bits through one line and output a plurality of delay signals based on the received signal. 9. The method of claim 8,
Wherein the pulse width adjuster comprises:
A plurality of inversion circuits configured to receive the plurality of delay signals and output a plurality of inverted delay signals, respectively;
A pull-up driver configured to adjust the width of the high period of the output signal based on the plurality of inverted delay signals and the zeroth and first feedback signals; And
And a pull-down driver configured to adjust the width of the low period of the output signal based on the plurality of inverted delay signals and the zeroth and first feedback signals. 10. The method of claim 9,
Further comprising control logic configured to provide at least one delay factor to the delay signal generator and to provide at least one adjustment factor to the pull-up driver and the pull-down driver,
Wherein the delay signal generator outputs the plurality of delay signals based on the at least one delay coefficient,
Wherein the pull-up driver and the pull-down driver control the widths of the high period and the low period based on the at least one adjustment coefficient. 9. The method of claim 8,
Wherein the pulse width adjuster comprises:
Increasing the width of the low period of the output signal based on the plurality of delay signals when the zeroth and first feedback signals are both logic high,
And increases the width of the high period of the output signal based on the plurality of delay signals when the zeroth and first feedback signals are both logic low. 9. The method of claim 8,
And a second delay configured to delay the first feedback signal and output a second feedback signal,
Wherein the pulse width adjuster comprises:
Increasing the width of the low period of the output signal based on the plurality of delay signals when the zero and first feedback signals are logic high or when the first and second feedback signals are logic high,
Wherein the first and second feedback signals are logic low, or when the first and second feedback signals are logic low, a pulse pulse that increases the width of the high period of the output signal based on the plurality of delay signals Width controller. 13. The method of claim 12,
Wherein the plurality of bits comprise first and second bits, the 0 < th > and second bits are sequentially received by the delay signal generator through the one line,
Wherein the zero-th feedback signal corresponds to the second bit, the first feedback signal corresponds to the first bit, and the second feedback signal corresponds to the zeroth bit. A delay signal generator for sequentially receiving signals corresponding to the 0th and 2nd bits and delaying the signals to generate a plurality of delay signals; And
A pulse width adjustment configured to adjust either the high or low width of the output signal based on the plurality of delay signals when the zeroth and first bits are equal or the first and second bits are equal, And a decision feedback equalizer. 15. The method of claim 14,
The pulse width modulation decision feedback equalizer increases the width of the low period of the output signal if the zeroth and first bits are logic high or if the first and second bits are logic high,
Wherein the pulse width modulation decision feedback equalizer increases the width of the high period of the output signal when the zeroth and first bits are logic low or when the first and second bits are logic low. 15. The method of claim 14,
Wherein if the zeroth and second bits are all the same, the pulse width modulation decision feedback equalizer increases the width of either the high section and the low section of the output signal by a first time,
Wherein if the zeroth and first bits are equal and the first and second bits are different or if the zeroth and first bits are different and the first and second bits are equal then the pulse width modulation decision feedback equalizer comprises: And increases the width of either the high section and the low section of the output signal by a second time shorter than the first time. 15. The method of claim 14,
Further comprising control logic configured to provide at least one delay factor to the delay signal generator and to provide at least one adjustment factor to the pulse width modulation decision feedback equalizer,
Wherein the delay signal generator generates the plurality of delay signals using the at least one delay coefficient,
Wherein the pulse width modulation decision feedback equalizer uses the at least one modulation factor to adjust the width of either the high section and the low section of the output signal. 15. The method of claim 14,
Wherein the pulse width modulation decision feedback equalizer comprises:
A sampler configured to sample the output signal to generate a zero-th feedback signal corresponding to the second bit;
A first delay configured to delay the zero-th feedback signal and output a first feedback signal corresponding to the first bit;
A second delay configured to delay the first feedback signal and output a second feedback signal corresponding to the zeroth bit; And
Wherein the first and second feedback signals are different from each other when the first and second feedback signals are identical or when the first and second feedback signals are identical, And a pulse width controller configured to adjust a width of one of the period and the low period. 15. The method of claim 14,
Wherein the pulse width modulation decision feedback equalizer comprises:
A first flip-flop configured to receive a first output signal of the output signal and to output a first feedback signal in response to the clock signal;
A second flip-flop configured to receive a second one of the output signals and to output a second feedback signal in response to the inverted clock signal having the inverted clock signal;
A third flip-flop configured to receive the first feedback signal and output a third feedback signal in response to the inverted clock signal;
A fourth flip-flop configured to receive the second feedback signal and output a fourth feedback signal in response to the clock signal;
A first pulse width controller configured to output the first output signal based on the first through fourth feedback signals and the plurality of delay signals; And
And a second pulse width controller configured to output the second output signal based on the first through fourth feedback signals and the plurality of delay signals. 15. The method of claim 14,
Wherein the pulse width modulation decision feedback equalizer comprises:
A zero pulse width controller configured to generate a zero intermediate signal based on the plurality of delay signals in response to a ground voltage and a supply voltage;
A first pulse width controller configured to generate a first intermediate signal based on the plurality of delay signals in response to the supply voltage;
A second pulse width controller configured to generate a second intermediate signal based on the plurality of delay signals in response to the ground voltage;
A first flip-flop configured to receive a first output signal of the output signal and to output a first feedback signal in response to the clock signal;
A second flip-flop configured to receive a second one of the output signals and to output a second feedback signal in response to the inverted clock signal having the inverted clock signal;
A first multiplexer configured to output any one of the zeroth and second intermediate signals based on the first and second feedback signals as the first output signal; And
And a first multiplexer configured to output either one of the zeroth and second intermediate signals as the second output signal based on the first and second feedback signals.

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