KR100887016B1 - Digital frequency locked delay line - Google Patents

Abstract

The apparatus includes a signal generator having a delay synchronization circuit that provides a plurality of output signals based on the input signal. These output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a selector that selects the enable signal from a range of signals formed by the output signal. The apparatus further includes a transceiver circuit, which uses the enable signal for data processing.

Semiconductor devices, digital frequency synchronization delay lines, delay synchronization circuits, phase detectors,

Description

Digital frequency synchronization delay line {DIGITAL FREQUENCY LOCKED DELAY LINE}

FIELD OF THE INVENTION The present invention generally relates to semiconductor devices, and more particularly to the generation of signals in semiconductor devices.

BACKGROUND Semiconductor devices, such as memory devices, memory controllers, and processors, exist in many computers and electronics to store and process data. Most of these devices use electrical signals to communicate with each other or within the same device.

The operating speed of the device depends in part on the frequency of the signal. As semiconductor devices become more advanced, one part of the device may operate at one frequency and another part of the same device or another device may operate at a different frequency. Thus, synchronizing different operations on different parts of the same device or on different devices can be complex and constrained.

Embodiments of the present invention provide circuits and methods for generating a range of stable signals over a wide range of frequencies to provide flexibility in semiconductor devices to improve operation within the same device or between different devices.

One aspect includes a device having a delay line. This delay line has a plurality of variable delay cells. Each variable delay cell has a number of delay control nodes that receive a delay code. The apparatus also includes a phase detector for comparing the signals from the input and output nodes of the delay line. The apparatus also includes a code adjuster that adjusts the delay code in response to the phase detector. The apparatus also includes a selector that selects from a range of output signals from the plurality of output nodes of the variable delay cell to provide an enable signal.

Another aspect includes a method of generating a signal. This method sets delay codes for a number of variable delay cells. This method propagates an input signal through the variable delay cell to obtain a delayed output signal. This method adjusts the delayed output signal until the input signal and the delayed output signal have a fixed signal relationship. This method selects from a range of output signals at multiple output nodes of the variable delay cell. This method delivers the selected output signal to an enable node.

Further aspects include a method of processing a signal. The method receives at least one data signal and at least one strobe signal. This method propagates the input signal through a plurality of variable delay cells to obtain a plurality of cell output signals such that each of the cell output signals has a fixed signal relationship with the input signal. This method selects one of the cell output signals as an enable signal. The method activates at least one receiver for transferring at least one of a data signal and a strobe signal from one part of the device to another part of the device.

Other aspects of the present invention will become apparent upon a review of the present application, including the drawings and the claims.

1 illustrates a signal generator having a delay synchronization circuit according to embodiments of the present invention.

2 is an exemplary timing diagram for FIG. 1.

3 illustrates a delay controller having a digital delay code generator in accordance with embodiments of the present invention.

4 illustrates a delay line having a variable delay cell according to embodiments of the present invention.

5 illustrates a memory device according to embodiments of the present invention.

6 illustrates a memory system in accordance with embodiments of the present invention.

7 illustrates an electronic system in accordance with embodiments of the present invention.

8 illustrates a testing system in accordance with embodiments of the present invention.

The following description and drawings illustrate specific embodiments of the present invention that will enable those skilled in the art to fully practice the present invention. Other embodiments may include structural, logical, electrical processes, and other changes. In the drawings, like reference numerals refer to like elements throughout the several views. The examples only represent possible variations. Portions and features of certain embodiments may be included in or substituted for parts and features of other embodiments. The scope of the invention is encompassed by the claims and all available equivalents.

1 illustrates a signal generator 100 having a delay synchronization circuit according to an embodiment of the present invention. The signal generator 100 includes a delay synchronization circuit 110, an enable controller 120, and selectors 131 and 132. The delay synchronization circuit 110 receives the input signal CLK_IN at the input node 101 and generates a delayed output signal DL_OUT at the output node 102. The DL_OUT signal is a delayed version of the CLK_IN signal. In some embodiments, the CLK_IN signal is a clock signal. Delay synchronization circuit 110 also generates a plurality of cell output signals EN0-EN3 (EN0, EN1, EN2, EN3) at node 101 and cell output nodes 111, 112, 113. The delay synchronization circuit 110 generates a lock signal LOCK on the selection node 109 to control the selection of the selector 131.

The selector 131 receives the clock signal CLK on the input node 133 and the preamble signal PREAMBLE_EN on the node 135. Based on the state of the LOCK signal, the selector 131 selects one of the CLK signal or the PREAMBLE_EN signal as the CLK_IN signal on the node 101. In some embodiments, the CLK signal is a clock signal.

Enable controller 120 provides a PREAMBLE_EN signal to selector 131 and an enable code EN_CODE on select node 128 in response to control signal CNTL. In some embodiments, EN_CODE is a combination of multiple binary bits provided by multiple different signals on different signal lines. 1 shows lines 128 as one line for clarity.

The selector 132 selects one of the EN0-EN3 signals and uses EN_CODE to send it to the enable node 190 as an enable (EN) signal. Thus, the EN signal is one of the EN0-EN3 signals selected by the enable controller 120 based on the value of EN_CODE.

The delay synchronization circuit 110 includes a delay line 104 having a plurality of delay cells 121-124 (121, 122, 123, 124), a phase detector 106, an inversion unit 115, and a code adjuster 108. Delay controller 105, In the embodiment shown in FIG. 1, delay line 104 includes, for example, four delay cells 121-124. In some embodiments, the number of delay cells of delay line 104 may differ from four. Thus, in some embodiments, the number of cell output signals, such as EN0-EN3 signals, may differ from four.

Delay line 104 applies a delay (delay time) to the signal path of the CLK_IN signal between input node 101 and output node 102. The delay amount applied by the delay line 104 is the total delay amount of the delay cells 121-124. The delay amount of each of the delay cells 121-124 is controlled by the same delay code DL_CODE on the line 138. Each of the delay cells 121-124 is a variable delay cell. Since each of the delay cells 121-124 is controlled by the same DL_CODE, each of the delay cells 121-124 has the same or the same amount of delay regardless of the value of the DL_CODE. In some embodiments, the DL_CODE is a digital code. Thus, in some embodiments, the delay of each of delay cells 121-124 is digitally controlled.

Phase detector 106 has an input node that receives signal CLK_IN * and DL_OUT signal. The CLK_IN * signal is the inversion of the CLK_IN signal at the output node of the inverter 115. In some embodiments, inverter 115 is included within phase detector 106. Phase detector 106 has output nodes 126, 127 that provide adjustment signals ADJ1, ADJ2.

The code regulator 108 outputs DL_CODE on line 138 in response to the ADJ1 and ADJ2 signals. In some embodiments, the DL_CODE is a digital code represented by a combination of a number of binary bits corresponding to a number of different signals on different signal lines. 1 shows lines 138 as one line for clarity.

The delay synchronization circuit 110 uses the CLK_IN signal to generate the DL_OUT signal so that the DL_OUT signal has a signal relationship with the CLK_IN signal. In FIG. 1, the DL_OUT signal is 180 degrees out of phase with the CLK_IN signal.

The delay synchronization circuit 110 has a pre-locked mode and a locked mode. In the pre-sync mode, the phase between the CLK_IN * signal and the DL_OUT signal may not be in a fixed relationship. The delay synchronization circuit 110 adjusts the delay line 104 until the phase between the CLK_IN * signal and the DL_OUT signal is fixed. In FIG. 1, the delay synchronization circuit 110 adjusts the delay line 104 until the CLK_IN signal and the DL_OUT signal have the same phase. When the CLK_IN signal and the DL_OUT signal have the same phase, the delay synchronization circuit 110 activates the LOCK signal to put the delay synchronization circuit 110 in the synchronization mode.

In the pre-sync mode, phase detector 106 compares the phase difference between the CLK_IN * signal and the DL_OUT signal. In some embodiments, phase detector 106 compares the rising edge (or falling edge) of the CLK_IN * signal with the DL_OUT signal. If the edges of the CLK_IN * and DL_OUT signals do not match, the phase detector 106 activates one of the ADJ1 signal and the ADJ2 signal. The code adjuster 108 adjusts (increases or decreases) the value of the DL_CODE in response to the ADJ1 or ADJ2 signal. The value of DL_CODE controls the amount of delay that delay line 104 applies to the CLK_IN signal. Therefore, when the value of DL_CODE is adjusted, the delay amount of delay line 104 is also adjusted. The comparison and adjustment process is performed until the CLK_IN * and DL_OUT signals have the same phase. When the CLK_IN * and DL_OUT signals have the same phase, the delay synchronization circuit 110 activates the LOCK signal to put the delay synchronization circuit 110 in the synchronization mode.

In Fig. 1, since the CLK_IN * signal is the inversion of the CLK_IN signal (out of 180 degree phase with the CLK_IN signal), when the delay synchronization circuit 110 is in the synchronous mode, the DL_OUT signal is also 180 degrees out of phase with the CLK_IN signal. Is out.

2 is an exemplary timing diagram for FIG. 1. 2 shows the timing of the delay synchronization circuit 100 (FIG. 1) in the synchronization mode. For clarity, FIG. 2 ignores the delay caused by the selectors 131, 132. As shown in Fig. 2, the DL_OUT and CLK_IN * signals have the same phase. The DL_OUT signal is 180 degrees out of phase with the CLK_IN signal. T _CK represents a cycle (cycle) of the CLK or CLK_IN signal.

2 shows that the EN0-EN3 signals have a fixed signal relationship with the CLK_IN signal. As shown in FIG. 2, each of the EN1-EN3 signals has a fixed delay of multiples of 1/8 T _CK (1/8 clock cycles) for the CLK or CLK_IN signal. For example, the EN1 signal has a delay of 1/8 T _CK relative to the CLK or CLK_IN signal. As another example, the EN2 signal has a delay twice the 1/8 T _CK for the CLK or CLK_IN signal. 2 also shows that each of the EN1-EN3 signals has a fixed delay multiple of 1/8 T _CK relative to each other. For example, the EN1 signal has a delay of 1/8 T _CK for the EN2 signal and twice the delay (or 1/4 clock cycle) of 1/8 T _CK for the EN3 signal.

In certain embodiments, EN0-EN3 signals each of N times the T CLK or CLK_IN signal _CK for the (NT _CK) (where, N is a real number being less than 1) has a fixed delay, such as.

Because the EN0-EN3 signal has a fixed signal relationship with the CLK or CLK_IN signal, the frequency of the EN0-EN3 signal changes when the frequency of the CLK or CLK_IN signal changes. However, the fixed relationship remains unchanged. For example, when the cycle of the CLK_IN signal is 1 nanosecond, each of the EN1-EN3 signals has a fixed delay of multiples of 0.125 nanoseconds (1/8 T _CK ) relative to the CLK_IN signal. As another example, when the cycle of the CLK_IN signal is 2 nanoseconds, each of the EN1-EN3 signals has a fixed delay of multiples of 0.25 nanoseconds (still 1/8 T _CK for the CLK_IN signal).

The PREAMBLE_EN signal has a fixed relationship with the CLK_IN signal. In the embodiment shown in FIG. 2, the PREAMBLE_EN signal has about 50 percent duty ratio. In some embodiments, the duty ratio of the PREAMBLE_EN signal may be different than 50 percent. In some embodiments, the PREAMBLE_EN signal includes a number of pulses where each rising edge of each pulse matches the rising edge of the CLK_IN signal.

FIG. 2 shows that signals EN0-EN3 of a certain range (each signal in this range has a fixed signal relationship with the CLK, CLK_IN and PREAMBLE_EN signals) are present in the signal generator 100. Thus, if the CLK, CLK_IN or PREAMBLE_EN signal is an inappropriate choice, any one of the EN1-EN3 signals may be used instead of the CLK, CLK_IN or PREAMBLE_EN signal.

3 illustrates a delay controller 300 having a digital delay code generator 330 in accordance with embodiments of the present invention. The delay controller 300 includes a phase detector 306, an inverter 315, and a code adjuster 308 having a logic unit 320 and a digital delay code generator 330. Phase detector 306 receives input signals CLK_IN *, DL_OUT and activates adjustment signals ADJ1, ADJ2. The logic unit 320 controls the lock signal LOCK in response to the ADJ1 and ADJ2 signals. The digital delay code generator 330 generates a plurality of code bits C0-CN on the bit lines 331 and 332 in response to the ADJ1 and ADJ2 signals.

Phase detector 306 compares the signal relationship between the CLK_IN * signal and the DL_OUT signal. In some embodiments, phase detector 306 compares the rising edge (or falling edge) of the CLK_IN * and DL_OUT signals to control the ADJ1 and ADJ2 signals. For example, the phase detector 306 activates the ADJ1 signal and deactivates the ADJ2 signal when the rising edge of the CLK_IN * signal is ahead of the rising edge of the DL_OUT signal. As another example, phase detector 306 activates the ADJ2 signal and deactivates the ADJ1 signal when the rising edge of the CLK_IN * signal is lagging behind the rising edge of the DL_OUT signal. In some embodiments, the anomaly detector can detect both ADJ1 and ADJ2 signals when the edges (eg, rising edges) of the CLK_IN * and DL_OUT signals match (which is also when the CLK_IN * and DL_OUT signals have the same phase). Deactivate.

In some embodiments, logic unit 320 is configured to activate the LOCK signal when both ADJ1 and ADJ2 signals have the same signal level. For example, logic unit 320 activates the LOCK signal when both ADJ1 and ADJ2 signals have a low signal level. In other embodiments, the logic unit 320 is configured to activate the LOCK signal when none of the ADJ1 and ADJ2 signals are active within multiple cycles of the clock signal CLK. For example, the logic unit 320 activates the LOCK signal when neither of the ADJ1 and ADJ2 signals are activated within three cycles of the CLK signal.

The digital delay code generator 330 includes a counter 334 having a counter bit line connected to the bit lines 331 and 332. In Fig. 3, the bit lines 331 and 332 are also referred to as counter bit lines. In some embodiments, counter 334 is an up-down counter. The combination of code bits C0-CN represents a binary value (digital value) corresponding to the count value of the counter 334. Digital delay code generator 330 uses counter 334 to adjust the value of the C0-CN code bits based on the ADJ1 and ADJ2 signals. In some embodiments, digital delay code generator 320 sets the value of counter 334 such that the value of the CO-CN code bit corresponds to the minimum delay of the delay line, such as delay line 104 of FIG. 1. .

In some embodiments, digital delay code generator 330 adjusts the value of the C0-CN code bit by increasing or decreasing the count value of counter 334. For example, the digital delay code generator 330 can increase the count value of the counter 334 when the ADJ1 signal is activated, and decrease the count value of the counter 334 when the ADJ2 signal is activated. .

In some embodiments, digital delay code generator 330 stops adjusting the value of the C0-CN code bit when both ADJ1 and ADJ2 signals have the same signal level. In other embodiments, the digital delay code generator 330 stops adjusting the value of the C0-CN code bit when none of the ADJ1 and ADJ2 signals are active within multiple cycles of the clock signal CLK. do. In some other embodiments the digital delay code generator 330 stops adjusting the value of the C0-CN code bit when the LOCK signal is activated by the logic unit 320.

In some embodiments, the delay controller 300 of FIG. 3 may be used to control a delay line, such as the delay line 104 of FIG. 1. In these embodiments, digital delay code generator 320 may set the value of counter 334 such that the value of the C0-CN code bit causes the delay line to have an initial delay value. In some embodiments, the initial delay value is the minimum delay value within the delay value range of the delay line. In other embodiments, the initial delay value is any value within the delay value range of the delay line.

In some embodiments, delay controller 300 replaces delay controller 105 of FIG. 1.

4 illustrates a delay line 400 having a variable delay cell according to embodiments of the present invention. Delay line 400 includes a plurality of delay cells 421-424 and 421 for applying a delay to input signal CLK_IN at input node 401 to generate an output signal DL_OUT at output node 402. 422, 423, 424. The DL_OUT signal is a delayed version of the CLK_IN signal. The CLK_IN and DL_OUT signals have a fixed signal relationship. In some embodiments, the CLK_IN and DL_OUT signals are 180 degrees out of phase. In other embodiments, the DL_OUT signal is also out of phase with the CLK_IN signal, where N is between 0 and 360. For example, N can be 90 or 270.

Delay line 400 also generates a plurality of cell output signals EN0, EN1, EN2, EN3. The EN0 signal is a CLK_IN signal. The EN1, EN2, and EN3 signals are the signals at the cell output nodes of delay cells 421, 422, and 423, respectively. In some embodiments, each of the EN1, EN2, and EN3 signals has a fixed signal relationship with each other. For example, the EN2 signal is a delay of the EN1 signal by the first delay amount, and the EN3 signal is a delay of the EN2 signal by the second delay amount, where the second delay amount is equal to the first delay amount. Each of the EN1, EN2 and EN3 signals has a fixed delay equal to N times T _CK (NT _CK ) relative to the CLK_IN signal, where N is a real number less than 1 and T _CK is the cycle (cycle) of the CLK_IN signal. For example, each of the signals EN1, EN2, and EN3 may be delayed by a multiple of 1/8 T _CK (1/8 clock cycles) of the CLK_IN signal. As another example, each of the EN1, EN2, and EN3 signals may be such that the CLK_IN signal is delayed by a multiple of 1/4 T _CK (1/4 clock cycles) of the CLK_IN signal.

Each of the delay cells 421-424 is a variable delay cell. Each of delay cells 421-424 applies the same amount of delay to the signal path of the CLK_IN signal between node 401 and node 402. Each cell includes a number of delay control nodes 411, 412, 413, 431, 432, 433. A number of delay code bits (signals) DL_C0, DL_C1, DL_CN, and DL_CO *, DL_C1 *, CL_CN * control the amount of delay in each of the cells 421-424. These code bits form multiple code bit pairs. For example, the code bits DL_C0 and DL_C0 * form a pair of code bits. Other code bit pairs include DL_C1 and DL_C1 *, and DL_CN and DL_CN *. The code bits in each pair may be represented as a pair of signals (one signal being an inverted version of the other signal). For simplicity, the code bits DL_C0, DL_C1, DL_CN, and DL_C0 *, DL_C1 *, DL_CN * are all referred to as DL_C codes.

In some embodiments, the DL_C code is a digital code. For example, DL_C may be a combination of binary bits representing a binary value. The DL_C code of FIG. 4 may indicate the DL_CODE of FIG. 1.

For clarity, FIG. 4 shows a detailed structure of only delay cell 421. The other delay cells 422, 423, 424 have a structure similar to the delay cell 421.

Delay cell 421 includes a number of delay stages 451, 452, 453 connected in parallel between power supply nodes 461, 462. Each of the delay stages includes an input node 471 and an output node 472. All input nodes 471 in one delay cell are connected to each other. The combination of the input nodes 471 of the delay stages in one delay cell is also an input node (cell input node) of the delay cell. The combination of the output nodes 472 of the delay stages in one delay cell is also the output node (cell output node) of the delay cell.

The output node of one delay cell is connected to the input node of the other delay cell in successive delay cells. For example, the output node 472 of the delay cell 421 is connected to the input node IN of the delay cell 422. For clarity, the input nodes and output nodes of delay cells 422, 423, 424 are labeled IN and OUT, respectively. All delay cells 421-424 have the same number of delay stages.

Each of the delay stages 451, 452, and 453 includes a plurality of transistors 481-484, 481, 482, 483, 484 connected in series between the node 461 and the node 462. The transistors in each stage form a current path in each stage. For example, transistors 481-484 in delay stage 451 form a current path between node 461 and node 462. Because delay cell 421 has multiple delay stages in parallel between node 461 and node 462, multiple parallel current paths exist in delay cell 421 (one current in each delay stage). Path exists).

The amount of current in each current path is controlled by a pair of code bits of the DL_C code. For example, in the delay stage 451, the code bits DL_C0 and DL_C0 * control the gate transistors 481, 484 to control the amount of current in the delay stage 451. Thus, the transistors 481 and 484 function as switches that control the amount of current in each current path, with the gate of the transistor serving as the switch control node of the switch. Similarly, the amount of current in delay stage 452 is controlled by code bits DL_C1 and DL_C1 *. The amount of current in delay stage 453 is controlled by the code bits DL_CN and DL_CN *. The amount of current in each delay cell can be increased or decreased by selecting multiple active delay stages in each delay cell. The active (activated) delay stage is a delay stage in which both transistors 481 and 484 are turned on. The inactive (deactivated) delay stage is a delay stage in which one or both transistors 481 and 484 are turned off.

Since the amount of current in each delay cell is controlled by the same code bit DL_C, the delay cells 421-424 have the same amount of current. Since the amount of current in each delay cell is controlled by the code bit DL_C, in embodiments where the DL_C code is a digital code, the amount of current in each of the delay cells 421, 422, 423 is digitally controlled.

The total delay amount of the delay line 400 depends on the delay of each of the delay cells 421-424. The delay amount of each delay cell depends on the current in the current path of each delay cell. Thus, by adjusting the current in the current path of each delay cell, the total delay of the delay line 400 is also adjusted. The current in the current path of each delay cell is proportional to the number of active delay stages in each delay cell. Since each delay stage can be activated by the code bits of the DL_C code, the number of active delay stages can be selected by selecting the value of the code bits of the DL_C code.

In some embodiments, the DL_C code is a combination of binary bits. In these embodiments, other combinations of binary bits may be selected to generate different numbers of active delay stages. For example, a combination of binary bits 001 can be selected to activate delay stage 453 and deactivate stages 451 and 452. Thus, in this example, only one of the delay stages is activated in each of the delay cells 421-424. As another example, a combination of binary bits 110 can be selected to activate delay stages 451 and 452 and deactivate delay stage 453. Thus, in this example, two delay stages are activated in each of delay cells 421-424.

In some embodiments, the delay stages in each of the delay cells 421-424 form an even number of current starved inverters, where each current lacking inbuffer is formed by an odd number of delay stages and each The current deficient inverter is controlled by the same delay code as the DL_C code. For example, delay cell 421 may include six delay stages, where three delay stages of the first group (delay stages 451, 452, 453, etc.) form a first current deficient inverter and Three delay stages of the second group (similar to delay stages 451, 452, 453) form a second current deficient inverter connected in series with the first current deficient inverter. The first and second current deficient inverters in this example are controlled by the same DL_C code. Since all current deficient inverters are controlled by the same delay code, all current deficient inverters have the same amount of delay.

In embodiments where each of the delay cells 421-424 has M current deficient inverters (where M is even) and each of the EN1-EN3 signals has a fixed delay (NT _CK ) relative to the CLK_IN signal, each current lack inverter (N / M) T _CK (i.e., N / M times the T _CK) (However, T being the cycle of the _CK signal CLK_IN) has a delay. For example, in an embodiment where the delay line 400 has eight current deficient inverters (two current deficient inverters in each delay cell), the EN1, EN2 and EN3 signals are each 1/8 T _CK for the CLK_IN signal. , 1/4 T _CK , and 3/8 T _CK . In this example, all eight current deficient inverters have the same delay of 1/16 T _CK .

In the delay line 400 of FIG. 4, since the DL_OUT signal is delayed by the amount applied by the delay cells 421-424, the relationship between CLK_IN and DL_OUT can be adjusted by adjusting the delay in each delay cell. have. As described above, different values of the DL_C code may be selected to adjust the amount of delay in each delay cell.

In some embodiments, the value of the DL_C code is controlled by a delay controller, such as delay controller 105 of FIG. 1 or delay controller 400 of FIG. 4.

In the embodiment shown by FIG. 4, delay line 400 includes, for example, four delay cells. In some embodiments, the number of delay cells in delay line 400 may differ from four. Thus, in some embodiments, the number of cell output signals, such as EN0-EN3 signals, may differ from four. In addition, FIG. 4 shows, for example, each delay cell having three delay stages. In some embodiments, the number of delay stages in each delay cell may be different from three.

In some embodiments, delay line 400 replaces delay line 104 of FIG. 1.

5 illustrates a memory device 500 according to embodiments of the present invention. The memory device 500 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, or a flash memory device. Examples of DRAM devices include synchronous DRAM (SDRAM), synchronous graphics random access memory (SGRAM), various generations of double data rate SDRAM (DDR SDRAM), various graphics double data rate DRAM (GDDR), and rambus DRAM devices. In FIG. 5, certain elements of the memory device 500 are omitted for clarity.

The memory device 500 includes a memory array 502 having a plurality of memory cells 503 for storing data. Memory cells 503 are arranged in rows and columns.

The row decoder 504 and the column decoder 506 access the memory cell 503 in response to the address signals A0 to AX (A0-AX) provided on the address line 508.

The row address buffer 534 transfers the row address on the line 508 to the row decoder 504 based on the signal on the line 544. The column address buffer 536 sends the column address on line 508 to column decoder 506 based on the signal on line 546.

The control circuit 518 controls the operation of the memory device 500 in response to a control signal on the control line 520. Examples of control signals on line 520 include RAS * (row access strobe) signal, CAS * (column access strobe) column, WE * (write enable, write enable) signal, CS * (Chip Select) signal, and CLK (Clock, Clock) signal. Examples of operations of the memory device 500 include read operations and write operations. The control circuit 518 issues a READ command in the read operation and a WRITE command in the write operation.

The write operation writes input data from the data line or data terminal 594 into the memory cell 503. The read operation reads output data from the memory cell 503 into the data line 594. The data line 594 is a bidirectional data line, which carries both input data provided to the memory device 500 by an external source and output data output from the memory device 500. The combination of address signals A0-AX, different from line 508, provides the address of the row or column of memory cell 503 that is being read or written.

The control circuit 518 includes a mode register 519 that stores values representing an operation code of the memory device 500. Examples of operation codes include a write latency time interval and a read latency time interval.

Memory device 500 also includes strobe transceiver circuitry 570, data transceiver circuitry 590, input data path 511, and output data path 522. Data transceiver circuitry 590 transfers data to and from memory device 500. The strobe transceiver circuit 570 transmits timing information of the data.

The strobe transceiver circuit 570 includes a write strobe unit 571 and a read strobe unit 573. The write strobe unit 571 has strobe input circuits (STRB IN) 572-0 to 572-M. The write strobe unit 571 transfers timing information of the input data. The write strobe signal (bits) WDQS-0 to WDQS-M on the line or strobe terminal 582 indicates timing information of the input data. The external source provides the WDQS-0 through WDQS-M signals with the input data to the memory device 500.

Read strobe unit 573 has strobe output circuits (STRB OUT) 574-0 to 574-M. The read strobe unit 573 carries timing information of the output data. The read strobe signals RDQS-0 to RDQS-M on the line or strobe terminal 584 represent timing information of the data output from the memory device 500.

The data transceiver circuit 590 includes a data transceiver (D TX) 592-0 through 592-N. The data transceivers 592-0 through 592-N are bidirectional circuits, which carry data in both directions. Data transceivers 592-0 through 592-N transmit both input data and output data. Data (data signal or data bits) DQ-0 to DQ-N on the data line 594 represent both input data and output data. When memory device 500 receives data during a write operation, DQ-0 through DQ-N represent input data. When the memory device 500 outputs data during a read operation, DQ-0 to DQ-N represent output data.

In some embodiments, each of the RDQS-0 to RDQS-M signals carries timing information of one of the DQ-0 to DQ-N signals, and in these embodiments, the number of RDQS-0 to RDQS-M signals is DQ- It is equal to the number of 0 to DQ-N signals (N = M). In other embodiments, each of the RDQS-0 through RDQS-M signals carries timing information of a group of DQ-0 through DQ-N signals, and in these embodiments, the number of RDQS-0 through RDQS-M signals is DQ. -0 to less than the number of DQ-N signals (M <N).

Input data path 511 transfers data between data transceiver circuit 590 and memory array 502 during a write operation. Output data path 522 transfers data between data transceiver circuit 590 and memory array 502 during a read operation.

In some embodiments, lines 508, 520, 582, 584, 594 correspond to pins or solder balls on packaged integrated circuits of memory device 500. In other embodiments, lines 508, 520, 582, 584, and 594 correspond to pads on the circuit die of memory device 500.

The memory device 500 further includes a signal generator 588 for generating a plurality of enable signals EN (0 -N) in response to the control signal CNTL on the line 589. In some embodiments, signal generator 588 includes an embodiment of signal generator 100 described in FIGS. In some embodiments, the EN (0-N) signal includes one of the EN0-EN3 signals described in Figures 1-4. In other embodiments, the EN (0-N) signal includes a combination of the EN0-EN3 signals described in Figures 1-4.

In some embodiments, signal generator 588 includes a signal generator, such as signal generator 100, wherein the signal generator includes a small number of delay cells such that signal generator 588 can be a relatively compact circuit. do. Thus, to provide a range of signals, such as the EN0-EN3 signals described in FIGS. 1-4, the signal generator 588 may be locally formed in a relatively small area at a suitable location of the memory device 500. There are embodiments that exist.

In some embodiments, the EN (0-N) signal is a strobe input circuit (STRB IN) 572-0 to 572-M, a strobe output circuit (STRB OUT) 574-0 to 574-M, and a data transceiver It serves as a timing signal for controlling the combination of (592-0 to 592-N). In another embodiment, the EN (0-N) signal serves as a control timing signal in another circuit portion of the memory device 500.

6 illustrates a memory system 600 in accordance with embodiments of the present invention. Memory system 600 includes devices 610 and 620, and an external clock generator 630.

External clock generator 630 provides an external clock CLK to both devices 610 and 620. In some embodiments, external clock generator 630 includes an oscillator on a circuit board.

Device 610 includes transceiver circuitry 612 having multiple data drivers 614 for providing multiple data signals DQ-0 through DQ-N, and multiple strobe signals DQS-0 through DQS-M. It includes a number of strobe drivers 616 to provide. Each of the strobe signals DQS-0 through DQS-M carries timing information of one or more of the data signals DQ-0 through DQ-N.

Apparatus 620 includes transceiver circuitry 622 with multiple data receivers 624 for receiving DQ-0 through DQ-N signals and multiple strobe receivers 628 for receiving DQS-0 through DQS-M signals. Include. Each of the strobe signals DQS-0 through DQS-M carries timing information of one or more of the data signals DQ-0 through DQ-N.

The signal generator 635 provides the enable signal EN to control the strobe receiver 629 during operations such as a write operation of the device 620. The EN signal activates receiver 628 to allow DQS-0 through DQS-M signals to be passed from input node 627 of receiver 628 to output node 629.

The data timing generator 640 provides a data enable signal D_EN to control the data receiver 624 during an operation such as a write operation of the device 620. The D_EN signal activates receiver 624 to allow DQ-0 through DQ-N signals to be passed from input node 623 of receiver 624 to output node 625.

In some embodiments, signal generator 635 includes embodiments of signal generators and other circuit elements, such as signal generator 100 described in FIGS. In other embodiments, the data timing generator 640 includes embodiments of signal generators and other circuit elements, such as the signal generator 100 described in FIGS. 1-5. In some other embodiments, both signal generator 635 and data timing generator 640 include embodiments of signal generators and other circuit elements, such as signal generator 100 described in FIGS.

Device 620 also includes an internal clock generator 650 for providing an input signal CLK_IN to signal generator 635. The data capture circuit 660 captures the DQ-0 through DQ-N signals and the DQS-0 through DQS-M signals for further processing. The control unit 670 controls the other circuit of the device 600.

The EN, CLK, and CLK_IN signals are similar to the signals described in Figures 1-4. As illustrated in FIGS. 1 to 4, the signal generator 100 provides a range of enable signals, such as an EN0-EN3 signal, wherein one of the EN0-EN3 signals is selected as the EN signal. In FIG. 6, signal generator 635 may include embodiments of generator 100. Accordingly, signal generator 635 also provides a range of enable signals similar to EN0-EN3 signals. This range of enable signals provides the device 620 with the flexibility to select an appropriate signal from the range of enable signals in this range in order to properly control the transmission of signals such as DQS-0 to DQS-M signals. In addition, enable signals in this range provide a useful alternative when signals such as CLK and CLK_IN signals are an inappropriate choice.

In some embodiments, device 610 is a memory device, such as memory device 500 of FIG. 5, and device 620 is a memory controller. In other embodiments, device 610 is a memory device, such as memory device 500 of FIG. 5, and device 620 is a processing unit, such as a microprocessor. In some embodiments, both devices 610 and 620 are formed on a single chip.

7 illustrates an electronic system 700 in accordance with embodiments of the present invention. The electronic system 700 includes a processor 710, a memory device 720, a memory controller 730, a graphics controller 740, an input and output (I / O) controller 750, a display 752, a keyboard 754. ), Pointing device 756, and peripheral device 758. Bus 760 connects all of these devices to each other. The clock generator 770 provides an external clock signal CLK to at least one of the devices of the electronic system 700. Two or more devices shown in electronic system 700 may be formed on a single chip. In some embodiments, the electronic system 700 may omit one or more devices shown in FIG. 7.

The bus 760 may be conductive wiring on a circuit board or may be one or more cables. The bus 760 may also connect the devices of the electronic system 700 by wireless means, such as electromagnetic radiation (eg, radio waves). Peripheral device 758 can be a printer, an optical device (eg, a CD-ROM device or a DVD device), a magnetic device (eg, a floppy disk driver), or an audio device (eg, a microphone). The memory device 720 may be a DRAM device, an SRAM device, or may be a flash memory device or a combination thereof.

At least one of the devices shown in the electronic system 700 includes embodiments of signal generators and other circuit elements, such as the signal generator 100 described in FIGS. Thus, at least one of the devices shown in the electronic system 700 has the option of selecting an enable signal from a range of enable signals, such as the EN0-EN3 signals described in FIGS. The option of selecting an enable signal from a range of enable signals is such that at least one of the devices in the electronic system 700 can properly transmit data within the same device or between two or more devices of the electronic system 700. I can do it.

The electronic system 700 of FIG. 7 may be a computer (eg, desktop, laptop, handheld, server, web appliance, router, etc.), a wireless communication device (eg, cellular telephone, cordless phone, pager, personal). Mobile terminals, etc.), computer-related peripherals (eg, printers, scanners, monitors, etc.), entertainment devices (eg, televisions, radios, stereos, tape and compact disc players, video cassette recorders, camcorders) , Digital cameras, Motion Picture Experts Group (MP3) players, video games, clocks, and the like), and the like.

8 illustrates a testing system 800 in accordance with embodiments of the present invention. The testing system 800 includes a circuit hub 810 that is connected to the device 820 through multiple conductor lines or channels 825. In some embodiments, circuit hub 810 is a tester and device 820 is a semiconductor device. In other embodiments, circuit hub 810 is a tester, and device 820 is a memory device, such as memory device 500 of FIG. 5. In some embodiments, the D0-DN signal on line 825 represents a combination of the DQ-0 through DQ-N signals, the WDQS-0 through WDQS-M signals, and the RDQS-0 through RDQS-M signals of FIG. 5. In another embodiment, the D0-DN signal on line 825 represents a combination of the DQ-0 through DQ-N signals and the DQS-0 through DQS-M signals in FIG. 6.

In some embodiments, device 820 operates at a first frequency. In another embodiment, the device 820 operates at a second frequency, which is not equal to the first frequency. The circuit hub 810 is configured to manage data transmissions with the device 820. In some embodiments, circuit hub 810 is configured to test device 820, where device 820 operates at varying frequencies.

The circuit hub 810 includes an apparatus 830 having a signal generator 840 and a control unit 850. In some embodiments, device 830 is a memory controller. In other embodiments, the apparatus 830 is a processing unit, such as a processor. The signal generator 840 of the device 830 generates a number of enable signals EN0-EN3 (EN0 through EN3). The control unit 810 provides control for the device 830. In some embodiments, the control unit 810 is configured to scan the EN0-EN3 signal to select one of the EN0-EN3 signals, wherein the selected signal is configured by the circuit hub 810 to circuit with the device 820. This allows proper management of the transmission of D0-DN signals between hubs 810. In some embodiments, device 830 of circuit hub 810 includes an embodiment of device 620 of FIG. 6.

Signal generator 830 includes an embodiment of signal generator 100, 588 or 635 described in FIGS. 1 to 7. In Fig. 8, the EN0-EN3 signal represents the EN0-EN3 signal described in Figs. As illustrated in Figures 1-7, the EN0-EN3 signal provides a range of enable signals, where an enable signal within that range can be selected to appropriately control the transmission of signals between devices. .

In FIG. 8, since device 820 operates at varying frequencies, device 820 may transmit D0-DN signals in the varying frequency domain. The EN0-EN3 signal provides flexibility to properly manage the transmission of the D0-DN signal by selecting from among EN0-EN3 signals a signal that fits the frequency domain of the circuit hub 810 to the respective frequency domain of the device 810. To 810. For example, the circuit hub 810 may select an EN1 signal to manage the transmission of the D0-DN signal when the device 820 operates at a first frequency, and the circuit hub 810 may select the device ( When 820 operates at a second frequency not equal to the first frequency, the EN2 signal may be selected to manage the transmission of the D0-DN signal. Thus, circuit hub 810 is configured to select an EN0-EN3 signal based on the operating frequency of device 810 to manage the transmission of the D0-DN signal between circuit hub 810 and device 820. have.

In the description of FIGS. 1-7, portions and features in certain embodiments may be included in or substituted for portions and features of other embodiments.

conclusion

Various embodiments of the present invention provide circuits and methods for generating a range of stable signals to improve operation within the same device or between different devices.

As integrated circuit devices become more advanced, one part of this device may operate at one frequency and another part of this device or another device may operate at different frequencies. Thus, synchronizing different operations in different parts of the same device or between different devices can be complicated. Embodiments of the present invention provide techniques that provide the flexibility to select a signal from a range of signals so that the selected signal can improve the accuracy of the transmission of data within the same device or between two or more devices. to provide. In addition, embodiments of the present invention also compensate for any variation in environmental factors such as manufacturing process, operating voltage, and temperature, such that the selected signal and its range of signals remain stable despite variations in environmental factors. In addition, embodiments of the present invention provide a relatively compact circuit for a signal generator that operates over a wide range of frequencies and also with reduced current or power consumption.

It will be appreciated that the above description is exemplary and not limiting. Many other embodiments will be apparent to those skilled in the art upon reading and understanding the above description. Accordingly, the scope of the invention should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

Claims (51)

A delay line comprising a delay input node, a delay output node, and a plurality of delay cells connected between the delay input node and the delay output node, each delay cell being the same representing a digital count value. A plurality of delay control nodes for receiving a digital delay code, each of the delay cells comprising a plurality of delay stages connected in parallel between a first power supply node and a second power supply node, each of the delay stages being the first delay node; A plurality of transistors connected in series between a first power node and said second power node-, A phase detector comprising a first input node coupled to the delay input node, and a second input node coupled to the delay output node, and A plurality of output nodes coupled to the delay control node, a plurality of input nodes that adjust the delay code in response to the phase detector, and a plurality of respectively connected to one of the delay control nodes to provide bits of the digital count value. An apparatus comprising a code adjuster comprising a counter having a counter bit line. delete delete delete delete The method of claim 1, wherein the plurality of transistors of each delay cell form a plurality of current paths connected in parallel between the first power node and the second power node, And the counter bit line is configured to control the amount of current on each current path based on the digital count value. The apparatus of claim 6, wherein each of the current paths comprises a switch connected in series between the first power node and the second power node, And the switch comprises a control node coupled to a first delay control node of the delay control nodes. The method of claim 7, wherein each of the current paths further comprises a second switch connected in series between the first power node and the second power node, And the second switch comprises a control node coupled to a second one of the delay control nodes. A first selector comprising a first input node receiving a clock signal, a second input node receiving a preamble enable signal, and a selector output node, A delay line comprising a delay input node coupled to the selector output node, a delay output node, and a plurality of delay cells coupled between the delay input node and the delay output node, each cell receiving a cell output node and a delay code; Includes a number of delay control nodes; A delay controller comprising a first input node coupled to the delay input node, a second input node coupled to the delay output node, and a selection node coupled to the first selector, and And a second selector comprising an output node and a plurality of input nodes, each of the input nodes being coupled to the cell output node of one of the delay cells. The method of claim 9, wherein the delay controller, A phase detector comprising a first input node coupled to the delay input node, and a second input node coupled to the delay output node, and A code adjuster comprising a plurality of input nodes coupled to the phase detector, a plurality of output nodes coupled to the delay control node, and a plurality of input nodes that adjust the delay code in response to the phase detector. Device. 11. The apparatus of claim 10, wherein the code regulator comprises a counter coupled to the phase detector and the delay control node. 12. The apparatus of claim 11, wherein the code adjuster further comprises a logic unit controlling a signal on the selection node in response to the phase detector. 13. The apparatus of claim 12, wherein the delay controller further comprises an inverter coupled between the delay input node and one of the first and second input nodes of the phase detector. 14. The apparatus of claim 13, wherein the first selector is configured to select the preamble signal to the selector output node when the delayed output signal is 180 degrees out of phase with the input signal. 15. The apparatus of claim 14, wherein the second selector is configured to select a cell output signal from one of the delay cells to an output node of the second selector when the delayed output signal is 180 degrees out of phase with the input signal. Device. A plurality of variable delay cells connected in series with a delay input node receiving an input signal and coupled with a delay output node providing a delayed output signal, each of the delay cells comprising a cell output node providing a cell output signal, the delay Each cell also includes a plurality of delay control nodes receiving a digital control code; A phase detector comprising a first input node coupled to the delayed input node, and a second input node coupled to the delayed output node, A counter comprising a plurality of counter bit lines coupled to said delay control node, and a plurality of input nodes for adjusting a count value on said counter bit line in response to said phase detector;  And a selector coupled to at least two cell output nodes of the delay cells to select the cell output node from one of the delay cells to provide an enable signal. 17. The apparatus of claim 16, wherein each of the delay cells comprises a plurality of current paths connected in parallel between a first power node and a second power node. 18. The apparatus of claim 17, wherein each of the current paths is configured to vary a delay amount of each of the delay cells. 19. The apparatus of claim 18, wherein each of the current paths comprises at least three transistors connected in series between the first power node and the second power node. 20. The apparatus of claim 19, wherein each of the current paths comprises a switch having a switch control node coupled to one of the delay control nodes. 17. The apparatus of claim 16, wherein the variable delay cell is configured to provide the enable signal delayed from the input signal by a delay equal to one-eighth of a cycle of the input signal. 22. The apparatus of claim 21, wherein the variable delay cell is configured to provide an equal amount of current flowing through each of the delay cells. 23. The method of claim 22, wherein the variable delay cell is configured to provide the cell output signal such that a delay from one cell output signal to another cell output signal is equal to a multiple of one eighth of a cycle of the input signal. Device. 24. The apparatus of claim 23, wherein the phase detector is configured to compare the delayed output signal with a version of the input signal, wherein the delayed output signal is 180 degrees out of phase with the version of the input signal. . A first device having at least one data terminal for providing a data signal, and at least one strobe terminal for providing a strobe signal indicative of the timing of the data signal, and At least one data receiver coupled to the data terminal of the first device, at least one strobe receiver receiving the strobe signal from the first device in response to an enable signal, and a signal generator coupled to the strobe receiver Includes 2 devices, The signal generator, A delay synchronization circuit having a delay input node receiving an input signal, a delay output node providing a delayed output signal, a plurality of delay control nodes, and a plurality of variable delay cells connected in series between the delay input node and the delay output node. (delay locked circuit) each of said delay cells comprises a plurality of delay control nodes and a cell output node providing a cell output signal, and An enable controller coupled to the delay synchronization circuit for selecting the cell output signal from the cell output node of at least two of the variable delay cells as the enable signal. The method of claim 25, wherein the delay synchronization circuit, An inverter comprising an input coupled to the delay input node, and an inverter output node, A phase detector comprising a first input node coupled to the inverter output node, a second input node coupled to the delayed output node, and a plurality of output nodes; and And a digital delay code generator comprising a plurality of input nodes coupled to the output node of the phase detector, and a plurality of bit lines coupled to the delay control node. 27. The system of claim 25, wherein the digital delay code generator comprises a counter having a plurality of counter bit lines coupled to the bit lines. 28. The system of claim 27, wherein each of the delay cells comprises a plurality of delay stages connected in parallel between a first power node and a second power node. 29. The at least one switch of claim 28, wherein each of the delay stages is connected in series between the first power node and the second power node to control an amount of current between the first power node and the second power node. System comprising a. 27. The system of claim 26, wherein the delay synchronization circuit is configured to provide the delayed output signal 180 degrees out of phase with the input signal. 31. The system of claim 30, wherein the delay synchronization circuit is configured to provide the cell output signal delayed from the input signal by a delay equal to one-eighth of a cycle of the input signal. 32. The apparatus of claim 31, wherein the delay synchronization circuit is configured to provide the cell output signal such that a delay from one cell delay signal to another cell output signal is equal to a multiple of one eighth of a cycle of the input signal. System. An apparatus having a terminal for transmitting data at an operating frequency, and A circuit hub coupled to the device, the circuit hub including a signal generator providing a plurality of enable signals, the circuit hub being coupled to the operating frequency of the device to manage the transfer of data between the circuit hub and the device. Select one of the enable signals based on the selected signal; The signal generator, A delay synchronization circuit having a plurality of variable delay cells connected in series between a delay input node and a delay output node, each of the delay cells including a plurality of delay control nodes receiving the same digital delay code; and And a selector coupled to at least two plurality of output nodes of the variable delay cell. 34. The system of claim 33, wherein the circuit hub is a tester. 35. The system of claim 34, wherein the device is a semiconductor device. The method of claim 35, wherein the delay synchronization circuit, An inverter comprising an input coupled to the delay input node, and an inverter output node, A phase detector comprising a first input node coupled to the inverter output node, a second input node coupled to the delayed output node, and a plurality of output nodes; and And a digital delay code generator comprising a plurality of input nodes coupled to the output node of the phase detector, and a plurality of bit lines coupled to the delay control node. 37. The system of claim 36, wherein each of the delay cells comprises a plurality of delay stages connected in parallel between a first power node and a second power node. 38. The at least one switch of claim 37, wherein each of the delay stages is connected in series between the first power node and the second power node to control an amount of current between the first power node and the second power node. System comprising a. 34. The system of claim 33, wherein the signal generator is configured to provide the enable signal such that each of the enable signals has a fixed signal relationship with each other. 40. The system of claim 39, wherein the variable delay cells have the same amount of delay. Setting a delay code in a plurality of delay cells of a delay line, Propagating an input signal through the delay cell to obtain a delayed output signal, Adjusting the delayed output signal until the input signal and the delayed output signal have a fixed signal relationship, Selecting a selected cell output signal among a plurality of cell output signals at the plurality of cell output nodes of the delay cell, and Delivering the selected cell output signal to an enable node. 42. The method of claim 41, wherein setting the delay code comprises setting a same binary bit combination at a control node of each of the delay cells. 43. The method of claim 42, wherein adjusting comprises modifying the value of the delay code. 44. The method of claim 43, wherein modifying the value of the delay code comprises controlling the amount of current in each of the delay cells. 45. The method of claim 44, wherein controlling the amount of current in each of the delay cells comprises allowing an equal amount of current to flow in each of the delay cells. 44. The method of claim 43, wherein modifying comprises changing the counter value such that a counter value corresponds to a value of the delay code. Receiving at least one data signal at an input node of the data receiver, Receiving at least one strobe signal at an input node of a strobe receiver, wherein the strobe signal carries timing information of the data signal; Propagating an input signal through a plurality of variable delay cells to obtain a plurality of cell output signals, each cell output signal having a fixed signal relationship with the input signal, Selecting one of the plurality of cell output signals as an enable signal, and Forward the enable signal to the data receiver to deliver at least one of the strobe signal and the data signal from the input node of at least one of the data receiver and the strobe receiver to an output node of the data receiver and the strobe receiver And transmitting to at least one of the strobe receivers. 48. The method of claim 47, wherein the selecting comprises selecting from the cell output signals such that the plurality of cell output signals have a fixed delay from one another. 49. The method of claim 48, wherein the fixed delay is a multiple of one eighth of a cycle of the input signal. 50. The method of claim 49, further comprising: transmitting the data signal from a data driver, and Transmitting the strobe signal from a strobe driver. 51. The method of claim 50, wherein transmitting the data signal and transmitting the strobe signal are performed by a first device, Receiving the data signal and receiving the strobe signal are performed by a second device.

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