KR20190053025A - Thin film transistor - Google Patents

Abstract

According to an embodiment of the present invention, a thin film transistor comprises: a substrate; a source electrode on the substrate; an insulating pattern disposed on the substrate and covering a part of an upper surface of the source electrode; a drain electrode on the insulating pattern; a spacer disposed on a side surface of the insulating pattern and on a side surface of the drain electrode; an active layer disposed on a surface of the spacer and extending from the drain electrode to the source electrode; and a gate electrode on the active layer.

Description

Thin Film Transistor {THIN FILM TRANSISTOR}

The present invention relates to a thin film transistor, and more particularly to a thin film transistor having an increased channel length.

Transistors are widely used in various electronic devices for various purposes. For example, the transistor may be used as a switching device, a driving device, and a photo sensing device, and may be used as a component of various electronic circuits.

2. Description of the Related Art Liquid crystal displays (LCDs) are one of the most widely used flat panel displays. In a liquid crystal display, a plurality of pixel electrodes are arranged in a matrix on one substrate (thin film transistor substrate), and one common electrode covers another substrate (common electrode substrate) on the whole substrate. In such a liquid crystal display device, display of an image is performed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three terminal device for switching a voltage applied to the pixel electrode, is connected to each pixel electrode, a gate line for transmitting a signal for controlling the thin film transistor, and a voltage to be applied to the pixel electrode A data line to be transferred is formed on one substrate.

A problem to be solved by the present invention is to provide a thin film transistor in which the pitch of pixels is reduced and current leakage can be prevented.

A thin film transistor according to embodiments of the present invention includes a substrate; A source electrode on the substrate; An insulating pattern disposed on the substrate, the insulating pattern covering a part of the upper surface of the source electrode; A drain electrode on the insulating pattern; A spacer disposed on a side surface of the insulating pattern and a side surface of the drain electrode; An active layer disposed on a surface of the spacer and extending from the drain electrode to the source electrode; And a gate electrode on the active layer.

According to the embodiments of the present invention, it is possible to provide a thin film transistor which can be applied to a high resolution display element by reducing the pixel pitch, reduce the leakage current, and is easy to manufacture.

1 is a plan view illustrating a thin film transistor according to embodiments of the present invention.
FIG. 2 is a cross-sectional view taken along line I-I 'of FIG. 1 for explaining a thin film transistor according to embodiments of the present invention.
3 is an enlarged cross-sectional view corresponding to part A of Fig.
4 is an enlarged cross-sectional view corresponding to part B of Fig.
5 is a cross-sectional view illustrating a structure in which a gate spacer is formed on a side surface of a gate electrode according to an embodiment of the present invention.
6 is an enlarged cross-sectional view corresponding to part C of Fig.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. To fully disclose the scope of the invention to a person skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Embodiments described herein will be described with reference to plan views and cross-sectional views, which are ideal schematics of the present invention. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 is a plan view illustrating a thin film transistor according to embodiments of the present invention.

Referring to FIG. 1, a data line DL and a gate line GL may be arranged to intersect with each other. The data line DL may extend in the first direction D1. The data line DL may carry the data voltage. The gate line GL may extend in a second direction D2 that intersects the first direction D1. The gate line GL can transfer the gate signal.

Although only one data line DL and one gate line GL are shown in FIG. 1 for the sake of simplicity, the thin film transistor substrate according to embodiments of the present invention includes a plurality of data lines DL and a plurality of Gate lines GL. In detail, the plurality of data lines DL may be spaced apart from each other in the second direction D2, and the plurality of gate lines GL may be spaced apart from each other in the first direction D1 .

The drain electrode 130 may be disposed adjacent to the gate line GL and the data line DL. Particularly, a part of the drain electrode 130 may vertically overlap with a portion where the gate line GL and the data line DL intersect with each other. That is, the thin film transistor may be formed adjacent to a portion where the gate line GL and the data line DL intersect with each other.

The data line DL, the gate line GL and the drain electrode 130 may include a metal having a low resistivity so as to reduce a signal delay or a voltage drop. The data line DL, the gate line GL and the drain electrode 130 may be formed of a metal such as magnesium (Mg), aluminum (Al), chromium (Cr), cobalt (Co), nickel (Ni), palladium (Pd) , Metallic materials such as silver (Ag), gold (Au), platinum (Pt), molybdenum (Mo) and titanium (Ti), and compounds thereof. The data line DL, the gate line GL, and the drain electrode 130 may include a plurality of films having different physical properties.

The pixel electrode 160 may be disposed between the data line DL and the gate line GL. A pixel region may be defined between the data line DL and the gate line GL, and the pixel electrode 160 may be disposed on the pixel region. The pixel electrode 160 may be electrically connected to the drain electrode 130 and may receive a data voltage according to a gate signal. The pixel electrode 160 may be formed of a transparent conductor such as ITO or IZO or a reflective conductor such as aluminum. 1, the pixel electrode 160 is arranged so as not to overlap the data line DL and the gate line GL and has a rectangular shape. However, the arrangement and the shape of the pixel electrode 160 are not limited thereto And can be variously modified.

FIG. 2 is a cross-sectional view taken along line I-I 'of FIG. 1 for explaining a thin film transistor according to embodiments of the present invention. 3 is an enlarged cross-sectional view corresponding to part A of Fig. 4 is an enlarged cross-sectional view corresponding to part B of Fig.

1 to 4, a thin film transistor according to embodiments of the present invention will be described in more detail. As shown in FIG. 2, the source electrode 110 and the drain electrode 130 may be disposed separately from each other with the insulating pattern 120 interposed therebetween. The gate electrode 140 may be disposed on a side surface of the insulating pattern 120. The source electrode 110, the drain electrode 130, and the gate electrode 140 may function as a thin film transistor together with the active layer 200 in which a channel is formed.

Specifically, the source electrode 110 may be disposed on the substrate 100. The substrate 100 may be an insulating substrate. The source electrode 110 may be a part of the data line DL extending in the first direction.

An insulating pattern 120 may be disposed on the substrate 100. The insulating pattern 120 may cover a part of the upper surface 110T of the source electrode 110. [ The insulating pattern 120 may comprise silicon oxide (SiO _x ) or silicon nitride (SiN _x ).

The drain electrode 130 may be disposed on the insulating pattern 120. The drain electrode 130 may be disposed adjacent to a portion where the gate line GL and the data line DL intersect, as shown in Fig. For example, at least a part of the drain electrode 130 may vertically overlap with a portion where the gate line GL and the data line DL intersect. The drain electrode 130 may be disposed between the gate line GL and the data line DL as shown in FIG. In other words, the vertical position of the upper surface of the drain electrode 130 is higher than the upper surface of the data line DL and lower than the upper surface of the gate line GL.

The active layer 200 may be disposed on the side surface of the insulating pattern 120. [ The active layer 200 may extend from the drain electrode 130 to the source electrode 110. The active layer 200 may be disposed on the upper surface of the drain electrode 130 and on the upper surface of the source electrode 110. The active layer 200 may include an oxide semiconductor. For example, the oxide semiconductor may include zinc oxide (ZnO), indium oxide (InO), indium-gallium-zinc oxide (In-Ga-Zn-O), and zinc-tin oxide (Zn-Sn-O). The oxide semiconductor may include an oxide including at least two elements of zinc (Zn), indium (In), gallium (Ga), tin (Sn) and aluminum (Al). A channel of the thin film transistor may be formed in the active layer 200 between the drain electrode 130 and the source electrode 110. That is, the channel of the thin film transistor may be formed so as to vertically overlap with a portion where the gate line GL and the data line DL intersect. Thus, the pitch of the pixels arranged on the thin film transistor can be reduced.

The spacer 122 may be arranged to surround the insulating pattern 120 and the drain electrode 130 in plan view, as shown in Fig. The spacer 122 may have the shape of a closed curve, for example, in a plan view. The spacer 122 may have a shape corresponding to the drain electrode 130. For example, when the drain electrode 130 has a rectangular shape, the spacer 122 may have a hollow square shape. The spacer 122 may be formed by performing an evaporation process to form an insulating film covering the substrate 100, the source electrode 110, the insulating pattern 120, and the drain electrode 130, To etch the insulating layer until the drain electrode 130 and the source electrode 110 are exposed.

The spacer 122 may be disposed between the active layer 200, the side surface 120S of the insulating pattern 120 and the side surface 130S of the drain electrode 130, as shown in FIG. The spacer 122 may have a narrow width as the distance from the substrate 100 increases. The spacer 122 may have a first surface 122S exposed by the top surface 110T of the source electrode 110, the side surface 120S of the insulating pattern 120 and the side surface 130S of the drain electrode 130 have. The first surface 122S of the spacer 122 may have the shape of a curved surface. The first surface 122S of the spacer 122 may be in contact with the active layer 200. That is, the active layer 200 may cover the first surface 122S of the spacer 122.

The length of the active layer 200 between the source electrode 110 and the drain electrode 130 is increased as the spacers 122 are interposed between the active layer 200, the insulating pattern 120 and the drain electrode 130 . Thus, the length of the channel in the thin film transistor can be increased. The spacer 122 may include a material having excellent bonding properties with the surrounding film materials. The spacers 122 may include, for example, silicon oxide (SiO2), silicon nitride (SiNx), alumina (AlOx), and the like.

A gate electrode 140 may be disposed on the active layer 200. A gate insulating layer 142 may be disposed between the gate electrode 140 and the active layer 200. The gate electrode 140 may extend over the source electrode 110 and / or the gate electrode 140. The gate electrode 140 may be a part of a gate line GL extending in a second direction intersecting the first direction. The side face 140S of the gate electrode 140 can be aligned with the side face 200S of the active layer 200 and the side face 142S of the gate insulating film 142 as shown in Fig. That is, the gate insulating film 142 can completely cover the upper surface of the active layer 200, and the gate electrode 140 can completely cover the upper surface of the gate insulating film 142. A gate insulating film 142 is, for example, may include a silicon oxide (SiO _2).

A protective film 150 may be formed to cover the source electrode 110, the gate electrode 140, and the drain electrode 130. [ The protective layer 150 may include an insulating material having excellent planarization characteristics. The passivation layer 150 may be formed of a low dielectric constant insulating material having a dielectric constant of 4.0 or less, for example, an organic material having photosensitivity, a-Si: C: O, a-Si: O: F formed by plasma- Or silicon nitride (SiN _x ), which is an inorganic material. The passivation layer 150 may include a contact hole 152 exposing the drain electrode 130.

The pixel electrode 160 may be disposed on the protective film 150. [ The pixel electrode 160 may be vertically overlapped with at least a portion of the drain electrode 130. The pixel electrode 160 may be electrically connected to the drain electrode 130 through a contact 162 disposed in the contact hole 152. When a gate voltage is applied to the gate electrode 140, the pixel electrode 160 can receive a data voltage from the drain electrode 130. A common electrode (not shown) to receive a common voltage may be disposed on the pixel electrode 160, and a liquid crystal layer (not shown) may be disposed between the pixel electrode 160 and the common electrode. The pixel electrode 160 receiving the data voltage can function to rearrange the liquid crystal molecules of the liquid crystal layer by generating an electric field together with a common electrode (not shown) to which a common voltage is applied.

5 is a cross-sectional view illustrating a structure in which a gate spacer is formed on a side surface of a gate electrode according to an embodiment of the present invention. 6 is an enlarged cross-sectional view corresponding to part C of Fig. In order to simplify the explanation, differences from the thin film transistors described with reference to FIGS. 1 to 4 will be mainly described, and detailed description of the overlapped structure will be omitted.

5 and 6, a thin film transistor according to embodiments of the present invention includes a gate spacer 144 formed on at least one side surface 140S of the side surfaces 140S of the gate electrode 140 can do. 6, the gate electrode 140 may expose a part of the upper surface 142T of the gate insulating film 142. [ The gate spacer 144 may be formed to cover the upper surface 142T of the gate insulating film 142 exposed by the side surface 140S of the gate electrode 140 and the gate electrode 140. [ The width of the gate spacer 144 may be reduced as the distance from the upper surface 142T of the gate insulating film 142 increases. The gate spacer 144 may have a second surface 144S exposed by the side 140S of the gate electrode 140 and the gate electrode 140. [ The second surface 144S may have the shape of a curved surface. The method of forming the gate spacer 144 may be similar to the method of forming the spacer 122 described with reference to FIGS. Since the gate spacer 144 is formed so as to cover the upper surface 142T of the gate insulating film 142 exposed by the side surface 140S of the gate electrode 140 and the gate electrode 140, .

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible. In addition, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, and all technical ideas which fall within the scope of the following claims and equivalents thereof should be interpreted as being included in the scope of the present invention .

Claims (1)

Board;
A source electrode on the substrate;
An insulating pattern disposed on the substrate, the insulating pattern covering a part of the upper surface of the source electrode;
A drain electrode on the insulating pattern;
A spacer disposed on a side surface of the insulating pattern;
An active layer disposed on a surface of the spacer and extending from the drain electrode to the source electrode; And
And a gate electrode on the active layer.

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