KR20190038502A - Image sensor - Google Patents

Abstract

Provided are an image sensor and a manufacturing method thereof. The image sensor comprises: a substrate including a light receiving portion having defined front and rear surfaces and including pixels, and including a circuit portion driving the pixels around the light receiving portion; an insulating structure formed on the front surface of the circuit portion and including a circuit; a lower pad disposed on a position higher than the upper end of the circuit in the insulating structure and formed to be electrically connected to the upper end of the circuit; an upper pad disposed on the rear surface of the circuit portion to be positioned on the upper side of the circuit; a contact hole penetrating the circuit portion to expose the lower pad; and a contact electrically connecting the upper pad and the lower pad formed within the contact hole.

Description

Image sensor {IMAGE SENSOR}

The present invention relates to an image sensor.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. Such an image sensor can be roughly divided into a charge coupled device (CCD) and a CMOS image sensor. The charge-coupled device is an element in which individual MOS capacitors are located at positions very close to each other, while the charge carriers are stored and transferred to the capacitors. The CMOS image sensor is a device that uses a switching method for generating MOS transistors as many as the number of pixels by using a CMOS technology using a control circuit and a signal processing circuit as peripheral circuits, and detecting output sequentially using the CMOS transistors.

The CMOS image sensor is easy to operate and can be implemented by various scanning methods. In addition, since the signal processing circuit can be integrated on a single chip, miniaturization of the product can be achieved, and the manufacturing cost can be reduced because the MOS process technology can be used in a compatible manner. Power consumption is also very low, making it easy to apply to products with limited battery capacity. Therefore, the CMOS image sensor has been rapidly used due to its ability to implement high resolution with the development of technology.

The CMOS image sensor includes a photoelectric conversion element that absorbs incident light and accumulates charges corresponding to the light amount, and a multi-layered metal wiring layer for receiving the light and outputting the optical signal stored in each photoelectric conversion element. However, the incident light is reflected by the metal wiring layer and absorbed by the interlayer insulating film, so that the sensitivity is lowered. In addition, the reflected light is absorbed by the adjacent pixels, causing crosstalk. Therefore, recently, a structure has been proposed in which the back side of the substrate is polished and light is incident from the back side of the substrate. This is called a backside illuminated (BI) image sensor. In such a BI image sensor, since the metal wiring layer is not formed on the rear surface where the light is incident, incident light is reflected by the metal wiring layer or light absorption is not caused by the interlayer insulating film.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image sensor in which a pad is formed at a position corresponding to a circuit without providing a separate pad region at the edge of the chip,

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided an image sensor comprising: a substrate including a light receiving portion including a pixel and a circuit portion formed with a circuit for driving pixels around the light receiving portion; An upper pad arranged to be positioned above the upper end of the circuit in the insulating structure and configured to be electrically connected to the upper end of the circuit, A contact hole penetrating the circuit portion to expose the lower pad, and a contact electrically connecting the upper pad and the lower pad formed in the contact hole.

Another aspect of the image sensor of the present invention for solving the above problems is a substrate including a circuit portion in which a front surface and a rear surface are defined and in which a circuit for driving a pixel around a light receiving portion and a light receiving portion around a light receiving portion is formed, A lower pad arranged to be positioned above the upper end of the circuit in the insulating structure and configured to be electrically connected to the upper end of the circuit, an upper pad disposed on the back of the circuit, A pad, a contact hole penetrating the circuit portion to expose the lower pad, and a contact electrically connecting the upper pad and the lower pad formed in the contact hole, wherein the upper pad and the lower pad are arranged to include portions overlapping the circuit.

According to another aspect of the present invention, there is provided an image sensor including a light receiving portion including a pixel and a circuit portion in which a circuit for driving pixels around the light receiving portion is formed, A lower pad formed on the front surface of the substrate and arranged to be positioned above the upper end of the driving circuit and electrically connected to the upper end of the driving circuit; And a contact electrically connecting the upper pad and the lower pad through the upper pad and the substrate.

Other specific details of the invention are included in the detailed description and drawings.

1 is a block diagram of an image sensor in accordance with embodiments of the present invention.
Figure 2 is an equivalent circuit diagram of the APS array of Figure 1;
3 is a plan view for explaining an image sensor according to an embodiment of the present invention.
4 is a cross-sectional view taken along line A-A 'in Fig.
5 is a reference view for explaining an effect of the image sensor according to the embodiments of the present invention.
6 is a plan view for explaining an image sensor according to another embodiment of the present invention.
7 is a plan view for explaining an image sensor according to another embodiment of the present invention.
8 is a cross-sectional view illustrating an image sensor according to another embodiment of the present invention.
9 is a cross-sectional view illustrating an image sensor according to another embodiment of the present invention.
10 to 15 are sectional views of an intermediate structure for explaining a method of manufacturing an image sensor according to an embodiment of the present invention.
16 is a schematic block diagram illustrating a processor-based system including an image sensor in accordance with embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

One element is referred to as being "connected to " or" coupled to "another element, either directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, embodiments of the present invention will be described using a backside illuminated (BI) image sensor in which light is incident on the rear surface of a substrate. Here, the front side (front side) and the back side (back side) of the substrate are not absolute directions, but merely terms for describing relative directions or positional relationships with each other. For the sake of convenience of explanation, in the following embodiments, 'FRONT SIDE' is defined as a direction or position in which a manufacturing process for a substrate is advanced in manufacturing an image sensor, and 'BACK SIDE ') is defined as a direction opposite to the front surface of the substrate or a position thereof.

1 is a block diagram of an image sensor in accordance with embodiments of the present invention.

1, an image sensor according to embodiments of the present invention includes an active pixel sensor (APS) array 10 in which pixels including photoelectric conversion elements are arranged two-dimensionally, a timing generator 20 A row decoder 30, a row driver 40, a correlated double sampler (CDS) 50, an analog to digital converter (ADC) 60, A latch 70, a column decoder 80, and the like.

The APS array 10 includes a plurality of unit pixels arranged two-dimensionally. The plurality of unit pixels serve to convert the optical image into an electrical output signal. The APS array 10 is driven by receiving a plurality of drive signals such as a row selection signal, a reset signal, and a charge transfer signal from the row driver 40. The converted electrical output signal is also provided to the correlated dual sampler 50 through a vertical signal line.

The timing generator 20 provides a timing signal and a control signal to the row decoder 30 and the column decoder 80.

The row driver 40 provides a plurality of driving signals to the active pixel sensor array 10 for driving a plurality of unit pixels according to the decoded result in the row decoder 30. [ Generally, when unit pixels are arranged in a matrix form, a driving signal is provided for each row.

The correlated dual sampler 50 receives and holds and samples the output signal formed on the active pixel sensor array 10 through the vertical signal line. That is, a specific noise level and a signal level by the output signal are sampled double, and a difference level corresponding to the difference between the noise level and the signal level is output.

The analog-to-digital converter 60 converts an analog signal corresponding to the difference level into a digital signal and outputs the digital signal.

The latch unit 70 latches the digital signal and the latched signal is sequentially output to the image signal processing unit (not shown) according to the decoding result in the column decoder 80.

Figure 2 is an equivalent circuit diagram of the APS array of Figure 1;

Referring to FIG. 2, the pixels P are arranged in a matrix form to constitute the APS array 10. Each pixel P includes a photoelectric conversion element 11, a floating diffusion region 13, a charge transfer element 15, a drive element 17, a reset element 18 and a selection element 19. (I, j + 1), P (i, j + 2), P (i, j + 3), ...) .

The photoelectric conversion element 11 absorbs the incident light and accumulates the electric charge corresponding to the light amount. As the photoelectric conversion element 11, a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof may be applied, and a photodiode is illustrated in the figure.

Each photoelectric conversion element 11 is coupled to each charge transfer element 15 that transfers the accumulated charge to the floating diffusion region 13. [ A floating diffusion region (FD) 13 is an area for converting a charge to a voltage, and has a parasitic capacitance, so that charges are stored cumulatively.

The drive element 17 illustrated in the source follower amplifier amplifies a change in the electric potential of the floating diffusion region 13 that receives the charge accumulated in each photoelectric converter 11 and outputs the amplified change to the output line Vout .

The reset element 18 periodically resets the floating diffusion region 13. The reset element 18 may be composed of one MOS transistor driven by a bias provided by a reset line RX (i) for applying a predetermined bias. When the reset element 18 is turned on by the bias provided by the reset line RX (i), a predetermined electrical potential, e.g., the power supply voltage VDD, provided to the drain of the reset element 18 is applied to the floating diffusion region 13).

The selection element 19 serves to select a pixel P to be read in units of rows. The selection element 19 may consist of one MOS transistor driven by a bias provided by the row selection line SEL (i). When the select element 19 is turned on by the bias provided by the row select line SEL (i), a predetermined electrical potential, such as the power supply voltage VDD, provided to the drain of the select element 19 is applied to the drive element 17).

A transmission line TX (i) for applying a bias to the charge transfer element 15, a reset line RX (i) for applying a bias to the reset element 18, a row for applying a bias to the selection element 19 The selection lines SEL (i) may be arranged extending substantially in parallel with each other in the row direction.

Hereinafter, an image sensor according to an embodiment of the present invention will be described with reference to FIGS. 3 to 5. FIG. 3 is a plan view for explaining an image sensor according to an embodiment of the present invention. 4 is a cross-sectional view taken along line A-A 'in Fig. 4 also shows the light receiving portion I in which the APS array is formed together with the circuit portion II for convenience of explanation. 5 is a reference view for explaining an effect of the image sensor according to the embodiments of the present invention.

3, the substrate 110 includes a light receiving portion I and a circuit portion II around the light receiving portion I. As shown in FIG. The light receiving section I may be an area where the active pixel sensor (APS) 10 of FIG. 1 is formed and the circuit section II may be a timing generator 20, a row decoder 30, a row driver 40 A correlated double sampler 50, an analog-to-digital converter 60, a latch unit 70, a column decoder 80, and the like. Further, as shown in Fig. 3, the circuit portion II may be formed so as to surround the light receiving portion I. Fig.

3, a plurality of upper pads 151 and 152 are arranged in the circuit part II. The upper pads 151 and 152 may be pads connected to an external circuit, for example, an external semiconductor chip or an external circuit board. Since the image sensor according to one embodiment of the present invention does not include a separate pad region (e.g., the periphery of the circuit portion, see III of FIG. 5), the upper pad 151, But are arranged randomly in the circuit portion II. Specifically, the upper pads 151 and 152 are connected to the back surface of the substrate 110 of the circuit part II so as to overlap circuits (see 210 and 220 in FIG. 4) formed on the front surface of the substrate 110 ), It is not necessary to separately provide a pad region. Referring to FIG. 5, when a separate pad region III is formed at the edge of the circuit portion II and a pad is disposed in the pad region III, the size of the image sensor may be increased. On the other hand, in the image sensor according to the embodiment of the present invention, the size of the image sensor can be reduced because the pad is formed at a position corresponding to the circuit on the circuit and does not need to have a separate pad area.

3 and 4, the active region of the substrate 110 is defined by the element isolation region 112. [ For example, the device isolation region 112 may be STI (Shallow Trench Isolation) or LOCOS (LOCAL Oxidation of Silicon). The substrate 110 may be of various types, for example, a bulk substrate of a first conductivity type (for example, P type) or a second conductivity type (for example, N type) The first conductive type or the second conductive type epitaxial layer may be grown on the first conductive type bulk substrate or the first conductive type or the second conductive type epitaxial layer may be grown on the second conductive type bulk substrate. In addition to the semiconductor substrate, an organic plastic substrate or the like can be used. The substrate 110 shown in FIG. 4 shows a case where all of the bulk substrate is removed through the polishing process and only the epi layer is left, but the present invention is not limited to this, and a part of the bulk substrate may be left if necessary . The thickness of the remaining substrate 110 may be, for example, about 3-5 [mu] m.

A plurality of photoelectric conversion elements 120 and a floating diffusion region 130 are formed in the substrate 110 of the light receiving section I and a plurality of gates 140 are arranged on a front surface of the substrate 110 . The gate 140 may be, for example, a gate of a charge transfer element, a gate of a reset element, a gate of a drive element, or the like. FIG. 4 shows a pinned photodiode as an example of the photoelectric conversion element 120. As shown in FIG. That is, the photoelectric conversion element 120 includes the impurity region 121 of the second conductivity type (for example, N type) and the impurity region of the first conductivity type (for example, the P type) 122 .

Insulating structures 200, 210, 220 and 230 are disposed on the front side of the substrate 110. The insulating structures 200, 210, 220, and 230 include an interlayer insulating layer 200, a metal wiring layer 230 including multiple layers of wirings 231, 232, and 233 sequentially formed on the light receiving portion I, And a plurality of circuits 210 and 220 formed in the circuit part II. Each of the plurality of circuits 210 and 220 includes a wiring contact 212 connecting a plurality of wirings 211, 213, 215, 217 and 221 and a plurality of wirings 211, 213, 215, 217 and 221 . The circuits 210 and 220 may be drive circuits for driving the APS of the light receiving section and may be implemented by a timing generator 20, a row decoder 30, a row driver 40, a correlated double sampler 50, an analog-to-digital converter 60, a latch unit 70, and a column decoder 80. 4 is a circuit diagram showing the first circuit 210 and the second circuit 220 formed in the circuit part II and the first circuit connecting the first to fourth wirings 211, 213, 215, Although a structure including the wiring contact 212 is shown, this is merely exemplary and the structure of the circuit is not limited thereto.

3 and 4, a plurality of upper pads, for example, a first upper pad 151 and a second upper pad 152 (not shown) are formed on the back side of the substrate 110 of the circuit part II. For example, a first contact hole 141 and a second contact hole 142 are formed to penetrate the substrate 110. In addition, The upper pads 151 and 152 are formed on the back side of the substrate 110 at positions corresponding to the circuits 210 and 220 formed on the front side of the substrate 110. The first upper pad 151 overlaps the first circuit 210 and the second upper pad 152 is disposed on the back side of the substrate 110 so as to overlap with the second circuit 220 . Contact holes 141 and 142 pass through the FRONT SIDE and BACK SIDE of the substrate 110 and expose the circuits 210 and 220 in the insulating structure. The first contact hole 141 may expose the first circuit 210 and the second contact hole 142 may expose the second circuit 220. For example, It is possible to expose the first wirings 211 and 221 located at the uppermost portion of the first wirings 211 and 221. The upper pads 151 and 152 are formed from the back side of the substrate 110 to the inside of the contact holes 141 and 142 and are electrically connected to the circuits 210 and 220. Here, the upper pads 151 and 152 contact the circuits 210 and 220 while filling only a part of the contact holes 141 and 142, or completely fill the contact holes 141 and 142, Can be contacted. 4 shows a state in which the circuits 210 and 220 and the upper pads 151 and 152 are in contact with the upper pads 151 and 152 in contact with the first wirings 211 and 221 located at the uppermost portions of the circuits 210 and 220 And the case of being electrically connected is exemplified. The upper pads 151 and 152 may be connected to an external circuit by wire bonding or the like.

The image sensor according to the embodiment of the present invention does not have a separate pad area but a pad is formed just above the circuit, that is, at a position overlapping the circuit, so that a separate dummy wiring line is formed to extend the circuit to the pad area no need. Thus, the process can be simplified and the resistance between the circuit and the pad can be reduced. Further, since the image sensor of the present invention is a BI image sensor, the substrate is supported by the lower part of the pad, so that the lower circuit is not damaged even if the wire bonding process is performed later on the pad.

A supporting substrate 300 is adhered and fixed on the insulating structures 200, 210, 220 and 230. The supporting substrate 300 is for securing the strength of the substrate 110 thinned due to the polishing process. The supporting substrate 300 can be any semiconductor substrate as long as it is made of a material capable of maintaining mechanical strength. For example, an organic substrate can be used.

Although not shown in FIG. 4, an adhesive layer (not shown) may be formed between the supporting substrate 300 and the insulating structures 200, 210, 220, and 230 to bond the supporting substrate 300 and the insulating structures 200, 210, 220, See 311 and 312 in Fig. 9) can be interposed. If the supporting substrate 300 is a silicon substrate, the bonding film may be, for example, a silicon oxide film.

An anti-reflection film 181 may be formed on the back side of the substrate 110. The material / thickness of the antireflection film 181 may vary depending on the wavelength of light used in the photolithography process. For example, the anti-reflection film 181 may be formed by laminating a silicon oxide film having a thickness of about 50-200 Å and a silicon nitride film having a thickness of about 300-500 Å.

A buffer film 182 may be disposed on the antireflection film 181. The buffer film 182 prevents the substrate 110 from being damaged in the patterning process for forming the upper pads 151 and 152. As the buffer film 182, for example, a silicon oxide film having a thickness of about 3000-8000 Å may be used.

A color filter 161 is formed on the back side of the substrate 110 of the light receiving unit I so as to correspond to the photoelectric conversion element 120. [ When the photoelectric conversion elements 120 are arranged in a matrix form, the color filters 161 are similarly arranged in a matrix form. The color filter 161 transmits a specific color to reach the photoelectric conversion element 120 of the substrate 110 to obtain a high-quality image. The color filter 161 may be a color filter in which red (R), green (G), and blue (B) are arranged in a Bayer pattern.

A microlens 171 is disposed on the upper surface of the color filter 161. The microlens 171 changes the path of light incident on the region other than the photoelectric conversion element 120 to condense the light into the photoelectric conversion element 120.

A planarization layer 162 may be formed between the color filter 161 and the microlens 171 and may be referred to as an overcoating layer (OCL). The planarization layer 162 may be formed of a thermosetting resin.

Hereinafter, another image sensor according to another embodiment of the present invention will be described with reference to Figs. 5 and 6. Fig. 6 is a plan view for explaining an image sensor according to another embodiment of the present invention. Another embodiment of the present invention differs from the embodiment of the present invention in that at least one pad adjacent to the light receiving portion is present. Hereinafter, the present embodiment will be described focusing on differences from an embodiment of the present invention.

Referring to FIG. 6, a plurality of upper pads are disposed in the circuit portion II of the substrate 110. FIG. At least one of the upper pads 251 and 252 of the plurality of upper pads is disposed adjacent to the light receiving unit I. 6 illustrates a first upper pad 251 and a second upper pad 252 as upper pads disposed adjacent to the light receiving portion II but only one upper pad is disposed adjacent to the light receiving portion II It is not excluded that the upper pad is formed adjacent to the light receiving portion II.

Here, the upper pad is not arranged in a separate pad area, but is disposed so as to overlap a circuit (see 210 and 220 in FIG. 4) formed on the front surface (front surface) of the substrate 110, The one or more upper pads 251 and 252 may be disposed such that the distance L1 from the upper pad to the light receiving portion I is closer to the distance L2 to the distal end of the circuit portion II. Here, L1 denotes the distance from the center of the upper pad to the end of the light receiving portion (I), and L2 denotes the distance from the center of the upper pad to the end of the circuit portion (II). Since the imager sensor according to this embodiment does not include a separate pad area, the end of the circuit part II may be the same as the end of the substrate. That is, some of the upper pads 251 and 152 may be disposed closer to the light-receiving portion II than the ends of the circuit portion II. This is because at least one of the driving circuits located in the circuit portion II can be formed to be close to the light receiving portion I, and an upper pad is formed on the upper portion of such a circuit. 5, when a separate pad region III is formed at the edge of the circuit portion II, since the pad 10 is disposed in the pad region III, The pad 10 is disposed so that the distance L2 from the pad 10 to the end of the substrate 110 is closer to the distance L1 from the light receiving portion I to the light receiving portion I.

Hereinafter, another image sensor according to another embodiment of the present invention will be described with reference to FIG. 7 is a plan view for explaining an image sensor according to another embodiment of the present invention. Another embodiment of the present invention differs from an embodiment of the present invention in that at least one pad adjacent to the light receiving portion is present, while at least one pad disposed at the edge of the circuit portion exists. Hereinafter, the present embodiment will be described focusing on differences from an embodiment of the present invention.

7, the image sensor according to another embodiment of the present invention includes a first upper pad 251 and a second upper pad 252 disposed adjacent to the light receiving portion I in the circuit portion II, And third top pads 351 and 352 disposed on the edge II ' The first upper pad 251 and the second upper pad 252 are disposed so that the distance L1 to the light receiving section I is closer to the distance L2 to the terminal end of the circuit section II, The upper pad 251 may be disposed such that the distance L2 to the distal end of the circuit portion II is closer to the distance L1 to the light receiving portion I. [ Although not shown in FIG. 7, circuits corresponding to the first, second, and third upper pads 251, 252, 351, and 352, that is, a front surface of the substrate (FRONT SIDE) . Since the pads are formed on the back side of the substrate 110 corresponding to the circuits in the image sensor according to the present embodiment, the pads are not aligned in the same area and need not be provided separately .

Hereinafter, an image sensor according to another embodiment of the present invention will be described with reference to FIG. 8 is a cross-sectional view illustrating an image sensor according to another embodiment of the present invention. This embodiment is different from the embodiment of the present invention in that a contact for connecting the upper pad and the circuit is formed.

8, the image sensor according to the present embodiment includes a contact 452 penetrating the substrate 110 of the circuit part II and an upper pad 451 formed on the contact 452. [

An insulating structure including an interlayer insulating film 200 and circuits 211, 212, 213, 215, and 217 is disposed on a front surface of a circuit part II substrate 110. A contact 452 is formed on the substrate 110 212, 213, 215, 217 and the circuit 211, 212, 213, 215, 217 through the front surface (FRONT SIDE) and the back surface Lt; / RTI > The upper pad 452 is formed in contact with the contact 452 on the back side of the substrate 110. Thus, the upper pad 452 and the circuits 211, 212, 213, 215 and 217 are electrically connected by the contact 452 so that the upper pad 452 is connected to the circuits 211, 212, 213, 215, 217, respectively. Here, the contact 452 may be in contact with the first wiring 211 located on the uppermost layer among the wiring layers constituting the circuit. However, the contact 452 may be formed on the upper portion of the first wiring 211, 2 wiring 213 or the third wiring 215, or the like. The image sensor of this embodiment has a separate contact 452 that contacts the circuits 211, 212, 213, 215 and 217 and is electrically connected to the pad 452 formed on the back side of the substrate 110 via the contact 452. [ Are electrically connected to the circuits 211, 212, 213, 215, and 217, respectively.

Hereinafter, an image sensor according to another embodiment of the present invention will be described with reference to FIG. 9 is a cross-sectional view illustrating an image sensor according to another embodiment of the present invention. The image sensor according to this embodiment is different from the embodiment of the present invention in that a lower pad is formed in an insulating structure, and different points will be mainly described below.

9, the insulating structure includes an insulating film 200, circuits 211, 212, 213, 215, and 217, and a lower pad 153, and a contact 452 is formed in the substrate 110 have.

The lower pad 153 is formed to be electrically connected to the circuit portions 211, 212, 213, 215, and 217 on the upper portions of the circuit portions 211, 212, 213, 215, Specifically, it is connected to the circuits 211, 212, 213, 215, and 217 through the lower pad contact 154. At this time, the lower pad contact 154 may be in contact with the first wiring 211 disposed on the uppermost layer among the multilayer wiring constituting the circuits 211, 212, 213, 215, and 217, but is not limited thereto . That is, the lower pad contact 153 is connected to the second wiring 213, the third wiring 215, or the fourth wiring 217 (not shown) formed below the first wiring 211, not the first wiring 211 disposed on the uppermost layer. ).

The contact 452 may be formed in a contact hole that penetrates the back side and the front side of the substrate 110 and exposes the lower pad 153 and may contact the lower pad 153. Thereby electrically connecting to the lower pad 253. An upper pad 451 is formed on the contact 452. Thus, the upper pad 451 and the lower pad 153 are electrically connected by the contact 452. In this embodiment, a separate lower pad positioned on the circuit is formed, so that the upper pad and the circuit can be electrically connected easily and the contact resistance can be reduced.

Hereinafter, a method of manufacturing an image sensor according to an embodiment of the present invention will be described with reference to FIGS. 10 to 15. FIG. 10 to 15 are sectional views of an intermediate structure for explaining a method of manufacturing an image sensor according to an embodiment of the present invention.

10, device isolation regions 111 such as STI (Shallow Trench Isolation) and DTI (Deep Trench Isolation) are formed on a substrate 110 to form a light receiving portion I and a circuit portion II).

Then, a plurality of pixels are formed in the light receiving portion I. More specifically, a photoelectric conversion element 120, for example, a photodiode PD and a floating diffusion region 130 are formed in the light receiving section I, and a plurality of gates 140 are formed on the light receiving section I . Such a gate 140 may be, for example, a gate of a charge transfer element, a gate of a reset element, a gate of a drive element, or the like.

Next, the insulating structures 200, 210, 220, and 230 are formed on the front surface of the substrate 110. More specifically, the insulating structures 200, 210, 220, and 230 are formed on the interlayer insulating layer 200 and a wiring layer 230 including a multilayer wiring 231, 232, and 233 formed on the light receiving portion I And a first circuit 210 and a second circuit 220 formed on the circuit part II. Here, the first circuit 210 includes a plurality of wirings, for example, first to fourth wirings 211, 213, 215, 217 and a wiring contact 212.

Referring to FIG. 11, the supporting substrate 300 is bonded on the insulating structures 200, 210, 220, and 230.

Specifically, an adhesive film 312 is formed on the insulating structures 200, 210, 220, and 230 to planarize the surface. An adhesive film 311 is formed on the supporting substrate 300. Thereafter, the adhesive films 311 and 312 are opposed to each other, and the substrate 110 and the supporting substrate 300 are bonded to each other.

Referring to FIG. 12, the top and bottom of the substrate 110 are inverted and the back side of the substrate 110 is polished.

Specifically, the back surface of the substrate 110 is polished by using CMP (Chemical Mechanical Polishing), BGR (Back Grinding), reactive ion etching, or a combination thereof. The thickness of the polished and remaining substrate 110 may be, for example, about 3-5 占 퐉.

Referring to FIG. 13, an anti-reflection film 181 is formed on the back side of the substrate 110. For example, a silicon oxide film about 50-200 angstroms thick and a silicon nitride film about 300-500 angstroms thick can be formed by using a CVD (Chemical Vapor Deposition) method.

Subsequently, a buffer film 182 is formed on the antireflection film 181. For example, a silicon oxide film having a thickness of about 3000-8000A can be formed by stacking using a CVD method.

Referring to FIG. 14, contact holes 141 and 142 penetrating the back side and the front side of the substrate 110 are formed in the circuit part II.

Specifically, a photoresist pattern (not shown) defining an area where a contact hole is to be formed is formed on the buffer film 182, and a buffer film 182, an antireflection film 181, a substrate 110 and the contact holes 141, 142 exposing the circuits 210, 220 are formed. When etching the contact holes 141 and 142, anisotropic etching may be used.

Referring to FIG. 15, upper pads 151 and 152 are formed on a back side of a substrate 110. Referring to FIG.

Specifically, a conductive film (not shown) for upper pads partially or completely filling the contact holes 141 and 142 is formed on the buffer film 182, and a conductive film After forming the defined photoresist pattern, the conductive film for the upper pad is etched using the photoresist pattern as a mask to partially or completely fill the inside of the contact holes 141 and 142, thereby forming an upper pad 151 and 152 can be formed.

Although not shown in the drawing, a color filler (161 in FIG. 4) is formed so as to correspond to the photoelectric conversion element (120 in FIG. 4) on the back side of the light receiving section (I) The color filter can be formed by a dyeing method, a pigment dispersion method, a printing method, or the like. The color filter may be formed of a dyed photoresist and may be formed of one of three colors of red, green, and blue. As a result, one color filter corresponding to each photoelectric conversion element is located on the back side of the substrate 110. Then, a planarization layer (162 in FIG. 4) can be formed using a polyimide-based or polyacrylic-based polymer having excellent light transmittance on the color filter. Then, microlenses (171 in Fig. 4) are formed on the planarization layer so as to correspond to the respective photoelectric conversion elements. The microlenses can be formed by forming patterns covering the photoelectric conversion elements using a photo-transparent photoresist, and then reflowing them. Thereby, it is possible to form a microlens having a certain curvature on the flattening layer and convex shape.

A method of manufacturing an image sensor according to another embodiment of the present invention will be described with reference to a method of manufacturing an image sensor according to an embodiment of the present invention.

16 is a schematic block diagram illustrating a processor-based system including an image sensor in accordance with embodiments of the present invention.

Referring to FIG. 16, a processor-based system 1000 is a system for processing an output image of a CMOS image sensor 1110. System 1000 may illustrate a computer system, a camera system, a scanner, a mechanized clock system, a navigation system, a video phone, a supervisory system, an autofocus system, a tracking system, an operation monitoring system, an image stabilization system, It is not.

A processor-based system 1000 such as a computer system or the like includes a central processing unit (CPU) 1120 such as a microprocessor or the like capable of communicating with an input / output (I / O) element 1130 via a bus 1005. The CMOS image sensor 1110 may communicate with the system via bus 1005 or other communication link. The processor-based system 1000 may further include a RAM 1140, a CD ROM drive 1150, and / or a port 1160 capable of communicating with the CPU 1120 via a bus 1005. The port 1160 may be a port capable of coupling a video card, a sound card, a memory card, a USB device, or the like, or communicating data with another system. The CMOS image sensor 1110 may be integrated with a CPU, a digital signal processing device (DSP), a microprocessor, or the like. Also, the memories may be integrated together. Of course, in some cases, it may be integrated on a separate chip from the processor.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

I: light receiving part II: circuit part
110: substrate 151: upper pad
153: lower pad 452: contact
210, 220: circuit 200: interlayer insulating film

Claims (10)

A substrate including a front surface and a back surface, and a circuit portion in which a light receiving portion including pixels and a circuit for driving the pixels around the light receiving portion are formed;
An insulating structure formed on a front surface of the circuit portion, the insulating structure including the circuit;
A lower pad disposed in the insulating structure above the upper end of the circuit and configured to be electrically connected to the upper end of the circuit;
An upper pad disposed on a rear surface of the circuit portion so as to be positioned above the circuit;
A contact hole penetrating through the circuit portion to expose the lower pad; And
And a contact electrically connecting the upper pad and the lower pad formed in the contact hole. The method according to claim 1,
Wherein the upper pad is formed in the circuit portion and includes a separate pad region. 3. The method of claim 2,
Wherein the upper pad is disposed in an area excluding an edge of the circuit part. 3. The method of claim 2,
A plurality of upper pads,
Wherein at least one of the plurality of upper pads is disposed such that the distance from the upper pad to the light receiving portion is closer to the distal end of the circuit portion. 5. The method of claim 4,
Wherein at least one of the plurality of upper pads is disposed at an edge of the circuit portion. A substrate including a front surface and a back surface, and a circuit portion in which a light receiving portion including pixels and a circuit for driving the pixels around the light receiving portion are formed;
An insulating structure formed on a front surface of the circuit portion, the insulating structure including the circuit;
A lower pad disposed in the insulating structure above the upper end of the circuit and configured to be electrically connected to the upper end of the circuit;
An upper pad disposed on a rear surface of the circuit portion so as to be positioned above the circuit;
A contact hole penetrating through the circuit portion to expose the lower pad; And
And a contact electrically connecting the upper pad and the lower pad formed in the contact hole,
Wherein the upper pad and the lower pad are arranged to include a portion overlapping the circuit. The method according to claim 6,
Wherein the upper pad is disposed in an area excluding an edge of the circuit part. The method according to claim 6,
A plurality of upper pads,
Wherein at least one of the plurality of upper pads is disposed such that the distance from the upper pad to the light receiving portion is closer to the distal end of the circuit portion. A substrate including a light receiving portion including a pixel and a circuit portion in which a circuit for driving the pixel around the light receiving portion is formed, the front surface and the rear surface being defined;
A driving circuit formed on a front surface of the substrate of the circuit portion;
A lower pad formed on a front surface of the substrate and arranged to be positioned above the upper end of the driving circuit and electrically connected to an upper end of the driving circuit;
An upper pad disposed on the rear surface of the substrate so as to overlap the driving circuit; And
And a contact electrically connecting the upper pad and the lower pad through the substrate. 10. The method of claim 9,
Wherein the distance between the upper pad and the light receiving portion is less than the distance between the upper pad and the end of the circuit portion.

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