KR20190028674A - Display panel and method of fabricating the same - Google Patents

Abstract

A display panel includes: an array substrate; an opposite substrate facing the array substrate, and a liquid crystal layer disposed between the array substrate and the opposite substrate. The array substrate includes a display area, a non-display area surrounding the display area, wherein the non-display area is a first non-display area disposed on one side of the display area, and a second non-display area other than the first non-display area; and the first non-display area overlaps with the opposite substrate. The display panel may have substantially the same size as the array substrate and the opposite substrate, and a wiring member connected to an external circuit module may be disposed below the array substrate. Therefore, the display device having the display panel does not need to separately provide a space for accommodating the wiring member, and an area other than the display area on which an image is displayed can be minimized.

Description

DISPLAY PANEL AND METHOD OF FABRICATING THE SAME [0002]

The present invention relates to a display panel and a method of manufacturing the same, and more particularly, to a display panel capable of minimizing a pad area connected to an external circuit module and a method of manufacturing the same.

 In general, the display device includes a display panel for displaying an image, and an external circuit module for providing various control signals to the display panel, wherein the display panel and the external circuit module are fixed to a storage container such as a chassis. The display panel and the external circuit module are connected to each other through a wiring member such as a tape carrier package (TCP) or a flexible printed circuit board (FPC) including a driver IC.

Meanwhile, the wiring member is generally attached to one side of the display panel and connected to the external circuit module. Therefore, the display panel is required to have a certain space at one side of the display panel to be connected to the wiring member, and the storage container should have a predetermined space for the wiring member. As described above, the space for the wiring member is limited in the recent research tendency in the display device to minimize the area other than the area where the image is displayed on the display panel.

It is an object of the present invention to provide a display panel capable of minimizing a pad area connected to an external circuit module.

Another object of the present invention is to provide a method of manufacturing the display panel.

According to an aspect of the present invention, a display panel includes an array substrate, an opposing substrate facing the array substrate, and a liquid crystal layer disposed between the array substrate and the opposing substrate. Wherein the array substrate is divided into a display region and a non-display region surrounding the display region, the non-display region includes a first non-display region disposed on one side of the display region, and a second non- Display region, and the first non-display region overlaps with the counter substrate.

The first non-display region may include a wiring region adjacent to the display region, and a pad region other than the wiring region.

The array substrate includes a base substrate disposed in the display region, the second non-display region, and the wiring region, a thin film transistor arranged on the base substrate in the display region, a pixel electrode connected to the thin film transistor, A signal input pad disposed in the region and electrically connected to the external circuit module, and a signal wiring disposed in the wiring region and connecting the signal input pad and the thin film transistor, And may be electrically connected to the external circuit module through a flexible circuit board attached to a lower surface of the external circuit module.

The array substrate may further include a polymer organic pattern supporting the signal input pad, and the signal input pad may be disposed on a lower surface of the polymer organic pattern.

And an encapsulation pattern disposed between the array substrate and the counter substrate in the non-display area. At least a portion of the encapsulation pattern may overlap the polymer organic material pattern in the first non-display region.

The array substrate includes a base substrate disposed in the display region and the non-display region, the base substrate having a through hole disposed in the first non-display region, a thin film transistor disposed on the base substrate in the display region, And a signal wiring which is disposed in the first non-display region and is electrically connected to the thin film transistor and fills the aperture, wherein the signal wiring is connected to the flexible circuit board attached to the lower surface of the array substrate, As shown in FIG.

The planar area of the array substrate and the opposing substrate may be the same.

According to another aspect of the present invention, there is provided a method of manufacturing a display panel, including the steps of: fabricating an array substrate; disposing a liquid crystal layer between the array substrate and a counter substrate including a common electrode facing the array substrate; And bonding the substrate and the counter substrate. Wherein the step of fabricating the array substrate is divided into a display area and a non-display area surrounding the display area, wherein the non-display area includes a first non-display area disposed on one side of the display area, The method comprising the steps of: preparing a base substrate including a second non-display region of the base substrate; forming a trench spaced apart from the display region in a first non-display region of the base substrate; Forming a signal input pad inside the trench, the signal input pad connected to the thin film transistor at the same time, and forming a pixel electrode connected to the thin film transistor. And removing the part of the base substrate from the first non-display area after the array substrate and the counter substrate are bonded together so that the signal input pad is exposed on the lower surface of the array substrate.

According to another aspect of the present invention, there is provided a method of manufacturing a display panel, including the steps of: fabricating an array substrate; disposing a liquid crystal layer between the array substrate and a counter substrate including a common electrode facing the array substrate; And bonding the array substrate and the counter substrate together. Wherein the step of fabricating the array substrate is divided into a display area and a non-display area surrounding the display area, wherein the non-display area includes a first non-display area disposed on one side of the display area, Forming a through hole in a first non-display area of the base substrate, the through hole being spaced apart from the display area; a step of forming a thin film transistor Forming a signal line to be connected to the thin film transistor, filling the through hole at the same time, and forming a pixel electrode connected to the thin film transistor.

In the display panel, the size of the array substrate and the counter substrate are substantially the same, and a wiring member connected to the external circuit module may be disposed below the array substrate. Therefore, the display device having the display panel does not need to separately provide a space for accommodating the wiring member, so that the area other than the display area where the image is displayed can be minimized.

1 is an exploded perspective view illustrating a display device to which a display panel according to an embodiment of the present invention is applied.
FIG. 2 is a perspective view of the display panel shown in FIG. 1, with the array substrate facing upward.
3 is a rear view for explaining a state before the flexible circuit board is attached to the display panel shown in Fig.
4 is an enlarged view of the area A in Fig.
5 is an enlarged view of the area B in Fig.
6 is a plan view for explaining a state where a flexible circuit board is attached to a display panel.
7 is a cross-sectional view taken along line I-I 'of Fig.
8 is a cross-sectional view for explaining a shape in which the flexible circuit board is bent in the display panel of FIG.
9 to 14 are process sectional views for explaining the manufacturing method of the display panel shown in Figs. 2 to 8. Fig.
15 is a cross-sectional view illustrating a display panel according to another embodiment of the present invention.
16 is a cross-sectional view illustrating a display panel according to another embodiment of the present invention.
17 is a sectional view for explaining a shape in which the flexible circuit board is bent in the display panel of Fig.
18 to 21 are process sectional views for explaining the manufacturing method of the display panel shown in Figs. 16 and 17. Fig.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exploded perspective view illustrating a display device to which a display panel according to an embodiment of the present invention is applied.

Referring to FIG. 1, the display device includes a display panel 100, a backlight unit 200, an upper cover 410, and a lower cover 420.

As the display panel 100, various types of display panels can be applied. For example, a liquid crystal display (LCD) panel, an electrophoretic display panel (EPD panel), and an electrowetting display panel (EWD panel) may be used as the display panel 100, It is possible to use a display panel as shown in Fig. In the present embodiment, the liquid crystal display panel will be described as the display panel 100 as an example.

The display panel 100 has a rectangular plate shape having long sides and short sides and includes a display area DA for displaying an image and a non-display area NDA around the display area DA. The display panel 100 includes an array substrate 110, a counter substrate 120 facing the array substrate 110, and a liquid crystal layer (not shown) formed between the array substrate 110 and the counter substrate 120 Time). A polarizing film (not shown) may be attached to both surfaces of the display panel 100, that is, the outer surfaces of the array substrate 110 and the counter substrate 120.

A plurality of pixels (not shown) arranged in a matrix may be arranged in the display area DA of the array substrate 110. Here, each pixel may include a plurality of sub-pixels, and each sub-pixel may have a different color. For example, each of the sub-pixels may have a color of red, green, and blue. Therefore, the light emitted from each of the sub-pixels may have one of red, green, and blue colors. Each of the pixels may include a gate line (not shown), a data line (not shown) that is insulated from the gate line, and a pixel electrode (not shown). In addition, a thin film transistor (not shown) electrically connected to the gate line and the data line and electrically connected to the pixel electrode may be provided for each pixel. The thin film transistor may switch the driving signal provided to the corresponding pixel electrode side.

A sealing pattern (not shown) for attaching the array substrate 110 and the counter substrate 120 to each other may be disposed in the non-display area NDA of the array substrate 110.

A signal input pad (not shown) electrically connected to the thin film transistor may be disposed in a part of the non-display area NDA of the array substrate 110. The signal input pad is connected to the flexible circuit board 140 on which the driver IC 141 is mounted and the flexible circuit board 140 can be connected to an external circuit module (not shown). The driver IC 141 receives various control signals from the external circuit module and outputs a driving signal for driving the display panel 100 to the thin film transistor side in response to input various control signals.

The driver IC 141 may be attached to a lower surface of the array substrate 110, that is, a surface of the array substrate 110 facing the backlight unit 200.

The counter substrate 120 includes a color filter (not shown) for realizing a predetermined color using light provided from the backlight unit 200 on a surface thereof, and a color filter (not shown) formed on the color filter, And a common electrode (not shown) opposite to the common electrode. Wherein the color filter has a hue of either red, green, or blue and may be formed through a process such as deposition or coating. In the present embodiment, the color filter is formed on the counter substrate 120, but the present invention is not limited thereto. For example, the color filter may be formed on the array substrate 110.

The liquid crystal layer is arranged in a specific direction by a voltage applied to the pixel electrode and the common electrode to control the transmittance of the light provided from the backlight unit 200 so that the display panel 100 displays an image .

The backlight unit 200 is disposed in a direction opposite to the direction in which the image is emitted from the display panel 100. The backlight unit 200 includes a light guide plate 210, a light source unit 220 including a plurality of light sources, an optical member 230, and a reflective sheet 240.

The light guide plate 210 is positioned below the display panel 100 and guides the light emitted from the light source unit 220 to emit the light toward the display panel 100. In particular, the light guide plate 210 overlaps the display area DA of the display panel 100 at least. Here, the light guide plate 210 includes an emission surface for emitting the light, a bottom surface facing the emission surface, and side surfaces connecting the emission surface and the bottom surface. At least one of the side surfaces may be an incident surface on which the light emitted from the light source unit 220 is incident on the light source unit 220 in opposition to the light source unit 220, .

The light source unit 220 may include a plurality of light sources 221, for example, a plurality of light-emitting diodes mounted on a printed circuit board (PCB) 222. Here, the light sources 221 may emit light of different colors. For example, some of the light sources 221 may emit red light, another of the light sources 221 may emit green light, and the remainder of the light sources 221 emit blue light .

The light source unit 220 is disposed to face the at least one of the side surfaces of the light guide plate 210 to emit light so that the display panel 100 transmits light used for displaying an image to the light guide plate 210 ).

The optical member 230 is provided between the light guide plate 210 and the display panel 100. The optical member 230 is provided in the light source unit 220 and controls light emitted through the light guide plate 210. In addition, the optical member 230 includes a diffusion sheet 236, a prism sheet 234, and a protective sheet 232 which are sequentially stacked.

The diffusion sheet 236 diffuses the light emitted from the light guide plate 210. The prism sheet 234 condenses the light diffused in the diffusion sheet 236 in a direction perpendicular to the plane of the upper display panel 100. The light passing through the prism sheet 234 is incident almost perpendicularly to the display panel 100. The protective sheet 232 is positioned on the prism sheet 234. The protective sheet 232 protects the prism sheet 234 from external impact.

In the present embodiment, the optical member 230 includes the diffusion sheet 236, the prism sheet 234, and the protection sheet 232, but the present invention is not limited thereto. The optical member 230 may use at least any one of the diffusion sheet 236, the prism sheet 234 and the protective sheet 232 in a stacked manner, It is possible.

The reflective sheet 240 is disposed under the light guide plate 210 and reflects light leaked from the light emitted from the light source unit 220 in the direction of the display panel 100, 100) direction. The reflective sheet 240 includes a material that reflects light. The reflection sheet 240 is provided on the lower cover 420 to reflect the light generated from the light source unit 220. As a result, the reflective sheet 240 increases the amount of light provided to the display panel 100 side.

Meanwhile, in the present embodiment, the light source unit 220 is arranged to provide light in the lateral direction of the light guide plate 210. However, the present invention is not limited thereto. For example, the light source unit 220 may be arranged to provide light in a direction of a lower surface of the light guide plate 210. In the backlight unit 200, the light guide plate 210 is omitted and the light source unit 220 is positioned below the display panel 100. The light emitted from the light source unit 220 is transmitted to the display panel 100, The light may be provided directly to the light source 100.

The upper cover 410 is provided on the upper portion of the display panel 100. The upper cover 410 includes a display window 411 for exposing the display area DA of the display panel 100. The upper cover 410 is engaged with the lower cover 420 to support the front edge of the display panel 100.

The lower cover 420 is provided at a lower portion of the backlight unit 200. The lower cover 420 includes a space for accommodating the display panel 100 and the backlight unit 200. The lower cover 420 is coupled with the upper cover 410 to receive and support the display panel 100 and the backlight unit 200 in the inner space.

FIG. 2 is a perspective view of the display panel shown in FIG. 1 with the array substrate facing upward. FIG. 3 is a rear view illustrating a state before the flexible circuit board is attached to the display panel shown in FIG. Fig. 4 is an enlarged view of region A in Fig. 3, Fig. 5 is an enlarged view of region B in Fig. 3, Fig. 6 is a plan view for explaining a state in which a flexible circuit board is attached to a display panel, 6 is a cross-sectional view taken along line I-I 'of FIG. 6, and FIG. 8 is a cross-sectional view illustrating a bent shape of the flexible circuit board in the display panel of FIG. On the other hand, in the description of FIGS. 2 to 8, the upper surface means the surface in the direction of the counter substrate in each component, and the lower surface means the surface in the opposite direction to the upper surface in each component.

2 to 8, the display panel 100 includes a display area DA for displaying an image and a non-display area NDA for surrounding the display area DA. The non-display area NDA includes a first non-display area NDA-1 disposed on one side of the display area DA, and a second non-display area NDA-1 other than the first non- Region (NDA-2).

The display panel 100 includes an array substrate 110, an opposing substrate 120 facing the array substrate 110, and a liquid crystal layer 120 disposed between the array substrate 110 and the opposing substrate 120. [ (130).

Since the array substrate 110 corresponds to the shape of the display panel 100, the display area DA and the first non-display area NDA-1 and the second non-display area NDA- And the non-display area NDA including the non-display area NDA. In addition, the array substrate 110 may include an upper surface facing the counter substrate 120 and a lower surface opposite to the upper surface.

A plurality of pixels capable of realizing colors may be arranged in a matrix form in the display area DA of the array substrate 110. A thin film transistor TFT and a pixel electrode 115 may be disposed in each pixel .

The encapsulation pattern SP may be disposed in the non-display area NDA of the array substrate 110. The sealing pattern SP is disposed to surround the display area DA to adhere the array substrate 110 and the counter substrate 120 to prevent the liquid crystal layer 130 from leaking to the outside have. In addition, the sealing pattern SP has conductivity so that a common voltage can be applied to the common electrode 125 of the counter substrate 120.

The first non-display area NDA-1 of the array substrate 110 overlaps with the counter substrate 120 and includes a wiring area SA adjacent to the display area DA, (PA) other than the pad region PA. That is, both the pad region PA and the wiring region SA of the array substrate 110 overlap with the counter substrate 120.

A signal input pad (SIP) electrically connected to the thin film transistor (TFT) may be disposed in the pad area PA of the array substrate 110. Here, the signal input pad SIP may be disposed on the lower surface of the array substrate 110 in the pad area PA.

Meanwhile, the signal input pad (SIP) may be supported by the polymer organic material pattern 116. For example, the signal input pad SIP is disposed on the lower surface of the polymer organic pattern 116 and is supported by a bonding force between the signal input pad SIP and the polymer organic pattern 116 .

A common voltage pad 117 may be disposed on the upper surface of the polymer organic material pattern 116. The common voltage pad 117 is in contact with the sealing pattern SP having conductivity to allow a common voltage to be applied to the common electrode 125. The common voltage pad 117 may include a transparent conductive oxide such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

The polymer organic material pattern 116 covers the pad region PA and may extend to a portion of the wiring region SA. In addition, the polymer organic material pattern 116 may include a photosensitive resin such as a photoresist. The polymer organic material pattern 116 may be disposed in the pad region PA and may be cured by light to support the signal input pad SIP. The polymer organic material pattern 116 may be a polymer organic material such as polyethyleneterephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), polyetherimide (PEI) ), Polyethersulfone (PES), polyetheretherketone (PEEK), and polyimide (PI).

A signal line SL connecting the thin film transistor TFT and the signal input pad SIP may be disposed in the wiring region SA of the array substrate 110. [

The encapsulation pattern SP may overlap at least part of the polymer organic material pattern 116. This is to maximize the area in which the signal input pad SIP contacts the flexible circuit board 140 on which the driver IC 141 is mounted. More specifically, as the overlapping area or width of the encapsulation pattern SP overlaps with the polymer organic material pattern 116, the area occupied by the pad area PA in the first non-display area NDA-1 Or the width becomes smaller. The area or width of the signal input pad SIP is reduced and the area or width of the signal input pad SIP contacting the flexible printed circuit board 140 on which the driver IC 141 is mounted becomes small . The area or width occupied by the pad area PA in the first non-display area NDA-1 becomes larger as the area or width of overlapping the encapsulation pattern SP with the polymer organic material pattern 116 increases. Therefore, the exposed area or width of the signal input pad SIP is increased and the area or width of the signal input pad SIP contacting the flexible circuit board 140 on which the driver IC 141 is mounted can be increased .

The array substrate 110 includes a first base substrate 111, the thin film transistors TFT disposed on the first base substrate 111 in the display region DA, And the pixel electrode 115 connected to the pixel electrode.

The first base substrate 111 may be disposed in a part of the non-display area NDA and in the display area DA. For example, the first base substrate 111 is disposed in the display area DA, the second non-display area NDA-2, and the wiring area SA, and has a rectangular shape having long sides and short sides It may be plate-like. That is, the first base substrate 111 does not overlap with the pad region PA.

The first base substrate 111 includes a transparent insulating material and is capable of transmitting light. The first base substrate 111 may be a rigid type substrate, or may be a flexible type. The rigid type substrate includes a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystalline glass substrate. The flexible type substrate includes a film substrate including a polymer organic substance and a plastic substrate. The material used for the first base substrate 111 preferably has resistance (or heat resistance) to a high processing temperature in the manufacturing process.

The thin film transistor TFT is disposed on the first base substrate 111 and may include a semiconductor layer SCL, a gate electrode GE, a source electrode SE, and a drain electrode DE. The gate electrode GE disposed on the first base substrate 111, the gate insulating film 112 covering the gate electrode GE, the gate insulating film And a source electrode SE and a drain electrode DE respectively connected to both ends of the semiconductor layer SCL. Here, the semiconductor layer SCL includes a channel region overlapping the gate electrode GE on a plane, a source region connected to the source electrode SE, and a drain region connected to the drain electrode DE . The gate electrode GE of the thin film transistor TFT may be connected to a gate line GL for transmitting a scan signal or a gate signal to the thin film transistor TFT. The source electrode SE of the thin film transistor TFT may be connected to a data line DL for transmitting a data voltage to the thin film transistor TFT.

Though the thin film transistor of the bottom gate structure in which the gate electrode GE of the thin film transistor TFT is located under the semiconductor layer SCL has been described above as an example, the present invention is not limited thereto. For example, the thin film transistor (TFT) may be a thin film transistor of a top gate structure in which the gate electrode GE is located above the semiconductor layer (SCL).

A protective film 114 is disposed on the thin film transistor TFT. A portion of the passivation layer 114 may be a contact hole CH that is open to expose a portion of the drain electrode DE. In addition, the protective layer 114 may have a multi-layer structure as the case may be. For example, the protective film 114 may include an inorganic protective film covering the TFT and the gate insulating film 112 and made of an inorganic material, and an organic protective film made of organic material disposed on the inorganic protective film. Here, the surface of the organic passivation layer may be planarized by removing a step generated by the underlying thin film transistor (TFT).

The pixel electrode 115 is disposed on the protection layer 114 and the pixel electrode 115 is electrically connected to the drain electrode DE through the contact hole CH. The pixel electrode 115 may include a transparent conductive oxide such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

At least one of the gate line GL and the data line DL, for example, the data line DL may be connected to the signal input pad SIP through a signal line SL.

A flexible circuit board 140 on which the driver IC 141 is mounted may be connected to the lower surface of the signal input pad SIP. Since the signal input pad SIP is disposed on the lower surface of the polymer organic material pattern 116, the flexible circuit board 140 may be attached to the lower portion of the array substrate 110. The driver IC 141 receives various control signals from an external circuit module and receives a driving signal for driving the display panel 100 in response to various input control signals through the signal input pad SIP To the thin film transistor (TFT) side.

The counter substrate 120 is disposed in the display area DA and the non-display area NDA. The counter substrate 120 includes a second base substrate 121 and a common electrode 125 formed on the second base substrate 121. Like the first base substrate 111, the second base substrate 121 may be a rigid substrate or a flexible type substrate. The common electrode 125 may include a transparent conductive oxide such as the pixel electrode 115. The common electrode 125 transmits the common voltage Vcom, which is transmitted through the encapsulation pattern SP having conductivity, to each pixel.

The liquid crystal layer 130 includes a plurality of liquid crystal molecules. The liquid crystal molecules are arranged in a specific direction by an electric field formed between the pixel electrode 115 and the common electrode 125 to control the transmittance of light. Therefore, the liquid crystal layer 130 transmits the light provided from the backlight unit 200 by the electric field, so that the display panel 100 can display an image.

The display panel 100 includes a driver IC 141 mounted thereon for outputting a driving signal for driving the display panel 100 and having a substantially same size as the array substrate 110 and the counter substrate 120 A flexible circuit board 140 is attached on the lower surface of the array substrate 110 in the pad area PA. Therefore, the display device including the display panel 100 need not have a separate space for accommodating the flexible circuit board 140 in the upper cover and the lower cover. Accordingly, the size of the upper cover and the lower cover can be reduced.

9 to 14 are process sectional views for explaining the manufacturing method of the display panel shown in Figs. 2 to 8. Fig. Here, Figs. 9 to 14 are respectively limited to the first non-display area and the display area of the display panel.

Thereby fabricating the array substrate 110. The array substrate 110 includes a display area DA and a non-display area NDA surrounding the display area DA. The non-display area NDA includes a first non-display area NDA-1 disposed on one side of the display area DA, and a second non-display area NDA-1 other than the first non- Region (NDA-2). The first non-display area NDA-1 may be divided into a wiring area SA adjacent to the display area DA and a pad area PA other than the wiring area SA.

The array substrate 110 includes a first base substrate 111, a polymer organic material pattern 116 disposed on one side of the first base substrate 111, a first base substrate 111, A thin film transistor (TFT) disposed on the insulating film 113, and the pixel electrode 115 connected to the thin film transistor (TFT).

A method for manufacturing the array substrate 110 will now be described in more detail.

First, referring to FIG. 9, a first base substrate 111 is prepared. Here, the first base substrate 111 is optically transmissive, and may be a rectangular plate having a long side and a short side. Also, the first base substrate 111 may be disposed in the display area DA and the non-display area NDA.

After the first base substrate 111 is prepared, the first non-display region NDA-1 of the first base substrate 111 is formed with one of the long side and the short side, for example, along the long side Thereby forming a trench T arranged in parallel. Here, the trench T may be spaced apart from the display area DA. Meanwhile, the trench T may be formed by various methods. For example, the trench T may be formed by removing the first non-display area NDA-1 of the first base substrate 111 using a laser. The trench T may be formed by forming a photoresist pattern so as to expose a part of the first non-display area NDA-1 of the first base substrate 111, . ≪ / RTI >

Referring to FIG. 10, after the trench T is formed, the thin film transistor TFT is formed on the first base substrate 111 of the display area DA. The thin film transistor TFT may include a gate electrode GE, a semiconductor layer SCL, a source electrode SE, and a drain electrode DE.

The gate electrode GE is formed on the first base substrate 111 and the gate insulating film 112 covering the gate electrode GE is formed on the first base substrate 111. [ ). A semiconductor layer SCL is formed on the gate insulating layer 112 and a source electrode SE and a drain electrode DE connected to the source region and the drain region of the semiconductor layer SCL are formed . The region between the source region and the drain region may be a channel region.

The data line DL is electrically connected to the source electrode SE and the source electrode SE and the drain electrode DE and is electrically connected to the data line DL. A signal input pad SIP disposed on the insulating film 113 of the region PA and a signal wiring pad SW1 connecting the data line DL and the signal input pad SIP, (SL) may be formed. Here, the signal input pad SIP may be disposed inside the trench T.

After forming the thin film transistor (TFT), the polymer organic material pattern 116 is formed by filling a polymer organic material in the trench T. The polymer organic material pattern 116 contacts the signal input pad SIP on the lower surface.

The polymer organic material pattern 116 may include a photosensitive resin. The polymer organic material pattern 116 may be formed of a polymer organic material capable of transmitting light such as polyethyleneterephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), polyetherimide At least one of polyetheretherketone (PEI), polyethersulfone (PES), polyetheretherketone (PEEK), and polyimide (PI).

After the polymer organic material pattern 116 is formed, a protective film 114 covering the thin film transistor TFT and the polymer organic material pattern 116 is formed. The protective layer 114 may include an inorganic material, an organic material, or an inorganic or organic composite material.

After the protective layer 114 is formed, a part of the protective layer 114 is removed to expose a part of the drain electrode DE. The removed region may be a contact hole (CH).

After exposing a part of the drain electrode DE, a transparent conductive oxide is deposited and patterned. The pixel electrode 115 connected to the drain electrode DE of the thin film transistor TFT through the contact hole CH is formed in the display region DA by the patterning. In addition, the common voltage pad 117 is formed in the first non-display area NDA-1 by the patterning.

Referring to FIG. 11, after the array substrate 110 is formed, a sealing pattern SP is disposed in the non-display area NDA of the array substrate 110. That is, the sealing pattern SP may have a shape to surround the display area DA.

The sealing pattern SP may have conductivity and the sealing pattern SP is connected to the common electrode 125 so that the common electrode 125 can apply the common voltage Vcom to each pixel . For example, the sealing pattern SP may be a polymer resin containing at least one of an epoxy resin, a phenol resin and an acryl resin, at least one of gold, silver, copper and aluminum , And a mixture of organic binders. In addition, the sealing pattern SP can be cured by heat or light.

After the sealing pattern SP is formed, a liquid crystal layer 130 including a plurality of liquid crystal molecules is disposed in the display area DA.

After the liquid crystal layer 130 is disposed, a counter substrate 120 including a second base substrate 121 and a common electrode 125 disposed on the second base substrate 121 is prepared. Here, the counter substrate 120 may be divided into the display area DA and the non-display area NDA.

Then, the common electrode 125 of the counter substrate 120 is disposed so as to face the array substrate 110. Here, the array substrate 110 and the counter substrate 120 are bonded together by the sealing pattern SP. Accordingly, the sealing pattern SP is disposed to surround the display area DA, and the array substrate 110 and the counter substrate 120 are bonded together, thereby preventing the liquid crystal layer 130 from leaking to the outside can do.

Although the liquid crystal layer 130 is disposed after the sealing pattern SP is formed and the array substrate 110 and the counter substrate 120 are attached to each other, But is not limited thereto. For example, after the seal pattern SP is formed and the array substrate 110 and the counter substrate 120 are bonded together, the liquid crystal layer 130 is bonded to the array substrate 110 and the counter substrate 120 may be used.

After the array substrate 110 and the counter substrate 120 are bonded to each other, heat or light is supplied to the sealing pattern SP to cure the sealing pattern SP.

Referring to FIG. 12, after the encapsulation pattern SP is cured, protrusions (not shown) protrude from the counter substrate 120 in the pad area PA of the array substrate 110, for example, And removes the area.

A part of the array substrate 110 is removed and then the first base substrate 111 and the gate insulating film 112 of the pad region PA are removed. Here, when the first base substrate 111 and the gate insulating layer 112 are removed from the pad region PA, the signal input pad SIP is exposed from the lower portion of the array substrate 110. The first base substrate 111 may be removed by laser cutting or wet etching.

13, after the first base substrate 111 is removed, a flexible circuit board 140 connected to an external circuit module is attached to the signal input pad SIP of the pad area PA, The signal input pad (SIP) and the driver IC 141 are electrically connected.

Referring to FIG. 14, after connecting the flexible circuit board 140 to the signal input pad SIP, the pad area PA is bent in the direction of the backlight unit.

Thereafter, the display panel 100 may be housed in the upper cover and the lower cover together with the backlight unit, thereby manufacturing the display device.

The display panel 100 manufactured through the above-described process has a pad region PA for connecting the signal input pad SIP and the flexible circuit board 140 on the array substrate 110, And may have a shape that does not protrude from the substrate 120. Therefore, the display device including the display panel 100 need not have a space for the pad area PA in the upper cover and the lower cover.

Hereinafter, other embodiments of the present invention will be described with reference to FIGS. 15 to 21. FIG. In Figs. 15 to 21, the same constituent elements as those shown in Figs. 1 to 14 are denoted by the same reference numerals, and a detailed description thereof will be omitted. In order to avoid redundant description in FIGS. 15 to 21, differences from FIGS. 1 to 14 will be mainly described.

15 is a cross-sectional view illustrating a display panel according to another embodiment of the present invention.

The display panel shown in Fig. 15 has a structure similar to that of the display panel 100 shown in Figs. However, the display panel shown in FIG. 15 has a structure in which the exposed surfaces of the first base substrate 111 and the signal input pad SIP of the array substrate 110 are substantially flat. Therefore, the thickness of the first base substrate 111 of the array substrate 110 is reduced, and the thickness of the entire display panel can be reduced.

The display panel shown in FIG. 15 has a process of removing a thickness of the first base substrate 111 before the flexible circuit board 140 on which the driver IC 141 is mounted is attached to the signal input pad SIP And can be produced in addition. For example, the surface of the signal input pad SIP and the surface of the first base substrate 111 may be flattened by performing a grinding or etching process on the lower surface of the first base substrate 111.

The display panel may be formed by curing the sealing pattern SP without separately performing a process of removing the first base substrate 111 of the pad area PA and then curing the bottom surface of the first base substrate 111 The surface of the signal input pad SIP and the surface of the first base substrate 111 may be flattened by performing a grinding or etching process. For example, the first base substrate 111 may be removed until the signal input pad SIP is exposed by removing the gate insulating layer 112 of the pad region PA. Therefore, the first base substrate 111 of the pad area PA is removed, and the display panel can reduce the entire thickness.

FIG. 16 is a cross-sectional view illustrating a display panel according to another embodiment of the present invention, and FIG. 17 is a cross-sectional view illustrating a bent shape of a flexible circuit board in the display panel of FIG.

16 and 17, the display device includes a display area DA and a non-display area NDA that surrounds the display area DA. The non-display area NDA includes a first non-display area NDA-1 disposed on one side of the display area DA, and a second non-display area NDA-1 other than the first non- Region (NDA-2).

The display panel 100 includes an array substrate 110, an opposing substrate 120 facing the array substrate 110, and a liquid crystal layer 120 disposed between the array substrate 110 and the opposing substrate 120. [ (130).

Since the array substrate 110 corresponds to the shape of the display panel 100, the array substrate 110 can be divided into the display area DA and the non-display area NDA. The array substrate 110 includes a first base substrate 111, a thin film transistor (TFT) disposed on the upper surface of the first base substrate 111, and a plurality of thin film transistors And a pixel electrode 115.

The first base substrate 111 may be a rectangular plate having long sides and short sides arranged in the display area DA and the non-display area NDA. In addition, the first base substrate 111 may include a through hole TH disposed in a part of the first non-display area NDA-1.

The thin film transistor (TFT) is disposed on the insulating film 113 and may include a semiconductor layer SCL, a gate electrode GE, a source electrode SE, and a drain electrode DE. The source electrode SE may be connected to a data line DL for transmitting a data voltage to the thin film transistor TFT.

A protective film 114 is disposed on the thin film transistor TFT. A portion of the passivation layer 114 may be a contact hole CH that is open to expose a portion of the drain electrode DE.

The pixel electrode 115 is disposed on the protection layer 114 and the pixel electrode 115 is electrically connected to the drain electrode DE through the contact hole CH.

A sealing pattern SP may be disposed between the array substrate 110 and the counter substrate 120 in the non-display area NDA. The encapsulation pattern SP is conductive and contacts the common voltage pad 117 so that a common voltage can be applied to the common electrode 125 of the counter substrate 120. [

The source electrode SE may be connected to a data line DL and the data line DL may be connected to a signal input pad SIP through a signal line SL. The signal line SL is disposed on the first base substrate 111 of the first non-display area NDA-1 and the signal input pad SIP is disposed on the second base substrate 111 of the first non- And may be disposed on the lower surface. Further, the signal line SL and the signal input pad SIP are connected through the through hole TH.

18 to 21 are process sectional views for explaining the manufacturing method of the display panel shown in Figs. 16 and 17. Fig.

First, the array substrate 110 is manufactured. The array substrate 110 includes a display area DA and a non-display area NDA of a display panel. The non-display area NDA includes a first non-display area NDA-1 disposed on one side of the display area DA, and a second non-display area NDA-1 other than the first non- Region (NDA-2). The array substrate 110 includes a first base substrate 111, the thin film transistors TFT disposed on the first base substrate 111 in the display area DA, The pixel electrode 115 is electrically connected to the thin film transistor TFT in the first non-display region NDA-1 and has a signal input Pad (SIP).

A method for manufacturing the array substrate 110 will now be described in more detail.

Referring to Fig. 18, first, a first base substrate 111 is prepared. Here, the first base substrate 111 is optically transmissive, and may be a rectangular plate having a long side and a short side.

Then, a conductive material is deposited on the upper surface of the first base substrate 111 and patterned to form a gate electrode GE and a gate line (not shown).

After the gate electrode GE and the gate line are formed, a gate insulating film 112 covering the gate electrode GE and the gate line is formed.

After forming the gate insulating film 112, a part of the first non-display area NDA-1 is removed to form a through hole TH (see FIG. 1) through the first base substrate 111 and the gate insulating film 112 ).

After the hole TH is formed, amorphous silicon is deposited on the gate insulating layer 112 and patterned to form a semiconductor layer SCL. The semiconductor layer SCL may have a shape partially overlapped with the gate electrode GE.

After the semiconductor layer SCL is formed, a conductive material is deposited on the semiconductor layer SCL and the gate insulating layer 112 and is patterned to form a source electrode SE, a drain electrode DE, a data line DL ), And a signal wiring line SL. Here, the source electrode SE and the drain electrode DE form a thin film transistor TFT together with the gate electrode GE and the semiconductor layer SCL. In addition, the source electrode SE and the drain electrode DE may be spaced apart from each other to contact the semiconductor layer SCL. The source electrode SE and the data line DL are connected to each other and the data line DL is connected to the signal line SL. The signal line SL may fill the through hole TH and be exposed from the lower surface of the first base substrate 111.

Then, a conductive material is deposited on the lower surface of the first base substrate 111 and patterned to form the signal input pad SIP in the first non-display area NDA-1. The signal input pad SIP may be in contact with the signal line SL.

Although the signal input pad SIP is separately formed in this embodiment, the present invention is not limited thereto. For example, the signal line SL may fill the through hole TH and be exposed on the lower surface of the first base substrate 111. The exposed surface of the signal line SL may play the same role as the signal input pad SIP.

Then, a protective film 114 covering the thin film transistor TFT is formed, and a part of the protective film 114 is removed to form a contact hole CH exposing the drain electrode DE.

After the contact hole CH is formed, the pixel electrode 115 connected to the drain electrode DE of the thin film transistor TFT through the contact hole CH is formed to fabricate an array substrate.

Referring to FIG. 19, after the array substrate 110 is manufactured, a sealing pattern SP is disposed in the non-display area NDA of the array substrate 110. The sealing pattern SP may have conductivity and may be cured by heat or light.

After the sealing pattern SP is formed, the liquid crystal layer 130 is disposed in the display area DA.

After the liquid crystal layer 130 is disposed, a counter substrate 120 including a second base substrate 121 and a common electrode 125 disposed on the second base substrate 121 is prepared, The common electrode 125 of the pixel electrode 120 is arranged to face the array substrate 110. Here, the array substrate 110 and the counter substrate 120 may be bonded together by the sealing pattern SP.

After the array substrate 110 and the counter substrate 120 are bonded to each other, heat or light is supplied to the sealing pattern SP to cure the sealing pattern SP.

Referring to FIG. 20, after the sealing pattern SP is cured, a part of the array substrate 110, for example, the first non-display area NDA-1 of the array substrate 110, The region protruding from the counter substrate 120 is removed.

21, a part of the array substrate 110 is removed and then the flexible circuit board 140 is attached to the signal input pad SIP to connect the signal input pad SIP and the driver IC 141 Connect electrically.

After the flexible circuit board 140 is connected to the signal input pad SIP, the flexible circuit board 140 is bent.

Thereafter, the display panel 100 may be housed in the upper cover and the lower cover together with the backlight unit, thereby manufacturing the display device.

The foregoing description is intended to illustrate and describe the present invention. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, It is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention. Accordingly, the foregoing description of the invention is not intended to limit the invention to the precise embodiments disclosed. In addition, the appended claims should be construed to include other embodiments.

Display panel; 100 array substrate; 110
A first base substrate; 111 gate insulating film; 112
Insulating film; 113 protective film; 114
A pixel electrode; 115 Polymer organic matter pattern; 116
Common voltage pad; 117 opposing substrate; 120
A second base substrate; 121 common electrode; 125
A liquid crystal layer; 130 Flexible circuit board; 140
Driver IC; 141 protective film; 150
Backlight unit; 200 light guide plate; 210
A light source unit; 220 light source; 221
Printed circuit board; 222 optical member; 230
Protective sheet; 232 prism sheet; 234
Diffusion sheet; 236 reflective sheet; 240
An upper cover; 410 display window; 411
A lower cover; 420 Thin Film Transistor; TFT
A gate electrode; A GE semiconductor layer; SCL
A source electrode; An SE drain electrode; DE
A data line; DL gate line GL
Contact holes; CH display area; DA
Non-display area; NDA first non-display area; NDA-1
A second non-display area; NDA-2 pad area; PA
Signal input pad; SIP etching bath; EB
Trench; T bag pattern: SP
Through hole; TH

Claims (8)

A base substrate including a top surface and a bottom surface defining a display region and a wiring region adjacent to the display region;
A thin film transistor superposed on the display region and disposed on the upper surface of the base substrate;
A protective film covering the thin film transistor and disposed on the upper surface of the base substrate, the protective film including at least a portion that does not overlap with the base substrate;
A polymer organic material pattern superposed on the one portion and disposed on a lower surface of the protective film; And
And a signal input pad superimposed on the one portion and disposed on a lower surface of the polymer organic material pattern. The method according to claim 1,
The base substrate includes:
A pixel electrode disposed on the upper surface of the base substrate and connected to the thin film transistor; And
And a signal wiring overlapping the wiring region and connecting the signal input pad and the thin film transistor,
Wherein the signal input pad is electrically connected to an external circuit module through a flexible circuit board attached to a lower surface of the signal input pad. The method according to claim 1,
Wherein the polymeric organic material pattern is disposed on the base substrate and overlaps a part of the wiring region. The method according to claim 1,
Wherein the lower surface of the signal input pad and the lower surface of the base substrate are flat. The method according to claim 1,
And said one portion of said wiring region and said protective film corresponds to a non-display region. A base substrate including a top surface and a bottom surface defining a display area and a non-display area adjacent to the display area, the through hole overlapping the non-display area and passing through the top surface and the bottom surface;
A thin film transistor superimposed on the display region and disposed on the upper surface of the base substrate;
A pixel electrode disposed on the upper surface of the base substrate and connected to the thin film transistor; And
And a signal wiring disposed in the through hole, the signal wiring overlapping the non-display region and electrically connected to the thin film transistor,
Wherein the signal wiring is electrically connected to a flexible circuit board attached to the lower surface of the base substrate. The method according to claim 6,
And a signal input pad disposed on the lower surface of the base substrate in the non-display area, the signal input pad electrically connecting the signal wiring and the flexible circuit board. A base substrate including a top surface and a bottom surface defining a display region and a wiring region adjacent to the display region;
A thin film transistor superposed on the display region and disposed on the upper surface of the base substrate;
A protective film covering the thin film transistor and disposed on the upper surface of the base substrate, the protective film including at least a portion that does not overlap with the base substrate;
A polymer organic material pattern superposed on the one portion and disposed on a lower surface of the protective film; And
And a signal input pad disposed on the lower surface of the polymer organic material pattern and electrically connected to the external circuit module through the flexible circuit board.

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