KR20190011475A - Method for manufacturing a wafer and the wafer - Google Patents

Abstract

According to an embodiment of the present invention, a wafer manufacturing method comprises: a step of preparing a substrate including a dopant doped at a low concentration of 1E17 atoms/cm^3 or less, having a resistivity of 0.2 Ω·cm or more, and not having a void defect; a step of rapidly and thermally heating the prepared substrate; a step of removing a nitride film from the rapidly and thermally heated substrate; a step of annealing the substrate; and a step of forming an epitaxial layer on the annealed substrate.

Description

[0001] The present invention relates to a method for manufacturing a wafer,

An embodiment relates to a wafer manufacturing method and a wafer.

The epitaxial wafer can prevent the deterioration of device characteristics and the yield reduction due to crystal defects and metal contamination by making a silicon layer free from defects in the active area of the device. Here, the defect may mean a suicide (silicide) defect caused by a void defect, metal contamination or the like.

For the above reasons, epitaxial wafers have been utilized as substrates for various semiconductor devices such as microprocessors, flash memories, image sensors or power devices.

In particular, due to the high integration and high performance of the devices, the demand for the fine quality of wafers is gradually increasing, and the technical interest about the perfectness and strength of epitaxial wafers is increasing.

Conventionally, epitaxial wafers were prepared using a substrate doped with Boron at a concentration of 1E18 atoms / cm3 or more. In this case, the boron-enhanced oxygen precipitation and dislocation pinning effects can increase the gettering ability of metal contamination on epitaxial wafers and increase the strength of epitaxial wafers.

When an epitaxial wafer is manufactured using a substrate doped with boron at a high concentration, various technical problems such as autodoping may be caused by a heat treatment process during the device manufacturing process. Therefore, it is a trend to manufacture epitaxial wafers using boron doped at a low concentration instead of high concentration.

However, epitaxial wafers manufactured using a boron doped substrate at a low concentration instead of a high concentration have a problem that gettering force and mechanical strength against metal contamination are lowered compared with epitaxial wafers manufactured using a boron doped substrate at a high concentration Problems can arise.

Japanese Unexamined Patent Publication No. 2011-54763 Japanese Patent Application Laid-Open No. 2017-50490

The embodiments provide a wafer manufacturing method and a wafer having high uniformity and high oxygen precipitate (BMD) density and gettering force and high strength.

A method of manufacturing a wafer according to an embodiment includes: preparing a substrate including a dopant doped at a low concentration of 1E17 atoms / cm3 or less, having a resistivity of 0.2 OMEGA .cm or more and having no void defect; Subjecting the prepared substrate to rapid thermal annealing; Removing the nitride film from the rapid thermal annealed substrate; Annealing the substrate; And forming an epitaxial layer over the annealed substrate.

For example, the substrate to be prepared may have an initial oxygen concentration of 5E17 atoms / cm3 to 7E17 atoms / cm3.

For example, the substrate to be prepared may comprise a constituent element; And a heterogeneous element different from the constituent element.

For example, the constituent element may include silicon, oxygen, and boron, the hetero element may include nitrogen, and the concentration of nitrogen may be 1E12 atoms / cm3 to 1E14 atoms / cm3.

For example, the rapid thermal annealing may be performed at a temperature ranging from 1100 ° C to 1300 ° C for 1 second to several tens of seconds.

For example, the rapid thermal annealing may be performed using a gas mixture of argon and a nitrogen-based compound.

For example, the rapid thermal processing may be performed in a plurality of thermal processing steps, and the temperature at which the plurality of thermal processing steps are performed may be different from each other.

For example, the plurality of thermal processing steps may include a first-stage rapid thermal processing process for rapidly heat-treating the substrate during a first period at a first temperature; And a second rapid thermal processing step of rapidly heat-treating the substrate during a second period at a second temperature different from the first temperature after the rapid thermal processing step in the first step.

For example, the first temperature may range from 1100 ° C. to 1150 ° C., the first period may range from 1 second to 10 seconds, the second temperature may range from 1150 ° C. to 1200 ° C., .

For example, the rate of temperature rise from the first temperature to the second temperature may be 20 ° C / s to 100 ° C / s.

For example, the step of removing the nitride layer may perform at least one of a chemical process or a mechanical process on the rapid thermal annealed substrate.

For example, the chemical process may use a cleaning liquid containing hydrofluoric acid.

For example, the mechanical process may include polishing the rapidly heat-treated substrate.

For example, the annealing may be performed at a temperature in the range of 600 ° C to 950 ° C for 10 minutes to several hours.

A wafer according to another embodiment includes: a substrate; And an epitaxial layer disposed on the substrate, wherein the substrate includes a dopant doped at a low concentration of 1E17 atoms / cm3 or less, has a resistivity of 0.2 OMEGA .cm or more, has no void defect, % ≪ / RTI > of the oxide precipitate density.

According to yet another embodiment, a wafer includes: a substrate; And an epitaxial layer disposed on the substrate, wherein the substrate includes a dopant doped at a low concentration of 1E17 atoms / cm3 or less, has a resistivity of 0.2 OMEGA .cm or more, has no void defect, It can have a potential propagation.

For example, the wafer may comprise a constituent element; And a heterogeneous element different from the constituent element.

For example, the conductive dopant is a p-type dopant, the initial oxygen concentration of the wafer is 5E17 atoms / cm3 to 7E17 atoms / cm3, the constituent elements include silicon, oxygen and boron, And the concentration of nitrogen may be 1E12 atoms / cm3 to 1E14 atoms / cm3.

For example, the oxide precipitate density may be 7E9 atoms / cm3 to 1.5E10 atoms / cm3.

For example, the wafer may have a metal gettering power of 80% to 90%.

The wafer manufacturing method and the wafer according to the embodiment have a uniform BMD density distribution in the radial direction even though the wafer does not have COPs while the wafer is manufactured using the substrate doped with a low concentration of dopant and the BMD density of the wafer is And the wafer has a high level of gettering force and has sufficient strength to resist deformation and slip during processing.

1 is a flowchart for explaining a wafer manufacturing method according to an embodiment.
2A and 2B show an exemplary process cross-sectional view of a wafer produced by the wafer manufacturing method shown in FIG.
Fig. 3 shows potential propagation depending on the initial oxygen concentration and the concentration of nitrogen.
Figs. 4 (a) to 4 (d) are graphs showing BMD densities of epi wafers depending on the concentration of nitrogen, which is a different element.
5 is a graph showing the occurrence of NILD in an epi wafer according to initial oxygen concentration and nitrogen concentration.
FIGS. 6A and 6B are diagrams showing the occurrence of a pattern of an epitaxial layer surface in an epitaxial wafer. FIG.
7 is an exemplary graph for explaining the RTA process according to the embodiment.
8 is an exemplary graph for explaining the annealing process according to the embodiment.
FIG. 9 is an exemplary graph for explaining the preprocessing step and step 160 according to the embodiment.
10 is a graph comparing the BMD densities of the epitaxial wafers manufactured by the first to fourth comparative examples and the examples.
11A to 11E are graphs comparing the uniformity of the BMD density of the epitaxial wafers manufactured by the first to fourth comparative examples and the embodiments.
12A to 12E are photographs of epi wafers manufactured by the first to fourth comparative examples and the embodiments.
13 is a graph showing the gettering power of the epitaxial wafers manufactured by the first, third and fourth comparative examples and the embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate understanding of the present invention. However, the embodiments according to the present invention can be modified into various other forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the invention are provided to more fully describe the present invention to those skilled in the art.

In the description of the present embodiment, in the case of being described as being formed "on or under" of each element, the upper (upper) or lower (lower) on or under includes both the two elements being directly in contact with each other or one or more other elements being indirectly formed between the two elements.

Also, when expressed as "on" or "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

Also, the terms "first" and "second", "upper atoms / upper atoms / upper" and "lower atoms / lower atoms / lower" Or may be used to distinguish one entity or element from another entity or element, without necessarily requiring or implying a logical relationship or order.

Hereinafter, an epitaxial wafer refers to a wafer formed on an epitaxial layer (for example, 220 in FIG. 2B) on a substrate (for example, 210A in FIG. 2B), and a bare wafer (or bulk wafer) The wafer 210 may be a wafer on which the semiconductor layer 220 is not formed on the substrate 210A. For example, the bulk wafer may correspond to the substrate 210A on which steps 120 through 150 shown in FIG. 1 have been performed.

In addition, a wafer not specifically referred to as an 'epi wafer' or a 'bare wafer' or a 'bulk wafer' may refer to an epitaxial wafer or a bulk wafer.

Hereinafter, a method of manufacturing a wafer according to an embodiment will be described with reference to the accompanying drawings.

1 is a flowchart for explaining a wafer manufacturing method 100 according to an embodiment.

2A and 2B show an exemplary process cross-sectional view of a wafer produced by the wafer manufacturing method 100 shown in FIG.

Referring to FIGS. 1 and 2A, a substrate 210 including a lightly doped dopant is prepared (operation 120). Here, the dopant may be a boron (B) or the like and a p-type dopant, or may be an n-type dopant such as phosphorus (P), and the embodiment is not limited to the kind of the dopant.

In addition, the maximum value of the concentration of the dopant doped to the low concentration may be 1E17 atoms / cm3, but the embodiment is not limited thereto. In this case, the substrate 210 may have a resistivity of 0.2 OMEGA .cm or more.

Further, the minimum value of the concentration of the dopant doped to the low concentration may be 1E13 atoms / cm3, but the embodiment is not limited thereto. In this case, the substrate 210 may have a resistivity of 100 Ω · cm or less.

As a result, in step 120, the substrate 210 having a dopant having a low concentration of 1E13 atoms / cm3 to 1E17 atoms / cm3 can be prepared. That is, the substrate 210 having a resistivity of 0.2 OMEGA .cm to 100 OMEGA .cm can be prepared.

In addition, the substrate 210 prepared in operation 120 may not have void defects, that is, COPs (Crystal-Originated Particles). If COPs are present, the shape of the COP may change to a needle shape or the like when the heterogeneous element 212 is present on the substrate 210 as described later. As a result, defects may be generated on the surface of the epitaxial layer 220 on the substrate 210A, which will be described later, resulting in a reduction in yield of the device. Thus, to improve the crystallinity of the epitaxial layer 220, a substrate 210 without COPs may be used.

For example, oxygen atoms contained in a single crystal ingot grown by the Czochralski method are impurities involved in oxygen precipitation formation and dislocation pinning. The greater the concentration of oxygen atoms (hereinafter, referred to as 'initial oxygen concentration'), the greater the strength of the wafer can be secured.

Fig. 3 shows dislocation propagation depending on the initial oxygen concentration (Oi) and the concentration of nitrogen. The abscissa is the initial oxygen concentration in units of ppma, and the ordinate is the dislocation propagation unit in μm.

As a result of measuring the length of the potential propagation (or slip propagation) through the heat treatment after the Vickers indentation while varying the initial oxygen concentration Oi, the initial oxygen concentration Oi, as illustrated in FIG. 3, The slip propagation length is continuously decreased as the number of slip waves increases. Therefore, when the initial oxygen concentration is high, the strength of the wafer can be sufficiently secured.

A method of evaluating the strength of a wafer will be briefly described below.

The wafer strength evaluation is performed with a Vickers hardness tester at a force of 100 gf on the wafer surface, followed by a diffusion heat treatment, for example, at a temperature of 900 캜 for one hour to generate and propagate the potential in the indentation damage. Then, selective etching is performed to measure the potential length, and the strength of the wafer is evaluated by measuring the potential length generated in the indentation mark. At this time, Wright etchant or Secco etchant can be used for selective etching.

At this time, as a strength evaluation method, there is an evaluation method called rosette, which evaluates the slip resistance against mechanical and thermal stress. The rosetta evaluation method is a well-known evaluation method for those skilled in the art, and therefore, a detailed description thereof will be omitted here.

On the other hand, if the initial oxygen concentration Oi is larger than 7E17 atoms / cm3, the oxygen of the substrate 210 is in-diffused into the epitaxial layer 220 during the device process, Etc., which may cause a leakage defect in an element using an epitaxial wafer. In addition, when the initial oxygen concentration included in the substrate 210 is less than 5E17 atoms / cm3, oxygen precipitates may not be generated.

Thus, in order to avoid the formation of defects and ensure the mechanical strength of the wafer, the substrate 210 prepared in operation 120 may have an initial oxygen concentration of 5E17 atoms / cm3 to 7E17 atoms / cm3. That is, according to the new ASTM standards, the substrate 210 prepared in operation 120 may be formed to have a thickness of 10 to 15 ppma, for example, 10 to 14 ppma or 11.5 to 15 ppma Lt; RTI ID = 0.0 > oxygen < / RTI > Alternatively, according to the old ASTM standard, the substrate 210 prepared in step 120 may have an initial oxygen concentration of 20 ppma to 30 ppma, for example 20 ppma to 28 ppma or 23 ppma to 30 ppma. have.

Referring again to FIG. 1, the substrate 210 prepared in operation 120 may include not only the constituent elements but also the hetero atoms 212. The heterogeneous element means a constituent element and a heterogeneous element of the substrate 210.

The constituent elements and the hetero elements of the substrate 210 may be varied depending on the characteristics of the device in which the epitaxial wafer is used. At this time, the kind of the hetero-element and the concentration of the hetero-element may be independent of the concentration of the dopant doped on the substrate 210. For example, the constituent elements of the substrate 210 may include silicon (Si), oxygen (O), and boron (B), and the heteroatom may include nitrogen (N) .

When heterogeneous elements 212 of a certain concentration or more are included in the substrate 210, stable nucleation nuclei are formed at high temperatures to form bulk microdefects (BMDs) (or precipitates ) May increase and the gettering ability of the wafer may be improved. Here, the grown-in precipitation nuclei may mean precipitation nuclei formed during the growth of a single crystal ingot. Here, the oxygen precipitates or BMD of the wafer is an index showing the oxygen precipitation ability of the wafer, and is a long time heat treatment in which oxygen precipitation is likely to occur. For example, after heat treatment at 800 ° C for 4 hours and at 1000 ° C for 16 hours, The formed oxide precipitate or BMD can be measured by a laser scattering method or a cross-sectional etching method.

4 (a) to 4 (d) are graphs showing BMD densities of epi wafers according to the concentration of nitrogen (N) which is the different element 212.

4 (a) shows the BMD density when nitrogen (N) is not included in the substrate 210 and FIG. 4 (b) shows the BMD density when the nitrogen (N) having a concentration of 1E12 atoms / 4D shows the BMD density when the substrate 210 contains nitrogen (N) having a concentration of 1E13 atoms / cm3, and FIG. 4D shows the BMD density when the substrate 210 is included. Is included in the substrate 210. The nitrogen concentration of the nitrogen (N)

4 (b) to 4 (d), when the substrate 210 is formed with the heterogeneous element 212 as shown in FIG. 4 (a) It can be seen that the BMD density increases when the DBD 212 is included.

It is also known that various atomic complex structures formed by nitrogen (N), which is a hetero element 212 in the bulk of the silicon substrate 210, contribute to dislocation fixation. Therefore, the strength of the wafer can be improved by including the hetero-elements 212 in the substrate 210. [ 3, when nitrogen (N), which is a hetero-element 212, is included in the substrate 210 rather than when the hetero-element 212 is not included in the substrate 210 (320, 330, 340) It can be seen that the length is further reduced. That is, when the hetero-element 212 is included in the substrate 210, the potential fixing effect can be enhanced.

3, reference numeral 320 denotes a case where the concentration of nitrogen (N) is 1E12 atoms / cm3 to 1E13 atoms / cm3, and reference numeral 330 denotes a case where the concentration of nitrogen (N) is 1E13 atoms / atoms / cm3, reference numeral 340 denotes a case where the concentration of nitrogen (N) is 1E14 atoms / cm3 to 1E15 atoms / cm3, reference numeral 350 denotes a case where the dopant is doped at a high concentration, Which is the third comparative example.

In particular, referring to FIG. 3, when the concentration of nitrogen (N) is 1E13 atoms / cm < 3 > or more, the effect of inhibiting dislocation propagation becomes clearer when the concentration of nitrogen (N) is 1E12 atoms / cm3 to 1E13 atoms / Able to know.

However, if the concentration of nitrogen (N) as the heteroelement 212 is larger than 1E14 atoms / cm3, the size of the oxide precipitate becomes too large to cause defects on the surface of the epitaxial wafer, thereby deteriorating the quality of the epitaxial wafer .

5 is a graph showing the occurrence of nitrogen-induced large defect (NILD) in an epi wafer according to initial oxygen concentration Oi and nitrogen concentration [N].

5, when the concentration ([N]) of nitrogen (N) is 1E14 atoms / cm3 or less, NILD is not found in the epitaxial wafer (NILD FREE) atoms / cm < 3 >, NILD is found in the epitaxial wafer (NILD FOUND). Particularly, when the concentration ([N]) of nitrogen (N) is 1E14 atoms / cm3 or less, the occurrence of NILD is independent of the initial oxygen concentration (Oi).

FIGS. 6A and 6B are diagrams showing the occurrence of a pattern on the surface of the epitaxial layer 220 in an epitaxial wafer.

If a NILD is found 410 as shown in FIG. 5, a pattern of defects may occur at the center of the surface of the epitaxial layer 220 as shown in FIG. 6A. However, if the NILD is not found (420) as shown in FIG. 5, no pattern is generated in the center of the surface of the epitaxial layer 220 as shown in FIG. 6B.

In addition, when the concentration of nitrogen (N) as the heteroelement 212 is less than 1E12 atoms / cm3, the potential propagation suppressing effect is insufficient as shown in Fig. 3 and the strength of the wafer can be weakened, Similarly, the BMD density may be small.

As a result, the concentration ([N]) of nitrogen in which the density of BMD is high and the strengthening effect is pronounced but NILD does not occur can be from 1E12 atoms / cm3 to 1E14 atoms / cm3, for example, from 1E12 atoms / cm3 to 6.8E13 atoms / However, the embodiment is not limited to this.

As a result, the substrate 210 prepared in the above step 120 has an initial oxygen concentration of 5E17 atoms / cm3 to 7E17 atoms / cm3, does not have a void defect, and is doped with a low concentration of 1E10 atoms / cm3 to 1E17 atoms / And having a resistivity of 0.2 Ω · cm to 100 Ω · cm and doped with a concentration of 1E12 atoms / cm3 to 1E14 atoms / cm3. The substrate 210 having these various conditions can be manufactured in various ways.

In general, as a method of manufacturing the substrate 210, a Floating Zone (FZ) method or a Czochralski (CZ) method is widely used. When the single crystal ingot is grown by applying the FZ method, it is difficult to manufacture the large diameter substrate 210 and there is a problem that the process cost is very high. Therefore, it is general to grow a single crystal ingot based on the CZ method.

When the constituent element of the substrate 210 is silicon, according to the CZ method, polycrystalline silicon is charged in a quartz crucible, the graphite heating body is heated and melted, the seed crystal is immersed in the silicon melt formed as a result of melting , The crystallization is caused at the melt interface, and the seed crystal is pulled up while rotating to grow the single crystal silicon ingot. Thereafter, the grown monocrystalline silicon ingot is sliced, etched and polished to produce a wafer 210 in the form of a wafer.

At this time, in order to make the substrate 210 having various conditions as described above, the amount of the doping of the hetero-element 212 and the dopant into the silicon melt, the time of injection, the feeding rate, the rotational speed of the silicon melt, At least one of various factors such as the number of the heaters to be heated, the position and the heat generating temperature, the position of the magnetic field to be applied to the silicon melt, the strength of the magnetic field, or the pulling rate and rotation speed of the seed crystal.

Referring to FIG. 1 again, the substrate 210 prepared in operation 120 is subjected to rapid thermal annealing (RTA) (operation 130). Step 130 may be performed to create a region in which the vacancy is supersaturated within the bulk of the substrate 210. In addition, by doping the substrate 210 with a hetero element such as nitrogen in addition to oxygen, the vacancy in the RTA process and the interaction of oxygen and nitrogen can be advantageously applied to the formation of oxygen precipitation nuclei Lt; RTI ID = 0.0 > complex. ≪ / RTI > The composite produced at this time may be a vacancy-oxygen complex (VO _x ) and a nitrogen-vacancy complex (NV), but the present invention is not limited thereto.

On the other hand, when rapid thermal annealing (RTA) is performed at a temperature lower than 1100 ° C, supersaturation of vacancies and formation of various complexes may not occur sufficiently. Further, when the rapid thermal annealing is performed at a temperature higher than 1300 ° C, the epitaxial wafers may be slipped and the strength may be weakened. Thus, rapid thermal annealing (RTA) may be performed in the range of 1100 ° C to 1300 ° C, but the embodiments are not limited thereto.

Also, rapid thermal annealing (RTA) can not be performed for 1 second. Also, if rapid thermal annealing (RTA) is performed for more than a few tens of seconds, the epitaxial wafers may be slip and weaken in strength. Thus, rapid thermal annealing (RTA) may be performed for 1 second to several tens of seconds, but the embodiments are not limited thereto.

In addition, the rapid thermal annealing can be performed using a gas mixture of argon (Ar) and a nitrogen-based compound.

Also, by rapid thermal annealing, vacancies are injected into the bulk of the substrate 210 at a high temperature, thereby creating an environment in which oxygen precipitates (BMD) are generated. Thus, in order to sufficiently inject the vacancies into the bulk, the rapid thermal processing can be performed in a plurality of thermal processing steps, and the temperature at which the plurality of thermal processing steps are performed may be different from each other.

Hereinafter, an example in which the rapid thermal annealing process is divided into two thermal process steps will be described with reference to the accompanying drawings. Here, the first thermal process step of the two thermal process steps is referred to as a 'first RTA process,' and the later thermal process step is referred to as a second RTA process.

7 is an exemplary graph for explaining the RTA process according to the embodiment.

Referring to FIG. 7, the RTA of the first stage is performed during the first period P1 at the first temperature T1, and the RTA at the second stage during the second period P2 is performed at the second temperature T2. can do. Here, the first period P1 means a period from the second time t2 to the third time t3, and the second period P2 means a period from the fourth time t4 to the fifth time t5 .

Here, the first temperature T1 and the second temperature T2 may be different from each other, and the second temperature T2 may be greater than the first temperature T1. Further, the second period P2 may be equal to or greater than the first period P1, and each of the first and second temperatures T1 and T2 is determined within a temperature range of 1100 DEG C to 1300 DEG C, Each of the periods P1 and P2 can be determined within a range of 1 second to several tens of seconds.

7, the temperature in the chamber (or the temperature of the substrate 210) is injected into the first ramp up (ramp up #) by injecting a mixed gas in which a nitrogen-based gas and an argon (Ar) 1) period. The first ramp up # 1 period is a period from the first time t1 to the second time t2 and the rate at which the temperature rises during this period may be 20 ° C / s to 100 ° C / s have.

Thereafter, the first stage RTA may be performed at the first temperature T1 during the first period P1. For example, the first period P1 may be between 1 second and 10 seconds, and the first temperature T1 may be between 1100 ° C and 1150 ° C. At this time, the nitrogen-based gas may be injected into the chamber by 10% or more of the partial pressure of the mixed gas to be injected. For example, when the total gas mixture injected into the chamber is 400 sccm per minute, the flow rate at which the nitrogen-based gas is introduced may be 41 sccm per minute. The reason why the nitrogen-based gas is introduced into the chamber during the period P1 during which the RTA in the first step is performed is to control the baking time concentration of the substrate 210. However, when the RTA in the second step is performed, the introduction of the nitrogen-based gas is stopped.

After the RTA of the first stage is performed, the temperature in the chamber (or the temperature of the substrate 210) is increased during the second ramp up # 2 period. The second ramp up # 2 period is a period from the third time t3 to the fourth time t4, and the rate at which the temperature rises during this period may be 20 占 폚 / s to 100 占 폚 / s have. Thereafter, the second stage RTA may be performed at the second temperature T2 during the second period P2. For example, the second period P2 may be between 1 second and 10 seconds, and the second temperature T2 may be between 1150 ° C and 1200 ° C.

In FIG. 7, the flow rate at which argon is supplied from the first time t1 to the sixth time t6 may be 10 slm to 30 slm, but the embodiment is not limited thereto.

After operation 130, the nitride layer may be removed from the rapid thermal annealed substrate 210 (Operation 140). Metal contamination caused by the furnace during the RTA process and a thermal nitride film (hereinafter referred to as 'nitride film') generated in the thermal process may exist. If the epitaxial layer 220 is formed without controlling the epitaxial layer 220, the integrity of the final epitaxial wafer can not be guaranteed, so that the contamination source can be removed by performing Step 140.

Alternatively, when this thermal nitride is subjected to additional heat treatment while remaining on the surface of the substrate 210, the nitrogen is diffused into the bulk of the substrate 210 by the nitride film on the surface of the substrate 210, The reaction between the silicon substrate 210 and the silicon-based gas is inhibited during the growth of the epitaxial layer 220 while the thermal nitride is present, so that the epitaxial layer 220 may not be grown, 220 can not be guaranteed. Therefore, in order to prevent undesired defects from occurring from the surface while performing the subsequent thermal process, step 140 may be performed to remove the nitride film as a contamination source.

According to the embodiment, in operation 140, the rapid thermal annealed substrate may be subjected to at least one of chemical processes or mechanical processes to remove the nitride film.

For example, when performing a chemical process to remove the nitride film, a cleaning method similar to RCA or RCA may be used, and the embodiment is not limited to a specific cleaning method. In addition, when performing a chemical process to remove the nitride film, a cleaning liquid containing hydrofluoric acid (HF) may be used, but the embodiment is not limited thereto.

Alternatively, when performing a mechanical process to remove the nitride film, the rapid thermal annealed substrate may be polished.

After operation 140, the substrate 210 on which the nitride film has been removed is annealed (operation 150). Step 150 is performed in order to induce strengthened oxygen precipitation nucleation and obtain additional thermal stability based on the baconial supersaturated region created in the bulk in step 130 and various complexes formed therein. The rate of formation of oxygen precipitation nuclei is accelerated as the degree of supersaturation of vacancies increases, and as the complex structure capable of acting as a nucleation site exists, the rate can be accelerated as well. For example, the oxygen precipitation nucleation rate enhanced in the annealing process can be obtained by using the vacancy-oxygen composite and the nitrogen-vacancy complex formed in the RTA process in operation 130 as nucleation sites. As described above, since more oxygen precipitation nuclei are formed after the step of applying in the embodiment, sufficient oxygen precipitation nuclei can survive the 160th step of forming the epitaxial layer 220, But the embodiment is not limited thereto.

For example, when the temperature of the annealing is higher than 950 ° C, a thermal slip may occur and the crystallinity of the epitaxial layer 220 in the epitaxial layer may be lowered. Further, when the annealing temperature is lower than 600 占 폚, generation of oxygen precipitation nuclei may not occur sufficiently. Thus, the annealing can be performed in the range of 600 캜 to 950 캜, but the embodiment is not limited thereto.

In addition, the annealing process can be performed for 10 minutes to several hours in consideration of the incubation time.

8 is an exemplary graph for explaining the annealing process according to the embodiment.

Referring to FIG. 8, the temperature in the chamber (or the temperature of the substrate 210) is increased during the third ramp up # 3 period while injecting argon (Ar) gas into the chamber. The third ramp up # 3 period is a period from the seventh time t7 to the eighth time t8, and the rate at which the temperature rises during this period is 2 ° C / min to 10 ° C / min have.

Thereafter, annealing may be performed at the third temperature T3 during the third period P3. For example, the third period P3 may be from 0.1 hour to 2 hours, and the third temperature T1 may be from 600 ° C to 950 ° C. Then, during the first ramp down # 1 period, the temperature in the chamber (or the temperature of the substrate 210) is lowered. The first ramp down # 1 period is a period from the ninth time t9 to the tenth time t10, and the rate at which the temperature falls during this period is 2 ° C / min to 10 ° C / min However, the embodiment is not limited to this.

In FIG. 8, the flow rate at which argon (Ar) gas is supplied from the seventh time t7 to the tenth time t10 may be from 10 slm to 30 slm, but the embodiment is not limited thereto.

After step 150, an epitaxial layer 220 is formed on the annealed substrate 210A as shown in FIG. 2B to complete the manufacture of the epitaxial wafer (step 160).

Although not shown in FIG. 1, after performing operation 150, a pre-processing operation may be performed before operation 160 is performed. The reason for performing the pretreatment process is to remove organic contamination and native oxide existing on the substrate 210A after step 150 is performed.

FIG. 9 is an exemplary graph for explaining the preprocessing step and step 160 according to the embodiment.

9, in the case of the preprocessing process, after the substrate 210A having been subjected to the 150 step is loaded into the chamber, the temperature in the chamber (or the temperature in the chamber) during the fourth ramp up # (I.e., the temperature of the heat exchanger 210A). The fourth ramp up # 4 period is a period from the eleventh time t11 to the twelfth time t12 and the rate at which the temperature rises during this period may be 1 占 폚 / s to 20 占 폚 / s have.

Thereafter, a pretreatment process may be performed through hydrogen (H ₂ ) baking and hydrogen chloride (HCl) etching during the fourth period P4 at the fourth temperature T4. Here, the fourth temperature T4 may be in the range of 1110 ° C to 1160 ° C, and the fourth period P4 may be 20 seconds to 40 seconds as the period from the twelfth time t12 to the thirteenth time t13. Here, the hydrogen is used to remove the natural oxide film formed on the substrate 210A on which step 150 has been performed, and to clean the substrate 210A on which step 150 has been performed. In addition, the hydrogen chloride is used to remove surface defects of the substrate 210A on which step 150 is performed.

Thereafter, the temperature in the chamber (or the temperature of the substrate 210A) is lowered during the second ramp down # 2 period. The second ramp down # 2 period is a period from the thirteenth time t13 to the fourteenth time t14, and the rate at which the temperature falls during this period may be 1 占 폚 / s to 20 占 폚 / s have.

Thereafter, during the fifth period P5 at the fifth temperature T5, the epitaxial layer 220 is formed on the substrate 210A while supplying the reactant. Here, the fifth temperature T5 may be 1090 to 1140 占 폚, and the fifth period P5 may be 10 to 30 seconds as a period from the 14th time t14 to the 15th time t15. During a fifth period of time (P5), SiH _4, such as _{Si 2 H 6, DCS (dichlorosilane} ), TCS (tetrachlorosilane) gas and B ₂ H ₆ (PH _3), such as TCS, which, for the reactants for example such containing silicon When the dopant gas is introduced into the chamber, the epitaxial layer 220 may be formed by causing a chemical vapor deposition reaction on the surface of the substrate 210A, but the embodiment is not limited thereto.

Thereafter, the temperature in the chamber (or the temperature of the substrate 210A) is lowered during the third ramp down # 3 period. The third ramp down # 3 period is a period from the fifteenth time t15 to the sixteenth time t16, and the rate at which the temperature falls during this period may be 1 占 폚 / s to 20 占 폚 / s have.

In FIG. 9, the flow rate at which hydrogen (H ₂ ) is supplied from the eleventh time t11 to the sixteenth time t16 may be from 50 slm to 100 slm, and from the 14th time t14 to the 15th time t15 The flow rate at which the reactants are fed may be from 0.01 slm to 0.1 slm, although the embodiments are not limited thereto.

For example, the thickness of the epitaxial layer 220 formed on the substrate 210A may be between 1 μm and 10 μm, but the embodiment is not limited thereto.

Hereinafter, the embodiment and the comparative example will be described as follows with reference to FIGS. 10 to 13 attached as follows. In addition, the above-described FIGS. 4 to 6 as well as FIGS. 10 to 13 to be described later, when the 130th, 140th, 150th, and 160th steps shown in FIG. 1 are performed as shown in FIGS. 7 to 9, Can be the result.

The first comparative example is the case where an epitaxial wafer is produced without performing the RTA process and the annealing process.

The second comparative example (hereinafter, referred to as "second comparative example") is a case in which step 150 is omitted in the wafer manufacturing method 100 shown in FIG. In addition, in the case of the second comparative example, step 140 shown in FIG. 1 may be omitted.

The third comparative example (hereinafter, referred to as "third comparative example") is a case where steps 130 and 140 are omitted in the wafer manufacturing method 100 shown in FIG.

A fourth comparative example (hereinafter, referred to as "fourth comparative example") is a method in which a substrate having a high concentration of dopant, for example, boron having a concentration of 1E18 atoms / cm3 or more as a dopant 210) was used to manufacture an epitaxial wafer.

In order to increase the thermal stability of the oxide precipitate, the second comparative example may be subjected to an RTA process and the third comparative example may be subjected to an annealing process.

In the third comparative example, when only the annealing process is performed without performing the RTA process, the precipitate nuclei existing in a grown-in state grows and only a slight amount of additional nucleation is induced . Accordingly, during the process of forming the epitaxial layer 220 at an ultra-high temperature of, for example, 1100 ° C in step 160, the density of nuclei that are not decayed may be insufficient.

In addition, the COP-free substrate 210 generally has nonuniform distributions of population-in-point defects, i.e., vacancy defects and / or self-interstitial point defects, in the initial state. As a result, the BMD density uniformity is poor in the radial direction of the wafer. However, as in the third comparative example, when the annealing process is performed only without performing the RTA process, such nonuniformity of BMD density can not be overcome.

In the second comparative example, when only the RTA process is performed and the annealing process is not performed, the substrate 210 is rapidly heated to a high temperature to make a supersaturated vacancy region in the bulk of the substrate 210, By rapidly cooling it, it is possible to retain the supersaturated vacancy area created by suppressing the recombination of the point defects. If only the uniformity of the heat treatment is ensured, only the RTA process is performed so that the supersaturated region of the beacon is uniformly formed over the entire substrate 210, so that the nonuniformity of the BMD can be compensated. However, since the supersaturated region formed in the RTA process is not stable in the high-temperature heat treatment process such as the epitaxial process in Step 160 described later, most of the supersaturated region is eliminated during the epitaxial layer 220 formation process, 220, the effect of the RTA process disappears and the BMD density of the epitaxial wafer may be lowered.

As a result, when the wafer is fabricated by the first, second, or third comparative example using the substrate 210 including a dopant having a low doping concentration, the BMD density can be low and non-uniform.

On the other hand, in the case of the wafer fabrication method according to the embodiment, the RTA process is performed in operation 130 to create a supersaturated region and various complexes in the bulk of the substrate 210, and annealing process is performed in operation 150, The number of oxygen precipitation nuclei surviving the high-temperature heat treatment of 1100 占 폚 or more is increased as in the formation of the textured layer 220. Therefore, when the epitaxial layer 220 is formed in step 160, metal contamination can be gettered through oxygen precipitates grown from the precipitation nuclei surviving the device process using an epitaxial wafer.

10 is a graph comparing the BMD densities of the epitaxial wafers manufactured by the first to fourth comparative examples and the examples. 10A corresponds to the first comparative example, FIG. 10B corresponds to the second comparative example, FIG. 10C corresponds to the third comparative example, FIG. 10D corresponds to the second comparative example, 10 (e) corresponds to the fourth comparative example.

10 (d) manufactured by the example than the BMD density of the epitaxial wafer shown in Figs. 10 (a) to 10 (c) respectively prepared by the first, second and third comparative examples It can be seen that the BMD density of the wafer is higher. The BMD density shown in FIG. 10 (d) is found to be approximately equal to the BMD density of the epitaxial wafer shown in FIG. 10 (e) manufactured by the fourth comparative example. The BMD density of the wafer according to the embodiment may be 7E9 atoms / cm3 to 1.5E10 atoms / cm3.

11A to 11E are graphs comparing the uniformity of the BMD density of the epitaxial wafers manufactured by the first to fourth comparative examples and the embodiments. In each graph, the abscissa represents the distance in the radial direction of the wafer, "0" represents the center of the wafer, and the ordinate represents the BMD density.

11A to 11E, the uniformity of the BMD density of an epitaxial wafer produced by various methods is as follows. The uniformity of the BMD density can be obtained by the following equation (1).

Here, D represents the uniformity of the BMD density, MAX represents the maximum value of the BMD density, MIN represents the minimum value of the BMD density, and AVG represents the average value of the BMD density.

As shown in Fig. 11A, the uniformity of the BMD density of the epitaxial wafer produced by the first comparative example is 141.4%.

As shown in Fig. 11B, the uniformity of the BMD density of the epitaxial wafer produced by the second comparative example is 51.8%.

As shown in Fig. 11C, the uniformity of the BMD density of the epitaxial wafer produced by the third comparative example is 96.6%.

As shown in Fig. 11D, the uniformity of the BMD density of the epitaxial wafers manufactured by the embodiment is 10.4%.

As shown in Fig. 11D, the uniformity of the BMD density of the epitaxial wafer produced by the fourth comparative example is 1.8%.

As a result, the uniformity of the BMD density of the wafer according to the embodiment may be within 20%, preferably about 10%, for example, 10.4%, but the embodiment is not limited thereto.

12A to 12E are photographs of epi wafers manufactured by the first to fourth comparative examples and the embodiments. The black dot in each figure represents BMD.

12A to 12E are photographs taken by an optical microscope after etching an epitaxial wafer.

In the case of the epitaxial wafer produced by the first comparative example, the BMD is very small as shown in Fig. 12A. The epi wafer produced by the second comparative example using the RTA process without the annealing process is as shown in Fig. 12B, and the BMD is very small as in Fig. 12A. However, the epitaxial wafer produced by the third comparative example using the annealing process without the RTA process is as shown in Fig. 12C and has more BMD than the case of Fig. 12A or 12B.

The epi wafer manufactured by the embodiment using both the RTA process and the annealing process is as shown in FIG. 12D, and it can be seen that the BMD is much larger than those of FIGS. 12A to 12C. As described above, when an epitaxial wafer is produced by the embodiment, the BMD increases to an extent corresponding to the epitaxial wafer produced by the fourth comparative example shown in Fig. 12E.

13 is a graph showing the gettering ability of the epitaxial wafers manufactured by the first, third and fourth comparative examples and the embodiments. Figure 13 shows the gettering power of contaminated metals, especially nickel (Ni).

In the case of the epitaxial wafer produced by the first comparative example, as shown in Fig. 13A, the gettering force is very small, being between 50% and 60%. The epi wafer manufactured by the third comparative example using the annealing process without the RTA process is as shown in FIG. 13B, and the gettering power of nickel is improved up to 70% as compared with the case of FIG. 13A.

In this case, the epitaxial wafer according to the embodiment manufactured by using both the RTA process and the annealing process is as shown in FIG. 13C, and the gettering power of nickel is much more improved than that of FIG. 13A and FIG. have. Thus, when the epitaxial wafer is produced by the embodiment, the gettering force is improved to a degree corresponding to the epitaxial wafer produced by the fourth comparative example shown in Fig. 13D.

As a result, when an epitaxial wafer is manufactured using both the RTA process and the annealing process as in the embodiment, the BMD density of the epitaxial wafer is increased, the BMD density uniformity is improved, and the gettering force is improved .

Hereinafter, a wafer according to an embodiment (for example, an epitaxial wafer or a bulk wafer) will be described with reference to the accompanying drawings.

A bulk wafer (or a bulk wafer) according to an embodiment can be manufactured by performing steps 120 to 150 in the wafer manufacturing method 100 shown in FIG. 1 described above, but the embodiments are not limited thereto. That is, a bulk wafer (or a bare wafer) according to another embodiment may be manufactured by a method other than the wafer manufacturing method 100 shown in Fig.

In addition, the epitaxial wafer according to the embodiment can be manufactured by performing steps 120 through 160 in the wafer manufacturing method 100 shown in FIG. 1, but the embodiments are not limited thereto. That is, according to another embodiment, the epitaxial wafer may be manufactured by a method other than the wafer manufacturing method 100 shown in FIG.

The wafer according to an embodiment may include a dopant doped at a low concentration of 1E17 atoms / cm3 or less. Further, the minimum value of the dopant concentration in the wafer may be 1E13 atoms / cm3, but the embodiment is not limited thereto. Here, the conductive dopant may be a p-type dopant or an n-type dopant. For example, boron may be included in the wafer as a p-type dopant. That is, the wafer according to the embodiment can have a resistivity of 0.2 Ω · cm or more. In addition, the wafer according to the embodiment can have a resistivity of 100 Ω · cm or less.

In addition, the uniformity of the oxide precipitate density (BMD) of the wafer according to the embodiment may be within 20%, preferably about 10%, for example, 10.4% in radius echo. Here, the uniformity of the oxide precipitate density can be calculated by the above-mentioned equation (1). In particular, the wafer according to the embodiment may not have a void defect, that is, a COP. When the wafer has no COP, the wafer may have defect-free properties.

In general, BMD density is not uniform if the wafer does not have COPs. On the other hand, although the wafer according to the embodiment has no COP, the BMD density is uniform, for example, as illustrated in Fig. 11D. This is because it performs both the RTA process and the annealing process as shown in FIG.

In addition, the initial oxygen concentration included in the wafer according to the embodiment may be 5E17 atoms / cm3 to 7E17 atoms / cm3. Thus, since the initial oxygen concentration of the wafer is as large as 7E17 atoms / cm3, the mechanical strength of the wafer can be improved as illustrated in Fig. In addition, when the wafer has an initial oxygen concentration in the above-described range, defects are not formed in the device using the wafer, so that leakage defects are not caused and oxygen precipitates can be stably produced.

In addition, the wafer according to the embodiment may include a constituent element and a heterogeneous element. The heterogeneous elements are heterogeneous in their constituent elements. For example, the constituent element may comprise silicon, and the heterogeneous element may comprise nitrogen. Since the wafer according to the embodiment contains a hetero element, the strength of the wafer is improved as illustrated in Fig. 3, and the BMD density increases as illustrated in Fig. 4, so that the gettering force can be improved.

The BMD density of the wafer according to the embodiment may be 7E9 atoms / cm3 to 1.5E10 atoms / cm3, and the metal gathering force of the wafer may be 80% to 90%.

For example, the concentration of the hetero-element (e.g., nitrogen) may be 1E12 atoms / cm3 to 1E14 atoms / cm3, but the embodiment is not limited thereto. When the concentration of the hetero element is within this range, as shown in Fig. 4, the BMD density is large, but the strength enhancing effect is pronounced as exemplified in Fig. 3 and NILD does not occur as illustrated in Figs. 5 and 6B. Referring to FIG. 3, it can be seen that the wafer according to the embodiment has a sufficient strength to resist deformation and slip during the process by having a potential wave of 40 m or less.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (20)

Preparing a substrate including a lightly doped dopant of 1E17 atoms / cm3 or less, having a resistivity of 0.2 OMEGA .cm or more and not having a void defect;
Subjecting the prepared substrate to rapid thermal annealing;
Removing the nitride film from the rapid thermal annealed substrate;
Annealing the substrate; And
And forming an epitaxial layer on the annealed substrate. 2. The method of claim 1, wherein the substrate to be prepared has an initial oxygen concentration of 5E17 atoms / cm3 to 7E17 atoms / cm3. The method of claim 1, wherein the substrate
Constituent elements; And
And a heterogeneous element different from the constituent element. 4. The method of claim 3, wherein the constituent element comprises silicon, oxygen and boron,
Wherein the heterogeneous element comprises nitrogen,
Wherein the concentration of nitrogen is 1E12 atoms / cm3 to 1E14 atoms / cm3. 2. The method of claim 1, wherein the rapid thermal annealing is performed at a temperature in the range of 1100 DEG C to 1300 DEG C for 1 second to several tens of seconds. The method of claim 1, wherein the rapid thermal annealing is performed using a gas mixture of argon and a nitrogen-based compound. The method of claim 1, wherein the rapid thermal annealing is performed in a plurality of thermal processing steps,
Wherein the plurality of thermal processing steps are performed at different temperatures. 8. The method of claim 7, wherein the plurality of thermal processing steps
A rapid thermal processing step of a first step of rapidly heat-treating the substrate during a first period at a first temperature; And
And a rapid thermal processing step of performing a rapid thermal processing of the substrate during a second period at a second temperature different from the first temperature after the rapid thermal processing step of the first step. 9. The method of claim 8, wherein the first temperature is from 1100 DEG C to 1150 DEG C, the first period is from 1 second to 10 seconds,
Wherein the second temperature is between 1150 DEG C and 1200 DEG C, and the second period is between 1 second and 10 seconds. 10. The method of claim 9, wherein the rate of temperature rise from the first temperature to the second temperature is 20 占 폚 / s to 100 占 폚 / s. The method of claim 1, wherein removing the nitride layer comprises:
Wherein the rapid thermal annealed substrate is subjected to at least one of a chemical process or a mechanical process. 12. The method of claim 11, wherein the chemical process comprises using a cleaning liquid containing hydrofluoric acid. 12. The method of claim 11, wherein the mechanical process comprises polishing the rapidly heat-treated substrate. The method of claim 1, wherein the annealing is performed at a temperature in the range of 600 캜 to 950 캜 for 10 minutes to several hours. Board; And
An epitaxial layer disposed over the substrate,
The substrate
And a lightly doped dopant of 1E17 atoms / cm < 3 > or less,
Having a resistivity of 0.2 Ω · cm or more,
Without void defects,
A wafer having a uniformity of oxide precipitate density within 20% with a radius echo. Board; And
An epitaxial layer disposed over the substrate,
The substrate
And a lightly doped dopant of 1E17 atoms / cm < 3 > or less,
Having a resistivity of 0.2 Ω · cm or more,
Without void defects,
A wafer having an electric potential of 40 m or less. 17. The method of claim 15 or 16, wherein the wafer
Constituent elements; And
And a heterogeneous heterogeneous element. 18. The method of claim 17, wherein the conductive dopant is a p-type dopant,
The initial oxygen concentration included in the wafer is 5E17 atoms / cm3 to 7E17 atoms / cm3,
Wherein the constituent element comprises silicon, oxygen and boron,
Wherein the heterogeneous element comprises nitrogen,
Wherein the concentration of nitrogen is 1E12 atoms / cm3 to 1E14 atoms / cm3. The wafer according to claim 15, wherein the oxide precipitate density is 7E9 atoms / cm3 to 1.5E10 atoms / cm3. 17. The wafer of claim 15 or 16, wherein the wafer has a metal gettering power of 80% to 90%.

Images