KR20180127152A - Display driver circuit for pre-empasis operation - Google Patents

Abstract

The present invention relates to a display driving circuit for a pre-emphasis operation. According to an embodiment of the present invention, the display driving circuit comprises: a comparator for comparing first pixel data with second pixel data among a plurality of pixel data, each corresponding to a plurality of pixels connected to a data line, respectively; a pre-emphasis controller for calculating an offset based on a comparison result of the comparator and gamma segment points, which are adjacent to the second pixel data, from among a plurality of gamma segment points used as a reference for dividing the pixel data; a calculator for calculating pre-emphasis pixel data based on the second pixel data and the offset; and an output circuit for transmitting a pre-emphasis gray scale voltage corresponding to the pre-emphasis pixel data and a target gray scale voltage corresponding to the second pixel data to a display panel through the data line.

Description

[0001] DISPLAY DRIVER CIRCUIT FOR PRE-EMPASIS OPERATION FOR PRE-

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display driving circuit, and more particularly to a display driving circuit for pre-emphasis operation.

The display panel may include gate lines arranged in the row direction, data lines arranged in the column direction, and pixels located at the intersections of the gate lines and the data lines. The data driver may provide an image signal (i.e., a gray scale voltage) to the pixels through the data lines in the column direction. When arbitrary image data is provided, the data driver outputs the gradation voltage to the pixels so that the image is displayed on the display panel.

As the size and resolution of the display panel increase, the load resistance connected to the output of the data driver and the capacitance of the load capacitor increase, correspondingly the target voltage of the image signal increases. The slew rate of the amplifier of the data driver may be lowered due to the increase of the load resistance and the load capacity. Pre-emphasis operation can be used to increase the slew rate of the amplifier of the data driver. A pre-emphasis operation considering the change and level of the gradation voltage is required.

SUMMARY OF THE INVENTION The present invention provides a display driving circuit for a pre-emphasis operation.

A display driving circuit according to an embodiment of the present invention includes a comparator for comparing first pixel data and second pixel data among a plurality of pixel data corresponding to a plurality of pixels connected to a data line, A pre-emphasis controller for calculating an offset based on a comparison result of the comparator and gamma segment points adjacent to the second pixel data among the plurality of gamma segment points to be divided, a pre-emphasis controller for calculating an offset based on the second pixel data and the offset, A calculator for calculating the emphasis pixel data, and an output circuit for transmitting the pre-emphasis gradation voltage corresponding to the pre-emphasis pixel data and the target gradation voltage corresponding to the second pixel data to the display panel through the data line have.

A display driving circuit according to another embodiment of the present invention includes a comparator for comparing first pixel data and second pixel data output respectively to a first pixel and a second pixel through a data line, A register that stores a plurality of line segment points that are reference points for dividing a plurality of pixels connected to each other via a data line into a plurality of line segments; a register for calculating an offset based on the comparison result of the comparator, A pre-emphasis controller for adjusting an interval in which the offset is output to the second pixel based on the line segment points adjacent to the second pixel among the plurality of pixel data, and a second emphasis controller for adjusting the second pixel data and the offset according to the section adjusted by the pre- And outputting the data to the second pixel through the data line.

A display driving circuit according to another embodiment of the present invention includes a comparator for comparing first pixel data and second pixel data output respectively with a first pixel and a second pixel via a data line, A pre-emphasis controller for calculating an offset, a calculator for calculating pre-emphasis pixel data based on the second pixel data and the offset, a pre-emphasis gradation voltage corresponding to pre-emphasis pixel data, and a target corresponding to the second pixel data And an output circuit for outputting the pre-emphasis gradation voltage and the target gradation voltage to the display panel through the data line. The range of the pre-emphasis gradation voltage may be a range of the target gradation voltage And an extended gradation voltage range other than the range of the target gradation voltage.

The display driving circuit according to the embodiment of the present invention can adjust the pre-emphasis level of the digital method in consideration of the non-linearity of the gamma curve.

The display driving circuit according to the embodiment of the present invention can adjust the pre-emphasis period in consideration of the distance between the data driver and the data line.

The display driving circuit according to the embodiment of the present invention can generate the gray scale voltage for the pre-emphasis operation.

1 is a block diagram illustrating an exemplary display device according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the display device of FIG. 1 in detail.
3 is a simplified circuit diagram of the data lines and pixels connected to the output circuit and the output circuit shown in FIG.
4 is a timing diagram illustrating an exemplary operation of the amplifier shown in FIG.
5 is a detailed block diagram of the data driver shown in FIG.
6 is an exemplary diagram illustrating a gamma curve of pixel data versus gradation voltage.
7 is an exemplary illustration of a gamma curve that is linearized by gamma segment points in accordance with an embodiment of the invention.
FIG. 8 is a flowchart illustrating an exemplary operation of the pre-emphasis controller shown in FIG. 5 to generate an offset.
FIG. 9 and FIG. 10 are views illustrating an exemplary operation of the pre-emphasis controller shown in FIG. 5 according to an embodiment of the present invention to set a pre-emphasis interval according to a line segment point.
FIG. 11 and FIG. 12 illustrate operations of the pre-emphasis controller shown in FIG. 5 according to another embodiment of the present invention to set a pre-emphasis period according to a line segment point.
FIG. 13 is a diagram illustrating an exemplary operation in which the pre-emphasis controller shown in FIG. 5 sets a pre-emphasis level according to a line segment point.
FIG. 14 is a flowchart exemplarily showing an operation of the pre-emphasis controller shown in FIG. 5 to set a pre-emphasis period according to an activation line.
FIG. 15 is a block diagram showing the pre-emphasis controller and the third register shown in FIG. 5 in more detail.
Figs. 16 and 17 are views showing an example of the packet configuration of the serial data of Fig.
18 is a flowchart illustrating an exemplary operation of the pre-emphasis controller to process setting data according to an embodiment of the present invention.
FIG. 19 is a flowchart illustrating an exemplary operation of processing the setting data by the pre-emphasis controller according to the embodiment of the present invention. FIG.
FIGS. 20 and 21 are circuit diagrams illustrating the gradation voltage generator of FIG. 5 by way of example.
FIG. 22 and FIG. 23 are circuit diagrams illustrating the gradation voltage generator of FIG. 5 as an example.
FIG. 24 and FIG. 25 are circuit diagrams illustrating the gradation voltage generator of FIG. 5 by way of example.
26 is a block diagram illustrating an exemplary display device according to another embodiment of the present invention.
FIG. 27 is a block diagram illustrating an exemplary display device according to another embodiment of the present invention. Referring to FIG.

In the following, embodiments of the present invention will be described in detail and in detail so that those skilled in the art can easily carry out the present invention.

1 is a block diagram illustrating an exemplary display device according to an embodiment of the present invention. Referring to FIG. 1, a display device 100 may include a display driver circuit 110 and a display panel 120. The display driving circuit may be referred to as a display driver IC (DDI).

The display driving circuit 110 may include a pre-emphasis controller 111. The pre-emphasis controller 111 can generate pre-emphasis pixel data based on a lookup table (LUT). The lookup table may include setting data for increasing the resolution of an image to be displayed on the display panel 120. [ The setting data may be a value for the pre-emphasis operation. The pre-emphasis controller 111 can drive the display panel 120 based on the pre-emphasis pixel data.

The display panel 120 may display an image on a frame-by-frame basis. The display panel 120 may be implemented as a liquid crystal display (LCD), an LED (light emitting diode) display, an OLED (organic LED) display, an AMOLED (active matrix OLED) display, a flexible display, Other types of flat panel displays may be implemented.

According to the embodiment of the present invention, the display drive circuit 110 can receive the setting data and the pixel data in the form of serial data. The setting data included in the lookup table may be changed according to the specification or performance of the display panel 120. [ Accordingly, the pre-emphasis pixel data can be generated in accordance with the specification or the performance of the display panel 120. Hereinafter, the detailed configuration of the display device 100 will be described.

FIG. 2 is a block diagram showing the display device of FIG. 1 in detail. 2, a display device 1000 includes a display panel 1100, a timing controller 1200, a gate driver 1300, a data driver 1400, and a voltage generator generator, 1500). The timing controller 1200, the gate driver 1300, and the data driver 1400 are circuits for driving the display panel 1100, respectively. Particularly, the data driver 1400 may be the display driving circuit 110 of FIG. 1, and the circuit including the timing controller 1200 and the data driver 1400 may be the display driving circuit 110 of FIG.

The display panel 1100 includes a plurality of gate lines G1 to Gx arranged in the row direction, a plurality of data lines D1 to Dy arranged in the column direction, a plurality of gate lines G1 to Gx, And may include a plurality of pixels disposed at the intersections of the plurality of data lines D1 to Dy. x and y are natural numbers. As shown, the pixel PX may include a thin film transistor TFT and a liquid crystal capacitor Clc and a storage capacitor Cst connected to the drain electrode of the thin film transistor TFT. When any gate line is selected, the thin film transistor (TFT) of the pixel connected to the selected gate line can be turned on. Thereafter, the gradation voltage corresponding to the pixel data may be applied to the liquid crystal capacitor Clc and the storage capacitor Cst. The display panel 1100 may be the display panel 120 of FIG.

The timing controller 1200 may receive control signals from an external device (e.g., a host, an application processor (AP), etc.). The control signals may include, for example, a clock CLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a data enable signal DE. The timing controller 1200 controls the gate driver 1300 and the data driver 1400 using the clock CLK, the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the data enable signal DE, The first and second control signals CTRL1 and CTRL2 can be generated.

The timing controller 1200 may receive serial data including setting data and image data. More specifically, the timing controller 1200 can receive the setting data and the image data through the same data terminal (not shown). The setting data can be stored in the register 1430. The configuration data may include information for controlling pre-emphasis operation. The setting data may be transmitted to the timing controller 1200 via the serial interface receiving the image data.

The timing controller 1200 may transmit configuration data and pixel data to the data driver 1400 in a similar fashion to the received serial data. The timing controller 1200 can transmit the received setting data to the data driver 1400 as it is. The timing controller 1200 may convert the image data to pixel data and then transmit the pixel data to the data driver 1400. [ Depending on the specifications of the data driver 1400 and the display panel 1100, the image data may or may not be converted. In either case, serial data can be transferred from the timing controller 1200 to the data driver 1400 as shown.

The gate driver 1300 may drive the plurality of gate lines G1 to Gx of the display panel 1100 according to the first control signal CTRL1. The gate driver 1300 can sequentially select the plurality of gate lines G1 to Gx by applying the gate-on voltage GON. The gate-off voltage GOFF may be applied to the unselected gate lines. The gradation voltage by the data driver 1400 may be applied to the activated pixels connected to the selected gate line.

The data driver 1400 can receive the serial data including the setting data and the pixel data from the timing controller 1200. [ In an embodiment, the data driver 1400 may receive serial data from an external device other than the timing controller 1200. [ Similar to the timing controller 1200, the data driver 1400 can receive the setting data and the pixel data through the same data terminal (not shown). That is, the configuration data may be transferred to the register 1430 of the data driver 1400 via the serial interface receiving the pixel data.

The data driver 1400 may drive the plurality of data lines D1 to Dy of the display panel 1100 according to the second control signal CTRL2. The data driver 1400 may include a digital circuit 1410 and an output circuit 1440. The digital circuitry 1410 can receive and store pixel data from the timing controller 1200. For example, the pixel data may be RGB data.

According to an embodiment of the present invention, the digital circuit 1410 may include a pre-emphasis controller 1420 and a register 1430. The pre-emphasis controller 1420 can generate the pre-emphasis pixel data based on the pixel data and the look-up table (LUT) stored in the register 1430. [ The pre-emphasis controller 1420 can provide the pre-emphasis pixel data to the output circuit 1440 and control the pre-emphasis operation for adjusting the slew rate of the gradation voltage applied to the pixel PX.

The output circuit 1440 can output the gradation voltages to the pixels through the plurality of data lines D1 to Dy. For example, the output circuit 1440 may output, as pixels, a target gray-scale voltage corresponding to the pixel data and a pre-emphasis gradation voltage corresponding to the pre-emphasis pixel data. The target gradation voltage represents the gradation voltage corresponding to the pixel data transmitted to the data driver 1400. [

The voltage generator 1500 can supply power to the display panel 1100, the timing controller 1200, the gate driver 1300, and the data driver 1400. The voltage generator 1500 generates the gate-on voltage GON, the gate-off voltage GOFF, the first power source AVDD1, the second power source AVSS, the third power source AVDD2, and the common voltage VCOM Can be generated. The gate-on voltage GON and the gate-off voltage GOFF may be supplied to the gate driver 1300, the common voltage VCOM may be commonly supplied to the pixels PX, The first power source AVDD1, the second power source AVSS and the third power source AVDD2 may be supplied to the data driver 1400. [

In an embodiment, the timing controller 1200, the gate driver 1300, the data driver 1400, and the voltage generator 1500 may be implemented on one integrated circuit (IC). In another embodiment, timing controller 1200, gate driver 1300, data driver 1400, and voltage generator 1500 may each be implemented as discrete integrated circuits.

3 is a simplified circuit diagram of the data lines and pixels connected to the output circuit and the output circuit shown in FIG. Output circuit 1440 may include at least one amplifier 1443. For example, amplifier 1443 may be an operational amplifier. Amplifier 1443 may drive the pixels through the data lines. The amplifier 1443 can receive and output the input voltage VIN through the non-inverting terminal. The input voltage VIN is the voltage supplied to the amplifier to output the gradation voltage to the pixel. The output voltage VOUT may be output to the pixel via the data line. The output voltage VOUT may be provided to the inverting terminal of the amplifier 1443. [ Amplifier 1443 may operate in a manner similar to a buffer.

3, the load of amplifier 1443 may be modeled as resistors R and capacitors C. [ The values of R and C can be determined by the width, the length, the size of the thin film transistor (TFT), and the like of the data line. The amplifier 1443 must drive both a pixel located at a close distance and a pixel located at a distance (e.g., an F node). In particular, when the amplifier 1443 drives a pixel located a long distance, a pre-emphasis operation may be required.

4 is a timing diagram illustrating an exemplary operation of the amplifier shown in FIG. Fig. 4 will be described with reference to Figs. 2 and 3. Fig. 4, the horizontal axis represents time and the vertical axis represents voltage. In Fig. 4, the input voltage VIN, the output voltage VOUT, and the voltage VF of the F node are shown.

In the embodiment, the voltage VF of the F node must reach the target gradation voltage VTARGET within the horizontal period (H1, T1 to T3 time points). The horizontal period H1 can be determined by the specification of the display panel 1100, the power consumption, the operation speed, and the like. If the voltage VF at the F node exceeds the target gradation voltage VTARGET or does not reach the target gradation voltage VTARGET, the image quality of the display panel 1100 may decrease. In order to drive the voltage VF of the F-node to the target gradation voltage VTARGET within the horizontal period H1, the data driver 1400 may increase the input voltage over the target voltage during the initial period of the horizontal period H1 ( Over driving). More specifically, the input voltage is VTARGET + VPE during the preemphasis interval (TPE, T1 to T2) and VTARGET after the preemphasis interval. The VTARGET + VPE gradation voltage corresponds to the pre-emphasis pixel data, and the VTARGET gradation voltage corresponds to the pixel data transmitted to the data driver 1400. [ VPE is the pre-emphasis level.

According to an embodiment of the present invention, the data driver 1400 may appropriately adjust the pre-emphasis level VPE and the pre-emphasis period TPE. It is important to appropriately adjust the pre-emphasis level VPE and the pre-emphasis period TPE according to the position of each pixel PX and the target gradation voltage VTARGET. Hereinafter, the structure and pre-emphasis operation of the data driver 1400 will be described in detail.

5 is a detailed block diagram of the data driver shown in FIG. The data driver 1400 may include a digital circuit 1410, an output circuit 1440, and a gray scale voltage generator 1450.

The digital circuit 1410 includes a line buffer 1411, a comparator 1412, a calculator 1413, first and second registers 1414 and 1415, a multiplexer 1416, A pre-emphasis controller 1420, and a third register 1430.

The line buffer 1411 may store the second pixel data DATA (n). When the line buffer 1411 receives the second pixel data DATA (n), the data previously stored in the line buffer 1411 may be the first pixel data DATA (n-1). The second pixel data DATA (n) may be updated each time pixel data is transmitted to the data driver 1400. [ Where n may represent the order or frequency of pixel data provided to the digital circuit 1410 (i.e., nth pixel data). For example, the line buffer 1411 may be a single port static random access memory (SPSRAM) or a shift register.

The comparator 1412 can compare the first pixel data DATA (n-1) and the second pixel data DATA (n). The first pixel data DATA (n-1) is referred to as previous pixel data DATA (n-1) and the second pixel data DATA (n) (DATA (n)). The first pixel to be supplied with the first pixel data DATA (n-1) refers to the previous pixel, and the second pixel to which the second pixel data (DATA (n)) is supplied refers to the current pixel. The previous pixel data DATA (n-1) and the current pixel data DATA (n) may be output through the one data line Dk to the previous pixel and the current pixel, respectively. The comparator 1412 may provide the comparison result COMP to the pre-emphasis controller 1420. [

The calculator 1413 can calculate the pre-emphasis pixel data PE_DATA based on the current pixel data DATA (n) and the offset. The offset is a value calculated by the pre-emphasis controller 1420. The calculator 1413 may add an offset to the current pixel data DATA (n) or subtract the offset from the current pixel data DATA (n). For example, the calculator 1413 may include an adder and a subtractor.

The size of the pre-emphasis pixel data PE_DATA may be larger than the size of the current pixel data DATA (n). Illustratively, if the current pixel data DATA (n) is 10 bits in size, the pre-emphasis pixel data PE_DATA may be 11 bits in size (1 bit extension). The number of bits of the pre-emphasis pixel data PE_DATA may be larger than the number of bits of the current pixel data DATA (n). The pre-emphasis pixel data PE_DATA may include a value obtained by adding an offset to the maximum current pixel data DATA (n) through a bit extension or a value missing an offset from the minimum current pixel data DATA (n) . All of the above numerical values are exemplary.

The first register 1414 can store the pre-emphasis pixel data PE_DATA and the second register 1415 can store the current pixel data DATA (n). Each of the first and second registers 1414 and 1415 may be implemented as an SPSRAM or a shift register. Due to the bit extension described above, the size of the first register 1414 may be larger than the size of the second register 1415.

The multiplexer 1416 can select either the first register data RD1 or the second register data RD2 according to the preemphasis interval control signal TPE_CTRL of the preemphasis controller 1420. [ When the first register data RD1 is selected, the output circuit 1440 can output the pre-emphasis gradation voltage corresponding to the pre-emphasis pixel data to the current pixel. When the second register data RD2 is selected, the output circuit 1440 can output the target gradation voltage corresponding to the current pixel data (DATA (n)) to the current pixel.

The pre-emphasis controller 1420 can calculate the offset based on the comparison result COMP and the look-up table (LUT) stored in the third register 1430. The pre-emphasis controller 1420 can generate the pre-emphasis period control signal TPE_CTRL in consideration of the distance between the output circuit 1440 and the pixel. The pre-emphasis controller 1420 can operate in a digital manner. The detailed operation and configuration of the pre-emphasis controller 1420 will be described later with reference to FIG. 6 to FIG.

The third register 1430 may store a look-up table (LUT) containing information necessary for the pre-emphasis controller 1420 to generate the offset. The third register 1430 may be a volatile memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM) or the like, a NOR flash memory, a NAND flash memory, a ferroelectric random access volatile memory such as a memory, a phase change random access memory (PRAM), a thyristor random access memory (TRAM), a resistive random access memory (ReRAM), a magnetic random access memory (MRAM), and the like. Unlike what is shown, the third register 1430 may be included in the pre-emphasis controller 1420.

The output circuit 1440 may include a level shifter 1441, a digital to analog converter 1442, and an amplifier 1443.

The level shifter 1441 can convert voltage levels of the first register data RD1 and the second register data RD2. The first register data RD1 and the second register data RD2 are provided to an output circuit 1440 which is an analog circuit in the digital circuit 1410. [ The level shifter 1441 outputs the voltage level of the first register data RD1 and the voltage level of the second register data RD2 according to the operating environment of the output circuit 1440 (for example, drive voltage, transistor type, Lt; / RTI >

The digital-to-analog converter 1442 receives the first register data RD1 and the second register data RD2 and can select one of the plurality of gradation voltages VG. The digital to analog converter 1442 may select one of the gradation voltages higher than the gradation voltage corresponding to the maximum value of the pixel data and the gradation voltage lower than the gradation voltage corresponding to the minimum value of the pixel data.

The amplifier 1443 is supplied with the input voltage VIN (that is, the gradation voltage) from the digital-analog converter 1442 and can output the input voltage VIN to the kth data line Dk. The kth data line Dk may be any one of the plurality of data lines D1 to Dy of FIG. 1 (k is a natural number). Although only one of the output circuits 1440 including the amplifier 1443 and the amplifier 1443 is shown in FIG. 5, the amplifier 1443 and the output circuit 1440 are connected in accordance with the number of the plurality of data lines D1 to Dy. ) Can be determined.

The gradation voltage generator 1450 generates a plurality of gradation voltages VG corresponding to the gradation represented by the pixel data. For example, when the pixel data is 10 bits in size, the gradation voltage generator 1450 can generate 1024 (= 2 ¹⁰ ) plurality of gradation voltages VG. Further, the gradation voltage generator 1450 may further generate gradation voltages higher than the gradation voltages corresponding to the maximum value of the pixel data for the pre-emphasis operation, and may generate gradations lower than the gradation voltage corresponding to the minimum value of the pixel data Voltages. ≪ / RTI >

6 is an exemplary diagram illustrating a gamma curve of pixel data versus gradation voltage. The horizontal axis represents the pixel data and the vertical axis represents the gray scale voltage. The amount of change of the pixel data and the amount of change of the gradation voltage are not exactly proportional to each other. As shown, the gamma curve may be non-linear. Therefore, the pre-emphasis controller 1420 must determine the pre-emphasis level VPE (see FIG. 4) in consideration of the non-linearity of the gamma curve. To this end, information on the gamma curve may be stored in the third register 1430.

However, if the gradation voltage levels for all pixel data values are stored in the third register 1430, the amount of information stored in the third register 1430 is too large. For example, if the pixel data is 10 bits in size, data of 2 ¹⁰ X 2 ¹⁰ size must be stored in the third register 1430. This scheme is inefficient because the amount of information stored in the third register 1430 is proportional to the square of the pixel data size. According to an embodiment of the present invention, the third register 1430 may store a plurality of gamma segment points (G_SEGP1 to G_SEGP9), which is a reference for dividing pixel data without storing information on all gray scale voltages corresponding to pixel data, Lt; / RTI >

FIG. 6 shows a plurality of gamma segment points (G_SEGP1 to G_SEGP9) and a plurality of gamma segments (G_SEG1 to G_SEG8). The plurality of gamma segments G_SEG1 to G_SEG8 may be determined according to the positions of the plurality of gamma segment points G_SEGP1 to G_SEGP9. Pixel data located between the first gamma segment point (G_SEGP1) and the second gamma segment point (G_SEGP2) may be included in the first gamma segment (G_SEG1). Pixel data located between the other gamma segments (G_SEG2 to G_SEG8) can also be segmented in a similar manner.

The partial gamma curve corresponding to each of the plurality of gamma segments G_SEG1 to G_SEG8 may be linear as compared to the entire gamma curve. Therefore, assuming that the gamma curve corresponding to the gamma segment is linear, the third register 1430 stores a plurality of slope values SL1 to SL8 instead of storing information on all the gradation voltages corresponding to the pixel data Can be stored. The plurality of slope values SL1 to SL8 may be respective ratios of the plurality of gradation voltage ranges for the plurality of gamma segments G_SEG1 to G_SEG8. As shown, the first gradation voltage range of the plurality of gradation voltage ranges means between the eighth reference voltage (VGMA8) to the ninth reference voltage (VGMA9). The second to ninth gradation voltage ranges may also be determined in a manner similar to the first gradation voltage range.

In an embodiment, the first slope value SL1 may be the gamma curve slope at the midpoint between the first gamma segment point G_SEGP1 and the second gamma segment point G_SEGP2. In another embodiment, the first slope value SL1 is a first reference voltage VGMA1 and a second reference voltage VGMA2 for the difference between the first gamma segment point G_SEGP1 and the second gamma segment point G_SEGP2, Lt; / RTI > Other slope values SL2 to SL8 may be determined in a similar manner.

Referring to FIG. 6, a plurality of gamma segment points (G_SEGP1 to G_SEGP9) may correspond to a plurality of reference voltages (VGMA1 to VGMA9), respectively. The plurality of reference voltages VGMA1 to VGMA9 may be used as a reference voltage in the gradation voltage generator 1450 described above. The result of linearizing the gamma curve of FIG. 6 is shown in FIG.

7 is an exemplary illustration of a gamma curve that is linearized by gamma segment points in accordance with an embodiment of the invention. The gamma curve in Fig. 6 is shown by a solid line, and the gamma curve in Fig. 7 is shown by a dotted line. The number of the plurality of gamma segment points (G_SEGP1 to G_SEGP9) is not limited to that shown in Fig. 6 and Fig. Also, the position of the plurality of gamma segment points (G_SEGP1 to G_SEGP9) may be changed by setting data provided by the host or the AP. In addition, the plurality of reference voltages VGMA1 to VGMA9 may be changed according to the positions of the plurality of gamma segment points G_SEGP1 to G_SEGP9.

FIG. 8 is a flowchart illustrating an exemplary operation of the pre-emphasis controller shown in FIG. 5 to generate an offset. This flowchart can illustratively illustrate the operation of the pre-emphasis controller shown in FIG. 5 to determine the offset. Fig. 8 will be described with reference to Figs. 2 and 5 to 7. Fig.

In step S110, the pre-emphasis controller 1420 can receive the comparison result COMP of the previous pixel data DATA (n-1) by the comparator 1412 and the current pixel data DATA (n) . The comparator 1412 compares the previous pixel data DATA (n-1), i.e., the first pixel data, output to the first pixel by the output circuit 1440 via the k-th data line Dk with the k- (N), i.e., the second pixel data, to be output to the second pixel via the data line Dk.

In step S120, the pre-emphasis controller 1420 can perform steps S131 to S134 if the current pixel data DATA (n) is greater than the previous pixel data (DATA (n-1)). The pre-emphasis controller 1420 can perform steps S141 to S144 if the current pixel data DATA (n) is smaller than the previous pixel data (DATA (n-1)). The pre-emphasis controller 1420 can perform step S160 if the current pixel data DATA (n) is equal to the previous pixel data DATA (n-1).

In step S131, the pre-emphasis controller 1420 can determine the gamma segment points adjacent to the current pixel data DATA (n) among the plurality of gamma segment points G_SEGP1 to G_SEGP9. The pre-emphasis controller 1420 can determine the current gamma segment in which the current pixel data DATA (n) among the plurality of gamma segments G_SEG1 to G_SEG8 is located.

In step S132, the pre-emphasis controller 1420 can check the weight of the current gamma segment. The weight may indicate the degree of emphasizing the difference between the target gradation voltage corresponding to the current pixel data DATA (n) and the previous gradation voltage corresponding to the previous pixel data DATA (n-1). For example, the weight may be a value based on the difference between the target gradation voltage and the previous gradation voltage. More specifically, the weight may be a ratio of the gradation voltage (see VPE in Fig. 4) corresponding to the offset to the difference between the target gradation voltage and the previous gradation voltage.

In step S133, the pre-emphasis controller 1420 can calculate an offset to be added to the current pixel data DATA (n). First, the pre-emphasis controller 1420 can calculate the difference between the target gradation voltage and the previous gradation voltage using at least one of the comparison result in step S110 and the plurality of slope values SL1 to SL8. In the embodiment, if the current pixel data DATA (n) and the previous pixel data DATA (n-1) belong to the same gamma segment, only one slope value of the corresponding gamma segment may be used. In another embodiment, if the gamma segment to which the current pixel data DATA (n) belongs is different from the gamma segment to which the previous pixel data DATA (n-1) belongs, at least two tilt values may be used.

The pre-emphasis controller 1420 can generate an offset using at least one of the difference and the plurality of weights determined in step S133. In the embodiment, the gamma segment of the previous pixel data DATA (n-1) is the fourth gamma segment G_SEG4 and the gamma segment of the current pixel data DATA (n) is the seventh gamma segment G_SEG7 I suppose.

The pre-emphasis controller 1420 uses the fourth to seventh inclination values SL4 to SL7 to compare the target gradation voltage corresponding to the current pixel data DATA (n) and the previous pixel data DATA (n-1) The difference between the previous gradation voltages corresponding to the previous gradation voltages can be calculated. The pre-emphasis controller 1420 can calculate the offset using the calculated difference and the weight value of the seventh gamma segment G_SEG7. The current pixel data DATA (n) is included in the seventh gamma segment G_SEG7 and the value obtained by adding an offset to the current pixel data DATA (n) may be included in the seventh gamma segment G_SEG7. However, a value obtained by adding an offset to the current pixel data DATA (n) may be included in the eighth gamma segment G_SEG8. Accordingly, the pre-emphasis controller 1420 calculates or calculates the offset by referring to the slope value SL8 of the adjacent gamma segment (the eighth gamma segment G_SEG8) as well as the slope value SL7 of the seventh gamma segment G_SEG7 Can be generated. Illustratively, the number of adjacent gamma segments may be one or more.

The pre-emphasis controller 1420 can calculate the offset based on the comparison result of the gamma segment points adjacent to the current pixel data and the comparator 1412 in steps S131 to S133. More specifically, the pre-emphasis controller 1420 may calculate the offset using at least one of the plurality of slope values and the plurality of weights.

In step S134, the pre-emphasis controller 1420 can set the calculator 1413 so that the offset calculated in step S133 is added to the current pixel data (DATA (n)) according to the comparison result of the comparator 1412. [ The pre-emphasis controller 1420 can activate the adder of the calculator 1413. In another embodiment, the pre-emphasis controller 1420 may set the most significant bit of the offset to 1 or 0. For example, if the most significant bit is 1, the calculator 1413 can perform an addition operation, and if the most significant bit is 0, the calculator 1413 can perform a subtraction operation. However, the above-described numerical values are illustrative and do not limit the scope of the present invention.

Steps S141 to S143 may be substantially similar to steps S131 to S133. Since the current pixel data DATA (n) is smaller than the previous pixel data DATA (n-1) in step S144, the pre-emphasis controller 1420 determines that the offset calculated in step S143 is the current pixel data DATA n) of the calculator 1413 or the offset.

In step S150, the pre-emphasis controller 1420 may provide the calculated offset to the calculator 1413 through steps S131 to S134 or S141 to S144. The calculator 1413 can calculate the pre-emphasis pixel data based on the offset and the current pixel data. The calculator 1413 can calculate the pre-emphasis pixel data by adding an offset to the current pixel data if the current pixel data is larger than the previous pixel data. The calculator 1413 can calculate the pre-emphasis pixel data by subtracting the offset from the current pixel data if the current pixel data is smaller than the previous pixel data.

In step S160, the current pixel data DATA (n) is equal to the previous pixel data DATA (n-1). In this case, since the pre-emphasis operation is not required, the pre-emphasis controller 1420 can set the offset to zero. That is, the calculator 1413 can directly calculate the current pixel data DATA (n) as pre-emphasis pixel data.

FIG. 9 and FIG. 10 illustrate operations of the pre-emphasis controller shown in FIG. 5 according to an embodiment of the present invention to set a pre-emphasis interval according to a line segment point. 9 and 10 will be described with reference to Figs. 2 and 5. Fig. 9 and 10, a plurality of data lines D1 to Dy intersecting a plurality of activation lines AL1 to ALx, a plurality of activation lines AL1 to ALx, And a data driver 1400 for driving the data lines D1 to Dy. Each of the plurality of activation lines AL1 to ALx may correspond to pixels connected to the gate line selected by the gate driver 1300 of FIG.

The gate driver 1300 of FIG. 1 can sequentially select the plurality of gate lines G1 to Gx. Here, it is assumed that the data driver 1400 in FIG. 9 sequentially transmits pixel data from the nearest activation line to the far activation line, and the data driver 1400 in FIG. 10 sequentially It is assumed that data is transmitted. The first activation line AL1, i.e., the pixels connected to the first gate line G1, may be closest to the output circuit 1440 (see Fig. 5) of the data driver 1400, ALx, i.e., pixels connected to the xth gate line Gx) may be farthest from the output circuit 1440. [

The pre-emphasis controller 1420 can adjust the pre-emphasis period TPE according to the position of the activation line. The pre-emphasis controller 1420 of FIG. 9 may increase the pre-emphasis period TPE for the current pixel according to the distance between the current pixel and the output circuit 1440. On the other hand, the pre-emphasis controller 1420 of FIG. 10 may reduce the pre-emphasis period TPE for the current pixel according to the distance between the current pixel and the output circuit 1440.

More specifically, the plurality of activation lines AL1 to ALx may be divided into a plurality of line segments L_SEG1 to L_SEG5. In view of the pixels, the plurality of line segment points (L_SEGP1 to L_SEGP6) divides a plurality of pixels including the previous pixel and the current pixel and connected through one data line into a plurality of line segments (L_SEG1 to L_SEG5) It can be a standard. A plurality of line segments L_SEG1 to L_SEG5 can be determined according to the positions of the plurality of line segment points L_SEGP1 to L_SEGP6. The number of the plurality of line segment points (L_SEGP1 to L_SEGP6) and the number of the plurality of line segments (L_SEG1 to L_SEG5) are all exemplary.

The pre-emphasis controller 1420 calculates the offset based on the comparison result of the comparator 1412 and calculates the offset (or the offset) based on the line segment points adjacent to the current pixel among the plurality of line segment points (L_SEGP1 to L_SEGP6) (I.e., the pre-emphasis period TPE) in which the current pixel is outputting the pre-emphasis pixel data in which the offset is added to or subtracted from the current pixel data).

More specifically, the pre-emphasis controller 1420 can set the narrowest pre-emphasis period TPE to the activation line belonging to the first line segment L_SEG1, It is possible to set the widest pre-emphasis period TPE. That is, the pre-emphasis controller 1420 can set the pre-emphasis period TPE in proportion to the distance between the current pixel and the output circuit 1440. Thereafter, the output circuit 1440 can output the current pixel data and the offset to the current pixel according to the section adjusted by the pre-emphasis controller 1420. [

9 and 10, the sizes of the plurality of line segments L_SEG1 to L_SEG5 are shown to be the same, but the scope of the present invention is not limited thereto. Specific embodiments thereof are described in Figs. 11 and 12. Fig.

FIG. 11 and FIG. 12 illustrate operations of the pre-emphasis controller shown in FIG. 5 according to another embodiment of the present invention to set a pre-emphasis period according to a line segment point. It is assumed that the data driver 1400 of FIG. 11 sequentially transmits pixel data from the nearest activation line to the far activation line, and the data driver 1400 of FIG. 12 sequentially outputs pixel data from the far activation line to the nearest activation line .

Referring to FIG. 11, the first line segment L_SEG1 is set larger than the second and third line segments L_SEG2 and L_SEG3. The pre-emphasis controller 1420 may set the same pre-emphasis period TPE for the activation lines belonging to the first line segment L_SEG1. The pre-emphasis controller 1420 can set a pre-emphasis period TPE that gradually increases from the activation line adjacent to the second line segment point L_SEGP2 to the x-th activation line ALx.

Conversely, referring to FIG. 12, the third line segment L_SEG3 is set larger than the first and second line segments L_SEG1 and L_SEG2. The pre-emphasis controller 1420 may set the same pre-emphasis period (TPE) for the activation lines belonging to the third line segment L_SEG3. The pre-emphasis controller 1420 may set a pre-emphasis period TPE that gradually decreases from the activation line adjacent to the third line segment point L_SEGP3 to the first activation line AL1.

In summary, the pre-emphasis controller 1420 can set the pre-emphasis period (TPE) constant for some activation lines among the plurality of activation lines AL1 to ALx, and for the remaining activation lines, It is possible to adjust the pre-emphasis period TPE according to the distance between the output terminal 1440 and the output circuit 1440.

FIG. 13 is a diagram illustrating an exemplary operation in which the pre-emphasis controller shown in FIG. 5 sets a pre-emphasis level according to a line segment point. 9, the pre-emphasis controller 1420 can set the pre-emphasis period TPE in proportion to the distance between the current pixel and the output circuit 1440. [ 13, the pre-emphasis controller 1420 can set the pre-emphasis level VPE in proportion to the distance between the current pixel and the output circuit 1440 instead of increasing the pre-emphasis period TPE. The pre-emphasis controller 1420 can adjust the pre-emphasis level VPE based on the line segment points adjacent to the current pixel.

FIG. 14 is a flowchart exemplarily showing an operation of the pre-emphasis controller shown in FIG. 5 to set a pre-emphasis period according to an activation line. Fig. 14 will be described with reference to Figs. 2, 5, and 9. Fig.

In step S210, the pre-emphasis controller 1420 may count the number of times the data line is driven by the output circuit 1440. [ For example, the pre-emphasis controller 1420 may count the number of times the data enable signal DE is activated. The data enable signal DE can be synchronized with the pixel data transmitted to the data driver 1400 and indicate which part of the serial data is pixel data.

In step S220, the pre-emphasis controller 1420 may determine line segment points adjacent to the current pixel based on the counting result. The pre-emphasis controller 1420 can determine how far the current pixel or activation line is from the output circuit 1440. For example, the larger the counting result, the greater the distance between the current pixel and the output circuit 1440.

In step S230, the pre-emphasis controller 1420 generates pre-emphasis pixel data emphasizing the comparison result of the comparator 1412, and based on the line segment points adjacent to the current pixel, the pre- It is possible to adjust the section output to the pixel. The pre-emphasis controller 1420 can transmit the pre-emphasis period control signal TPE_CTRL to the multiplexer 1416. Thereafter, the multiplexer 1416 can select either the current pixel data or the pre-emphasis pixel data according to the section adjusted by the pre-emphasis controller 1420. [

FIG. 15 is a block diagram showing the pre-emphasis controller and the third register shown in FIG. 5 in more detail. Fig. 15 will be described with reference to Figs. 5 to 14. Fig. First, a third register 1430 for storing a lookup table (LUT) will be described first.

The third register 1430 may store a plurality of gamma segment points (G_SEGP1 to G_SEGP9) that divide the range of pixel data according to the nonlinearity of the gradation voltage for the pixel data. The third register 1430 includes a plurality of weight values for a plurality of gamma segments G_SEG1 to G_SEG8 located between a plurality of gamma segment points G_SEGP1 to G_SEGP9 and a plurality of slope values SL1 to SL8, Lt; / RTI >

The third register 1430 can provide the pre-emphasis level determination circuit 1422 with information on the gamma segment to which the current pixel data belongs by referring to the gamma segment points adjacent to the current pixel data. For example, the third register 1430 may provide a weight (WEIGHT) and a slope value (SL_VALUE) of the gamma segment to which the current pixel data belongs to the pre-emphasis level determination circuit 1422. [ The slope value SL_VALUE may include a plurality of slope values SL1 to SL8.

The third register 1430 includes a plurality of line segment points (hereinafter referred to as " L ") that are used as a reference for dividing the plurality of pixels including the previous pixel and the current pixel and connected through one data line into the plurality of line segments L_SEG1 to L_SEG5 L_SEGP1 to L_SEGP6). The third register 1430 may store a plurality of pre-emphasis interval values for a plurality of line segments L_SEG1 to L_SEG5 located between the plurality of line segment points L_SEGP1 to L_SEGP6. Each of the plurality of pre-emphasis interval values may indicate how much the pre-emphasis interval is set for the pixel. In an embodiment, the plurality of pre-emphasis interval values may be values calculated by the pre-emphasis controller 1420 based on the reference pre-emphasis interval value. In another embodiment, the plurality of pre-emphasis interval values may be externally provided values.

The third register 1430 can provide the pre-emphasis period determination circuit 1424 with information on the line segment to which the current pixel belongs by referring to the line segment points adjacent to the current pixel. For example, the third register 1430 may provide a pre-emphasis interval value (TPE_VALUE) of the line segment to which the current pixel belongs to the pre-emphasis interval determination circuit 1424.

The third register 1430 may store information for the pre-emphasis operation. To this end, the third register 1430 may receive the gamma segment point set signal SET_G_SEGP, the weight set signal SET_W_VALUE, the line segment point set signal SET_L_SEGP, and the reference pre- have. The reference pre-emphasis interval setting signal SET_REF_TPE may include a reference pre-emphasis interval value used for calculating the plurality of pre-emphasis interval values described above. Unlike the illustrated example, the third register 1430 may receive a plurality of pre-emphasis interval values instead of the reference pre-emphasis interval setting signal SET_REF_TPE. In the embodiment, the external device generates a third register (a first register) by using a gamma segment point setting signal (SET_G_SEGP), a weight setting signal (SET_W_VALUE), a segment point setting signal (SET_L_SEGP), and a reference pre-emphasis interval setting signal (SET_REF_TPE) (E.g., a lookup table) stored in the storage unit 1430 can be changed.

In an embodiment, the look-up table comprises a plurality of gamma segment points (G_SEGP1 to G_SEGP9), a plurality of weights, a plurality of slope values (SL1 to SL8), a plurality of line segment points (L_SEGP1 to L_SEGP6) And may be configured to include pre-emphasis interval values. The lookup table may be stored in the third register 1430.

The pre-emphasis controller 1420 includes a pre-emphasis level determination circuit 1422, a line counter 1423, and a pre-emphasis period determination circuit 1424 ).

The pre-emphasis level determination circuit 1422 performs steps S131 to S134, S141 to S144, or S 160 in FIG. 8 based on the comparison result COMP, the weight WEIGHT, and the slope value SL_VALUE can do. The pre-emphasis level determination circuit 1422 can provide an offset to the calculator 1413.

The line counter 1423 can count the number of times the data line is driven by the output circuit 1440. To this end, the line counter 1423 may receive the data enable signal DE. The line counter 1423 can quantify how far the current pixel is from the output circuit 1440. The line counter 1423 may provide the counting result (C_RESULT) to the pre-emphasis period determining circuit 1424. [

The pre-emphasis interval determination circuit 1424 can receive the pre-emphasis interval value (TPE_VALUE) of the line segment to which the current pixel belongs based on the counting result (C_RESULT). The pre-emphasis interval determination circuit 1424 can determine the line segment points adjacent to the current pixel and the line segment to which the current pixel belongs based on the counting result (C_RESULT), and based on the pre-emphasis interval value (TPE_VALUE) And may provide the pre-emphasis period control signal TPE_CTRL to the multiplexer 1416. [

Figs. 16 and 17 are views showing an example of the packet configuration of the serial data of Fig. 16 and 17 will be described with reference to Fig. Referring to FIG. 16, a serial data packet may be transmitted to the display device 1000 through a serial interface. The serial data packet may include configuration data and image data. The configuration data may be transferred to the third register 1430 via a serial interface through which image data or pixel data is transmitted. The setting data may be first transmitted to the display device 1000 rather than the image data.

The setting data includes a plurality of gamma segment points (G_SEGP1 to G_SEGP_9), a plurality of weights, a plurality of slope values (SL1 to SL8), a plurality of line segment points (L_SEGP1 to L_SEGP6), and a reference pre- Information about the same pre-emphasis operation may be included. The setting data can be updated by an external device. In the embodiment, the serial data packet shown in Fig. 16 may be a serial data packet transmitted from the timing controller 1200 to the data driver 1400. Fig.

The serial data packet of FIG. 17 represents an exemplary packet transmitted over an intra interface. Referring to FIG. 17, a serial data packet includes a start of line (SOL) field, a configuration data field, a pixel data field, a wait field, and a horizontal blank period ; HBP) field.

The line start field indicates the beginning of each line of the image frame. The line start field may be a horizontal blank field for the previous line of the current image frame or a field for distinction between the current image frame and the vertical blank interval between the previous image frame.

Similar to the setting data field of FIG. 16, the configuration data field may include information on gamma segment points, weight information on segments, information on line segment points, and information on reference pre-emphasis interval values.

Pixel data to be displayed in the active line unit of the display panel is written in the pixel data field. The wait field is an interval allocated for securing the time for the data driver 1400 to receive and store pixel data. The horizontal blank field is an interval allocated to secure time for the data driver 1400 to drive the display panel based on the pixel data (RGB). In an embodiment, the serial data packet shown in FIG. 17 may be a serial pixel data packet that is sent from the timing controller 1200 to the data driver 1400.

18 is a flowchart illustrating an exemplary operation of the pre-emphasis controller to process setting data according to an embodiment of the present invention. The setting data may include information on a plurality of gamma segment points (G_SEGP1 to G_SEGP9), a plurality of weights, and a pre-emphasis level such as a plurality of slope values (SL1 to SL8).

In step S310, the pre-emphasis controller 1420 can receive the serial data setting data through the serial interface. In step S320, the pre-emphasis controller 1420 may divide the pixel data into a plurality of gamma segments G_SEG1 to G_SEG8 based on the plurality of gamma segment points G_SEGP1 to G_SEGP9. In step S330, the pre-emphasis controller 1420 can set the respective weight values and the respective slope values for the plurality of gamma segments G_SEG1 to G_SEG8.

FIG. 19 is a flowchart illustrating an exemplary operation of processing the setting data by the pre-emphasis controller according to the embodiment of the present invention. FIG. The setting data may include information on a pre-emphasis interval such as a plurality of line segment points (L_SEGP1 to L_SEGP6) and a reference pre-emphasis interval value.

In step S410, the pre-emphasis controller 1420 can receive the serial data setting data via the serial interface. In step S420, the pre-emphasis controller 1420 divides a plurality of pixels connected through one data line into a plurality of line segments L_SEG1 to L_SEG5 based on the plurality of line segment points L_SEGP1 to L_SEGP6 . In step S430, the pre-emphasis controller 1420 can set the respective pre-emphasis interval values for the plurality of line segments L_SEG1 to L_SEG5.

FIGS. 20 and 21 are circuit diagrams illustrating the gradation voltage generator of FIG. 5 by way of example. 20 and 21 will be described with reference to Figs. 2 and 5. Fig. In the case where the display panel 1100 is an LCD, deterioration may occur in the liquid crystal layer if an electric field is applied only to one direction of the liquid crystal layer of the pixel. In order to prevent this, the direction of the electric field applied to the liquid crystal layer can be periodically reversed. In order to invert the direction of the electric field, the gradation voltage generator 1450 may generate a positive gray scale voltage and a negative gray scale voltage. Fig. 20 relates to positive gradation voltage generation, and Fig. 21 relates to negative gradation voltage generation. The gradation voltage generator 1450 may generate the pre-emphasis gradation voltage corresponding to the target gradation voltage corresponding to the current pixel data and the pre-emphasis pixel data.

20 and 21, the gradation voltage generator 1450 includes first through third positive resistance strings 1451_1 through 1451_3, first through third negative resistance strings 1452_1 through 1452_3, To 9th gradation voltage amplifiers 1453_1 to 1453_9, and first to ninth negative gradation voltage amplifiers 1454_1 to 1454_9.

The first positive resistance string 1451_1 can generate the first to 1024th gradation voltages (VGP_1 to VGP_1024). The number of the first to 1024th gradation voltages (VGP_1 to VGP_1024) is determined by the number of bits of the pixel data. For example, if the pixel data is 10 bits in size, the first positive resistance string 1451_1 may include 1024 (= 2 ¹⁰ ) gradation voltages and resistors for generating gradation voltages. That is, the number of gradation voltages and the number of resistances shown are merely illustrative.

The range of the first to 1024th gradation voltages (VGP_1 to VGP_1024) may be the range of the target gradation voltage corresponding to the above-described current pixel data. The range of the pre-emphasis gradation voltage may include a range of the target gradation voltage and an extended gradation voltage range other than the target gradation voltage range. To this end, the gradation voltage generator 1450 may include second and third positive resistance strings 1451_2 - 1451_3.

The second positive resistance string 1451_2 is connected between the first positive voltage (VGP_1, the output of the first positive voltage amplifier 1453_1) and the first power source AVDD1 and the first positive voltage VGP_1) and lower than the first power source (AVDD1). The third positive resistance string 1451_3 is connected between the 1024th positive tone voltage (VGP_1024, the output of the ninth positive tone voltage amplifier 1453_9) and the second power source AVSS, and the 1024th negative tone voltage It is possible to generate a pre-emphasis gradation voltage lower than the second power source (AVSS) and higher than the second power source (AVSS). Each of the second and third amounts of resistance strings 1451_2 to 1451_3 may generate gradation voltages included in the extended gradation voltage range.

Each of the first through ninth gradation voltage amplifiers 1453_1 through 1453_9 can receive and amplify each of the positive reference voltages VGMA1_P through VGMA9_P. The first amount of gradation voltage amplifier 1453_1 can generate the maximum gradation voltage in the range of the target gradation voltage and the ninth amount of gradation voltage amplifier 1453_9 can generate the minimum gradation voltage in the range of the target gradation voltage have. The positive reference voltages VGMA1_P to VGMA9_P may correspond to the reference voltages VGMA1 to VGMA9 described above in FIG. The number of the first to ninth gradation voltage amplifiers 1453_1 to 1453_9 may be determined according to the number of the plurality of gamma segment points G_SEGP1 to G_SEGP9.

The first to third negative resistance strings 1452_1 to 1452_3 and the first to ninth negative tone voltage amplifiers 1454_1 to 1454_9 are connected to the first to third positive resistance strings 1451_1 to 1451_3, 1 to the ninth gradation voltage amplifiers 1453_1 to 1453_9, respectively. However, the first through third resistive strings 1452_1 through 1452_3 and the first through ninth negative tone voltage amplifiers 1454_1 through 1454_9 are connected to the second power source AVSS and the third power source AVDD2 . The absolute value of the first power source AVDD1 and the absolute value of the third power source AVDD2 may be equal to or different from each other, unlike the first power source AVDD1, which is a positive power source, and the third power source AVDD2 is a negative power source. have.

FIG. 22 and FIG. 23 are circuit diagrams illustrating the gradation voltage generator of FIG. 5 as an example. Fig. 22 relates to positive gradation voltage generation, and Fig. 23 relates to negative gradation voltage generation. The gradation voltage generator 2450 can also generate the target gradation voltage corresponding to the current pixel data and the pre-emphasis gradation voltage corresponding to the pre-emphasis pixel data. The difference between the gradation voltage generator 2450 and the positive gradation voltage generator 1450 of FIGS. 20 and 21 will be mainly described.

Referring to FIGS. 22 and 23, the gradation voltage generator 2450 includes first through third positive resistance strings 2451_1 through 2451_3, first through third negative resistance strings 2452_1 through 2452_3, To 9th gradation voltage amplifiers 2453_1 to 2453_9, and first to ninth negative gradation voltage amplifiers 2454_1 to 2454_9. The first to third resistive strings 2451_1 to 2451_3 and the first to third negative resistive strings 2452_1 to 2452_3 correspond to the first to third positive resistance strings 1451_1 To 1451_3 and the first to third negative resistor strings 1452_1 to 1452_3, respectively.

The second positive resistance string 2451_2 may be connected to the output of the first positive tone voltage amplifier 2453_1 instead of being connected to the first power source AVDD1. The third positive resistance string 2451_3 may be connected to the output of the ninth positive polarity voltage amplifier 2453_9 instead of being connected to the second power source AVSS. The second negative resistance string 2452_2 may be connected to the output of the first negative tone voltage amplifier 2453_1 instead of being connected to the third power source AVDD2. The third negative resistance string 2452_3 may be connected to the output of the ninth negative tone voltage amplifier 2454_9 instead of being connected to the second power supply AVSS.

That is, the first amount of the gradation voltage amplifier 2453_1 can generate the maximum gradation voltage in the range of the pre-emphasis gradation voltage, and the ninth amount of the gradation voltage amplifier 2453_9 can generate the minimum of the pre-emphasis gradation voltage range The gradation voltage can be generated. The second and third positive resistance strings 1451_2 and 1451_3 and the second and third negative resistance strings 1452_2 and 1452_3 in the gradation voltage generator 1450 in order to adjust the range of the pre- ) Can be adjusted. In contrast, in the gradation voltage generator 2450, the positive reference voltages VGAM1_P to VGAM9_P and the negative reference voltages VGAM1_N to VGAM9_N may be adjusted instead of adjusting the number of resistors.

FIG. 24 and FIG. 25 are circuit diagrams illustrating the gradation voltage generator of FIG. 5 by way of example. Fig. 24 relates to positive gradation voltage generation, and Fig. 25 relates to negative gradation voltage generation. The gradation voltage generator 3450 can also generate the target gradation voltage corresponding to the current pixel data and the pre-emphasis gradation voltage corresponding to the pre-emphasis pixel data. The difference between the gradation voltage generator 3450 and the gradation voltage generator 1450 of FIGS. 20 and 21 will be mainly described.

Referring to FIGS. 24 and 25, the gradation voltage generator 3450 includes first through third positive resistance strings 3451_1 through 3451_3, first through third negative resistance strings 3452_1 through 3452_3, To 9th gradation voltage amplifiers 3453_1 to 3453_9, and first to ninth negative gradation voltage amplifiers 3454_1 to 3454_9. The first to third positive resistance strings 3451_1 to 3451_3 and the first to third negative resistance strings 3452_1 to 3452_3 are connected to the first to third positive resistance strings 1451_1 to 1452_3 of FIGS. To 1451_3 and the first to third negative resistor strings 1452_1 to 1452_3, respectively.

The gradation voltage generator 3450 generates the tenth and eleventh positive tone voltage generators 3453_10 and 3453_11 and the tenth and eleventh negative tone voltage generators 3454_10 and 3454_11 as compared with the gradation voltage generator 1450 . The tenth and eleventh positive tone voltage generators 3453_10 and 3453_11 and the tenth and eleventh negative tone voltage generators 3454_10 and 3454_11 can generate the gray scale voltages included in the extended tone voltage range, respectively.

The second positive resistance string 3451_2 may be connected to the output of the tenth positive polarity voltage amplifier 3453_10 instead of being connected to the first power source AVDD1. The third positive resistance string 3451_3 may be connected to the output of the eleventh positive tone voltage amplifier 3453_11 instead of being connected to the second power source AVSS. The second negative resistor string 3452_2 may be connected to the output of the tenth negative tone voltage amplifier 3454_10 instead of being connected to the third power source AVDD2. The third negative resistance string 3452_3 may be connected to the output of the eleventh negative tone voltage amplifier 3454_11 instead of being connected to the second power source AVSS.

In order to adjust the range of the pre-emphasis gradation voltage, the positive reference voltages VGAM10_P and VGAM11_P and the negative reference voltages VGAM10_N and VGAM11_N may be adjusted. Further, in order to adjust the range of the target gradation voltage, the positive reference voltages VGAM1_P to VGAM9_P and the negative reference voltages VGAM1_N to VGAM9_N may be adjusted. That is, the gradation voltage generator 3450 can adjust the range of the target gradation voltage and the range of the pre-emphasis gradation voltage by adjusting the reference voltages VGAM1_P to VGAM11_P and VGAM1_N to VGAM11_N.

26 is a block diagram illustrating an exemplary display device according to another embodiment of the present invention. Referring to FIG. 26, the display device 4000 may include a display panel 4100, a timing controller 4200, a gate driver 4300, a data driver 4400, and a voltage generator 4500. The display panel 4100, the gate driver 4300 and the voltage generator 4500 may perform substantially the same functions as the display panel 1100, the gate driver 1300, and the voltage generator 1500 of FIG. 1 . Hereinafter, differences between the display device 4000 and the display device 1000 of FIG. 1 will be mainly described.

Referring to FIG. 26, the timing controller 4200 may include a line buffer 4411, a comparator 4412, a calculator 4413, a pre-emphasis controller 4420, and a third register 4430. The data driver 4400 may include a digital circuit 4410 and an output circuit 4440 and the digital circuit 4410 may include first and second registers 4414 and 4415 and a multiplexer 4416 have.

The line buffer 4411, the comparator 4412, the calculator 4413, the first and second registers 4414 and 4415, the multiplexer 4416, the preemphasis controller 4420, and the third register 4430 The line buffer 1411, the comparator 1412, the calculator 1413, the first and second registers 1414 and 1415, the multiplexer 1416, the preemphasis controller 1420, and the third register 1430 And can perform substantially the same function. That is, other circuits connected to the pre-emphasis controller 4420 and the pre-emphasis controller 4420 according to the embodiment of the present invention may be implemented in either the timing controller 4200 or the data driver 4400.

FIG. 27 is a block diagram illustrating an exemplary display device according to another embodiment of the present invention. Referring to FIG. 27, the display device 5000 may include a display panel 5100, a timing controller 5200, a gate driver 5300, a data driver 5400, and a voltage generator 5500. [ The display panel 5100, the gate driver 5300 and the voltage generator 5500 may perform substantially the same functions as the display panel 1100, the gate driver 1300, and the voltage generator 1500 of FIG. 1 . Hereinafter, differences between the display device 5000 and the display device 1000 of FIG. 1 will be mainly described.

The timing controller 5200 can receive setting data via a dedicated terminal (not shown) different from a data terminal (not shown) for receiving image data. That is, the setting data and the image data can be transmitted to the timing controller 5200 separately. Similarly, data driver 5400 may receive configuration data via a dedicated terminal (not shown) other than a data terminal (not shown) that receives pixel data. That is, the setting data and the pixel data may be transmitted to the data driver 5400 separately. As described above, the setting data includes a plurality of gamma segment points (G_SEGP1 to G_SEGP_9), a plurality of weights, a plurality of slope values (SL1 to SL8), a plurality of line segment points (L_SEGP1 to L_SEGP6), and a reference pre- Information about the pre-emphasis operation such as the interval value may be included.

The above description is a concrete example for carrying out the present invention. The present invention includes not only the above-described embodiments, but also embodiments that can be simply modified or easily changed. In addition, the present invention includes techniques that can be easily modified by using the above-described embodiments.

1000: display device;
1100: display panel;
1200: timing controller;
1300: gate driver;
1400: data driver;
1420: pre-emphasis controller;
1500: voltage generator;

Claims (10)

A comparator for comparing first pixel data and second pixel data among a plurality of pixel data corresponding to a plurality of pixels connected to a data line;
A pre-emphasis controller for calculating an offset based on a comparison result of the comparator and gamma segment points adjacent to the second pixel data among a plurality of gamma segment points serving as a reference for dividing the plurality of pixel data;
A calculator for calculating pre-emphasis pixel data based on the second pixel data and the offset; And
And an output circuit for transmitting a pre-emphasis gradation voltage corresponding to the pre-emphasis pixel data and a target gradation voltage corresponding to the second pixel data to the display panel through the data line. The method according to claim 1,
Wherein the pre-emphasis controller comprises a display driving circuit for calculating the offset using at least one of a plurality of slope values which are respective ratios of a plurality of gradation voltage ranges for a plurality of gamma segments between the plurality of gamma segment points, . 3. The method of claim 2,
Wherein the pre-emphasis controller calculates the offset using at least one of a plurality of weights for the plurality of gamma segments. The method of claim 3,
Wherein a weight for a gamma segment to which the second pixel data belongs is a value based on a difference between the target gradation voltage and a gradation voltage corresponding to the first pixel data. 3. The method of claim 2,
And a register for storing a lookup table including the plurality of gamma segment points, the plurality of weights, and the plurality of slope values. 6. The method of claim 5,
Wherein the plurality of gamma segment points, the plurality of weights, and the plurality of tilt values are transmitted to the register through a serial interface through which the first pixel data and the second pixel data are transmitted. 6. The method of claim 5,
The plurality of gamma segment points, the plurality of weights, and the plurality of tilt values are transmitted to the register through a dedicated terminal different from a data terminal receiving the first pixel data and the second pixel data Display drive circuit. The method according to claim 1,
And the pre-emphasis controller sets the most significant bit of the offset according to the comparison result. The method according to claim 1,
The calculator comprising:
Adding the offset to the second pixel data to calculate the pre-emphasis pixel data if the second pixel data is greater than the first pixel data,
Calculating the pre-emphasis pixel data by subtracting the offset from the second pixel data if the second pixel data is smaller than the first pixel data, and
And calculates the second pixel data as the pre-emphasis pixel data if the second pixel data and the first pixel data are the same. The method according to claim 1,
Wherein the number of bits of the pre-emphasis pixel data is larger than the number of bits of the second pixel data.

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