KR20180115198A - Display panel, display device, and operation method of display device - Google Patents

Abstract

According to an embodiment of the present invention, a display device having reduced power consumption comprises: a plurality of pixels connected to each of the plurality of gate lines and each of the first and second data lines; a gate driver activating the gate lines; a switch driver connected to the first and second data lines and responded to the first and second switch signals for providing a data signal to either the first or second data line; and a source driver generating the data signal and activating the first and second switch signals so that the data signal is provided to a second pixel having the same pixel color as a previously activated first pixel among the pixels.

Description

DISPLAY PANEL, DISPLAY DEVICE, AND OPERATION METHOD OF DISPLAY DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display panel, a display device, and a method of operating the display device.

The display device includes gate lines, data lines, and a plurality of pixels. Each of the plurality of pixels is connected to the gate lines and the data lines, respectively. The display device includes a gate driving circuit for controlling the gate lines and a data driving circuit for controlling the data lines, respectively. The gate drive circuit provides a gate signal to each of the plurality of gate lines, the data drive circuit provides a data signal to each of the plurality of data lines, and each pixel displays image information based on the received signal.

In recent years, as the resolution of a display device increases, power consumption for driving the display device increases. In particular, the power consumption of the display device is a large part of the power consumption of small electronic devices (e.g., smart phones, tablet PCs, IOT devices, etc.). Accordingly, various methods for reducing the power consumption of such display devices have been studied.

It is an object of the present invention to provide a method of operating a display panel, a display device, and a display device having reduced power consumption.

A display device according to an embodiment of the present invention includes a plurality of pixels connected to each of a plurality of gate lines and each of first and second data lines, a gate driver for activating the plurality of gate lines, A switch driver coupled to the first and second data lines and providing a data signal to one of the first and second data lines in response to the first and second switch signals; And a source driver for activating one of the first and second switch signals so that the data signal is provided to a second pixel having the same pixel color as the previously activated first pixel.

A method of operating a display device according to an embodiment of the present invention includes the steps of activating a first one of a plurality of gate lines, generating data in a first pixel connected to the first gate line in an active period of the first gate line And providing a data signal to a second pixel that is subsequently coupled to the first gate line, activating a second one of the plurality of gate lines, and activating a second one of the plurality of gate lines, Providing a data signal to a third pixel coupled to the second gate line and then providing a data signal to a fourth pixel coupled to the second gate line. The third pixel is connected to the same data line as the second pixel and has the same pixel color.

A display panel according to an embodiment of the present invention includes a plurality of pixels connected to a plurality of gate lines and a plurality of data lines, respectively, and a plurality of gate lines and a plurality of data lines, And a peripheral circuit for activating the second pixel. The first and second pixels are connected to different gate lines, connected to the same data line, and have the same pixel color.

A source driver according to an embodiment of the present invention includes a gamma voltage generating unit configured to generate a gamma voltage corresponding to a pixel color of an external pixel, and a source driving unit configured to generate a data signal to be provided to the external pixel based on the gamma voltage, Wherein the source driver generates a data signal at least twice in succession based on a gamma voltage corresponding to at least the same pixel color.

According to the embodiment of the present invention, the display device can drive the gate lines and the switch signals in a non-sequential manner. Accordingly, the power consumed for charging / discharging the capacitor in the display panel and the consumed power due to the gamma voltage change can be reduced. Therefore, a method of operating a display panel, a display device, and a display device having reduced power consumption is provided.

1 is a block diagram showing a display device according to an embodiment of the present invention.
2 is a circuit diagram illustrating an exemplary structure of the pixel of Fig.
FIG. 3 is a block diagram illustrating an exemplary display device of FIG. 1;
4A to 7B are timing diagrams for explaining a driving method of a display device according to an embodiment of the present invention.
8A and 8B are timing diagrams showing the operation of the source drivers of FIG.
9 is a flowchart showing an operation method of the display apparatus of FIG.
10 is a block diagram showing a display device according to an embodiment of the present invention.
11A and 11B are diagrams for explaining the operation of the display device of Fig.
12A-12D are exemplary diagrams illustrating exemplary pixel placement or color filter placement in accordance with an embodiment of the present invention.
13 is a diagram illustrating various pixel arrangements in accordance with an embodiment of the present invention.
14 is a block diagram illustrating an exemplary source driver according to an embodiment of the present invention.
FIG. 15 is a block diagram illustrating an exemplary touch display device to which the display device according to the present invention is applied.

In the following, embodiments of the present invention will be described in detail and in detail so that those skilled in the art can easily carry out the present invention.

1 is a block diagram showing a display device according to an embodiment of the present invention. Referring to FIG. 1, a display device 100 may include a pixel array 110, a gate driver 120, a switch driver 130, a source driver 140, and a controller 150. Illustratively, the display device 100 may be a small electronic device such as a portable communication terminal, a PDA (Personal Digital Assistant), a PMP (Portable Media Player), a smart phone, or a wearable device or a large electronic device such as a high- Products and the like.

For example, the functional blocks shown in FIG. 1 are for distinguishing the functions of the respective components, and the technical idea of the present invention is not limited to the components shown in FIG. For example, each of pixel array 110, gate driver 120, switch driver 130, source driver 140, and controller 150 may be implemented as separate semiconductor die, chip, or module. Or some or all of pixel array 110, gate driver 120, switch driver 130, source driver 140 and controller 150 may be implemented as a single semiconductor die, chip, or module.

Alternatively, the pixel array 110, the gate driver 120, and the switch driver 130 may be formed on the same semiconductor substrate and included in one display panel. At this time, the gate driver 120 and the switch driver 130 may be provided as peripheral circuits of the display panel.

Or source driver 140 and controller 150 may be implemented as a single semiconductor die, chip, package, or module. Or the gate driver 120, the switch driver 130, the source driver 140 and the controller 150 are implemented as a semiconductor die, a chip, a package, or a module to control the display device 100 Can be provided.

The pixel array 110 may include a plurality of pixels PIX. Each of the plurality of pixels PIX is connected to the gate line GL and the data line DL and is configured to display corresponding image information in response to a voltage or a signal of the gate line GL and the data line DL . Each of the plurality of pixels PIX may be divided into a plurality of groups according to a color to be displayed. For example, each of the plurality of pixels PIX may be configured to display one of the primary colors. At this time, the main color may include at least one of red, green, blue, and white. Alternatively, the primary color may further include various colors such as magenta, cyan, yellow, and the like. Hereinafter, the color displayed by the pixel is referred to as "pixel color ". The pixel color may be determined according to the color filter included in each pixel element or each pixel.

Illustratively, the pixel array 110 may include an organic light emitting display panel (OLED), a liquid crystal display panel (LCD), an electrophoretic display panel, an electrowetting display panel an electrowetting display panel, and the like. However, the pixel array 110 according to the present invention is not limited thereto, and the pixel array 110 according to the present invention can be implemented with the above-described display panels or other display panels. Illustratively, the display device 100 including a liquid crystal display panel (LCD) may further include a polarizer (not shown), a backlight unit (not shown), and the like.

The gate driver 120 may be configured to control the plurality of gate lines GL under the control of the controller 150. [ For example, the gate driver 120 may be configured to provide a gate signal to each of the plurality of gate lines GL, under the control of the controller 150. Illustratively, the gate signal may indicate a signal for activating pixels PIX connected to the corresponding gate line.

The switch driver 130 may be connected to a plurality of pixels PIX through a plurality of data lines DL. The switch driver 130 may be configured to provide the data signal from the source driver 140 to the corresponding data line DL under the control of the controller 150. [ For example, the switch driver 130 may be implemented as a 2: 1, 3: 1, or n: 1 demultiplexer. The switch driver 130 performs a switch operation to provide the data signal DATA provided from the source driver 140 to any one of the data lines DL in response to the switch signal SW from the controller 150 .

The source driver 140 may generate a data signal DATA to be provided to the plurality of pixels PIX under the control of the controller 150. [ The generated data signal DATA may be provided to the plurality of pixels PIX through the switch driver 130. [

The controller 150 may be configured to control the gate driver 120, the switch driver 130, and the source driver 140 so that each of the plurality of pixels PIX displays the corresponding image information. The controller 150 is a timing controller that generates various control signals (e.g., a vertical synchronization signal, a horizontal synchronization signal, and the like) for controlling the gate driver 120, the switch driver 130, (TCON). The controller 150 may be included in the source driver 140 and the source driver 140 may control the operation of the controller 150 ) Of the control signal).

Illustratively, the display device 100 can select an active pixel among the plurality of pixels PIX by controlling the gate line GL and the switch signal SW. At this time, the active pixel refers to a pixel that displays image information in response to a data signal from the source driver 140. That is, in order to activate a specific pixel (referred to as a first pixel), the display device 100 activates a gate line GL connected to the first pixel, It is possible to control the switch signal SW so that the data signal DATA is provided. The data signal DATA from the source driver 140 can be provided to the first pixel through the control of the gate line GL and the switch signal SW. The display device 100 may repeat the above-described operation so that each of the plurality of pixels PIX may be configured to display image information for a corresponding data signal DATA.

The display device 100 according to the embodiment of the present invention can control the gate line GL and the switch signal SW so that power consumption required to display the image information can be minimized. For example, the display device 100 can activate the gate line GL such that pixels having the same pixel color are displayed consecutively or adjacent to each other. Alternatively, the display device 100 can activate the switch signal SW so that the pixels having the same pixel color are displayed consecutively or adjacently. At this time, pixels of the same color may be pixels connected to the same data line.

The display device 100 controls the gate line GL or the switch signal SW so that the pixels having the same pixel color are displayed consecutively or adjacent to each other to charge the capacitors in the data line DL or the switch driver 130 / Power consumed in discharging or power consumption due to pixel color changes on the source driver 140 can be reduced. The control method for the gate line GL and the switch signal SW of the display device 100 according to the present invention will be described in more detail with reference to the following drawings.

2 is a circuit diagram illustrating an exemplary structure of the pixel of Fig. 2, a structure for one pixel PIX is described, but other pixels may also have a structure similar to the pixel PIX of FIG. Further, the structure of an organic light emitting display (OLED) pixel is exemplarily described with reference to FIG. However, the scope of the present invention is not limited thereto, and the structure of the pixel PIX may be implemented in various forms.

1 and 2, the pixel PIX may include a selection transistor SEL, a driving transistor DRV, a capacitor CAP, and an organic light emitting diode OLED. Illustratively, the pixel PIX of FIG. 2 includes a pixel structure including two transistors SEL and DRV, but the scope of the present invention is not limited thereto.

The anode of the organic light emitting diode OLED receives the first power supply voltage ELVDD through the driving transistor DRV. The cathode of the organic light emitting diode OLED receives the second power supply voltage ELVSS. The selection transistor SEL outputs a data signal applied to the data line DL in response to a signal applied to the gate line GL. The capacitor CAP charges or discharges a voltage corresponding to the data signal received from the selection transistor SEL. The driving transistor DRV controls the driving current flowing in the organic light emitting element OLED in accordance with the voltage stored in the capacitor CAP. Illustratively, the second power supply voltage ELVss may be a ground voltage. The organic light emitting diode OLED emits light according to the driving current. Illustratively, the organic light emitting diode (OLED) is configured to display either red (red), green, blue, or white (i.e., pixel color) .

FIG. 3 is a block diagram illustrating an exemplary display device of FIG. 1; For simplicity and ease of illustration, it is assumed that a plurality of pixels are arranged in a 4 x 4 array. Further, for each of the plurality of pixels, reference numeral is assigned based on the corresponding pixel color. That is, a reference symbol of "RD" is given to pixels whose pixel color is red, a reference symbol of "GR" is assigned to pixels whose pixel color is green, Quot; BL " That is, the reference symbol given to each pixel is merely for expressing the pixel color, and such a reference symbol does not limit the technical idea of the present invention.

Further, for the sake of brevity of the drawing, the gate driver 120 is omitted in Fig. However, it will be understood that a plurality of gate lines GL1 to GL4 may be controlled by the gate driver 120. [ It is also assumed that the switch driver 130 includes first and second switch circuits 131 and 132 and that each of the first and second switch circuits 131 and 132 is a 2: 1 demultiplexer. The configuration of the switch driver 130 is intended to explain the embodiment of the present invention briefly and clearly, and the scope of the present invention is not limited thereto.

1 and 3, the pixel array 110 includes a plurality of pixels RD11, GR12, BL13, GR14, BL21, GR22, RD23, GR24, RD31, GR32, BL33, GR34, BL41, GR44). The plurality of pixels may be arranged in a pentile structure, as shown in Fig. However, the pixel arrangement shown in FIG. 3 is exemplary and the scope of the present invention is not limited thereto.

Each of the plurality of pixels is connected to the first to fourth gate lines GL1 to GL4 and the first to fourth data lines DL1 to DL4, respectively. Each of the plurality of pixels is activated by a corresponding gate line, and the activated pixels may display a corresponding pixel color in response to the voltage of the corresponding data line.

Each of the plurality of pixels RD11, GR12, BL13, GR14, BL21, GR22, RD23, GR24, RD31, GR32, BL33, GR34, BL41, GR42, RD43, GR44 shown in FIG. . Some subpixels may constitute one pixel capable of representing one color. However, in order not to obscure the embodiments of the present invention in the following, the element representing one pixel color will be referred to as a pixel. However, it will be appreciated that the pixels described in the text may be sub-pixels, and that a plurality of sub-pixels may constitute a single pixel.

Each of the first and second switch circuits 131 and 132 is connected to the first to fourth data lines DL1 to DL4 and switches in response to the first and second switch signals SW1 and SW2. Can be performed.

For example, the first switch circuit 131 may include transistors T11 and T12. One end of the transistor T11 is connected to the first data line DL1 and the other end is connected to the first terminal TM1 and the gate is configured to receive the first switch signal SW1. The transistor T11 provides the signal (or voltage) of the first terminal TM1 to the first data line DL1 in response to the first switch signal SW1. One end of the transistor T12 is connected to the second data line DL2, the other end is connected to the first terminal TM1, and the gate is configured to receive the second switch signal SW2. The transistor T12 provides the signal (or voltage) of the first terminal TM1 to the second data line DL2 in response to the second switch signal SW2.

Similarly, the second switch circuit 132 may include transistors T21 and T22. One end of the transistor T21 is connected to the third data line DL3 and the other end is connected to the second terminal TM2, and the gate is configured to receive the first switch signal SW1. The transistor T21 provides the signal (or voltage) of the second terminal TM2 to the third data line DL3 in response to the first switch signal SW1. One end of the transistor T22 is connected to the fourth data line DL4, the other end is connected to the second terminal TM2, and the gate is configured to receive the second switch signal SW2. The transistor T22 provides the signal (or voltage) of the second terminal TM2 to the fourth data line DL4 in response to the second switch signal SW2.

As described above, each of the first and second switch circuits 131 and 132 is connected to the first and second terminals TM1 and TM2 in response to the first and second switch signals SW1 and SW2, 1 < / RTI > to 4 < th > data lines DL1 to DL4. However, the scope of the present invention is not limited thereto, and the switch circuits may be implemented in the form of a MUX of n: 1 (where n is an integer greater than 2).

The source driver 140 may include first and second source drivers SD1 and SD2 (source driving units). Each of the first and second source drivers SD1 and SD2 is connected to the first and second terminals TM1 and TM2 and receives a corresponding data signal through the first and second terminals TM1 and TM2 Lt; / RTI >

Illustratively, the operation of displaying the image information by the pixels RD11, GR12, BL13, and GR14 connected to the first gate line GL1 will be described. First, the first gate line GL1 is activated so that the pixels RD11, GR12, BL13, and GR14 connected to the first gate line GL1 display image information. At this time, "activating the gate line" means providing the turn-on voltage to the gate line so that the selection transistor SEL (see FIG. 2) of each pixel connected to the gate line is turned on.

The first and second switch signals SW1 and SW2 are sequentially activated in the active period of the first gate line GL1 so that the pixels RD11 to GR12 connected to the first gate lines GL1, GR14 may be provided with corresponding data signals. For example, when the first switch signal SW1 is activated, the first terminal TM1 and the first data line DL1 are connected by the first switch circuit 131, the second switch circuit 132 is connected to the first terminal TM1, The second terminal TM2 and the third data line DL3 are connected to each other. Accordingly, the one source driver SD1 may provide the data signal corresponding to the RD11 pixel, and the second source driver SD2 may provide the data signal corresponding to the BL13 pixel.

Thereafter, when the second switch signal SW2 is activated, the first terminal TM1 and the second data line DL2 are connected by the first switch circuit 131 and the first terminal TM1 is connected to the second switch circuit 132 The second terminal TM2 and the fourth data line DL4 are connected. Accordingly, the first source driver SD1 may provide a data signal corresponding to a GR12 pixel, and the second source driver SD2 may be provided with a data signal corresponding to a GR14 pixel.

As described above, by controlling the gate lines GL1 to GL4 and the switch signals SW1 and SW2, each of the plurality of pixels can display image information (or color) corresponding to the data signal.

Illustratively, while each of the plurality of pixels displays image information, power may be consumed due to various factors. For example, each of the first and second source drivers SD1 and SD2 may provide a data signal through the first and second terminals TM1 and TM2. At this time, when the switch signals SW1 and SW2 are changed, since the pixel color of the pixel to be displayed is changed, the data signal level from each of the first and second source drivers SD1 and SD2 can be changed have.

With this data signal level change, the voltage of the wiring connected to the first and second terminals TM1 and TM2 will be charged or discharged. The charging or discharging at the first and second terminals TM1 and TM2 may be performed by the capacitors C _A1 and C of the wirings connected to the first and second terminals TM1 and TM2, _A2 ). That is, the power charged / discharged by the data signal level change of the first and second source drivers SD1 and SD2 can be expressed by the charge / discharge power of the capacitors C _A1 and C _A2 .

Similarly, in each of the first to fourth data lines DL1 to DL4, when the activated gate line is changed, the data signal level from each of the first and second source drivers SD1 and SD2 can be changed have. By changing the level of the data signal, the voltage of each of the first to fourth data lines DL1 to DL4 will be charged or discharged. The charge / discharge power of the data line may be represented by capacitors C _B1 to C _B4 connected to the first to fourth data lines DL1 to DL4, respectively, as shown in FIG. That is, the power consumed for charging / discharging each of the first to fourth data lines DL1 to DL4 can be expressed by the charge / discharge power of the capacitors C _B1 to C _B4 .

Illustratively, the power consumed by the display device 100 can be minimized by minimizing the power charged / discharged by the capacitors C _A1 and C _A2 and the capacitors C _B1 to C _B4 . The display device 100 according to the present invention can control the capacitors C _A1 and C _A2 and the capacitors C _A1 and C _A2 described above by controlling the plurality of gate lines GL1 to GL4 and the plurality of switch signals SW1 and SW2 in a non- The power charged / discharged by the capacitors C _B1 to C _B4 can be minimized. The driving method of the display apparatus 100 according to the present invention will be described in more detail with reference to the following timing diagrams.

4A to 7B are timing diagrams for explaining a driving method of a display device according to an embodiment of the present invention. The horizontal axis of each of the timing diagrams of Figs. 4A to 7B indicates time. For the sake of brevity, the pixels (i.e., RD11, GR12, BL21, GR22, RD31, GR32, BL41, GR42) connected to the first and second data lines DL1, The first switch circuit 131, and the first source driver SD1 will be described. However, the scope of the present invention is not so limited, and other pixels, other switch circuits, and other source driver circuits may also operate in a manner similar to that described with reference to FIGS. 4A-B.

Illustratively, in each of the timing diagrams of Figs. 4A to 7B, the first section represents the voltage level (or gate signal) of the first to fourth gate lines GL1 to GL4, And the third section indicates the voltage level of the first source driver SD1 according to the color of the image information to be displayed by each of the pixels.

Illustratively, in the third section, the red reference symbol indicates that the image information (or the displayed screen) to be displayed by the pixels indicates red color, and the red reference symbol corresponding to red reference symbol The timing diagram may indicate the output voltage of the first source driver SD1 in the case where image information of red color is displayed. Each of the reference symbols of green, blue, magenta, cyan, and yellow may indicate the voltage level of the first source driver SD1 when image information of a corresponding color is output.

Illustratively, when red color image information is displayed, only the pixels whose pixel color is red (i.e., the RD pixels) are emitted, and the remaining other pixels (i.e., GR pixels, BL pixels) . Likewise, in the reference symbol of Green, only the GR pixel is emitted, and the RD pixel and the BL pixel are not emitted. In the reference symbol of Blue, only the BL pixel is emitted, In the reference symbol of magenta, only the RD pixel and the BL pixel emit light and the GR pixel emits no light. In the cyan reference symbol, only the GR pixel and the BL pixel emit light, The RD pixel is operated so as not to emit light, and in the yellow reference symbol, only the RD pixel and the GR pixel are emitted, and the BL pixel is not emitted.

Illustratively, in the timing diagrams of Figures 4A-B, it is assumed that each pixel activates or emits in response to a low level (L) signal. For example, when the first gate line GL1 is activated, the level of the first gate line GL1 is a low level (L). The first switch circuit 131 can provide the data signal from the first source driver SD1 as a pixel RD11 in response to the low level L signal of the first switch signal SW1. That is, when both the first gate line GL1 and the first switch signal SW1 are at the low level (L), the pixel RD11 is activated. At this time, when the data signal from the first source driver SD1 is at the low level (L), the pixel RD11 emits light to display the pixel color of the red color, and when the data signal is at the high level (H) The pixel may not emit light.

Illustratively, in the timing diagrams of Figures 4A-B, each of the signals, the low level (L) or the high level (H) of the voltage may be a value relative to each other. That is, the low (L) / high (H) levels of the first gate line GL1 are either the low (L) / high (H) signals of the first switch signal SW1, (L) / high (H) signals.

That is, as described above, the timing charts shown in Figs. 4A to 7B are merely illustrative for easily explaining the technical idea of the present invention, and the scope of the present invention is not limited thereto. It will also be appreciated that the waveforms of the actual signals can be modified from the waveforms shown in Figures 4A-B.

Hereinafter, for convenience of explanation, "a specific gate line is activated" means that a gate signal (that is, a low-level signal) is supplied to a specific gate line so that the selection transistor of the pixels connected to the gate line is turned on . In addition, it is assumed that the activation of a specific switch signal means that a specific switch signal of a low level (L) is provided to the switch circuit so that the data signal is supplied to the data line corresponding to the specific switch signal. Also, it is assumed that the activation of a specific pixel means that a gate line connected to a specific pixel is activated, and a specific switch signal is activated to provide a data signal to a data line connected to a specific pixel.

Hereinafter, for convenience of explanation, the capacitor C _A1 connected to the first terminal TM1 is referred to as a driving cap and is connected to the first and second data lines DL1 and DL2 The capacitors C _B1 , C _{B2 are} referred to as first and second line caps. This driving cap and line cap. May be parasitic capacitors present in the display.

Illustratively, discharging the drive cap (C _A1 ) and the first and second line caps (C _B1 , C _B2 ) does not consume power or dissipates the caps (C _A1 , C _B1 , C _B2 ) which electric power is due caps (C _A1, C _B1, C _B2) to very small compared to the power consumed for charging, the power consumption of the display device 100 is for charging the caps (C _A1, C _B1, C _B2) Only power consumed is considered.

It is to be understood, however, that the scope of the present invention is not limited to these examples or assumptions.

First, referring to FIGS. 1, 3, and 4A, the gate driver 120 may sequentially activate the first through fourth gate lines GL1 through GL4. For example, as shown in the first section of FIG. 4A, the gate driver 120 activates the first gate line GL1 at the 0-th time point t0 and, at the first time point t1, The second gate line GL2 may be activated at the second time point t2 to activate the third gate line GL3 and the fourth gate line GL4 may be activated at the third time point t3.

In the active period of each of the first to fourth gate lines GL1 to GL4, the first switch circuit 131 can operate in response to the first and second switch signals SW1 and SW2. At this time, the first and second switch signals SW1 and SW2 may be alternately (or sequentially) provided in the active periods of the first to fourth gate lines GL1 to GL4.

For example, in the active period of the first gate line GL1, the first switch signal SW1 may be activated, and then the second switch signal SW2 may be activated. In the active period of the second gate line GL2, the first switch signal SW1 may be activated, and then the second switch signal SW2 may be activated. Similarly, in the active period of each of the third and fourth gate lines GL3 and GL4, the first switch signal SW1 may be activated, and then the second switch signal SW2 may be activated.

As described above, when the first to fourth gate lines GL1 to GL4 and the first and second switch signals SW1 and SW2 are activated, the pixels are switched from RD11 to GR12 to BL21 to GR22 to RD31 to GR32 → BL41 → GR42.

In the third section of FIG. 4A, the operation of the first source driver SD1 will be described with reference to a case in which image information of red color is displayed. As described above, in order to display image information of a red color, the first source driver SD1 will emit only the RD pixel, and the remaining GR pixels and BL pixels will not emit light.

For example, at the zero time point t0, it is assumed that the first and second line caps C _B1 and C _B2 are all in the high level state. The first data line DL1 and the first terminal TM1 are connected in the active period of the RD11 pixel and the first source driver SD1 supplies the data signal of the low level L so that the RD11 pixel emits light will be. At this time, the driving cap C _A1 and the first line cap C _B1 will be discharged at a low level.

Thereafter, the second data line DL2 and the first terminal TM1 are connected in the active period of the GR12 pixel, and the first source driver SD1 supplies the data signal of the high level (H) . ≪ / RTI > At this time, the driving cap C _A1 is discharged to the low level (L) in the active period of the RD 11 pixel, and the second line cap (C _B2 ) is at the high level. That is, the first source driver SD1 will consume power to charge the driving cap C _A1 to the high level (H). The power consumed at this time can be expressed by the capacity of the driving cap C _A1 .

The first data line DL1 and the first terminal TM1 are connected in the active period of the BL21 pixel and the first source driver SD1 is connected to the data signal of the high level H . ≪ / RTI > At this time, the driving cap C _A1 is charged to the high level (H) in the active period of the GR 12 pixel, and the first line cap C _B1 is discharged to the low level (L) State. That is, the first source driver SD1 will consume power to charge the first line cap C _B1 to the high level (H).

Thereafter, the second data line DL2 and the first terminal TM1 are connected in the active period of the GR22 pixel, and the first source driver SD1 supplies the data signal of the high level (H) . ≪ / RTI > At this time, the driving cap C _A1 is charged at the high level (H) in the active period of the BL21 pixel and the second line cap C _B2 is charged at the high level (H) in the active period of the GR 12 pixel State. That is, the first source driver SD1 does not consume power to charge the driving cap C _A1 and the second line cap C _B2 .

Thereafter, the first data line DL1 and the first terminal TM1 are connected in the active period of the RD31 pixel, and the first source driver SD1 is connected to the low level L At this time, the first source driver SD1 will discharge the driving cap C _A1 and the first line cap C _B1 to a low level.

The second data line DL2 and the first terminal TM1 are connected in the active period of the GR32 pixel and the first source driver SD1 is connected to the data signal of the high level H . ≪ / RTI > At this time, the driving cap C _A1 is discharged to the low level L in the active period of the RD 31 pixel, and the second line cap C _B2 is charged to the high level H in the active period of the GR 22 pixel. Respectively. That is, the first source driver SD1 will consume power to charge the driving cap C _A1 to the high level (H).

Thereafter, in the active periods of the BL41 pixel and the GR42 pixel, the first source driver SD1 provides a high level data signal so that the BL41 pixel and the GR42 pixel do not emit light, and the first line cap C _B1 And consumes power for charging to the high level (H). The active periods of the BL41 pixel and the GR42 pixel are similar to the active periods of the BL21 pixel and the GR22 pixel, so that a description thereof is omitted.

As described above, in order to display image information of red color, while the first to fourth gate lines GL1 to GL4 are activated, the first source driver SD1 is driven by 2C _A1 + 2C _B1 It can be expressed as consuming power. For the sake of clarity of the drawing, the section in which the power is consumed (i.e., the filling period of the cap) is represented by a thick solid line in FIG. 4A.

Similarly, in the case of displaying image information of each of the colors of green, blue, magenta, cyan, and yellow, as shown in FIG. 4A, Power can be consumed to charge the driving cap C _A1 according to the data signal (or pixel color) for the pixel, and the data signal (or pixel color) for the last active pixel among the pixels connected to the same data line Power may be consumed to charge the first and second line caps C _B1 , C _B2 . Table 1 is a table showing the power consumption according to each display color shown in FIG. 4A.

Display color Red Green blue magenta draft yellow Display pixel
RD / GR / BL / GR L / H / H / H H / L / H / L H / H / L / H L / H / L / H H / L / L / L L / L / H / L Power consumption 2C _A1 + 2C _B1 4C _A1 2C _A1 + 2C _B1 4C _A1 2C _A1 + 2C _B1 2C _A1 + 2C _B1

Referring to Table 1, the display color indicates the color of the image information displayed by the plurality of pixels, and the display pixel indicates the pixel color of the pixel emitting light according to the display color. At this time, a pixel represented by a low level (L) emits light, and a pixel represented by a high level (H) does not emit light. The power consumption refers to the power consumed by the displayed color.

The power consumed when driving the two data lines DL1 and DL2 while being activated in the four gate lines GL1 to GL4 may be as shown in Table 1. [ As shown in FIG. 4A and described in Table 1, the driving cap C _A1 is charged or discharged according to the level (or pixel color) of the data signal for the immediately previous activated pixel, and the first and second line caps C _B1 , and C _B2 may be charged or discharged according to the data signal (or pixel color) for the recently activated pixel (or the last pixel) among the pixels connected to the same data line.

Illustratively, the embodiment of FIG. 4B differs from the embodiment of FIG. 4A in that the section where the gate lines to be activated are changed is omitted. For example, in the embodiment of FIG. 4A, after the first gate line GL1 is inactivated and a predetermined time has elapsed, the second gate line GL2 may be activated.

However, according to the embodiment of FIG. 4B, immediately after the first gate line GL1 is deactivated, the second gate line GL2 can be activated. That is, according to the embodiment of FIG. 4B, gate lines can be activated in succession (or without intermediate time) in the order of GL1? GL2? GL3? GL4. Illustratively, the first and second switch signals SW1 and SW2 may operate in a manner similar to that described with reference to Fig. 4A in the activation period of each of the gate lines. In the embodiment of FIG. 4B, except for the points described above, the remaining operation is the same as that of FIG. 4A, so a detailed description thereof will be omitted.

Next, referring to FIGS. 1, 3, and 5A, the gate driver 120 may activate the first through fourth gate lines GL1 through GL4 in a non-sequential manner. Illustratively, the non-sequential activation of the first through fourth gate lines GL1 through GL4 means activating differently from the physically aligned order (e.g., the order of the lower gate lines in the upper gate line) do. For example, in the embodiment described with reference to FIG. 4A, the gate lines are activated sequentially (i.e., in physically aligned order) in the order of GL1? GL2? GL3? GL4, but in the embodiment of FIG. The gate lines can be activated in a non-sequential order (i.e., different from the physically aligned order) in the order of → GL2 → GL4 → GL3.

Illustratively, according to the embodiment of FIG. 5A, the continuously activated gate lines may not be physically adjacent to each other. For example, according to the embodiment shown in FIG. 5A, the second gate line GL2 may be activated, and then the fourth gate line GL4 may be activated. At this time, the second and fourth gate lines GL2 and GL4 are activated successively but are not physically adjacent to each other.

Illustratively, the activation sequence of the gate lines GL1 to GL4 according to the embodiment of FIG. 5A may be implemented by changing the configuration of the gate driver 120 or by changing the connection order of the gate lines GL1 to GL4 .

The first and second switch signals SW1 and SW2 are sequentially applied in the active period of each of the first to fourth gate lines GL1 to GL4 in the same manner as described with reference to FIG. → SW2).

When the gate lines GL1 to GL4 and the switch signals SW1 and SW2 are driven as shown in FIG. 5A, the pixels are driven in the order of RD11? GR12? BL21? GR22? BL41? GR42? RD31? Can be activated.

Similar to the above description, the operation of the first source driver SD1 will be described with reference to a case in which image information of a red color is displayed in the third section of FIG. 5A.

When image information of a red color is displayed, a data signal will be provided to each pixel so that only the RD pixel emits light and the other pixels (GR pixel, BL pixel) do not emit light. In the active periods of the RD11 pixel, the GR12 pixel, the BL21 pixel, and the GR22 pixel, the first source driver SD1 may provide a data signal to emit only the RD11 pixel. At this time, the first source driver SD1 will consume power to charge the driving cap C _A1 and the first line cap C _B1 . The operation of the active periods of the RD11 pixel, the GR12 pixel, the BL21 pixel, and the GR22 pixels in Fig. 5A is the same as the operation of the active periods of the RD11 pixel, the GR12 pixel, the BL21 pixel, and the GR22 pixels in Fig. 4A, Is omitted.

As shown in FIG. 5A, the BL41 pixel can be activated after the active period of the GR22 pixel, as the activation order of the gate lines is changed (i.e., activated in the order of GL1? GL2? GL4? GL3). In the active period of BL41, the first source driver SD1 will provide a data signal of high level (H) so that the BL41 pixel does not emit light. At this time, the driving cap C _A1 is charged to the high level H in the active period of the GR 22 pixel and the first line cap C _B1 is charged to the high level H in the active period of the BL 21 pixel State. That is, charging of the driving cap C _A1 and the first line cap C _B1 is not required so that the first source driver SD1 supplies the data signal of high level H with the BL41 pixel.

Similarly, in the active period of the GR42 pixel, the first source driver SD1 will provide a data signal of a low level (H) so that the GR42 pixel does not emit light. At this time, the driving cap C _A1 is charged at the high level (H) in the active period of the BL 41 pixel and the second line cap C _B2 is charged at the high level (H) State, no separate charging is required.

Thereafter, in the active periods of the RD31 pixel and the GR32 pixel, the source driver SD1 consumes power to charge the driving cap C _A to the high level (H). The active periods of the RD31 pixel and the GR32 pixel are similar to the active periods of the RD11 pixel and the GR12 pixel, and thus a detailed description thereof is omitted.

5A, in order to display image information of red color, while the first to fourth gate lines GL1 to GL4 are activated, the first source driver SD1 is driven by 2C Can be expressed as consuming power of _A1 + C _B1 . For the sake of clarity of the figure, the section in which the power is consumed (i.e., the charging section of the cap) is represented by a thick solid line in Fig. 5A.

The power consumed to display other colors, e.g., Green, Blue, Magenta, Cyan, and Yellow colors is also shown in bold solid lines in FIG. 5a. The consumed power indicated by a bold solid line in FIG. 5A is the power consumed to charge the driving cap C _A1 according to the data signal (or pixel color) for the immediately previous activated pixel, May be the power consumed to charge the first and second line caps C _B1 , C _B2 according to the data signal (or pixel color) for the activated pixel. The power consumed to display each color according to the embodiment of FIG.

Display color Red Green blue magenta draft yellow Display pixel
RD / GR / BL / GR L / H / H / H H / L / H / L H / H / L / H L / H / L / H H / L / L / L L / L / H / L Power consumption 2C _A1 + C _B1 4C _A1 2C _A1 + C _B1 4C _A1 2C _A1 + C _B1 2C _A1 + C _B1

Descriptions and reference symbols for Table 2 have been described with reference to Table 1, and a description thereof will be omitted. Referring to Tables 1 and 2, by non-sequentially activating the gate lines, pixels having the same pixel color among the pixels connected to the same data line (for example, the first data line DL1) . Thus, the power consumed in charging the line cap (for example, the first line cap C _B1 ) can be reduced.

For example, when considering only the pixels connected to the first data line DL1 in the embodiment of FIG. 5A, the pixels are activated in the order of RD11? BL21? BL41? RD31. At this time, when displaying the color (that is, Blue) in which the BL pixel emits light, the power consumed in charging the first line cap C _B1 can be reduced as compared with the embodiment of FIG. 4A. That is, by non-sequentially activating the gate lines such that pixels having the same pixel color among the pixels connected to the same data line are activated in succession or in close proximity to each other, the consumed power (i.e., consumed in charging the line cap C _B1 Power) can be reduced.

Illustratively, the embodiment of FIG. 5B differs from the embodiment of FIG. 5A in that the section where the gate lines to be activated are changed is omitted. For example, in the embodiment of FIG. 5A, after the first gate line GL1 is deactivated and a predetermined time has elapsed, the second gate line GL2 may be activated.

However, according to the embodiment of FIG. 5B, immediately after the first gate line GL1 is deactivated, the second gate line GL2 can be activated. That is, according to the embodiment of FIG. 5B, gate lines can be activated in succession (or without intermediate time, no delay time) in the order of GL1? GL2? GL4? GL3. Illustratively, the first and second switch signals SW1 and SW2 may operate in a manner similar to that described with reference to Fig. 5A in the activation period of each of the gate lines. In the embodiment of Fig. 5B, except for the points described above, the remaining operation is the same as that of Fig. 5A, so a detailed description thereof is omitted.

Next, referring to FIGS. 1, 3, and 6A, the gate driver 120 sequentially connects the first to fourth gate lines GL1 to GL4 Can be activated. While the first to fourth gate lines GL1 to GL4 are sequentially activated, the first and second switch signals SW1 and SW2 are activated in a non-sequential manner as shown in the second section of Fig. 6A .

By way of example, the non-sequential activation of the switch signals SW1 and SW2 means that they are activated in any order, not in a cyclic order. For example, the activation sequence of the first and second switch signals SW1 and SW2 shown in FIG.

However, according to the embodiment shown in FIG. 6A, in the active period of the first gate line GL1, the first switch signal SW1 may be activated, and then the second switch signal SW2 may be activated. In the active period of the second gate line GL2, the second switch signal SW2 is activated, and then the first switch signal SW1 can be activated. In the active period of the third gate line GL3, the first switch signal SW1 may be activated, and then the second switch signal SW2 may be activated. In the active period of the fourth gate line GL4, the second switch signal SW1 is activated, and then the first switch signal SW1 is activated. That is, while the first to fourth gate lines GL1 to GL4 are sequentially activated, the first and second switch signals SW1 and SW2 are [SW1? SW2]? [SW2? SW1]? [SW1 → SW2] → [SW2 → SW1] (that is, in a non-sequential manner).

In this case, the pixels will be activated in the order of RD11? GR12? GR22? BL21? RD31? GR32? GR42? BL41. Similar to that described with reference to Figs. 4A and 5A, the first source driver SD1 may be configured to provide a corresponding data signal to a corresponding pixel to display various colors. Regarding each display color, a section for charging the driving cap C _A1 and the first line cap C _B1 is indicated by a thick solid line in the third section of Fig. 6A. For each of the display colors, a configuration in which the source driver SD1 provides the corresponding data signal, a configuration for charging the drive cap C _A1 and the first line cap C _B1 , And the order in which the pixels are activated except for the order in which the pixels are activated. Therefore, a detailed description thereof is omitted. The power consumed to display each display color according to the embodiment of FIG. 6A may be as shown in Table 3. [

Display color Red Green blue magenta draft yellow Display pixel
RD / GR / BL / GR L / H / H / H H / L / H / L H / H / L / H L / H / L / H H / L / L / L L / L / H / L Power consumption 2C _A1 + 2C _B1 2C _A1 2C _A1 + 2C _B1 2C _A1 2C _A1 + 2C _B1 2C _A1 + 2C _B1

Explanations and reference symbols for Table 3 have been described with reference to Table 1, and a description thereof will be omitted.

In comparison with the embodiments of Figs. 4A and 5A, in the embodiment of Fig. 6A, the GR pixels can be activated continuously. For example, GR12 pixels and GR22 pixels are activated successively from each other, and GR32 pixels and GR42 pixels are activated in succession to each other. In this case, the power consumed to display the color in which the GR pixel emits light (in other words, the power consumed to charge the driving cap C _A1 ) can be reduced.

That is, referring to Table 3 and FIG. 6A, the switch signals SW1 and SW2 can be activated in a non-sequential manner such that pixels having the same pixel color are displayed successively to each other. Thus, the power consumed in charging the driving cap C _A1 can be reduced.

Illustratively, the embodiment of FIG. 6B differs from the embodiment of FIG. 6A in that the section where the gate lines to be activated are changed is omitted. For example, in the embodiment of FIG. 6A, after the first gate line GL1 is deactivated and a predetermined time has elapsed, the second gate line GL2 may be activated.

However, according to the embodiment of FIG. 6B, immediately after the first gate line GL1 is deactivated, the second gate line GL2 can be activated. That is, according to the embodiment of FIG. 6B, the gate lines can be activated in succession (or without intermediate time) in the order of GL1? GL2? GL3? GL4. Illustratively, the first and second switch signals SW1, SW2 may operate in a manner similar to that described with reference to Fig. 6A in the activation period of each of the gate lines. In the embodiment of FIG. 6B, except for the points described above, the remaining operation method is the same as that of FIG. 6A, so a detailed description thereof will be omitted.

Next, referring to FIGS. 1, 3 and 7A, as shown in the first section of FIG. 7A, the gate driver 120 sequentially applies the first to fourth gate lines GL1 to GL4 to the non- . For example, the gate driver 120 may non-sequentially activate the gate lines in the order of GL1? GL2? GL4? GL3, similar to that described with reference to FIG. 5A.

As shown in the second section of Fig. 7A, while the first to fourth gate lines GL1 to GL4 are activated in a non-sequential manner, the first and second switch signals SW1 and SW2 are non- Can be activated. For example, in the active period of the first gate line GL1, the first switch signal SW1 may be activated, and then the second switch signal SW2 may be activated. In the active period of the second gate line GL2, the second switch signal SW2 is activated, and then the first switch signal SW1 can be activated. In the active period of the fourth gate line GL4, the first switch signal SW1 may be activated, and then the second switch signal SW2 may be activated. In the active period of the third gate line GL3, the second switch signal SW2 is activated, and then the first switch signal SW1 can be activated.

That is, the first and second switch signals SW1 and SW2 are similar to those described with reference to FIG. 6A. [SW1? SW2]? [SW2? SW1]? [SW1? SW2]? [SW2? SW1 ]. At this time, the pixels can be activated in the order of RD11? GR12? GR22? BL21? BL41? GR42? GR32? RD31.

The operation of the first source driver SD1 will be described with reference to a case in which image information of the red color shown in the third section of FIG. 7A is displayed. The first data line DL1 and the first terminal TM1 are connected in the active period of the RD11 pixel and the first source driver SD1 is connected to the first data line DL1 and the first terminal TM1 in order to emit the data signal of the low level 1 terminal (TM1). Accordingly, the driving cap C _A1 and the first line cap C _B1 will be discharged to a low level.

Thereafter, the second data line DL2 and the first terminal TM1 are connected in the active period of the GR12 pixel, and the first source driver SD1 does not emit light of the GR12 pixel, And provides the data signal to the first terminal TM1. At this time, since the driving cap C _A1 is in the low level state, the first source driving unit SD 1 will consume power to charge the driving cap C _A1 to the high level H.

Thereafter, the second data line DL2 and the first terminal TM1 are connected in the active period of the GR22 pixel, and the first source driver SD1 does not emit the GR22 pixel, And provides the data signal to the first terminal TM1. At this time, since the driving cap C _A1 and the second line cap C _B2 are already in a high level (H) state, no extra charging power is consumed.

Thereafter, the first data line DL1 and the first terminal TM1 are connected in the active period of the BL21 pixel, and the first source driver SD1 does not emit light of the BL21 pixel, And provides the data signal to the first terminal TM1. At this time, since the first line cap C _B1 is discharged to the low level in the active period of the RD 11 pixel, power is consumed to charge the first line cap C _B1 to the high level.

Thereafter, in the active periods of BL41 pixel, GR42 pixel, and GR32 pixel, the first source driver SD1 applies a high-level (H) data signal to the BL41 pixel, the GR42 pixel, and the GR32 pixel To the first terminal TM1. At this time, since the driving cap C _A1 and the first and second line caps C _B1 and C _B2 are already in a high level state, no extra charging power is consumed.

Thereafter, the first data line DL1 and the first terminal TM1 are connected in the active period of the RD31 pixel, and the first source driver SD1 supplies the data signal of the low level (L) To the first terminal TM1. At this time, the driving cap C _A1 and the first line cap C _B1 will be discharged to a low level.

As described above, according to the embodiment shown in FIG. 7A, in the case of displaying image information of red color, when the first to fourth gate lines GL1 to GL4 are activated in a non-sequential manner, The power consumed to charge the cap C _A1 and the first and second line caps C _B1 , C _B2 can be expressed as C _A1 + C _B1 . That is, by non-sequentially activating the gate lines and the switch signals, power consumption can be reduced.

Similar to that described above, power can be consumed to charge the driving cap C _A1 according to the pixel color (or the corresponding data signal) of the immediately previous activated pixel, and the last of the pixels connected to the same data line Power can be consumed to charge the line caps (C _B1 , C _B2 ) according to the pixel color (or the corresponding data signal) of the activated pixel. The power consumed to display each display color in accordance with the embodiment of FIG. 7A may be as shown in Table 4. < tb >< TABLE >

Display color Red Green blue magenta draft yellow Display pixel
RD / GR / BL / GR L / H / H / H H / L / H / L H / H / L / H L / H / L / H H / L / L / L L / L / H / L Power consumption C _A1 + C _B1 2C _A1 C _A1 + C _B1 2C _A1 C _A1 + C _B1 C _A1 + C _B1

Descriptions and reference symbols for Table 4 have been described with reference to Table 1, and a description thereof will be omitted.

Referring to Tables 1 to 4, according to the embodiment of FIG. 7A, power consumed in displaying image information of each color is reduced as compared with the embodiments described with reference to FIGS. 4A to 6A. That is, by controlling the gate lines and the switch signals in a non-sequential manner, power consumption can be reduced by having pixels having the same pixel color and pixels connected to the same data line being activated in succession.

Illustratively, the embodiment of FIG. 7B differs from the embodiment of FIG. 7A in that the section where the gate lines to be activated are changed is omitted. For example, in the embodiment of FIG. 7A, after the first gate line GL1 is inactivated and a predetermined time has elapsed, the second gate line GL2 may be activated.

However, according to the embodiment of FIG. 7B, immediately after the first gate line GL1 is deactivated, the second gate line GL2 can be activated. That is, according to the embodiment of FIG. 7B, gate lines can be activated in succession (or without intermediate time, no delay time) in the order of GL1? GL2? GL4? GL3. Illustratively, the first and second switch signals SW1 and SW2 may operate in a manner similar to that described with reference to Fig. 7A in the activation period of each of the gate lines. In the embodiment of FIG. 7B, except for the points described above, the remaining operation is the same as that of FIG. 7A, so a detailed description thereof will be omitted.

That is, according to the embodiment of the present invention, the display device 100 can non-sequentially control the gate lines and the switch signals such that a pixel having the same pixel color as the last pixel (i.e., the current pixel) is activated. At this time, the last pixel indicates the last active pixel among the pixels connected to the immediately preceding activated gate line. The current pixel has the same pixel color as the last pixel and may point to a pixel connected to the same data line. By thus activating the gate lines and the switch signals in a non-sequential manner, the power consumed in charging the driving cap C _A1 and the line caps C _B1 , C _B2 can be reduced.

8A and 8B are timing diagrams showing the operation of the source drivers of FIG. Referring to Figs. 8A and 8B, power consumption by the gamma voltage change of the first and second source drivers SD1 and SD2 will be described. Illustratively, the horizontal axis in the timing diagrams of Figs. 8A and 8B indicates time. The first section of Figs. 8A and 8B indicates the voltage level or gate signal of the first to fourth gate lines GL1 to GL4, and the second section shows the voltage level or gate signal of the first and second switch signals SW1 and SW2 And the third section shows the type of the gamma voltage corresponding to the data signal provided by the first and second source drivers SD1 and SD2 (i.e., red (RD), green (GR), or green Blue (BL)).

Illustratively, the first and second source drivers SD1 and SD2 of FIG. 3 may be configured to receive a gamma voltage from a gamma voltage generator (not shown) and provide a data signal using the received gamma voltage have. At this time, the gamma voltage may be different depending on the pixel color of the active pixel. At this time, the gamma voltage is changed in accordance with the pixel color of the active pixel, whereby analog power may be consumed in the source driver 140. [ That is, the more frequently the pixel color of the active pixels is changed, the higher the power consumption due to the gamma voltage change.

Similar to the above description, FIG. 8A shows an embodiment in which a predetermined time exists between active periods of gate lines, and FIG. 8B shows an embodiment in which gate lines are activated in succession. Since such a configuration has been described above, a detailed description thereof will be omitted. Hereinafter, an embodiment of the present invention will be described with reference to Fig. 8A in order to avoid duplication of description.

Referring to FIGS. 1, 3, and 8A, as shown in the first section of FIG. 8A, the gate driver 120 can activate the first through fourth gate lines GL1 through GL4 in a non- have. As shown in the second section of Fig. 8A, the first and second switch signals SW1 and SW2 can be activated in a non-sequential manner. The activation sequence of the first to fourth gate lines GL1 to GL4 and the first and second switch signals SW1 and SW2 is the same as that of the embodiment of FIG. 7A or 7B, and thus a detailed description thereof will be omitted.

8A, the first and second source drivers SD1 and SD2 are connected to the first to fourth gate lines GL1 to GL4 and the first and second switch signals SW1 and SW2, , SW2) according to the activation order of the active pixels.

For example, in the active period of the first gate line GL1 and the first switch signal SW1, the first source driver SD1 outputs a data signal using the gamma voltage corresponding to the red (RD) color , And the second source driver SD2 outputs a data signal using the gamma voltage corresponding to the blue (BL) color. Thereafter, in the active periods of the first gate line GL1 and the second switch signal SW2, the first source driver SD1 and the second source driver SD2 apply a gamma voltage corresponding to the green (GR) And outputs a data signal.

Similarly, the first source driver SD1 is turned on and off according to the activation order of the second to fourth gate lines GL2 to GL4 and the first and second switch signals SW1 and SW2. And outputs the data signal using the gamma voltage corresponding to each color in the order of? GR? GR? RD. The second source driver SD2 is turned on in accordance with the sequence of activation of the second to fourth gate lines GL2 to GL4 and the first and second switch signals SW1 and SW2. The data signal is output using the gamma voltage corresponding to each color in the order of " >

As described above, the first to fourth gate lines GL1 to GL4 and the first and second switch signals SW1 and SW2 are activated so that a pixel having the same pixel color as the pixel color of the previous active pixel is activated, The number of times of changing the gamma voltage used in the first and second source drivers SD1 and SD2 can be reduced.

According to a more detailed example, although not shown in the drawing, according to the activation sequence of the gate lines and the switch signals shown in FIG. 4A, the first source driver SD1 is turned on in the order of RD, GR, BL, GR, The data signal will be outputted by using the gamma voltage corresponding to each color in the order of → BL → GR. At this time, the number of times of changing the gamma voltage according to the pixel color change of the active pixel will be seven.

However, according to the embodiment shown in FIG. 8, the first source driver SD1 uses the gamma voltage corresponding to each color in the order of RD? GR? GR? BL? BL? GR? . At this time, the number of times of changing the gamma voltage according to the pixel color change of the active pixel is four. That is, by non-sequentially activating the first to fourth gate lines GL1 to GL4 and the first and second switch signals SW1 and SW2, the number of times of change of the gamma voltage due to the pixel color change can be reduced have. Thus, power consumption due to the gamma voltage change can be reduced.

9 is a flowchart showing an operation method of the display apparatus of FIG. For the sake of brevity, a method of operating the display device 100 will be described with reference to the configuration of one source driver SD1 and two data lines DL1 and DL2. Also, for the sake of brevity, an operation method in which the display apparatus 100 displays one frame will be described. However, it is to be understood that the scope of the present invention is not limited thereto, but can be extended to a plurality of data lines, a plurality of source drivers.

Referring to FIGS. 3 and 9, in step S110, the display device 100 may activate one gate line of the plurality of gate lines GL. For example, as described above, the gate driver 120 may activate one gate line of the plurality of gate lines.

In step S120, the display device 100 may provide a corresponding data signal through the first and second data lines DL1 and DL2 in the active period of the gate line. For example, when the activated gate line is the first gate line GL1, the first source driver SD1 supplies the corresponding data signal through the first data line DL1 with the pixel RD11, And a corresponding data signal with GR12 pixels through the second data line DL2. At this time, the first and second switch signals SW1 and SW2 can be activated so that the corresponding data signal is provided in the order of the RD11 pixel and the GR12 pixel.

In step S130, the display device 100 can activate the next gate line connected to the next pixel among the remaining gate lines. At this time, the next pixel has the same pixel color as the last pixel and is connected to the same data line as the last pixel. The last pixel may be the last active pixel in the active period of the immediately previous activated gate line.

For example, as described in step S120, when the first gate line GL1 is activated, the RD11 pixel may be activated, and then the GR12 pixel may be activated. At this time, the GR12 pixel may be the last activated pixel (i.e., the last pixel). In this case, the next pixel may be a GR22 pixel having the same pixel color (i.e., green) as the last pixel (i.e., GR12 pixel) and connected to the same data line (i.e., the second data line DL2). The gate driver 120 of the display device 100 can activate the next gate line (i.e., the second gate line GL2) in connection with the next pixel (i.e., the GR22 pixel).

In step S140, the display device 100 can provide the data signal through the first and second data lines DL1 and DL2 so that the data signal is first supplied to the next pixel in the active period of the next gate line .

For example, as described in step < RTI ID = 0.0 > S130, < / RTI > In this case, in the active period of the next gate line (i.e., the second gate line GL2), the second switch signal SW2 is activated first so that the data signal can be supplied first to the next pixel (i.e., GR22 pixel) have. Thereafter, the first switch signal SW1 is activated, so that the data signal can be supplied to the BL21 pixel.

In step S150, the display apparatus 100 can determine whether all the gate lines are activated. If all of the gate lines are not activated (i.e., the gate line that has not been activated remains), the display device 100 can repeat the operations of steps S130 and S140.

For example, returning to step S130, the display device 100 may activate the next one of the remaining gate lines. At this time, as described above, the next gate line is connected to the next pixel, and the next pixel is connected to the same data line as the last pixel, and has the same pixel color.

As a more detailed example, the last pixel in the active period of the second gate line GL2 is BL21 pixels. At this time, the BL41 pixel having the same pixel color (i.e., blue) as the BL21 pixel and connected to the same data line (i.e., the first data line DL1) may be the next pixel. Accordingly, the display device 100 can activate the next data line (i.e., the fourth data line DL4) connected to the next pixel (i.e., BL41 pixel). Thereafter, in step S140, the display device 100 can control the switch signals SW1 and SW2 and provide the data signals so that data is provided first with the next pixel (i.e., BL41 pixel).

When all the gate lines are activated, the display device 100 can terminate the display operation for one frame. Illustratively, the display apparatus 100 can display a plurality of frames by repeating steps S110 to S150.

As described above, the display device 100 according to the present invention activates the gate line connected to the current pixel having the same pixel color as the last pixel, and the data signal is first supplied to the pixel having the same pixel color as the last active pixel By activating the switch signals, the power consumption used in the driving cap C _A or the line cap C _B in the display device 100 can be reduced. In addition, by activating the gate lines and the switch signals so that the pixels having the same pixel color are activated successively or adjacently, the power consumption due to the gamma voltage change can be reduced.

10 is a block diagram showing a display device according to an embodiment of the present invention. For the sake of brevity and ease of explanation, overlapping components and their explanations are omitted. Referring to FIG. 10, the display device 200 may include a pixel array 210, a switch driver 230, and a source driver 240. Although not shown in the drawings, the display device 200 may further include components such as a gate driver, a controller, and the like.

Each of the plurality of pixels PIX of the pixel array 210 is connected to a plurality of gate lines GL1 to GLm and a plurality of data lines DL1 to DLn. Since the pixel array 210 and the plurality of pixels PIX have been described above, detailed description thereof is omitted.

Unlike the switch driver 130 (or the switch circuit) shown in FIGS. 1 to 9, the switch driver 230 is connected to the plurality of pixels PIX through the plurality of data lines DL1 to DLn, And a switch circuit 231 configured to receive a data signal from the source driver SD of the second transistor 240 through the first terminal TM1. The switch circuit 231 is configured to provide a signal received via the first terminal TM1 to one of the plurality of data lines DL1 to DLm in response to the switch signal SW. That is, the switch circuit 231 may be implemented in the form of an n: 1 MUX (where n is an integer greater than 2).

Although not shown in the drawing, the switch driver 230 may further include a plurality of switch circuits implemented in an n: 1 MUX form, and the source driver 240 further includes a plurality of source drivers SD .

11A and 11B are diagrams for explaining the operation of the display device of Fig. For the sake of brevity, a detailed description of the content or configuration described above is omitted. In order to simplify the drawing and simplify the description, the display device (for example, a display device) may be formed on the basis of the shape of the pixels connected to the first to sixth gate lines GL1 to GL6 and the first to third data lines DL1 to DL3 200 will be described. Further, each pixel gives a reference symbol (RD, GR, or BL) of the corresponding color filter.

It is also assumed that the switch circuit 231 is in the form of a 3: 1 MUX. That is, the switch circuit 231 supplies the data signal from the source driver SD to one of the first to third data lines DL1 to DL3 in response to the first to third switch signals SW1 to SW3 . However, the scope of the present invention is not limited thereto.

Also, as described above, FIG. 11A shows an embodiment in which a predetermined time exists between active periods of gate lines, and FIG. 11B shows an embodiment in which gate lines are activated in succession. In order to avoid duplication of the description, such a configuration has been described above, and thus a detailed description thereof will be omitted. Hereinafter, an embodiment of the present invention will be described with reference to FIG.

Referring to FIG. 11A, the display device 200 may activate the first to sixth gate lines GL1 to GL6 in a non-sequential manner. For example, the display device 200 can activate the gate lines in the order of GL1? GL3? GL2? GL4? GL6? GL5.

The display device 200 can activate the first to third switch signals SW1 to SW3 in the active periods of the first to sixth gate lines GL1 to GL6 in a non-sequential manner. For example, in the active periods of the first to sixth gate lines GL1 to GL6, the display device 200 displays [SW1? SW2? SW3]? [SW3? SW1? SW2]? [SW2? SW3? The first to third switch signals SW1 to SW3 can be activated in the order of [SW1] → [SW1 → SW2 → SW3] → [SW3 → SW1 → SW2] → [SW2 → SW3 → SW1]

At this time, the order in which the first to sixth gate lines GL1 to GL6 are activated is connected to the same data line as the last active pixel, as described above, and the gate line connected to the pixel having the same pixel color May be determined to be activated. For example, the last active pixel in the active period of the first gate line GL1 is the BL13 pixel connected to the third data line DL3. In this case, the third gate line GL3 connected to the third data line DL3 and connected to the BL33 pixel having the same pixel color can be activated. Likewise, the last active pixel in the active period of the third gate line GL3 is a GR32 pixel connected to the second data line DL2. In this case, the second gate line GL2 connected to the second data line DL2 and connected to the GR22 pixel having the same pixel color can be activated.

According to the above-described manner, the display device 200 is connected to the same data line as the last active pixel, and the first to sixth gate lines GL1 to GL6 are connected to a gate line connected to a pixel having the same pixel color Can be activated.

The order in which the first to third switch signals SW1 to SW3 are activated can be determined so that the data signal is provided to the pixel having the same pixel color as that of the last pixel that has been activated as described above. For example, the last active pixel in the active period of the first gate line GL1 is BL13 pixels. Thus, in the active period of the third gate line GL3 gate line, the third switch signal SW3 can be activated first such that the data signal is first provided to the BL33 pixel having the same pixel color (i.e., blue) . Similarly, in the active period of the second gate line GL2, the data signal is first supplied to the GR22 pixel having the same pixel color (i.e., green) as the previous last pixel (i.e., GR32 pixel) SW2 may be activated first.

According to the activation sequence of the first to sixth gate lines GL1 to GL6 and the first to third switch signals SW1 to SW3 described above, the pixels are [RD11? GR12? BL13]? [BL33? RD31? GR32] → [GR22 → RD23 → BL21] → [BL41 → GR42 → RD43] → [RD63 → BL61 → GR62] → [GR52 → BL53 → RD51]. In this case, as described above, since the pixels connected to the same data line and having the same pixel color are activated adjacent to each other, the power consumed in charging the driving cap and the line caps and the power consumption due to the change in the gamma voltage are reduced do.

12A-12D are views showing an exemplary pixel arrangement or color filter arrangement according to an embodiment of the present invention. For the sake of simplicity of the drawing, elements unnecessary for explaining the pixel layout are omitted. Further, for the sake of convenience of explanation, detailed description of the pixel arrangement shown in the figure is omitted.

First, referring to FIG. 12A, the pixel array 310a may include a plurality of pixels. Each of the plurality of pixels has a corresponding pixel color, and can be arranged as shown in Fig. 12A. For example, in the first row of the pixel array 310a, the pixels may be arranged in the order RD11, GR12, BL13, and GR14, and in the second row, the pixels are arranged in the order BL21, GR22, RD23, Lt; / RTI > Likewise, in the third and fourth rows, the pixels may be arranged as shown in FIG. 12A. Illustratively, the pixel array 310a described with reference to FIG. 12A may comprise a pixel arrangement of a pental structure. However, the scope of the present invention is not limited thereto.

Next, referring to FIG. 12B, the pixel array 310b may include a plurality of pixels. Each of the plurality of pixels has a corresponding pixel color, and can be arranged as shown in Fig. 12B. Illustratively, according to the pixel array 310b shown in FIG. 12B, even if the gate lines and the switch signals are sequentially provided, the effect of the power consumption reduction according to the present invention can be expected. For example, as described with reference to FIG. 4A, when the switch circuit is a 2: 1 MUX structure and gate lines and switch signals are provided sequentially, according to the pixel array 310 shown in FIG. 12, The pixels can be activated in the order of RD11? GR12? GR21? BL22? BL31? GR32? GR41? RD42. In this case, since the pixels having the same pixel color are activated adjacent to each other, the power consumption consumed in charging the cap (particularly, the driving cap C _A ) on the display panel is reduced, Consumption can also be reduced.

Next, referring to FIG. 12C, the pixel array 310c may include a plurality of pixels. Each of the plurality of pixels has a corresponding pixel color, and can be arranged as shown in Fig. 12C. Illustratively, according to the pixel array 310c shown in FIG. 12C, even if the gate lines are sequentially provided and the switch signals are provided in a non-sequential manner, as described with reference to FIG. 6A, The effect of reduction can be expected. For example, as described with reference to FIG. 6A, if the switch circuit is a 2: 1 MUX structure, the gates are sequentially provided, and the switch signals are provided in a non-sequential manner, the pixels are switched from RD11 GR12 GR22 BL21 → BL31 → GR32 → GR42 → RD41. In this case, since the pixels having the same pixel color connected to the same data line are activated adjacent to each other, the power consumption consumed in charging the caps (i.e., the driving cap C _A and the line cap C _B ) on the display panel The power consumption due to the gamma voltage change can be reduced.

Next, referring to FIG. 12D, the pixel array 310d may include a plurality of pixels. Each of the plurality of pixels has a corresponding pixel color, and can be arranged as shown in Fig. 12C. Illustratively, according to the pixel array 310d shown in FIG. 12D, even if the gate lines are provided in a non-sequential manner and the switch signals are sequentially provided, as described with reference to FIG. 5A, The effect of reduction can be expected. For example, as described with reference to FIG. 5A, when the switch circuit is a 2: 1 MUX structure, the gates are non-sequential, and the switch signals are provided sequentially, the pixels are set to RD11 GR12 GR21 BL22 → BL41 → GR42 → GR31 → RD32. In this case, since the pixels having the same pixel color are activated adjacent to each other, the power consumption consumed in charging the cap (particularly, the driving cap C _A ) on the display panel is reduced, Consumption can also be reduced.

That is, it will be appreciated that, as described above, the technical idea of the present invention can be implemented not only by the pixel layout of the penta-structure, but also by various pixel layouts. Illustratively, when the display device is implemented as an LCD device, the pixel layout shown in Figs. 12A to 12D may represent a color filter array (CFA).

13 is a view showing the structure of various pixel arrays according to an embodiment of the present invention. Referring to FIG. 13, the pixel array according to the present invention may be implemented with various types of pixel arrangements. For example, a pixel array according to the present invention may include pixels arranged in a penta-structure as described with reference to Figs. 1-12.

In addition, the pixel array 410a may include pixels arranged in a stripe structure. Or pixel array 410b may comprise pixels arranged in an S-stripe configuration. Alternatively, the pixel array 410c may include pixels arranged in a delta structure or a diamond structure. That is, the structure of the pixel array according to the present invention is not limited to a specific structure, and can be modified into various pixel arrays or structures.

14 is a block diagram illustrating an exemplary source driver according to an embodiment of the present invention. 14, a source driver 1000 (called a display driving IC (DDI)) includes a source driver 1100, a gamma voltage generator 1200, a power generator 1300, A memory 1400, and a timing controller 1500.

The source driver 1100 may be configured to generate a data signal to be provided with a plurality of pixels. The gamma voltage generator 1200 may be configured to generate gamma voltages necessary for the source driver 1100 to generate a data signal. The power generator 1300 may be configured to generate a power source AVDD_OUT used in the source driver 1000 (or a display device including the source driver). Display memory 1400 may be configured to store image information received from an external (e.g., CPU, GPU, graphics control device, etc.). The timing controller 1500 may be configured to control all operations of the source driver 1000 in response to a control signal CTRL from the outside. The control signal CTRL may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal, and clock signals. The timing controller 1500 can control operations of the source driver 1100, the gate driver (not shown), and the switch driver (not shown) in synchronization with the control signal CTRL. Illustratively, the timing controller 1500 can be configured to output switch signals SW for controlling the switch driver described above.

According to the embodiments of the present invention described above, the display device activates the gate line connected with the pixel having the same pixel color as the last active pixel, and switches the pixel with the same pixel color as the last active pixel, Signals. Illustratively, the order of activation of the gate lines or the order of activation of the switch signals may be performed by the timing controller 1500 of the source driver 1000 or the source driver 1000. The source driver 1000 may be configured to output the data signal corresponding to the active pixel in accordance with the activation sequence of the gate line or the activation sequence of the switch signal.

FIG. 15 is a block diagram illustrating an exemplary touch display device to which the display device according to the present invention is applied. 15, the touch display device 2000 may include a display panel 2100, a DDI 2200 (Display Driving IC), a touch panel 2300, and a TDI 2400 (Touch Driving IC) .

Display panel 2100 can include the pixel array described with reference to Figs. Or the display panel 2100 may include the pixel array, gate driver, or switch driver described with reference to Figs.

The DDI 2200 may control a plurality of pixels included in the display panel 2100 to display image information through a plurality of pixels. Illustratively, the DDI 2200 may be the source driver described with reference to FIGS. Illustratively, the display panel 2100 and the DDI 2200 may display image information based on the operating method described with reference to FIGS.

The touch panel 2300 includes a plurality of touch electrodes for sensing a user's touch. The TDI 2400 may be configured to sense a signal change or a capacitance change on a plurality of touch electrodes, and to sense a user's touch.

Illustratively, the touch panel 2300 may be implemented as an out-cell or on-cell type formed on top of the display panel 2100. Or the display panel 2100 and the touch panel 2300 may be formed of an in-cell type formed on the same semiconductor substrate. Illustratively, the DDI 2200 and the TDI 2300 may be implemented as a single integrated circuit (i.e., touch & display driving IC) to drive the display panel 2100 and the touch panel 2300.

As described above, the display device according to the embodiment of the present invention can activate the gate lines and the switch signals in a non-sequential manner. At this time, the display device is connected to the same data line as the last active pixel and activates the gate lines so that the gate line connected to the pixel having the same pixel color is activated. In addition, the display device activates the switch signals such that the data signal is first provided to the pixel having the same pixel color as the last active pixel. Accordingly, power consumption required for charging the cap on the display panel and power consumption due to the gamma voltage change can be reduced. Therefore, a display device with reduced power consumption and an operation method thereof are provided.

The above description is specific embodiments for carrying out the present invention. The present invention will also include embodiments that are not only described in the above-described embodiments, but also can be simply modified or changed easily. In addition, the present invention will also include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the following claims.

100: display device 110: pixel array
120: gate driver 130: switch driver
140: Source driver

Claims (21)

A plurality of pixels coupled to each of the plurality of gate lines and each of the first and second data lines;
A gate driver for activating the plurality of gate lines;
A switch driver coupled to the first and second data lines and providing a data signal to either the first or second data lines in response to the first and second switch signals; And
Generating the data signal and activating one of the first and second switch signals so that the data signal is provided to a second pixel of the plurality of pixels having the same pixel color as the previously activated first pixel A display device comprising a source driver. The method according to claim 1,
The first pixel is connected to a first one of the plurality of gate lines, the second pixel is connected to a second one of the plurality of gate lines,
Wherein the gate driver activates the first gate line, and thereafter activates the second gate line. 3. The method of claim 2,
Wherein the first and second gate lines are not physically adjacent to each other. 3. The method of claim 2,
Wherein the switch driver is responsive to the first and second switch signals to provide the data signal to a data line of the first and second data lines coupled to the second pixel, And provides a data signal to a third pixel connected to the line. 5. The method of claim 4,
Wherein each of the second and third pixels has a different pixel color. 5. The method of claim 4,
Wherein the gate driver activates the third gate line connected to the fourth pixel among the plurality of gate lines after activating the second gate line,
And the fourth pixel is connected to the same data line as the third pixel and has the same pixel color. The method according to claim 6,
Wherein, in the active period of the third gate line, the switch driver, in response to the first and second switch signals, outputs the data line connected to the fourth pixel among the first data line and the second data line And provides a data signal to a fifth pixel that is subsequently coupled to the third gate line. The method according to claim 1,
Wherein the source driver includes a gamma voltage generator for generating a gamma voltage corresponding to a pixel color of each of the plurality of pixels. The method according to claim 1,
And the source driver includes a source driver for generating a data signal provided to the first and second data lines. The method according to claim 1,
Wherein each of the plurality of pixels is an organic light emitting display pixel. The method according to claim 1,
Wherein the plurality of pixels are arranged in a penta-structure. A method of operating a display device,
Activating a first one of the plurality of gate lines;
Providing a data signal to a first pixel coupled to the first gate line in an active period of the first gate line and then providing a data signal to a second pixel coupled to the first gate line;
Activating a second one of the plurality of gate lines; And
Providing a data signal to a third pixel coupled to the second gate line in an active period of the second gate line and then providing a data signal to a fourth pixel coupled to the second gate line,
Wherein the third pixel is connected to the same data line as the second pixel and has the same pixel color. 13. The method of claim 12,
Activating a third one of the plurality of gate lines; And
Providing a data signal to a fifth pixel coupled to the third gate line in an active period of the third gate line and then providing a data signal to a sixth pixel coupled to the third gate line, ,
Wherein the fifth pixel is connected to the same data line as the fourth pixel and has the same pixel color. 13. The method of claim 12,
Providing a data signal to a first pixel coupled to the first gate line in an active period of the first gate line and subsequently providing a data signal to a second pixel coupled to the first gate line,
Providing a data signal to the first pixel;
Providing a data signal to a fifth pixel coupled to the first gate line; And
And providing a data signal to the second pixel. 13. The method of claim 12,
Wherein the first and second pixels have different pixel colors and the third and fourth pixels have different pixel colors. A plurality of pixels each connected to a plurality of gate lines and a plurality of data lines; And
A peripheral circuit for activating the plurality of gate lines and the plurality of data lines to activate a first one of the plurality of pixels and then activating a second pixel,
Wherein the first and second pixels are connected to different gate lines, connected to the same data line, and have the same pixel color. 17. The method of claim 16,
Wherein the plurality of pixels are arranged in a penta-
Wherein the pixel color of the first and second pixels is either blue or red. 17. The method of claim 16,
The peripheral circuit
A gate driver connected to the plurality of gate lines and activating one of the plurality of gate lines; And
And a switch driver responsive to a switch signal from an external device for activating one of the plurality of data lines to provide a data signal from the external device to the activated data line. 19. The method of claim 18,
Wherein the gate driver activates a first gate line connected to the first pixel among the plurality of gate lines and then activates a second gate line connected to the second pixel. 20. The method of claim 19,
Wherein the switch driver activates a first data line connected to a third pixel connected to the first gate line in an active period of the first gate line in response to the switch signal, Activating a second data line,
In response to the switch signal, activating the second data line connected to the second pixel in the active period of the second gate line, and then activating the first data connected to the fourth pixel connected to the second gate line Display panel to activate the line. A gamma voltage generator configured to generate a gamma voltage corresponding to a pixel color of an external pixel; And
And a source driver for generating a data signal to be provided to the external pixel based on the gamma voltage,
Wherein the source driver generates a data signal at least twice consecutively based on a gamma voltage corresponding to at least the same pixel color.

Images