KR20180090414A - System and method for improving the reliability of wear-leveling by recording and monitoring the number of ldpc decoding interations - Google Patents

Abstract

An embodiment of the present invention relates to a system and a method for improving a wear-reliability by recording and monitoring the number of LDPC decoding iterations. The system comprises: a decoding iteration number recording unit for obtaining decoding iterations number information for each data reading operation, and storing the information with a block unit; and a wear-out monitoring unit for finding wear-out based on the decoding iteration number and the number of times of actually performed writing and erasing. Therefore, the overall durability of an SSD is increased, thereby increasing reliability of the SSD, and reducing the costs required for replacing the SSD.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a system and method for enhancing wear-leveling reliability by recording and monitoring the number of repetitions of LDPC decoding,

The present invention relates to a system and method for improving wear-leveling reliability, and more particularly, to a system and method for improving wear-leveling reliability through recording and monitoring the number of iterations of LDPC decoding.

Solid-state-drive (SSD) is a flash memory-based storage device with high-speed I / O and low power. However, flash memory has a disadvantage in that it has a limited number of write and erase operations. The floating gate of the cell, which is the basic unit for storing the data, is worn out by repeating the write and / or erase process of putting the electrons in and out, resulting in a failure state which is no longer usable. Because of this, the lifetime of the flash memory is limited. The flash memory is made up of a number of blocks, and each block is divided into units called pages. The write operation is performed on a page basis, and the erase operation is performed on a block basis, which leads to a faster failure state when a write or erase operation is concentrated on a specific block or a specific page. A technique called Wear-Leveling is applied to the SSD to prevent this and to increase the overall life of the flash memory. Wear-leveling is to record information related to the number of write and / or erase operations that have been performed on a block-by-block basis, and to equalize the number of operations so as to use all blocks as evenly as possible. However, since complicated semiconductor manufacturing processes are complicated and minute, even the flash memories produced through the same process can not have the same degree of wear. Also, the degree of abrasion between blocks and between pages may be different within a single flash memory to be used. In other words, the maximum number of write and / or erase operations per block and per page may be different within the same SSD. Therefore, it is necessary to grasp the actual wear progress rather than merely considering the number of write and / or erase operations. That is, it is necessary to monitor the wear rate of each block or page constituting the flash memory, and to restrict the use of the relatively rapidly worn portion.

Error Correction Code (ECC) is essential for reliability of SSD. The error correction code can be roughly divided into two processes. First, in the signing process, additional data (redundancy) for error correction is generated before the actual data (message) is stored in the memory, and the data (codeword) of the two is stored in the memory. Second, in the decoding process, if an error occurs in reading the data, the error is eliminated by using the redundancy generated in the coding process. In general, error correction codes applied to SSDs are BCH (Bose, Chaudhri, Hocquenghem) codes. In recent years, application of LDPC (Low-Density Parity-Check) codes with a higher error correction rate has been considered. Unlike the conventional error correction code, the LDPC code changes the codeword to be decoded to stochastic information and then repeats a series of processes. The process is as follows.

① Initialization: Change the codeword to be decoded to probability information and set it in the memory of the decoding circuit

② Check-node update: update the probability information based on the parity-check matrix configuration of the LDPC code

③ Variable - Update node: Determine each bit of code word based on the updated information in ②

④ Parity - Check: Check whether the determined codeword is a valid codeword (all errors are removed)

Unlike the conventional BCH code for error correction of the SSD, the LDPC code performs the first ① once after starting the decoding operation, and then repeats ②, ③ and ④ until a valid codeword is generated. The number of times that it is possible to repeat the above decoding process is limited. If it is not possible to generate a valid codeword even if decoding is repeated a limited number of times, decoding failure is declared and decoding is stopped.

Generally, the more errors included in a codeword, the greater the number of times the decoding is repeated. Therefore, when the LDPC code is applied to the SSD, the increase in the number of decoding iterations indicates that the corresponding block or page contains a large number of errors, which may be a basis for indicating that the wear has progressed.

Korean Patent Laid-Open Publication No. 10-2015-0024489 (publication date: 2015.03.09) Korean Registered Patent No. 10-1484066 (Registration date: Jan. 13, 2013) Korean Registered Patent No. 10-1466555 (Registration date: November 24, 2014)

When the LDPC code is applied as the error correction code of the SSD, the number of decoding iterations can be obtained in the data decoding process of the read operation of the flash memory. The meaning of the number of iterations of decoding in the LDPC code indicates how many times it has been repeated until all the errors are corrected in order to correct the error. Therefore, the more decoding errors are included in the read data, the greater the number of decoding iterations. The occurrence of an error is directly related to the wear of the flash memory. Therefore, the number of decoding iterations can be a basis for predicting the wear of the flash memory.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and it is an object of the present invention to provide a decoding method and a decoding method, Leveling reliability by recording and monitoring the number of iterations of LDPC decoding that can perform flexible wear-leveling that limits the use of relatively rapidly worn blocks.

According to an aspect of the present invention, there is provided a wear-leveling reliability improvement system for recording and monitoring the number of iterations of LDPC decoding, comprising: a flash memory based storage device operating in block or page units, A decoding repetition count recording unit for acquiring decoding repetition count information for each data reading operation and storing the decoding repetition count information for each data reading operation and an abrasion monitoring unit for estimating a wear degree based on the actually performed times of writing and erasing and the number of times of decoding.

Meanwhile, a method for improving wear-leveling reliability by recording and monitoring the number of LDPC decoding repetition counts of the present invention is a flash memory-based storage device that operates on a block or page basis and verifies whether an error has occurred by using an LDPC code, And a wear rate monitoring step of calculating a wear rate based on the number of times of actually performing the write and erase operations and the number of times of the decoding operations.

As described above, the system and method for improving wear-leveling reliability through recording and monitoring the number of repetitions of LDPC decoding according to the present invention provides the following effects.

According to the system and method for improving wear-leveling reliability by recording and monitoring the number of repetitions of LDPC decoding according to the present invention, it is possible to perform flexible wear-leveling on a block basis. In addition, since the number of decoding iterations naturally occurring in the decoding process of the LDPC code in the reading process is used, the overhead of measuring the error rate or the number of errors can be avoided. In addition to the wear-leveling considering the number of decoding iterations, a high lifetime of the SSD can be expected if the high error correction rate of the LDPC code is considered.

FIG. 1 is a block diagram schematically showing a configuration of a whole flash conversion layer of a flash memory to which a system for and method for improving wear-leveling reliability by recording and monitoring the number of repetitions of LDPC decoding according to the present invention is applied.
FIG. 2 is a block diagram schematically illustrating a configuration of a wear-leveling reliability improving system through recording and monitoring the number of repetitions of LDPC decoding according to a preferred embodiment of the present invention.
FIG. 3 is a flowchart schematically illustrating the overall flow of a method for improving wear-leveling reliability by recording and monitoring the number of repetitions of LDPC decoding according to a preferred embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

FIG. 1 is a block diagram schematically showing a configuration of a whole flash conversion layer of a flash memory to which a system for and method for improving wear-leveling reliability by recording and monitoring the number of repetitions of LDPC decoding according to the present invention is applied.

The system and method for improving wear-leveling reliability according to the present invention, which will be described below, are composed of structures for performing mapping, ware-leveling, garbage collection, bad block management, and error correction code located between a flash memory and a file system, It is based on Flash Translation Layer (FTL), which not only performs mapping technology that enables flash memory to be used like a disk, but also compensates for the finite defects of the maximum write / erase count of flash memory sectors As a preferred embodiment.

In this specification, for convenience of description, the wear-leveling system and method according to a preferred embodiment of the present invention is applied to an SSD, but ordinary skill in the art will recognize that the present invention is not limited thereto, As well as any other flash memory based storage devices operating in block or page units such as SSDs.

Hereinafter, a system for improving wear-leveling reliability by recording and monitoring the number of repetitions of LDPC decoding according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram schematically illustrating a configuration of a wear-leveling reliability improving system through recording and monitoring the number of repetitions of LDPC decoding according to a preferred embodiment of the present invention.

2, the wear-leveling system 100 according to the preferred embodiment of the present invention includes a decoding repeat count recording unit 110 for obtaining decoding repeat count information for each data read operation and storing the decoding repeat count information for each block, And an abrasion monitoring unit 120 for calculating a wear rate based on the actual number of times of writing and erasing and the number of times of decoding.

The small unit constituting the flash memory is a cell, and the wear of each cell, that is, the maximum number of write and erase operations may be different. Therefore, the degree of wear of the cells may vary depending on the pages constituting the cells and the blocks constituted by the pages. Since wear-leveling is usually performed in block units of flash memory, it is necessary to record the number of decoding iterations for wear monitoring in block units. Accordingly, the decoding repeat number recording section 110 acquires the decoding repeat number information for each data reading operation from the error correction code checking configuration (FIG. 1) and stores it in the decoding repeat number table of the block unit as shown in FIG. 2 .

The information on the number of decoding iterations can be obtained in the read operation of the flash memory, and the normal read operation is performed on a page basis instead of the block. Therefore, the decoding repeat number recording section 110 generalizes the number of decoding iterations obtained in units of pages on a block-by-block basis. The information recorded in the block-by-block decoding repeat count table is the number ( cnt _i ) of decoding repetitions per block, and the formula for obtaining cnt _i is as follows:

The decoding repeat number recording section 110 first sets the value of the block unit repeat number cnt _i at the beginning (before the first read operation in the block) to a basic value (e.g., 1 or 0). Then, cnt _i is updated as shown in Equation (1) based on the number of decoding iterations ( cnt _ipage ) obtained from the page unit read operation and the cnt _i previously held. Here, a plays a role of adjusting the average decoding repeat number of the block and the decoding repeat number weight of the corresponding page. For example, if write and erase and read operations occur frequently in the block, you can rely on cnt _i , otherwise you can increase the weight of cnt _ipage . In addition, in a flash memory, a block is composed of a plurality of pages, and a read operation is generally more frequently performed than a write and erase operation. Therefore, updating the cnt _i value every time a page read operation occurs may cause a performance overhead. Therefore, it is necessary to adjust the period of updating the cnt _i value through a value or to update the cnt _i value .

Next, the wear rate monitoring unit 120 obtains the wear rate per block based on the number of times of actual writing and erasure performed and the number of times of decoding iterations calculated in Equation (1), and provides it to a wear-leveling configuration (FIG. 1) To perform flexible wear-leveling that controls the number of star write and erase operations. The wear amount ( age ) of each block is expressed by the following equation (2).

Cnt _pe in Equation (2) for obtaining the wear rate per block Cnt _i represents the average number of decoding repetitions of the block, and cnt _imax represents the maximum number of decoding iterations set in the LDPC code applied to the corresponding SSD. Here, b is a variable for adjusting the weight between the number of actual write and erase times to obtain the wear rate and the number of times of decoding. For example, if the value of b is 1, the degree of wear depends only on the number of actual write and erase operations. If the value of b is 0, it depends on the number of times of decoding. Therefore, the setting of the b value can be adjusted according to the characteristics of the SSD and the flash memory, and the period of use or the surrounding environment.

Looking in more detail for the cnt _{imax, imax} cnt represents the maximum number of times to repeat the series of processes discussed in the technical section of the background of the invention in the LDPC code decoding process. In the LDPC code, even if the error rate is high or the decoding process is repeated infinitely according to the pattern of the error, the error can not be corrected. In order to prevent this, there is a maximum number of iterations. That is, when the repetition of decoding reaches the maximum number of decoding iterations, decoding failure is declared and decoding is stopped.

As a result, the age indicating the wear rate per block is a value for comparing the inter-block wear, and is used to determine which block the write and erase operations should be performed on, and determines the life (maximum write and erase count) It is not used.

Hereinafter, a method for improving the wear-leveling reliability by recording and monitoring the number of repetitions of LDPC decoding according to a preferred embodiment of the present invention using the system configured as described above will be described. This will be described in detail as follows.

FIG. 3 is a flowchart schematically illustrating the overall flow of a method for improving wear-leveling reliability by recording and monitoring the number of repetitions of LDPC decoding according to a preferred embodiment of the present invention.

Referring to FIG. 3, in the wear-leveling method according to the preferred embodiment of the present invention, the wear-leveling reliability improving system 100 of the present invention first acquires information on the number of decoding repetitions for each data reading operation, And the number of times of decoding repetition is recorded (step S310). The detailed description of the operation of updating the number of decoding iterations in the corresponding step is as described above with respect to the number of times of decoding iterations 110.

Next, the wear-leveling reliability improving system 100 performs a wear rate monitoring step of obtaining a wear rate based on the number of actually performed write and erase operations and the number of decoding iterations obtained in step S310 (step S320). A detailed description of the operation of obtaining the wear rate at the corresponding step is as described above with respect to the wear rate monitoring unit 120. [

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the present invention is not limited to the disclosed exemplary embodiments, but various modifications may be made without departing from the spirit of the invention.

100: Software - Leveling Reliability Enhancement System
110: Number of times of repetition of decoding
120: abrasion monitoring unit

Claims (6)

A flash memory-based storage device operating in units of blocks or pages and verifying an error by using an LDPC code,
A decoding repeat number recording section for obtaining decoding repeat number information for each data read operation and storing the decoding repeat number information in units of blocks;
And a wear rate monitoring unit for calculating a wear rate based on the number of times of actually performing the writing and erasing and the number of times of decoding. The method according to claim 1,
Wherein the decoding repetition number recording unit generalizes the number of decoding repetitions per page unit to the number of decoding repetitions per block through the following equation:

In the above equation, cnt _i is the number of repetitions of block unit decoding, cnt _ipage is the number of repetitions of page unit decoding, and a is a variable for adjusting the average decoding repetition count of the block and the decoding repetition count weight of the page. The method of claim 2,
The wear-level monitoring unit obtains wear-level through the following equation: Wear-leveling reliability improvement system:

In the above equation, age is the degree of wear and cnt _pe is Is the current practice to perform the write and erase count up to the corresponding block, cnt _i is the average decoding iteration count for the block, cnt _imax is the maximum decoding iteration count set in the applied LDPC code in the storage device, b is the actual obtaining the degree of wear Is a variable for adjusting the weight between the number of times of writing and erasing and the number of times of decoding. A flash memory-based storage device operating in units of blocks or pages and verifying an error by using an LDPC code,
A decoding repeat number recording step of obtaining decoding repeat number information for each data read operation and storing the decoding repeat number information in units of blocks;
And a wear degree monitoring step of calculating a wear degree based on the number of actual write and erase operations and the number of repetition of decoding. The method of claim 4,
Wherein the step of recording the number of times of decoding repeats is a step of generalizing the number of decoding iterations in units of pages to the number of iterations of decoding in units of blocks through the following equation:

In the above equation, cnt _i is the number of repetitions of block unit decoding, cnt _ipage is the number of repetitions of page unit decoding, and a is a variable for adjusting the average decoding repetition count of the block and the decoding repetition count weight of the page. The method of claim 5,
Wherein the wear rate monitoring step calculates a wear level through the following equation: Wear-leveling reliability improvement method:

In the above equation, age is the degree of wear and cnt _pe is Is the current practice to perform the write and erase count up to the corresponding block, cnt _i is the average decoding iteration count for the block, cnt _imax is the maximum decoding iteration count set in the applied LDPC code in the storage device, b is the actual obtaining the degree of wear Is a variable for adjusting the weight between the number of times of writing and erasing and the number of times of decoding.

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