KR20180074857A - Substrate for Thin Film Transistor And Display Device Of The Same - Google Patents

Abstract

The present invention provides an array substrate for a thin film transistor, in which an active layer including a carbon allotrope is formed to improve characteristic of an element, and a display device comprising the array substrate. An array substrate for a thin film transistor according to an embodiment of the present invention includes a substrate, a gate electrode, an active layer, a gate insulating film, a source electrode, a drain electrode, a first auxiliary electrode, and a second auxiliary electrode. Additionally, the gate electrode is positioned on the substrate. The active layer is opposite to the gate electrode, and includes a first carbon allotrope and a semiconductor material. The gate insulating film is interposed between the gate electrode and the active layer. Each of the source electrode and the drain electrode is in contact with the active layer. The first auxiliary electrode is arranged between the active layer and the gate insulating film, and is in contact with a part of the bottom surface of the active layer. The second auxiliary electrode is in contact with a part of the bottom surface of the active layer.

Description

TECHNICAL FIELD [0001] The present invention relates to a thin film transistor array substrate and a display device including the thin film transistor array substrate.

The present invention relates to a thin film transistor array substrate and a display device including the same.

2. Description of the Related Art In recent years, the importance of a flat panel display (FPD) has been increasing with the development of multimedia. In response to this, a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), an organic light emitting display Various displays are put into practical use.

A passive matrix method and an active matrix method using a thin film transistor are used for driving the display device. In the passive matrix method, an anode and a cathode are formed so as to be orthogonal to each other and a line is selected and driven. In contrast, the active matrix method is a method in which a thin film transistor is connected to each pixel electrode to perform on / off switching.

Thin film transistors are important not only for the basic characteristics of thin film transistors such as electron mobility and leakage current, but also for durability and electrical reliability that can maintain a long lifetime. Here, the active layer of the thin film transistor may be formed mainly of amorphous silicon, polycrystalline silicon, or oxide semiconductor. However, amorphous silicon is advantageous in that the film forming process is simple and the production cost is low, but the electron mobility is as low as 0.5 cm 2 / Vs. The oxide semiconductor has an on / off ratio of about 10 ⁸ and a low leakage current, but has an electron mobility of 10 cm 2 / Vs, which is lower than that of polycrystalline silicon. The polycrystalline silicon has a high electron mobility of about 100 cm 2 / Vs, but has a disadvantage in that it has a low on / off ratio compared to oxide semiconductors and is expensive to be applied to a large area. Therefore, studies for improving characteristics such as electron mobility, leakage current, and on / off ratio of the thin film transistor have been continued.

The present invention provides a thin film transistor array substrate and a display device including the thin film transistor array substrate, which can improve an element characteristic by forming an active layer including a carbon isotope.

In order to achieve the above object, a thin film transistor array substrate according to an embodiment of the present invention includes a substrate, a gate electrode, an active layer, a gate insulating film, a source electrode, a drain electrode, a first auxiliary electrode and a second auxiliary electrode . The gate electrode is located on the substrate. The active layer is opposite the gate electrode and comprises a first carbon isotope and a semiconductor material. A gate insulating film is interposed between the gate electrode and the active layer. The source electrode and the drain electrode respectively contact the active layer. The first auxiliary electrode is disposed between the active layer and the gate insulating film and contacts a part of the lower surface of the active layer, and the second auxiliary electrode contacts a part of the lower surface of the active layer.

The active layer includes a first region which contacts and overlaps with the first auxiliary electrode, a second region which contacts and overlaps with the second auxiliary electrode, and a third region which is in contact with the gate insulating film.

The plane area of the first region and the second region is 30 to 60% of the plane area of the active layer.

The third region overlaps the channel of the active layer.

The first auxiliary electrode contacts the source electrode and the second auxiliary electrode contacts the drain electrode.

The first auxiliary electrode is disposed below the source electrode and the active layer, and the second auxiliary electrode is disposed below the drain electrode and the active layer.

The first auxiliary electrode is disposed above the source electrode, and the second auxiliary electrode is disposed above the drain electrode.

The first auxiliary electrode and the second auxiliary electrode are made of a second carbon isotope.

The first carbon isotope and the second carbon isotope are any one or a mixture of reduced graphene oxide (rGO), non-oxidized graphene, graphene nanoribbon or carbon nanotube (CNT).

The semiconductor material is any one of a ceramic semiconductor, an organic semiconductor, a transition metal chalcogenide compound, or an oxide semiconductor, or a mixture thereof.

A thin film transistor array substrate according to an embodiment of the present invention includes a substrate, a gate electrode, an active layer, a gate insulating film, a source electrode, and a drain electrode. The gate electrode is located on the substrate. The active layer is opposed to the gate electrode and comprises metal nanoparticles, a first carbon isotope and a semiconductor material. A gate insulating film is interposed between the gate electrode and the active layer. The source electrode and the drain electrode respectively contact the active layer.

The plurality of metal nanoparticles are spaced apart at regular intervals.

According to another aspect of the present invention, there is provided a display device including: a thin film transistor array substrate; An organic insulating film located on the thin film transistor array substrate, and a pixel electrode located on the organic insulating film.

An organic light emitting diode electrically connected to the pixel electrode, an encapsulation layer disposed on the organic light emitting diode, and a cover window disposed on the encapsulation layer.

A common electrode spaced from the pixel electrode in the same plane or lower region, and a liquid crystal layer disposed on the common electrode.

The thin film transistor array substrate according to an embodiment of the present invention includes a carbon isotope and conductive metal nanoparticles which are conductive in a semiconductor material and thus carriers can move along the carbon isotope and the metal nanoparticles to improve the charge mobility There is an advantage.

The thin film transistor array substrate according to an embodiment of the present invention includes a first auxiliary electrode and a second auxiliary electrode made of a carbon isotope between a source electrode and a drain electrode and an active layer, Layer is provided, there is an advantage that the contact resistance between the source electrode and the drain electrode and the active layer can be reduced and the charge mobility can be improved.

1 is a cross-sectional view of a thin film transistor array substrate according to a first embodiment of the present invention;
FIG. 2 is a cross-sectional view of the active layer of FIG. 1, and FIG. 3 is a cross-sectional view of a charge transfer path of the active layer of the present invention.
4 to 6 are cross-sectional views illustrating a manufacturing process of a thin film transistor array substrate according to a first embodiment of the present invention;
7 and 8 are cross-sectional views illustrating a thin film transistor array substrate according to a second embodiment of the present invention.
9 is a sectional view showing a thin film transistor array substrate according to a third embodiment of the present invention.
10 is a cross-sectional view illustrating a liquid crystal display device according to an embodiment of the present invention.
11 is a cross-sectional view illustrating an organic light emitting display according to an embodiment of the present invention.
12 is a graph showing drain currents according to gate voltages of thin film transistors manufactured according to Comparative Examples 1 and 2 and Example.
13 is a graph showing the charge mobility of the thin film transistor manufactured according to Comparative Examples 1 and 2 and Example.
14 is a graph showing the charge mobility and flicker ratio of the thin film transistor manufactured according to the embodiment.
15 is a SEM image of region A of Fig.
16 is an SEM image of region B in Fig. 8;
17 is a SEM image showing the C region in Fig.
18 is an SEM image showing the area D in Fig.
19 to 21 are graphs of Raman analysis of the thin film transistor manufactured according to the embodiment.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. It should be noted that, in adding reference numerals to the constituent elements of the drawings, the same constituent elements are denoted by the same reference symbols as possible even if they are shown in different drawings. In the following description of the embodiments of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are intended to distinguish the constituent elements from other constituent elements, and the terms do not limit the nature, order or order of the constituent elements. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected to or connected to the other component, It should be understood that an element may be "connected," "coupled," or "connected." In the same context, when an element is described as being formed on an "upper" or "lower" side of another element, the element may be formed either directly or indirectly through another element As will be understood by those skilled in the art.

The display device according to the present invention described below may be an organic light emitting display device, a liquid crystal display device, an electrophoretic display device, or the like. In the present invention, a liquid crystal display device will be described as an example. The liquid crystal display device includes a thin film transistor array substrate on which a pixel electrode and a common electrode are formed on a thin film transistor, a color filter substrate, and a liquid crystal layer interposed between the two substrates. In such a liquid crystal display device, The liquid crystal is driven by an electric field which is horizontally applied. The display device according to the present invention can also be used in an organic light emitting display. For example, an organic light emitting display includes a first electrode connected to a thin film transistor, a second electrode, and a light emitting layer made of organic material therebetween. Therefore, the holes supplied from the first electrode and the electrons supplied from the second electrode are combined in the light emitting layer to form an exciton as a hole-electron pair, and the excitons emit light by energy generated as they return to the ground state. The active layer containing the carbon isotope of the present invention described later can be used in the thin film transistor of the above-described display device.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

The present invention discloses an active layer comprising a carbon isotope and a semiconductor material, and specifically discloses a thin film transistor array substrate on which an active layer comprising a carbon isotope and a semiconductor material is formed. The thin film transistor is used as a switching element or a driving element of a display device.

Carbon allotrope

The carbon isotope disclosed in the present invention represents a polycyclic aromatic molecule having carbon atoms covalently bonded to each other. A covalently bonded carbon atom may form a ring of six constituent units as a repeating unit, and may also include at least one of a ring of five constituent units and a ring of seven constituent unit. The carbon isotope may be a single layer or it may comprise a plurality of carbon isotope layers stacked on different layers of the carbon isotope. The carbon isotope has a one-dimensional or two-dimensional structure. The carbon isomer has a maximum thickness of about 100 nm, specifically about 10 nm to about 90 nm, and more specifically about 20 nm to about 80 nm.

There are four methods for producing the carbon isotope, such as a physical exfoliation method, a chemical vapor deposition method, a chemical exfoliation method, or an epitaxial synthesis method. In the physical exfoliation method, a scotch tape is attached to a graphite sample, and then the scotch tape is peeled off to obtain an allotment sheet of carbon off the graphite on the surface of the scotch tape. The chemical vapor deposition method adsorbs and decomposes carbon precursor in gas or vapor form with high kinetic energy on the surface of the substrate on which the carbon isotope is to be grown, separates the carbon precursor into carbon atoms and causes the carbon atoms to bond to each other, . The chemical stripping method utilizes the oxidation-reduction properties of graphite. The graphite is put into a mixture of sulfuric acid and nitric acid, and a carboxyl compound is attached to the edges of the carbon homogeneous plates. It is converted to the acid chloride by the chlorinated thinol, and again the octadecylamine is used to make the carbon isomer amide. When this is recycled using a solution such as tetrahydrofuran, pulverization occurs to obtain individual carbon isotope sheets. In the epitaxial synthesis method, silicon carbide (SiC) is heated to a high temperature of 1,500 ° C to remove silicon (Si), and carbon isotope is obtained by the remaining carbon (C).

The carbon isotope of the present invention can use reduced graphene oxide (rGO), non-oxidized graphene or graphene nanoribbon, carbon nanotube (CNT), or the like. Reduced graphene oxide is produced by reducing graphene oxide (GO). When a strong acid is added to graphite, it is oxidized and formed into a chemically small particle state to produce graphene oxide and reduce graphene oxide. Non-oxidized graphene refers to a carbon isotope prepared by a method other than the oxidation-reduction process among the above-mentioned methods for producing an isotopic carbon. Graphene nanoribbons are graphenes cut into nanometer (nm) wide ribbon, with a constant energy bandgap along the width. The graphene nanoribbons can be synthesized from monomers containing carbon isotopes or can be prepared by cutting and flattening carbon nanotubes. The carbon nanotubes can be single-wall carbon nanotubes (SWCNTs) or multi-wall carbon nanotubes (MWCNTs). The carbon nanotubes can be semiconducting or metallic Carbon nanotubes can also be used. In addition to the above-mentioned types of carbon isotopes, the carbon isotopes of the present invention can employ known carbon isotopic structures such as graphene nanomesh.

The carbon isotope of the present invention is used in the form of flakes. The carbon isotopic flakes can be prepared by coating the dispersion on a substrate using a dispersion in which the carbon isotope is dispersed in a solvent, drying the solvent, and then applying physical force. As a method of applying a physical force, a carbon isotopic flake can be obtained by a method such as a ball mill, a bead mill, an ultrasonic homogenizer, and stirring.

Semiconductor material

The semiconductor material of the present invention may be a ceramic semiconductor, an organic semiconductor, a transition metal chalcogenide compound or a material capable of being coated with a solution with an oxide semiconductor.

Ceramic semiconductors are based on the electrical properties of ceramics. Since ceramics are bound to certain ions or atoms, they can not move freely, so electricity is hardly conducted. When an electric field is applied from the outside, The electrons move as the state is changed by generating an array. Ceramic semiconductors are made of metal elements such as silicon (Si), germanium (Ge), selenium (Se), aluminum (Al), titanium (Ti), zirconium (Zr) ), And the like, and is made of an oxide, a carbide, and a nitride. A typical ceramic semiconductor is barium titanate (BaTiO ₃ ).

An organic semiconductor is an organic compound having semiconductor characteristics, and may be a polymer organic semiconductor or a low molecular weight organic semiconductor. Examples of the polymer organic semiconductor include F8T2 (Poly [(9,9-dioctylfluorenyl-2,7-diyl) -co-bithiophene], PBDTBOTPDO (Poly [(5,6-dihydro- 4H-thieno [3,4-C] pyrrole-1,3-diyl) {4,8-bis [(2-butyloctyl) oxy] benzo [1,2- b: 4,5- b '] dithiophene- , 6-diyl}], PBDT-TPD (Poly [[5- (2-ethylhexyl) -5,6-dihydro-4,6-dioxo-4H-thieno [ 2,6-diyl]), PBDTTT-CF (Poly [1, 2-biphenyl- - (6- {4,8-bis [(2-ethylhexyl) oxy] -6-methylbenzo [1,2-b: 4,5- bithiothiophen-2-yl} -3-fluoro-4- [3,4-b] thiophen-2-yl) -1-octanone]), PCDTBT (Poly [N-9'-heptadecanyl-2,7- di [2-thienyl] -2 ', 1', 3'-benzothiadiazole)], Poly [[9- (1-octylononyl) -9H- , 3-benzothiadiazole-4,7-diyl-2,5-thiophenediyl]), PCPDTBT (Poly [2,6- (4,4-bis- (2-ethylhexyl) -4H-cyclopenta [2,1-b; 3,4-b '] dithiophene) -tallow-4,7 (2,1,3-benzothiadiazole)]), PFO-DBT (Poly [2,7- (9,9-dioctylfluorene) -bis (thiophen-2-yl) benzo-2,1,3-thiadiazole]), PTAA (Poly [(5,6-dihydro-5-octyl-4,6-dioxo-4H-thieno [3,4- c] pyrrole-1,3-diyl) [4,8-bis [(2-ethylhexyl) oxy] benzo [1,2- b: 4,5- b '] dithiophene-2,6-diyl] (Poly [(9,9-di-n-octylfluorenyl-2,7-diyl) -tallow- (benzo [2,1,3] thiadiazol-4,8-diyl)], P3DDT (Poly (3- dodecylthiophene -2,5-diyl), P3HT (Poly (3-hexylthiophene-2,5-diyl)), MDMOPPV (Poly [2-methoxy-5- (3 ', 7'-dimethyloctyloxy) ), MEH-PPV (Poly (3-octylthiophene-2,5-diyl), PTB7 (Poly (2-methoxy-5- 2,8-bis [(2-ethylhexyl) oxy] benzo [1,2-b: 4,5-b '] dithiophene-2,6-diyl {3-fluoro-2- ] thieno [3,4-b] thiophenediyl})).

Examples of low-molecular organic semiconductors include TIPS-pentacene (6,13-bis (triisopropylsilylethynyl) pentacene), TESPentacene (6,13-Bis (triethylsilyl) ethynyl) pentacene, DH-FTTF (2,8-Difluoro-5,11-bis (triethylsilylethynyl) anthradithiophene), DH2T (5,5-hexafluorophenyl) -Dihexyl-2,2'-bithiophene), DH4T (3,3 '' - Dihexyl-2,2 ': 5', 2 '': 5 '', 2 '' '- quaterthiophene), DH6T , 5 '' '' - Dihexyl-2,2 ': 5', 2 '': 5 '', 2 '' ': 5' '', 2 ' (2-ethylhexyl) -4H-silolo [3,2-b: 4,5-b '] dithiophene-2-carboxylate, DTS (PTTh2) 2 (4,4' 2,6-diyl] bis [7- (5'-hexyl- [2,2'-bithiophen] -5- yl) - [1,2,5] thiadiazolo [ 2 ', 5'-Bis {[4- (7-hexylthiophen-2-yl) thiophen-2-yl] - [1,2,5] thiadiazolo [3,4- c] pyridine} -3,3'- -ethylhexylsilylene-2,2'-bithiophene), SMDPPEH (2,5-Di- (2-ethylhexyl) -3,6-bis- (5'-n-hexyl- [2,2 ', 5', 2 5-yl) -pyrrolo [3,4-c] pyrrole-1,4-d] pyrimidin- ion and TES-ADT (5,11-bis (triethylsilylethynyl) anthradithiophene).

The organic semiconductor may use two or more kinds of polymer organic semiconductors and low molecular weight organic semiconductors, different polymer organic semiconductors, or different low molecular organic semiconductors.

Transition metal dichalcogenides are materials having semiconductor properties such as transition metal sulfides, transition metal selenides, transition metal tellurides, and the like. As the transition metal chalcogen compound, for example, SnSe ₂ , CdSe, ZnSe, ZnTe, MoS ₂ , MoSe ₂ , MoTe ₂ , WS ₂ , WSe ₂ , WTe ₂ and the like can be used.

Oxide semiconductors are materials having semiconductor properties and include metals such as gallium (Ga), indium (In), zinc (Zn), tin (Sn), silicon (Si), and zirconium (Zr) Oxide. As an example of the oxide semiconductor, IGZO, In ₂ O ₃ , ZnO, IZO, IGO and the like can be used, but known materials can be used without being limited thereto.

Hereinafter, a thin film transistor array substrate and a display device including the above-mentioned carbon isotope and a semiconductor material will be described.

FIG. 1 is a cross-sectional view of a thin film transistor array substrate according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view illustrating the active layer of FIG. 1, FIG. 3 is a cross- And FIGS. 4 to 6 are cross-sectional views illustrating a manufacturing process of the thin film transistor array substrate according to the first embodiment of the present invention.

Thin film transistor  Array substrate

The thin film transistor array substrate disclosed in the present invention will be described by taking as an example a bottom-gate type thin film transistor in which a gate electrode is located under an active layer. However, the present invention is not limited thereto, and all structures of known thin film transistors such as a top-gate type thin film transistor in which a gate electrode is located on an active layer can be applied.

Referring to FIG. 1, a gate electrode 120 is disposed on a substrate 110. The substrate 110 is made of transparent or opaque glass, plastic or metal. The gate electrode 120 may be formed of a metal such as copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), tantalum And tungsten (W), or an alloy thereof. A gate insulating film 130 for insulating the gate electrode 120 is disposed on the gate electrode 120. The gate insulating film 130 is formed of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.

An active layer 140 is located on the gate insulating film 130. The active layer 140 is composed of a carbon isotope and a semiconductor material.

Referring to FIG. 2, the active layer 140 of the present invention includes a semiconductor material OC, a plurality of carbon isotopes (CNT), and a plurality of metal nanoparticles (MN). The semiconductor material OC forms the main body of the active layer 140, which allows the active layer 140 to function as a semiconductor to control the threshold voltage. The plurality of carbon isotopes (CNTs) allow carriers to rapidly move through the conductive carbon isotope (CNT), thereby increasing the charge mobility of the active layer 140. The plurality of metal nanoparticles (MN) enable charges to move rapidly through the conductive metal nanoparticles (MN), thereby increasing the charge mobility of the active layer (140).

The metal nanoparticles MN may be made of a metal material such as molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium ), Copper (Cu), or an alloy thereof. However, the metal nanoparticles (MN) of the present invention are not limited thereto, and any known metal materials can be used.

In addition, the metal nanoparticles (MN) can be dispersed in the active layer 140 with a particle diameter of several to several hundred nanometers. At this time, the metal nanoparticles (MN) may be spaced apart from each other at regular intervals in order to exhibit uniform charge mobility in the active layer 140.

Referring again to FIG. 1, a source electrode 150a, which contacts one side of the active layer 140, and a drain electrode 150b, which contacts the other side of the active layer 140, are located on the active layer 140. The source electrode 150a and the drain electrode 150b may be formed of a single layer or a multilayer. In the case of a single layer, Mo, Al, Cr, Au, Ti, (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. Aluminum or neodymium, molybdenum / aluminum or titanium / aluminum or molybdenum / aluminum / neodymium / molybdenum, molybdenum / aluminum / molybdenum or titanium / Aluminum / titanium. ≪ / RTI >

Referring to FIG. 3, when the source electrode 150a and the drain electrode 150b are energized, the active layer 140 of the present invention moves carriers and electrons to the channel of the active layer 140. Since the active layer 140 is composed of carbon nanotubes (CNTs), metal nanoparticles (MN), and semiconductor materials (OC), electrons and holes are transported to the CNTs and the metal nanoparticles And moves in accordance with the charge mobility of the semiconductor material OC in the semiconductor material OC. Therefore, electrons and holes move along the carbon nanotubes (CNT) and the metal nanoparticles (MN) in the semiconductor material (OC), and the charge mobility can be greatly improved.

A thin film transistor array substrate including the above-described active layer 140 can be manufactured as follows.

Referring to FIG. 4, a gate electrode material is deposited on a substrate 110 and patterned to form a gate electrode 120. A gate insulating layer 130 is formed by depositing a gate insulating layer material on the entire surface of the substrate 110 including the gate electrode 120. Next, the metal nanoparticles (MN) are formed by coating a solution in which the metal nanoparticles (MN) are mixed on the gate insulating film 130 and drying the solution. At this time, the metal nanoparticles (MN) are formed only in a region where the active layer 140 is formed later.

Next, referring to FIG. 5, a semiconductor solution in which a carbon isotope (CNT) and a semiconductor material (OC) are mixed is manufactured. The semiconductor solution may be prepared by mixing powdery carbon isotopes and semiconductor materials in a solvent, or may be prepared by mixing a carbon precursor solution with a semiconductor precursor solution. To better disperse the carbon isotope and the semiconductor material, other additives may be added or an ultrasonic wave may be applied. In the case of irradiating the semiconductor solution mixed with the carbon isotope with ultrasonic waves, it is preferable to irradiate ultrasonic waves several times. For example, the carbon isotope is mixed with the semiconductor precursor solution and irradiated with a strong ultrasonic wave (about 250 W) with an ultrasonic wave crusher for about 30 minutes. By repeating such a process, a semiconductor solution in which carbon isotopes are well dispersed can be produced.

The amount of the carbon isotope used in the semiconductor solution of the present invention may be 0.0001 to 1% by weight based on 100% by weight of the semiconductor precursor solution. Here, if the carbon isotope is 0.0001 wt% or more based on 100 wt% of the semiconductor precursor solution, the charge mobility characteristics can be improved. If the carbon isotope is 1 wt% or less based on 100 wt% of the semiconductor precursor solution, Can be improved and the coating property can be improved.

The semiconductor solution thus prepared is coated on the substrate 110 on which the metal nanoparticles MN are formed and dried to form the active layer 140 including the metal nanoparticles MN. As a method of coating a semiconductor solution, spin coating, slit coating, screen printing, ink-jet printing, or the like can be used. Any method is applicable. Then, the coating film is heat-treated at 250 ° C for 2 hours to remove the solvent, and then patterned by photolithography to produce the active layer 140 of the present invention. The active layer 140 thus formed may have a structure in which metal nanoparticles (MN) and carbon isotopes (CNTs) are dispersed in a semiconductor material (OC).

As described above, the thin film transistor array substrate according to the first embodiment of the present invention includes the carbon isotope and the metal nanoparticles which are conductive in the semiconductor material, so that the carriers move along the carbon isotope and the metal nanoparticles, There is an advantage that the degree of freedom can be improved.

FIGS. 7 and 8 are cross-sectional views illustrating a thin film transistor array substrate according to a second embodiment of the present invention, and FIG. 9 is a cross-sectional view illustrating a thin film transistor array substrate according to a third embodiment of the present invention. The description of the same configuration as that of the first embodiment described above will be omitted.

7, in the thin film transistor array substrate according to the second embodiment of the present invention, a gate electrode 220 is disposed on a substrate 210, and a gate insulating film 230 is disposed on the gate electrode 220 .

A first auxiliary electrode 260a and a second auxiliary electrode 260b are disposed on the gate insulating layer 230. [ The first auxiliary electrode 260a and the second auxiliary electrode 260b are spaced apart from each other with a source electrode 250a disposed on the first auxiliary electrode 260a and a drain electrode 250b disposed on the second auxiliary electrode 260b, An electrode 250b is disposed. The active layer 240 is disposed on the first auxiliary electrode 260a and the second auxiliary electrode 260b and on the gate insulating layer 230. [ The active layer 240 includes a semiconductor material (OC) in which a first carbon isotope (CNT) is dispersed. One side of the active layer 240 is in contact with the source electrode 250a and the other side is in contact with the drain electrode 250b.

More specifically, the first auxiliary electrode 260a and the second auxiliary electrode 260b are made of a second carbon isotope. The first carbon isotope (CNT) and the second carbon isotope of the active layer 240 are composed of a homogeneous carbon isotope. For example, the first carbon isotope (CNT) and the second carbon isotope may be any one of reduced graphene oxide (rGO), non-oxidized graphene, graphene nanoribbon, or carbon nanotube (CNT) Lt; / RTI > In an embodiment of the present invention, the first carbon isotope (CNT) included in the active layer 240 is a carbon nanotube and the second carbon isotope is a reduced graphene oxide (rGO), a non-oxidized graphene or a graphene It is the selected graphene among the nanoribbons. The first auxiliary electrode 260a and the second auxiliary electrode 260b are formed to have a thickness of 1 to 50 nm to form a contact between the source electrode 250a and the active layer 240 and between the drain electrode 250b and the active layer 240. [ The resistance can be lowered and the carrier mobility can be increased to improve the charge mobility.

The active layer 240 includes a first region AT1 in contact with and a first auxiliary electrode 260a and a second region AT2 in contact with the second auxiliary electrode 260b and a gate insulating layer 230, And a third area AT3 for contact. The first auxiliary electrode 260a of the present invention contacts the lower surface of the first region AT1 of the active layer 240 while making contact with the source electrode 250a. Particularly, one side of the first auxiliary electrode 260a contacts the side surface of the third region AT3 of the active layer 240. [ The third region AT3 of the active layer 240 is a region corresponding to a channel. The carrier injected from the source electrode 250a may move to the third region AT3 through the first auxiliary electrode 260a, which is the channel of the active layer 240. [

The second auxiliary electrode 260b of the present invention contacts the bottom surface of the second area AT2 of the active layer 240 while contacting the drain electrode 250b. Particularly, one side of the second auxiliary electrode 260b contacts the side surface of the third region AT3 of the active layer 240. [ The carrier moving through the channel of the third region AT3 of the active layer 240 may move to the drain electrode 250b through the second auxiliary electrode 260b. In addition, the active layer 240 of the present invention includes a semiconductor material (OC) in which a plurality of carbon isotopes (CNTs) are dispersed. Carriers moving within the active layer 240 can move very fast on the carbon nanotubes (CNT) and move in accordance with the charge mobility of the semiconductor material OC in the semiconductor material OC.

Referring to FIG. 8, the movement path TP of the carrier in the thin film transistor array substrate of the present invention is as follows. The carriers injected from the source electrode 250a travel very quickly at the first auxiliary electrode 260a made of graphene close to the conductor and are injected into the active layer 240. [ Since the channel CH of the active layer 240 includes a plurality of carbon isotopes (CNTs) and a semiconductor material (OCs), the injected carriers move very quickly on the carbon isotope (CNT). The carriers that have passed through the channel CH of the active layer 240 move very quickly from the second auxiliary electrode 260b made of graphene close to the conductor once again to move to the drain electrode 250b.

The active layer 240 of the present invention includes a first area AT1 in contact with and overlapping with the first auxiliary electrode 260a with respect to a plane area of the entire active layer 240 and a second area AT1 in contact with the second auxiliary electrode 260b, The area of the second area AT2 occupying 30% to 60% of the area. Here, if the plane area of the first region AT1 and the second region AT2 is 30% or more as compared with the plane area of the entire active layer 240, the charge mobility of the active layer can be improved and the total active layer 240 It is possible to prevent the active layer 240 from being substantially conductive and fail to serve as a switching region when the planar area of the first region AT1 and the second region AT2 is 60%

The thin film transistor array substrate according to the second embodiment of the present invention includes a first auxiliary electrode and a second auxiliary electrode made of a carbon isotope between a source electrode and a drain electrode and an active layer, By providing the active layer, there is an advantage that the contact resistance between the source electrode and the drain electrode and the active layer can be reduced and the charge mobility can be improved.

Meanwhile, in the thin film transistor array substrate of the present invention, the positions of the first auxiliary electrode 260a and the second auxiliary electrode 260b may be different from those of the second embodiment.

9, in the thin film transistor array substrate according to the third embodiment of the present invention, a gate electrode 220 is disposed on a substrate 210, and a gate insulating layer 230 is disposed on the gate electrode 220 . A source electrode 250a and a drain electrode 250b are disposed on the gate insulating film 230 so as to be spaced apart from each other. A first auxiliary electrode 260a is disposed on the source electrode 250a and a second auxiliary electrode 260b is disposed on the drain electrode 250b. The first auxiliary electrode 260a extends from the upper surface of the gate insulating layer 230 along the upper portion of the source electrode 250a and the second auxiliary electrode 260b extends from the upper surface of the gate insulating layer 230 to the drain electrode 250b. As shown in FIG. The first auxiliary electrode 260a and the second auxiliary electrode 260b are spaced apart from each other.

An active layer 240 is disposed on the first auxiliary electrode 260a and the second auxiliary electrode 260b. The active layer 240 includes a semiconductor material (OC) in which a first carbon isotope (CNT) is dispersed. One side of the active layer 240 contacts the first auxiliary electrode 260a and the other side contacts the second auxiliary electrode 260b. The first auxiliary electrode 260a and the second auxiliary electrode 260b are made of a second carbon isotope, and the first carbon isotope (CNT) and the second carbon isotope are formed in the same manner as in the second embodiment. The first auxiliary electrode 260a and the second auxiliary electrode 260b are formed to have a thickness of 1 to 50 nm to form a contact between the source electrode 250a and the active layer 240 and between the drain electrode 250b and the active layer 240. [ The resistance can be lowered and the carrier mobility can be increased to improve the charge mobility.

The active layer 240 includes a first region AT1 in contact with the first auxiliary electrode 260a and a second region AT2 in contact with the second auxiliary electrode 260b and a third region AT2 in contact with the gate insulating layer 230. [ Area AT3. The first auxiliary electrode 260a of the present invention contacts the lower surface of the first region AT1 of the active layer 240 and contacts the one side of the active layer 240. [ One side of the first auxiliary electrode 260a contacts the side surface of the third region AT3 of the active layer 240. [ The carrier injected from the source electrode 250a may move to the third region AT3 through the first auxiliary electrode 260a, which is the channel of the active layer 240. [ The second auxiliary electrode 260b of the present invention contacts the lower surface of the second region AT2 of the active layer 240 while contacting the other surface of the active layer 240. [ One side of the second auxiliary electrode 260b contacts the side surface of the third region AT3 of the active layer 240. [ The carrier moving through the channel of the third region AT3 of the active layer 240 may move to the drain electrode 250b through the second auxiliary electrode 260b. In addition, the active layer 240 of the present invention includes a semiconductor material (OC) in which a plurality of carbon isotopes (CNTs) are dispersed. Carriers moving within the active layer 240 can move very fast on the carbon nanotubes (CNT) and move in accordance with the charge mobility of the semiconductor material OC in the semiconductor material OC. The thin film transistor array substrate according to the third embodiment of the present invention operates in the same manner as the first embodiment, except that the positions of the first auxiliary electrode and the second auxiliary electrode are different from each other.

The thin film transistor array substrate according to the third embodiment of the present invention includes a first auxiliary electrode and a second auxiliary electrode made of a carbon isotope between a source electrode and a drain electrode and an active layer, By providing the active layer, there is an advantage that the contact resistance between the source electrode and the drain electrode and the active layer can be reduced and the charge mobility can be improved.

Hereinafter, a display device including the thin film transistor array substrate of the present invention will be described with reference to FIGS. 10 and 11. FIG. In the following, a display device including a thin film transistor array substrate according to the above-described embodiment is disclosed, and a duplicate description will be omitted. FIG. 10 is a cross-sectional view illustrating a liquid crystal display device according to an embodiment of the present invention, and FIG. 11 is a cross-sectional view illustrating an organic light emitting display device according to an embodiment of the present invention.

Display device

Referring to FIG. 10, an organic insulating layer 160 is formed on the source electrode 150a and the drain electrode 150b. The organic insulating layer 160 may be formed of an organic material such as photo acryl, polyimide, benzocyclobutene resin, acrylate resin, or the like, have. The organic insulating layer 160 includes a via hole 165 exposing the drain electrode 150b. Although not shown, a passivation film made of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof may be disposed on the source electrode 150a and the drain electrode 150b.

The pixel electrode 170 and the common electrode 180 are located on the organic insulating layer 160. The pixel electrode 170 is connected to the drain electrode 150b through a via hole 165 formed in the organic insulating layer 160. [ The pixel electrode 170 is made of a transparent and conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The common electrode 180 is made of the same material as the pixel electrode 170. The pixel electrode 170 and the common electrode 180 are alternately arranged to form a horizontal electric field between the pixel electrode 170 and the common electrode 180.

An upper substrate 190 facing the substrate 110 is positioned and a liquid crystal layer LC is positioned between the substrate 110 and the upper substrate 190. In the embodiment of the present invention, an in-plane switching (IPS) liquid crystal display device in which the pixel electrode 170 and the common electrode 180 are located on the same plane has been described as an example. However, the present invention is not limited to this, and the common electrode 180 may be positioned below the pixel electrode 170, and the common electrode 180 may be located on the upper substrate 190.

Meanwhile, referring to FIG. 11, the display device of the present invention may be an organic light emitting display device including an organic light emitting diode. More specifically, the organic insulating film 160 is located on the source electrode 150a and the drain electrode 150b. The organic insulating layer 160 includes a via hole 165 exposing the drain electrode 150b.

A pixel electrode 170 is disposed on the organic insulating layer 160. The pixel electrode 170 is connected to the drain electrode 150b through a via hole 165 formed in the organic insulating layer 160. [ A bank layer 175 is located on the pixel electrode 170. The bank layer 175 may be a pixel defining film that defines a pixel by exposing a part of the pixel electrode 170. [ An organic layer 190 is located on the bank layer 175 and the exposed pixel electrode 170. The organic layer 190 may include a hole injecting layer, a hole transporting layer, an electron transporting layer, or an electron injecting layer. The counter electrode 200 is positioned on the substrate 110 on which the organic layer 190 is formed. The counter electrode 200 may be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof having a low work function as a cathode electrode. Accordingly, an organic light emitting diode (OLED) including the pixel electrode 170, the organic layer 190, and the counter electrode 200 is formed.

An encapsulation layer 210 is positioned on a substrate 110 on which an organic light emitting diode (OLED) is formed. The sealing layer 210 encapsulates the substrate 110 including the lower organic light emitting diode OLED, and may be an inorganic film, an organic film, or a multilayer structure thereof. A cover window 220 is placed on the sealing layer 210 to constitute an OLED display.

Hereinafter, an experimental example of an active layer according to an embodiment of the present invention will be described. The following experimental examples are only examples of the present invention, but the present invention is not limited thereto.

Experiment 1: Thin film transistor  Characterization

Comparative Example  One

A gate electrode and a gate insulating film were formed on a 2 x 2 cm glass substrate, an oxide semiconductor solution was coated thereon, and heat treatment was performed at 350 DEG C for 1 hour to form an active layer. A source electrode and a drain electrode were formed on the active layer to produce a bottom gate type thin film transistor.

Comparative Example  2

A thin film transistor was fabricated under the same conditions as in Comparative Example 1 except that an active layer in which carbon nanotubes and an oxide semiconductor material were mixed was formed.

Example

A gate electrode and a gate insulating film were formed on a 2 x 2 cm glass substrate, a graphene solution was coated on the gate insulating film and patterned to form a first auxiliary electrode and a second auxiliary electrode. An active layer in which carbon nanotubes and an oxide semiconductor material are mixed is formed on the active layer, and then a source electrode and a drain electrode are formed to manufacture a bottom gate type thin film transistor.

The drain current according to the gate voltages of the thin film transistors manufactured according to the comparative examples 1 and 2 and the example described above was measured, and it was shown in FIG. 12, and the charge mobility was measured and shown in FIG. (Channel W / L = 100) was measured by a linear mobility extraction method (measurement equipment: probe station (MS-Tech, MST-8000CHC) ), Blink ratio: the ratio of the off current to the off current of the drain current)

Referring to FIG. 12, in the thin film transistor manufactured according to Comparative Examples 1 and 2, the ON current was increased and the mobility was increased, but the threshold voltage (Vth) was shifted and the subthreshold swing was decreased. On the other hand, in the thin film transistor manufactured according to the embodiment, the threshold voltage (Vth) is shifted to the right, the slope is increased, and the charge mobility is improved.

As a result, in Comparative Examples 1 and 2, the threshold voltage and the slope characteristics of the thin film transistor were degraded due to the scattering phenomenon caused by the carbon isotope of the active layer and the contact resistance between the active layer and the source / drain electrode. On the other hand, the embodiment of the present invention has graphene auxiliary electrodes between the active layer and the source / drain electrodes, so that the auxiliary electrode and the carbon isotope of the active layer can reduce the contact resistance with the same material and improve the charge mobility. I could.

Experiment 2: Depending on the area of the auxiliary electrodes Thin film transistor  Characterization

In the above-described embodiments, the thin film transistors are manufactured in different planar areas of the first auxiliary electrode and the second auxiliary electrode overlapping the active layer with respect to the plane area of the entire active layer. The charge mobility and flicker ratio of the manufactured thin film transistor were measured and shown in Fig.

Referring to FIG. 14, as the plane area of the first auxiliary electrode and the second auxiliary electrode overlapping the active layer is increased from 20% to 80% with respect to the plane area of the entire active layer, the charge mobility is changed from about 10 ⁴ to 10 ⁸ And the blink rate decreased from about 10 ⁵ to 10 ¹ .

As a result, if the plane area of the first auxiliary electrode and the second auxiliary electrode overlapping the active layer is less than 30% of the total area of the active layer, the charge mobility can be improved by the first auxiliary electrode and the second auxiliary electrode, The active layer does not have a switching function when the plane area of the first auxiliary electrode and the second auxiliary electrode overlapping the active layer is more than 60% of the area of the entire active layer. Therefore, it is understood that the planar area of the first auxiliary electrode and the second auxiliary electrode overlapping the active layer with respect to the plane area of the entire active layer is preferably 30 to 60%.

Experiment 3: Thin film transistor SEM  Measure

FIG. 15 shows an SEM image of the region A of FIG. 8 in the thin film transistor manufactured according to the embodiment, FIG. 16 shows an SEM image of the region B of FIG. 8, FIG. 17 shows the region C of FIG. The region D in Fig. 16 is shown in Fig.

Referring to FIGS. 15 to 17, first and second auxiliary electrodes (graphenes) are observed on the gate insulating layer GI, and an active layer in which a carbon isotope and a semiconductor material are mixed (CNT + oxide composite) is observed. Referring to FIG. 18, a second auxiliary electrode (graphene) and a drain electrode (drain) are observed on the gate insulating film GI. Here, the graphene can be identified as a portion forming a layered structure in which flakes are layered on the SEM image, and the carbon nanotubes in the active layer can be distinguished from each other due to the difference in brightness from the semiconductor material on the SEM image.

As a result, it can be seen that the first and second auxiliary electrodes made of graphenes exist under the active layer.

Experiment 4: Thin film transistor  Raman analysis

Raman analysis of the thin film transistor manufactured according to the embodiment is shown in FIGS. 19 to 21, respectively.

Referring to FIG. 19, no carbon isotope peaks were observed in the Raman analysis of the source electrode and the drain electrode itself.

Referring to FIG. 20, peaks of carbon isotopes of 1360 nm and 1580 nm were observed under the source electrode and the drain electrode, and it was confirmed that the first and second auxiliary electrodes were graphenes.

Referring to FIG. 21, since carbon nanotubes and a semiconductor material are present in the active layer, peaks of carbon isotope are exhibited.

At this time, the peak of graphene of FIG. 20 and the peak of carbon nanotube of FIG. 21 appear at the same position, but different peak intensities can be distinguished.

As described above, the thin film transistor array substrate according to an embodiment of the present invention includes the carbon isotope and the metal nanoparticles which are conductive in the semiconductor material, so that the carriers move along the carbon isotope and the metal nanoparticles, Can be improved.

The thin film transistor array substrate according to an embodiment of the present invention includes a first auxiliary electrode and a second auxiliary electrode made of a carbon isotope between a source electrode and a drain electrode and an active layer, Layer is provided, there is an advantage that the contact resistance between the source electrode and the drain electrode and the active layer can be reduced and the charge mobility can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

110: substrate 120: gate electrode
130: gate insulating film 140: active layer
150a: source electrode 150b: drain electrode

Claims (15)

Board;
A gate electrode disposed on the substrate;
An active layer opposing the gate electrode, the active layer comprising a first carbon isotope and a semiconductor material;
A gate insulating film interposed between the gate electrode and the active layer;
A source electrode and a drain electrode which respectively contact the active layer; And
A first auxiliary electrode disposed between the active layer and the gate insulating film and contacting a part of the lower surface of the active layer and a second auxiliary electrode contacting a part of the lower surface of the active layer. The method according to claim 1,
Wherein the active layer includes a first region which contacts and overlaps with the first auxiliary electrode, a second region which contacts and overlaps with the second auxiliary electrode, and a third region which is in contact with the gate insulating film. 3. The method of claim 2,
Wherein the planar area of the first region and the second region is 30 to 60% of the planar area of the active layer. 3. The method of claim 2,
And the third region overlaps the channel of the active layer. The method according to claim 1,
Wherein the first auxiliary electrode contacts the source electrode and the second auxiliary electrode contacts the drain electrode. 6. The method of claim 5,
The first auxiliary electrode is disposed below the source electrode and the active layer, and the second auxiliary electrode is disposed below the drain electrode and the active layer. The method according to claim 1,
Wherein the first auxiliary electrode is disposed above the source electrode and the second auxiliary electrode is disposed over the drain electrode. The method according to claim 1,
Wherein the first auxiliary electrode and the second auxiliary electrode comprise a second carbon isotope. 9. The method of claim 8,
Wherein the first carbon isotope and the second carbon isotope are selected from the group consisting of a reduced graphene oxide (rGO), a non-oxidized graphene, a graphene nanoribbon, or a carbon nanotube (CNT) Board. The method according to claim 1,
Wherein the semiconductor material is any one of a ceramic semiconductor, an organic semiconductor, a transition metal chalcogenide compound, and an oxide semiconductor, or a mixture thereof. Board;
A gate electrode disposed on the substrate;
An active layer opposing the gate electrode, the active layer comprising metal nanoparticles, a first carbon isotope and a semiconductor material;
A gate insulating film interposed between the gate electrode and the active layer; And
And a source electrode and a drain electrode which respectively contact the active layer. 12. The method of claim 11,
Wherein the plurality of metal nanoparticles are spaced apart from each other at regular intervals. A thin film transistor array substrate according to any one of claims 1 to 10,
An organic insulating film disposed on the thin film transistor array substrate; And
And a pixel electrode located on the organic insulating film. 14. The method of claim 13,
An organic light emitting diode electrically connected to the pixel electrode;
An encapsulation layer disposed on the organic light emitting diode; And
And a cover window positioned on the sealing layer. 14. The method of claim 13,
A common electrode disposed on the same plane as or spaced apart from the pixel electrode; And
And a liquid crystal layer disposed on the common electrode.

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