KR102555217B1 - Substrate for Thin Film Transistor And Display Device Of The Same - Google Patents

Abstract

The present invention provides a thin film transistor array substrate capable of improving device characteristics by forming an active layer containing a carbon allotrope and a display device including the same. A thin film transistor array substrate according to an embodiment of the present invention includes a substrate, a gate electrode, an active layer, a gate insulating layer, a source electrode, a drain electrode, a first auxiliary electrode and a second auxiliary electrode. A gate electrode is located on the substrate. The active layer faces the gate electrode and includes a first carbon allotrope and a semiconductor material. A gate insulating film is interposed between the gate electrode and the active layer. The source electrode and the drain electrode respectively contact the active layer. The first auxiliary electrode is disposed between the active layer and the gate insulating layer and contacts a part of the lower surface of the active layer, and the second auxiliary electrode contacts a part of the lower surface of the active layer.

Description

Thin film transistor array substrate and display device including the same {Substrate for Thin Film Transistor And Display Device Of The Same}

The present invention relates to a thin film transistor array substrate and a display device including the same.

Recently, the importance of a display device (FPD: Flat Panel Display) is increasing along with the development of multimedia. In response to this, liquid crystal display (LCD), plasma display panel (PDP), field emission display (FED), organic light emitting display (Organic Light Emitting Device), etc. Various displays are put into practical use.

Methods for driving a display device include a passive matrix method and an active matrix method using thin film transistors. In the passive matrix method, an anode and a cathode are orthogonally formed and a line is selected and driven, whereas in an active matrix method, thin film transistors are connected to each pixel electrode and driven according to on/off switching.

In addition to basic characteristics of the thin film transistor, such as electron mobility and leakage current, durability and electrical reliability for maintaining a long lifespan are very important for the thin film transistor. Here, the active layer of the thin film transistor may be mainly formed of amorphous silicon, polycrystalline silicon, or an oxide semiconductor. However, amorphous silicon has the advantage of a simple film formation process and low production cost, but has a low electron mobility of 0.5 cm 2 /Vs. Oxide semiconductors have an on/off ratio of about 10 ⁸ and a low leakage current, but an electron mobility of 10 cm 2 /Vs, which is lower than that of polycrystalline silicon. Polycrystalline silicon has a fast electron mobility of about 100 cm 2 /Vs, but has a low on/off ratio compared to oxide semiconductors and has a disadvantage in that it is expensive to apply to a large area. Therefore, studies are being conducted to improve the characteristics of thin film transistors, such as electron mobility, leakage current, and on/off ratio.

The present invention provides a thin film transistor array substrate capable of improving device characteristics by forming an active layer containing a carbon allotrope and a display device including the same.

In order to achieve the above object, a thin film transistor array substrate according to an embodiment of the present invention includes a substrate, a gate electrode, an active layer, a gate insulating film, a source electrode, a drain electrode, a first auxiliary electrode and a second auxiliary electrode. . A gate electrode is located on the substrate. The active layer faces the gate electrode and includes a first carbon allotrope and a semiconductor material. A gate insulating film is interposed between the gate electrode and the active layer. The source electrode and the drain electrode respectively contact the active layer. The first auxiliary electrode is disposed between the active layer and the gate insulating layer and contacts a part of the lower surface of the active layer, and the second auxiliary electrode contacts a part of the lower surface of the active layer.

The active layer includes a first region contacting and overlapping the first auxiliary electrode, a second region contacting and overlapping the second auxiliary electrode, and a third region contacting the gate insulating layer.

The planar area of the first region and the second region relative to the planar area of the active layer occupies a ratio of 30 to 60%.

The third region overlaps the channel of the active layer.

The first auxiliary electrode contacts the source electrode and the second auxiliary electrode contacts the drain electrode.

The first auxiliary electrode is disposed below the source electrode and the active layer, and the second auxiliary electrode is disposed below the drain electrode and the active layer.

The first auxiliary electrode is disposed on the source electrode, and the second auxiliary electrode is disposed on the drain electrode.

The first auxiliary electrode and the second auxiliary electrode are made of the second carbon allotrope.

The first carbon allotrope and the second carbon allotrope may be any one of reduced graphene oxide (rGO), non-oxidized graphene, graphene nanoribbon or carbon nanotube (CNT), or a mixture thereof.

The semiconductor material is any one of a ceramic semiconductor, an organic semiconductor, a transition metal chalcogenide compound, or an oxide semiconductor, or a mixture thereof.

A thin film transistor array substrate according to an embodiment of the present invention includes a substrate, a gate electrode, an active layer, a gate insulating layer, a source electrode, and a drain electrode. A gate electrode is located on the substrate. The active layer faces the gate electrode and includes metal nanoparticles, a first carbon allotrope, and a semiconductor material. A gate insulating film is interposed between the gate electrode and the active layer. The source electrode and the drain electrode respectively contact the active layer.

A plurality of metal nanoparticles are arranged spaced apart at regular intervals.

In addition, a display device according to an embodiment of the present invention includes a thin film transistor array substrate; It includes an organic insulating film positioned on the thin film transistor array substrate and a pixel electrode positioned on the organic insulating film.

It further includes an organic light emitting diode electrically connected to the pixel electrode, an encapsulation layer positioned on the organic light emitting diode, and a cover window positioned on the encapsulation layer.

The pixel electrode may further include a common electrode positioned on the same plane or spaced apart from the bottom of the pixel electrode, and a liquid crystal layer positioned on the common electrode.

A thin film transistor array substrate according to an embodiment of the present invention includes conductive carbon allotrope and metal nanoparticles in a semiconductor material, so that carriers can move along the carbon allotrope and metal nanoparticles to improve charge mobility. There is an advantage.

In addition, the thin film transistor array substrate according to an embodiment of the present invention includes a first auxiliary electrode and a second auxiliary electrode made of a carbon allotrope between a source electrode and a drain electrode and an active layer, and an active layer including a carbon allotrope and a semiconductor material. By providing the layer, there is an advantage of reducing contact resistance between the source and drain electrodes and the active layer and improving charge mobility.

1 is a cross-sectional view showing a thin film transistor array substrate according to a first embodiment of the present invention.
2 is a cross-sectional view showing the active layer of FIG. 1, and FIG. 3 is a cross-sectional view showing a charge transfer path of the active layer of the present invention.
4 to 6 are cross-sectional views showing manufacturing processes of the thin film transistor array substrate according to the first embodiment of the present invention.
7 and 8 are cross-sectional views showing a thin film transistor array substrate according to a second embodiment of the present invention.
9 is a cross-sectional view showing a thin film transistor array substrate according to a third embodiment of the present invention.
10 is a cross-sectional view illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
11 is a cross-sectional view illustrating an organic light emitting display device according to an exemplary embodiment of the present invention.
12 is a graph showing the drain current according to the gate voltage of the thin film transistors manufactured according to Comparative Examples 1 and 2 and Examples.
13 is a graph showing charge mobility of thin film transistors manufactured according to Comparative Examples 1 and 2 and Examples.
14 is a graph showing charge mobility and blinking ratio of thin film transistors manufactured according to an embodiment.
15 is a SEM image of area A of FIG. 8;
16 is a SEM image of region B of FIG. 8;
17 is a SEM image showing region C of FIG. 16;
18 is a SEM image showing region D of FIG. 16;
19 to 21 are Raman analysis graphs of thin film transistors manufactured according to embodiments.

Hereinafter, some embodiments of the present invention will be described in detail through exemplary drawings. In adding reference numerals to components of each drawing, it should be noted that the same components have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing the embodiments of the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description will be omitted.

Also, terms such as first, second, A, B, (a), and (b) may be used in describing the components of the invention. These terms are only used to distinguish the component from other components, and the nature, sequence, or order of the corresponding component is not limited by the term. When an element is described as being “connected,” “coupled to,” or “connected” to another element, that element is directly connected or connectable to the other element, but there is another element between the elements. It will be understood that elements may be “connected”, “coupled” or “connected”. In the same vein, when a component is described as being formed “on” or “below” another component, that component is formed either directly by the other component or indirectly through another component. It should be understood as including

The display device according to the present invention described below may be an organic light emitting display device, a liquid crystal display device, an electrophoretic display device, and the like. In the present invention, a liquid crystal display device will be described as an example. A liquid crystal display device is composed of a thin film transistor array substrate on which a pixel electrode and a common electrode are formed on a thin film transistor, a color filter substrate, and a liquid crystal layer interposed between the two substrates. A liquid crystal is driven by an electric field applied horizontally. Also, the display device according to the present invention can be used for an organic light emitting display device. For example, an organic light emitting display device includes a first electrode connected to a thin film transistor, a second electrode, and an emission layer made of an organic material between the first electrode and the second electrode. Accordingly, holes supplied from the first electrode and electrons supplied from the second electrode are combined in the light emitting layer to form an exciton, which is a hole-electron pair, and light is emitted by energy generated as the exciton returns to the ground state. The active layer including the carbon allotrope of the present invention described later can be used for the thin film transistor of the aforementioned display device.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

The present invention discloses an active layer including a carbon allotrope and a semiconductor material, and specifically discloses a thin film transistor array substrate having an active layer including a carbon allotrope and a semiconductor material. A thin film transistor is used as a switching element or a driving element of a display device.

carbon allotrope

Carbon allotropes disclosed in the present invention represent polycyclic aromatic molecules of carbon atoms covalently bonded to each other. The covalently bonded carbon atoms may form a six-membered ring as a repeating unit, and may also contain one or more of a five-membered ring and a seven-membered ring. The carbon allotrope may be a single layer or may include multiple layers of carbon allotropes stacked on top of other layers of carbon allotrope. Carbon allotropes have either one-dimensional or two-dimensional structures. The carbon allotrope has a maximum thickness of about 100 nm, specifically about 10 nm to about 90 nm, more specifically about 20 nm to about 80 nm.

There are four major methods of preparing carbon allotropes: physical exfoliation, chemical vapor deposition, chemical exfoliation, or epitaxial synthesis. The physical exfoliation method is a method in which scotch tape is attached to a graphite sample and then peeled off to obtain a carbon allotrope sheet separated from the graphite on the surface of the scotch tape. The chemical vapor deposition method adsorbs and decomposes a carbon precursor in the form of a gas or vapor with high kinetic energy on the surface of a substrate on which a carbon allotrope is to be grown, separates it into carbon atoms, and makes the carbon atoms bond with each other to form a crystalline carbon allotrope. way to grow. The chemical exfoliation method uses the oxidation-reduction properties of graphite, and attaches carboxyl compounds to the edges of carbon allotrope plates by putting graphite in a mixture of sulfuric acid and nitric acid. It is converted into an acid chloride by tinol chloride and then made into a carbon allotrope amide by using octadecylamine. When this is recovered using a solution such as tetrahydrofuran, pulverization occurs to obtain individual carbon allotrope sheets. The epitaxial synthesis method is a method of heating silicon carbide (SiC) to a high temperature of 1,500 ° C. to obtain a carbon allotrope by removing silicon (Si) and remaining carbon (C).

As the carbon allotrope of the present invention, reduced graphene oxide (rGO), non-oxidized graphene or graphene nanoribbon, carbon nanotube (CNT), or the like may be used. Reduced graphene oxide is obtained by reducing graphene oxide (GO), which is oxidized when a strong acid is added to graphite, chemically formed into small particles to produce graphene oxide, and reduced graphene oxide. Non-oxidized graphene refers to a carbon allotrope prepared by a method excluding the oxidation-reduction process among the above-described methods for producing a carbon allotrope. Graphene nanoribbons are graphene cut in the form of ribbons with a width of nanometers (nm), and have a certain energy band gap depending on the width. Graphene nanoribbons can be synthesized from monomers containing carbon allotropes or prepared by cutting and spreading carbon nanotubes on a plane. Carbon nanotubes may be single-wall CNTs (SWCNTs) or multi-wall CNTs (MWCNTs), which have semiconductor properties or metallic properties. Carbon nanotubes can also be used. In addition to the aforementioned types of carbon allotropes, known carbon allotrope structures such as graphene nanomesh may be applied to the carbon allotrope of the present invention.

The carbon allotrope of the present invention is used in the form of flakes. The carbon allotrope flakes may be prepared by coating the dispersion on a substrate using a dispersion in which the carbon allotrope is dispersed in a solvent, drying the solvent, and then applying physical force. As a method of applying physical force, carbon allotrope flakes may be obtained using a method such as a ball mill, a bead mill, an ultrasonic homogenizer, or stirring.

semiconductor material

As the semiconductor material of the present invention, materials capable of being solution-coated with ceramic semiconductors, organic semiconductors, transition metal chalcogen compounds, or oxide semiconductors may be used.

Ceramic semiconductors use the electrical properties of ceramics. In ceramics, electrons cannot move freely because they are bound to certain ions or atoms, so electricity hardly flows. Electrons move as they change states by causing an arrangement. A ceramic semiconductor is a metal element such as silicon (Si), germanium (Ge), selenium (Se), aluminum (Al), titanium (Ti), zirconium (Zr), oxygen (O), carbon (C), nitrogen (N ), etc. are made of oxides, carbides, and nitrides. Representative ceramic semiconductors include barium titanate (BaTiO ₃ ).

The organic semiconductor is an organic compound having semiconductor properties, and may include a high-molecular organic semiconductor or a low-molecular organic semiconductor. Polymer organic semiconductors include F8T2 (Poly[(9,9-dioctylfluorenyl-2,7-diyl)-co-bithiophene]), PBDTBOTPDO (Poly[(5,6-dihydro-5-octyl-4,6-dioxo- 4H-thieno[3,4-C]pyrrole-1,3-diyl){4,8-bis[(2-butyloctyl)oxy]benzo[1,2-b:4,5-b′]dithiophene-2 ,6-diyl}]), PBDT-TPD (Poly[[5-(2-ethylhexyl)-5,6-dihydro-4,6-dioxo-4H-thieno[3,4-c]pyrrole-1,3 -diyl][4,8-bis[(2-ethylhexyl)oxy]benzo[1,2-b:4,5-b′]dithiophene-2,6-diyl]]), PBDTTT-CF (Poly[1 -(6-{4,8-bis[(2-ethylhexyl)oxy]-6-methylbenzo[1,2-b:4,5-b′]dithiophen-2-yl}-3-fluoro-4-methylthieno [3,4-b]thiophen-2-yl)-1-octanone]), PCDTBT (Poly[N-9′-heptadecanyl-2,7-carbazole-alt-5,5-(4′,7′- di-2-thienyl-2′,1′,3′-benzothiadiazole)], Poly[[9-(1-octylnonyl)-9H-carbazole-2,7-diyl]-2,5-thiophenediyl-2,1 ,3-benzothiadiazole-4,7-diyl-2,5-thiophenediyl]), PCPDTBT (Poly[2,6-(4,4-bis-(2-ethylhexyl)-4H-cyclopenta [2,1-b; 3,4-b′]dithiophene)-alt-4,7(2,1,3-benzothiadiazole)]), PFO-DBT(Poly[2,7-(9,9-dioctylfluorene)-alt-4,7 -bis(thiophen-2-yl)benzo-2,1,3-thiadiazole]), PTAA (Poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine]), Poly[(5,6 -dihydro-5-octyl-4,6-dioxo-4H-thieno[3,4-c]pyrrole-1,3-diyl)[4,8-bis[(2-ethylhexyl)oxy]benzo[1,2 -b:4,5-b′]dithiophene-2,6-diyl]], F8BT(Poly[(9,9-di-n-octylfluorenyl-2,7-diyl)-alt-(benzo[2,1 ,3]thiadiazol-4,8-diyl)]), P3DDT (Poly(3-dodecylthiophene-2,5-diyl)), P3HT (Poly(3-hexylthiophene-2,5-diyl)), MDMOPPV (Poly[ 2-methoxy-5-(3′,7′-dimethyloctyloxy)-1,4-phenylenevinylene]), MEH-PPV (Poly[2-methoxy-5-(2-ethylhexyloxy)-1,4-phenylenevinylene]), P3OT (Poly(3-octylthiophene-2,5-diyl)), PTB7 (Poly({4,8-bis[(2-ethylhexyl)oxy]benzo[1,2-b:4,5-b′]dithiophene -2,6-diyl}{3-fluoro-2-[(2-ethylhexyl)carbonyl]thieno[3,4-b]thiophenediyl})) etc. are mentioned.

Examples of low-molecular organic semiconductors include TIPS-pentacene (6,13-Bis (triisopropylsilylethynyl) pentacene), TESPentacene (6,13-Bis ((triethylsilyl) ethynyl) pentacene), DH-FTTF (5,5′-Bis (7-hexyl-9H-fluoren-2-yl)-2,2′-bithiophene), diF-TES-ADT (2,8-Difluoro-5,11-bis(triethylsilylethynyl)anthradithiophene), DH2T (5,5 ′-Dihexyl-2,2′-bithiophene), DH4T (3,3′′′-Dihexyl-2,2′:5′,2′′:5′′,2′′′-quaterthiophene), DH6T (5 ,5′′′′-Dihexyl-2,2′:5′,2′′:5′′,2′′′:5′′′,2′′′′:5′′′′,2′ ′′′′-sexithiophene), DTS(PTTh2)2(4,4′-[4,4-Bis(2-ethylhexyl)-4H-silolo[3,2-b:4,5-b′]dithiophene- 2,6-diyl]bis[7-(5′-hexyl-[2,2′-bithiophen]-5-yl)-[1,2,5]thiadiazolo[3,4-c]pyridine], 5, 5′-Bis{[4-(7-hexylthiophen-2-yl)thiophen-2-yl]-[1,2,5]thiadiazolo[3,4-c]pyridine}-3,3′-di-2 -ethylhexylsilylene-2,2′-bithiophene), SMDPPEH(2,5-Di-(2-ethylhexyl)-3,6-bis-(5′′-n-hexyl-[2,2′,5′,2 ′′]terthiophen-5-yl)-pyrrolo[3,4-c]pyrrole-1,4-dione), TES-ADT (5,11-Bis(triethylsilylethynyl)anthradithiophene), and the like.

As the organic semiconductor described above, two or more of a polymer organic semiconductor and a small molecular organic semiconductor may be used, different polymer organic semiconductors may be used, or different small molecular organic semiconductors may be used.

Transition metal dichalcogenides are materials having semiconductor properties, and may include, for example, transition metal sulfides, transition metal selenides, transition metal tellurides, and the like. Examples of the transition metal chalcogen compound include SnSe ₂ , CdSe, ZnSe, ZnTe, MoS ₂ , MoSe ₂ , MoTe ₂ , WS ₂ , WSe ₂ , WTe ₂ and the like.

Oxide semi-conductor is a material with semiconductor characteristics, which includes metals such as gallium (Ga), indium (In), zinc (Zn), tin (Sn), silicon (Si), and zirconium (Zr). may be an oxide. As an example of the oxide semiconductor, IGZO, In ₂ O ₃ , ZnO, IZO, IGO, etc. may be used, and known materials may be used without being limited thereto.

Hereinafter, a thin film transistor array substrate and a display device including the aforementioned carbon allotrope and semiconductor material will be described.

1 is a cross-sectional view showing a thin film transistor array substrate according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view showing the active layer of FIG. 1, and FIG. 3 is a cross-sectional view showing a charge transfer path of the active layer of the present invention. 4 to 6 are cross-sectional views showing the manufacturing process of the thin film transistor array substrate according to the first embodiment of the present invention.

thin film transistor array board

The thin film transistor array substrate disclosed in the present invention will be described as an example of a bottom-gate type thin film transistor in which a gate electrode is positioned under an active layer. However, the present invention is not limited thereto, and all known structures of thin film transistors, such as a top-gate type thin film transistor in which a gate electrode is positioned above the active layer, may be applied.

Referring to FIG. 1 , a gate electrode 120 is positioned on a substrate 110 . The substrate 110 is made of transparent or opaque glass, plastic or metal. The gate electrode 120 is made of copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), tantalum (Ta) and tungsten (W), or a single layer or multiple layers of alloys thereof. A gate insulating layer 130 insulating the gate electrode 120 is positioned on the gate electrode 120 . The gate insulating film 130 is made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multi-layer thereof.

An active layer 140 is positioned on the gate insulating layer 130 . The active layer 140 includes a carbon allotrope and a semiconductor material.

Referring to FIG. 2 , the active layer 140 of the present invention includes a semiconductor material (OC), a plurality of carbon allotropes (CNT), and a plurality of metal nanoparticles (MN). The semiconductor material OC forms the main body of the active layer 140 and controls the threshold voltage by enabling the active layer 140 to act as a semiconductor. The plurality of carbon allotropes (CNTs) allow charges (carriers) to move quickly through the conductive carbon allotropes (CNTs), thereby speeding up the charge mobility of the active layer 140 . The plurality of metal nanoparticles (MN) allows charges to move rapidly through the conductive metal nanoparticles (MN), thereby speeding up the charge mobility of the active layer 140 .

Metal nanoparticles (MN) are metal materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd) ), copper (Cu), or any one or more of alloys thereof. However, the metal nanoparticles (MN) of the present invention are not limited thereto, and any known metal material can be used.

In addition, the metal nanoparticles (MN) may have a particle size of several to hundreds of nanometers and be dispersed in the active layer 140 . In this case, the metal nanoparticles (MN) may be spaced apart from each other at regular intervals to exhibit uniform charge mobility in the active layer 140 .

Referring back to FIG. 1 , a source electrode 150a contacting one side of the active layer 140 and a drain electrode 150b contacting the other side of the active layer 140 are positioned on the active layer 140 . The source electrode 150a and the drain electrode 150b may be formed of a single layer or multiple layers, and in the case of a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti, It may be made of any one selected from the group consisting of nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof. In addition, when the source electrode 150a and the drain electrode 150b are multi-layered, they are a double layer of molybdenum/aluminum-neodymium, molybdenum/aluminum, or titanium/aluminum, or molybdenum/aluminum-neodymium/molybdenum, molybdenum/aluminum/molybdenum, or titanium. It can be made of a triple layer of /aluminum/titanium.

Referring to FIG. 3 , when a voltage is applied to the source electrode 150a and the drain electrode 150b of the active layer 140 of the present invention, electrons and holes, which are carriers, move to a channel of the active layer 140 . At this time, since the active layer 140 is composed of carbon allotrope (CNT), metal nanoparticles (MN), and semiconductor material (OC), electrons and holes ride very quickly through the carbon allotrope (CNT) and metal nanoparticles (MN). and moves according to the charge mobility of the semiconductor material (OC) in the semiconductor material (OC). Accordingly, electrons and holes move along the carbon allotrope (CNT) and the metal nanoparticles (MN) in the semiconductor material (OC), and charge mobility can be greatly improved.

The thin film transistor array substrate including the above-described active layer 140 may be manufactured as follows.

Referring to FIG. 4 , the gate electrode 120 is formed by depositing and patterning a gate electrode material on the substrate 110 . A gate insulating layer material is deposited on the entire surface of the substrate 110 including the gate electrode 120 to form the gate insulating layer 130 . Next, metal nanoparticles (MN) are formed by coating a solution in which metal nanoparticles (MN) are mixed on the gate insulating layer 130 and drying. At this time, the metal nanoparticles (MN) are formed only in the region to be fabricated as the active layer 140 later.

Subsequently, referring to FIG. 5 , a semiconductor solution in which the carbon allotrope (CNT) and the semiconductor material (OC) are mixed is prepared. The semiconductor solution may be prepared by mixing a powdered carbon allotrope and a semiconductor material in a solvent, or may be prepared by mixing a carbon allotrope dispersion with a semiconductor precursor solution. In order to favorably disperse the carbon allotrope and the semiconductor material, other additives may be added or ultrasonic waves may be irradiated. In the case of irradiating ultrasonic waves to a semiconductor solution in which carbon allotropes are mixed, it is preferable to irradiate the ultrasonic waves by dividing them several times. For example, a carbon allotrope is mixed with a semiconductor precursor solution, and strong ultrasonic waves (about 250 W) are irradiated with an ultrasonic disruptor for about 30 minutes. By repeating such a process, a semiconductor solution in which the carbon allotrope is well dispersed can be prepared.

The amount of the carbon allotrope used in the semiconductor solution of the present invention may be included in an amount of 0.0001 to 1% by weight based on 100% by weight of the semiconductor precursor solution. Here, if the carbon allotrope is 0.0001% by weight or more with respect to 100% by weight of the semiconductor precursor solution, the effect of improving charge mobility characteristics can be exhibited, and if the carbon allotrope is 1% by weight or less with respect to 100% by weight of the semiconductor precursor solution, the carbon allotrope It is possible to improve the dispersibility of and improve the coating property.

The prepared semiconductor solution is coated on the substrate 110 on which the metal nanoparticles (MN) are formed and dried to form an active layer 140 including the metal nanoparticles (MN). As a method of coating the semiconductor solution, methods such as spin coating, slit coating, screen printing, and ink-jet printing may be used. Any method is applicable. In addition, the active layer 140 of the present invention is prepared by heat-treating the coating film at 250° C. for 2 hours to remove the solvent and then patterning the coating film using photolithography. The active layer 140 manufactured in this way may have a structure in which metal nanoparticles (MN) and carbon allotrope (CNT) are dispersed in the semiconductor material (OC).

As described above, the thin film transistor array substrate according to the first embodiment of the present invention includes conductive carbon allotrope and metal nanoparticles in a semiconductor material, so that carriers ride on the carbon allotrope and metal nanoparticles to transfer charge. There are advantages to improving the degree.

7 and 8 are cross-sectional views showing a thin film transistor array substrate according to a second embodiment of the present invention, and FIG. 9 is a cross-sectional view showing a thin film transistor array substrate according to a third embodiment of the present invention. In the following, descriptions of the same components as those of the first embodiment will be omitted.

Referring to FIG. 7 , in the thin film transistor array substrate according to the second embodiment of the present invention, a gate electrode 220 is disposed on a substrate 210, and a gate insulating film 230 is disposed on the gate electrode 220. .

A first auxiliary electrode 260a and a second auxiliary electrode 260b are disposed on the gate insulating layer 230 . The first auxiliary electrode 260a and the second auxiliary electrode 260b are disposed spaced apart from each other. The source electrode 250a is disposed on the first auxiliary electrode 260a, and the drain is disposed on the second auxiliary electrode 260b. An electrode 250b is disposed. An active layer 240 is disposed on the first auxiliary electrode 260a, the second auxiliary electrode 260b, and the gate insulating layer 230 . The active layer 240 includes a semiconductor material OC in which a first carbon allotrope (CNT) is dispersed. One side of the active layer 240 contacts the source electrode 250a and the other side contacts the drain electrode 250b.

More specifically, the first auxiliary electrode 260a and the second auxiliary electrode 260b are made of the second carbon allotrope. The first carbon allotrope (CNT) and the second carbon allotrope of the active layer 240 are made of the same type of carbon allotrope. For example, the first carbon allotrope (CNT) and the second carbon allotrope are reduced graphene oxide (rGO), non-oxidized graphene (graphene), graphene nanoribbon or carbon nanotube (CNT), or any one of these. may be a mixture. In an embodiment of the present invention, the first carbon allotrope (CNT) included in the active layer 240 is a carbon nanotube, and the second carbon allotrope is reduced graphene oxide (rGO), non-oxidized graphene, or graphene. It is graphene selected among nanoribbons. The first auxiliary electrode 260a and the second auxiliary electrode 260b are formed to have a thickness of 1 to 50 nm and provide contact between the source electrode 250a and the active layer 240 and between the drain electrode 250b and the active layer 240. Resistance can be lowered and carrier mobility can be accelerated to improve charge mobility.

The active layer 240 includes a first region AT1 that contacts and overlaps the first auxiliary electrode 260a, a second region AT2 that contacts and overlaps the second auxiliary electrode 260b, and the gate insulating layer 230. It includes a third area (AT3) that makes contact. The first auxiliary electrode 260a of the present invention contacts the lower surface of the first region AT1 of the active layer 240 and the source electrode 250a. In particular, one side surface of the first auxiliary electrode 260a contacts the side surface of the third region AT3 of the active layer 240 . The third area AT3 of the active layer 240 corresponds to a channel. Carriers injected from the source electrode 250a may move to the third region AT3 that is a channel of the active layer 240 through the first auxiliary electrode 260a.

The second auxiliary electrode 260b of the present invention contacts the drain electrode 250b while contacting the lower surface of the second region AT2 of the active layer 240 . In particular, one side surface of the second auxiliary electrode 260b contacts the side surface of the third region AT3 of the active layer 240 . Carriers moving through the channel of the third region AT3 of the active layer 240 may move to the drain electrode 250b through the second auxiliary electrode 260b. In addition, the active layer 240 of the present invention includes a semiconductor material (OC) in which a plurality of carbon allotropes (CNT) are dispersed. Carriers moving inside the active layer 240 can move very quickly along the carbon allotrope (CNT) and can move in the semiconductor material (OC) according to the charge mobility of the semiconductor material (OC).

Referring to FIG. 8, the movement path (TP) of the carrier in the thin film transistor array substrate of the present invention is as follows. Carriers injected from the source electrode 250a move very quickly in the first auxiliary electrode 260a made of graphene, which is close to a conductor, and are injected into the active layer 240 . Since the channel CH of the active layer 240 includes a plurality of carbon allotropes (CNTs) and a semiconductor material (OC), injected carriers move very quickly along the carbon allotropes (CNTs). Carriers passing through the channel CH of the active layer 240 move very quickly from the second auxiliary electrode 260b made of graphene, which is close to a conductor, to the drain electrode 250b.

The active layer 240 of the present invention contacts and overlaps the first region AT1 that contacts and overlaps the first auxiliary electrode 260a relative to the planar area of the entire active layer 240 and the second auxiliary electrode 260b. The planar area of the second area AT2 may occupy 30 to 60%. Here, when the plane area of the first region AT1 and the second region AT2 is 30% or more compared to the plane area of the entire active layer 240, the charge mobility of the active layer can be improved, and the entire active layer 240 When the planar area of the first and second areas AT1 and AT2 is 60% or less compared to the planar area of ), it is possible to prevent the active layer 240 from being almost conductive and failing to play a switching role.

The thin film transistor array substrate according to the second embodiment of the present invention described above includes a first auxiliary electrode and a second auxiliary electrode made of a carbon allotrope between a source electrode and a drain electrode and an active layer, and including a carbon allotrope and a semiconductor material. By providing the active layer, there is an advantage of reducing contact resistance between the source and drain electrodes and the active layer and improving charge mobility.

Meanwhile, in the thin film transistor array substrate of the present invention, the positions of the first auxiliary electrode 260a and the second auxiliary electrode 260b may be disposed differently from those of the second embodiment.

Referring to FIG. 9 , in the thin film transistor array substrate according to the third embodiment of the present invention, a gate electrode 220 is disposed on a substrate 210, and a gate insulating film 230 is disposed on the gate electrode 220. . The source electrode 250a and the drain electrode 250b are spaced apart from each other on the gate insulating layer 230 . The first auxiliary electrode 260a is disposed on the source electrode 250a and the second auxiliary electrode 260b is disposed on the drain electrode 250b. The first auxiliary electrode 260a extends from the top surface of the gate insulating film 230 along the top of the source electrode 250a, and the second auxiliary electrode 260b also extends from the top surface of the gate insulating film 230 to the top of the drain electrode 250b. It is arranged extending along the top. The first auxiliary electrode 260a and the second auxiliary electrode 260b are spaced apart from each other.

An active layer 240 is disposed on the first auxiliary electrode 260a and the second auxiliary electrode 260b. The active layer 240 includes a semiconductor material OC in which a first carbon allotrope (CNT) is dispersed. One side of the active layer 240 contacts the first auxiliary electrode 260a and the other side contacts the second auxiliary electrode 260b. The first auxiliary electrode 260a and the second auxiliary electrode 260b are made of the second carbon allotrope, and the first carbon allotrope (CNT) and the second carbon allotrope are made the same as in the second embodiment described above. The first auxiliary electrode 260a and the second auxiliary electrode 260b are formed to have a thickness of 1 to 50 nm and provide contact between the source electrode 250a and the active layer 240 and between the drain electrode 250b and the active layer 240. Resistance can be lowered and carrier mobility can be accelerated to improve charge mobility.

The active layer 240 includes a first region AT1 contacting the first auxiliary electrode 260a, a second region AT2 contacting the second auxiliary electrode 260b, and a third contacting the gate insulating layer 230. area AT3 is included. The first auxiliary electrode 260a of the present invention contacts one side of the active layer 240 while contacting the lower surface of the first region AT1 of the active layer 240 . In addition, one side surface of the first auxiliary electrode 260a contacts the side surface of the third region AT3 of the active layer 240 . Carriers injected from the source electrode 250a may move to the third region AT3 that is a channel of the active layer 240 through the first auxiliary electrode 260a. The second auxiliary electrode 260b of the present invention contacts the other side of the active layer 240 while contacting the lower surface of the second region AT2 of the active layer 240 . One side surface of the second auxiliary electrode 260b contacts the side surface of the third region AT3 of the active layer 240 . Carriers moving through the channel of the third region AT3 of the active layer 240 may move to the drain electrode 250b through the second auxiliary electrode 260b. In addition, the active layer 240 of the present invention includes a semiconductor material (OC) in which a plurality of carbon allotropes (CNT) are dispersed. Carriers moving inside the active layer 240 can move very quickly along the carbon allotrope (CNT) and can move in the semiconductor material (OC) according to the charge mobility of the semiconductor material (OC). The thin film transistor array substrate according to the third embodiment of the present invention functions the same as the second embodiment described above except for the positions of the first auxiliary electrode and the second auxiliary electrode.

The thin film transistor array substrate according to the third embodiment of the present invention described above includes a first auxiliary electrode and a second auxiliary electrode made of a carbon allotrope between a source electrode and a drain electrode and an active layer, and including a carbon allotrope and a semiconductor material. By providing the active layer, there is an advantage of reducing contact resistance between the source and drain electrodes and the active layer and improving charge mobility.

Hereinafter, a display device including the thin film transistor array substrate of the present invention will be described with reference to FIGS. 10 and 11 . In the following, a display device including the thin film transistor array substrate according to the above-described embodiment will be disclosed, and redundant description will be omitted. 10 is a cross-sectional view of a liquid crystal display device according to an exemplary embodiment, and FIG. 11 is a cross-sectional view of an organic light emitting display device according to an exemplary embodiment.

display device

Referring to FIG. 10 , an organic insulating layer 160 is positioned on the source electrode 150a and the drain electrode 150b. The organic insulating film 160 flattens the level difference at the bottom, and may be made of an organic material such as photo acryl, polyimide, benzocyclobutene resin, or acrylate resin. there is. The organic insulating layer 160 includes a via hole 165 exposing the drain electrode 150b. Although not shown, a passivation layer made of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof may be positioned on the source electrode 150a and the drain electrode 150b.

A pixel electrode 170 and a common electrode 180 are positioned on the organic insulating layer 160 . The pixel electrode 170 is connected to the drain electrode 150b through a via hole 165 formed in the organic insulating layer 160 . The pixel electrode 170 is made of a transparent and conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The common electrode 180 is made of the same material as the pixel electrode 170 . The pixel electrode 170 and the common electrode 180 are alternately disposed to form a horizontal electric field between the pixel electrode 170 and the common electrode 180 .

An upper substrate 190 facing the substrate 110 is positioned, and a liquid crystal layer LC is positioned between the substrate 110 and the upper substrate 190 . In the embodiment of the present invention, an in-plane switching (IPS) liquid crystal display device in which the pixel electrode 170 and the common electrode 180 are positioned on the same plane has been described as an example. However, the present invention is not limited thereto, and the common electrode 180 may be positioned under the pixel electrode 170 or the common electrode 180 may be positioned on the upper substrate 190 .

Meanwhile, referring to FIG. 11 , the display device of the present invention may be an organic light emitting display device including an organic light emitting diode. In more detail, the organic insulating layer 160 is positioned on the source electrode 150a and the drain electrode 150b. The organic insulating layer 160 includes a via hole 165 exposing the drain electrode 150b.

A pixel electrode 170 is positioned on the organic insulating layer 160 . The pixel electrode 170 is connected to the drain electrode 150b through a via hole 165 formed in the organic insulating layer 160 . A bank layer 175 is positioned on the pixel electrode 170 . The bank layer 175 may be a pixel defining layer defining a pixel by exposing a portion of the pixel electrode 170 . An organic film layer 190 is positioned on the bank layer 175 and the exposed pixel electrode 170 . The organic film layer 190 includes a light emitting layer in which electrons and holes combine to emit light, and may include a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer. The counter electrode 200 is positioned on the substrate 110 on which the organic film layer 190 is formed. The counter electrode 200 is a cathode electrode and may be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof having a low work function. Accordingly, an organic light emitting diode (OLED) including the pixel electrode 170, the organic film layer 190, and the counter electrode 200 is configured.

An encapsulation layer 210 is positioned on the substrate 110 on which the organic light emitting diode (OLED) is formed. The encapsulation layer 210 encapsulates the substrate 110 including the lower organic light emitting diode (OLED) and may be formed of an inorganic film, an organic film, or a multilayer structure thereof. A cover window 220 is positioned on the encapsulation layer 210 to form an organic light emitting display device.

Hereinafter, an experimental example for an active layer according to an embodiment of the present invention will be disclosed. The following experimental example is only one embodiment of the present invention, but the present invention is not limited thereto.

Experiment 1: thin film transistor characteristic measurement

comparative example One

A gate electrode and a gate insulating film were formed on a 2×2 cm glass substrate, coated with an oxide semiconductor solution, and heat-treated at 350° C. for 1 hour to form an active layer. A bottom gate type thin film transistor was manufactured by forming a source electrode and a drain electrode on the active layer.

comparative example 2

Under the same conditions as in Comparative Example 1 described above, a thin film transistor was manufactured except that an active layer in which carbon nanotubes and an oxide semiconductor material were mixed was formed.

Example

A gate electrode and a gate insulating film were formed on a 2×2 cm glass substrate, and a graphene solution was coated on the gate insulating film and then patterned to form a first auxiliary electrode and a second auxiliary electrode. After forming an active layer in which carbon nanotubes and an oxide semiconductor material were mixed thereon, a source electrode and a drain electrode were formed to manufacture a bottom gate type thin film transistor.

The drain current according to the gate voltage of the thin film transistor manufactured according to Comparative Examples 1 and 2 and the Example was measured and shown in FIG. 12, and the charge mobility was measured and shown in FIG. (Measurement equipment: probe station (MS-Tech, MST-8000CHC), measurement conditions: gate voltage (-40~40V), drain voltage (0.1V), mobility extraction by linear mobility extraction method (channel W/L=100 ), blinking ratio: the ratio of the drain current to the off current to the on current)

Referring to FIG. 12, the thin film transistors manufactured according to Comparative Examples 1 and 2 had an increased on-current and increased mobility, but a shifted threshold voltage (Vth) and a reduced subthreshold swing. On the other hand, in the thin film transistor manufactured according to the embodiment, the threshold voltage (Vth) is moved to the right, the slope is increased, and the charge mobility is improved.

Through these results, Comparative Examples 1 and 2 showed that the threshold voltage and slope characteristics of the thin film transistors were reduced due to the scattering phenomenon caused by the carbon allotrope of the active layer and the contact resistance between the active layer and the source/drain electrodes. On the other hand, in the embodiment of the present invention, by providing auxiliary electrodes of graphene between the active layer and the source/drain electrode, the carbon allotrope of the auxiliary electrode and the active layer can reduce contact resistance and improve charge mobility with the same material. could

Experiment 2: Depending on the area of auxiliary electrodes thin film transistor characteristic measurement

In the above-described embodiment, thin film transistors were manufactured by varying the planar area of the first auxiliary electrode and the second auxiliary electrode overlapping the active layer compared to the planar area of the entire active layer. The charge mobility and the blinking ratio of the manufactured thin film transistor were measured and shown in FIG. 14 .

Referring to FIG. 14 , as the planar area of the first auxiliary electrode and the second auxiliary electrode overlapping the active layer increases from 20% to 80% compared to the planar area of the entire active layer, the charge mobility increases from about 10 ⁴ to 10 ⁸ . and the blinking ratio decreased from about 10 ⁵ to 10 ¹ .

Through this result, when the plane area of the first auxiliary electrode and the second auxiliary electrode overlapping the active layer is less than 30% compared to the plane area of the entire active layer, charge mobility by the first auxiliary electrode and the second auxiliary electrode is improved and When the passage role is insufficient and the planar area of the first auxiliary electrode and the second auxiliary electrode overlapping the active layer exceeds 60% of the planar area of the entire active layer, the active layer cannot play a switching role. Therefore, it can be seen that the planar area of the first auxiliary electrode and the second auxiliary electrode overlapping the active layer is preferably 30 to 60% compared to the planar area of the entire active layer.

Experiment 3: thin film transistor SEM measurement

In the thin film transistor manufactured according to the embodiment, the SEM image of area A of FIG. 8 is shown in FIG. 15, the SEM image of area B of FIG. 8 is shown in FIG. 16, and area C of FIG. 16 is shown in FIG. Region D of FIG. 16 is shown in FIG. 18 .

15 to 17, first and second auxiliary electrodes (graphene) are observed on the gate insulating layer (GI), and an active layer that is a mixture of a carbon allotrope and a semiconductor material (CNT+Oxide Composite) is observed. Referring to FIG. 18 , a second auxiliary electrode (graphene) and a drain electrode (drain) are observed on the gate insulating film (GI). Here, graphene can be identified as a part forming a layered structure in which flakes are stacked on top of each other on the SEM image, and carbon nanotubes in the active layer can be identified because they have a brightness difference from the semiconductor material on the SEM image.

Through this result, it can be confirmed that the first and second auxiliary electrodes made of graphene exist under the active layer.

Experiment 4: thin film transistor Raman analysis

Raman analysis of the thin film transistor manufactured according to the embodiment is shown in FIGS. 19 to 21, respectively.

Referring to FIG. 19, the source electrode and the drain electrode themselves do not show carbon allotrope peaks during Raman analysis.

Referring to FIG. 20 , carbon allotrope peaks of 1360 nm and 1580 nm appeared below the source electrode and the drain electrode, confirming the existence of graphene as the first and second auxiliary electrodes.

Referring to FIG. 21 , carbon allotrope peaks appeared because carbon nanotubes and semiconductor materials were present in the active layer.

At this time, although the peak of the graphene of FIG. 20 and the peak of the carbon nanotube of FIG. 21 appear at the same position, they can be distinguished because they show different peak intensities.

As described above, the thin film transistor array substrate according to an embodiment of the present invention includes conductive carbon allotrope and metal nanoparticles in a semiconductor material, so that carriers move along the carbon allotrope and metal nanoparticles, resulting in charge mobility. has the advantage of improving

In addition, the thin film transistor array substrate according to an embodiment of the present invention includes a first auxiliary electrode and a second auxiliary electrode made of a carbon allotrope between a source electrode and a drain electrode and an active layer, and an active layer including a carbon allotrope and a semiconductor material. By providing the layer, there is an advantage of reducing contact resistance between the source and drain electrodes and the active layer and improving charge mobility.

Through the above description, those skilled in the art will know that various changes and modifications are possible without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

110: substrate 120: gate electrode
130: gate insulating film 140: active layer
150a: source electrode 150b: drain electrode

Claims (19)

Board;
a gate electrode positioned on the substrate;
an active layer facing the gate electrode and including a first carbon allotrope and a semiconductor material;
a gate insulating layer interposed between the gate electrode and the active layer;
a source electrode and a drain electrode electrically contacting the active layer, respectively; and
It is disposed between the active layer and the gate insulating layer, and includes a first auxiliary electrode contacting a part of the lower surface of the active layer and a second auxiliary electrode contacting a part of the lower surface of the active layer,
The thin film transistor array substrate of claim 1 , wherein the first auxiliary electrode and the second auxiliary electrode are spaced apart from each other. According to claim 1,
The active layer includes a first region contacting and overlapping the first auxiliary electrode, a second region contacting and overlapping the second auxiliary electrode, and a third region contacting the gate insulating layer. According to claim 2,
The thin film transistor array substrate of According to claim 2,
The thin film transistor array substrate of claim 1 , wherein the third region overlaps a channel of the active layer. According to claim 1,
The first auxiliary electrode contacts the source electrode and the second auxiliary electrode contacts the drain electrode. According to claim 5,
The first auxiliary electrode is disposed under the source electrode and the active layer, and the second auxiliary electrode is disposed under the drain electrode and the active layer. According to claim 1,
The first auxiliary electrode is disposed on the source electrode, and the second auxiliary electrode is disposed on the drain electrode. According to claim 1,
The thin film transistor array substrate of claim 1 , wherein the first auxiliary electrode and the second auxiliary electrode are made of a second carbon allotrope. According to claim 8,
The first carbon allotrope and the second carbon allotrope may be any one of reduced graphene oxide (rGO), non-oxidized graphene, graphene nanoribbon or carbon nanotube (CNT), or a mixture thereof. Board. According to claim 1,
The semiconductor material is any one of ceramic semiconductors, organic semiconductors, transition metal chalcogen compounds and oxide semiconductors, or a mixture thereof. Board;
a gate electrode positioned on the substrate;
an active layer facing the gate electrode and including a first carbon allotrope and a semiconductor material;
a gate insulating layer interposed between the gate electrode and the active layer;
a source electrode and a drain electrode over the gate insulating layer; and
A first auxiliary electrode disposed on the gate insulating film and positioned between the active layer and the source electrode and a second auxiliary electrode positioned between the active layer and the drain electrode
A thin film transistor array substrate comprising a. According to claim 11,
The thin film transistor array substrate of claim 1 , wherein the source electrode and the drain electrode are spaced apart from the active layer. A thin film transistor array substrate according to any one of claims 1 to 10;
an organic insulating film positioned on the thin film transistor array substrate; and
A display device including a pixel electrode positioned on the organic insulating layer. According to claim 13,
an organic light emitting diode electrically connected to the pixel electrode;
an encapsulation layer positioned on the organic light emitting diode; and
The display device further comprising a cover window positioned on the encapsulation layer. According to claim 13,
a common electrode spaced apart from the pixel electrode on the same plane or below; and
The display device further comprising a liquid crystal layer positioned on the common electrode. According to claim 1,
The thin film transistor array substrate of claim 1 , wherein a distance between the first auxiliary electrode and the second auxiliary electrode is smaller than a distance between the source electrode and the drain electrode. According to claim 1,
The active layer directly contacts the gate insulating layer, the first auxiliary electrode, the second auxiliary electrode, the source electrode, and the drain electrode. According to claim 11,
The first auxiliary electrode is disposed on the side surface and upper surface of the source electrode, and the second auxiliary electrode is disposed on the side surface and upper surface of the drain electrode. According to claim 11,
The thin film transistor array substrate of claim 1 , wherein the first auxiliary electrode and the second auxiliary electrode are made of a second carbon allotrope.

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