JP2009065057A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an organic-carbon nanotube display device, wherein reduction in a pixel area-bus wiring width is suppressed, while suppressing leakage current, at off-operation. <P>SOLUTION: A field effect transistor uses carbon nanotubes as channels, wherein the drain electrode and the source electrode are connected in series with a plurality of carbon nanotubes, and carbon nanotubes 1, in contact with the gate via a gate insulating layer, are doped to have an n-type or a p-type, and carbon nanotubes 2, in contact with the source and drain electrodes, are doped in a complementary fashion with the carbon nanotubes 1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a field effect transistor (hereinafter abbreviated as FET) using a carbon nanotube (hereinafter abbreviated as CNT) as a channel, and more particularly to a method for realizing a CNT-FET with improved hysteresis with respect to gate voltage.

  Since CNT can be dissolved in a solution, a manufacturing method such as coating and printing can be used for a CNT transistor (hereinafter referred to as CNT-FET). Therefore, a huge vacuum apparatus is unnecessary, and the manufacturing cost of the CNT-FET can be greatly suppressed. In addition, since processing at a high temperature is unnecessary, a plastic substrate or the like can be used, and a flexible display device or the like can be manufactured.

  FIG. 7 shows a cross-sectional structure of a currently common CNT-FET. The source electrode 1 and the drain electrode 2 are electrically connected by CNT4. In this case, the CNT portion between the source electrode and the drain electrode is referred to as a channel portion. The gate electrode 3 and the CNT 4 constitute a capacitor (capacitor) through the insulating layer 7, and the voltage (or potential, potential) of a part of the channel portion can be changed by the voltage of the gate electrode 3. By changing the potential of the channel portion, the charge concentration or the barrier in the channel can be changed. Thus, the amount of current in the channel is controlled by the gate voltage. This is the same operation as a general silicon field effect transistor. Actually, it is considered that there is another operation principle as described later.

  The CNT constituting the channel may be composed of a single CNT or a plurality of CNTs. In the case of being composed of a plurality of CNTs, the source and drain are not electrically connected by a single CNT, and the source and drain are electrically connected by a plurality of CNTs connected in series. This is the case. Here, only such a channel configured by connecting a plurality of CNTs in series will be described.

  In the configuration in which the source and drain are electrically connected via a plurality of CNTs instead of a single CNT, the source and drain are electrically connected by a single CNT (including a case where there are a plurality of CNTs in parallel). There are advantages in terms of the manufacturing method and electrical characteristics compared to the configuration in which the connection is made electrically.

  First, in terms of the manufacturing method, there is an advantage that a method of printing / coating CNT can be employed. Further, since the channel length can be increased (longer than the CNT length), there is an advantage that an advanced fine processing technique is not required. In terms of electrical characteristics, as will be described later, it is possible to reduce the number of cases of short-circuiting with metal CNTs.

A method for manufacturing a transistor by printing and coating is as follows.
(1) An insulating film is formed on the substrate. If the substrate is insulating, it can be used as it is.
(2) A gate electrode is formed.
(3) A gate insulating film is formed.
(4) An electrode to be a source / drain is formed.
(5) Print and apply the material to be the channel.
(6) A protective film or the like is formed.

  As another method, the order of (1) → (5) → (4) → (3) → (2) → (6), (1) → (2) → (3) → (5) The order of (4) → (6) is also possible.

  The above is the most basic process configuration.

  Although the CNT-FET exhibits excellent characteristics such as high mobility, the problem of hysteresis is a major obstacle to practical use in the current CNT-FET. The reason for the large hysteresis in CNT-FET is that there is no particular conclusion among the researchers, but the fact that moisture is attached to the CNT surface captures charges and affects the gate electric field. (Non-patent Document 1). It is also considered that the gate electric field is dynamically shielded by injecting a current flowing through the channel into a dielectric adjacent to the CNT (Non-Patent Document 2). In any case, the gate electric field is subjected to some correction, and it appears as an electrical characteristic that changes in a reciprocating manner in which the gate voltage is swept, thereby causing a problem of hysteresis.

  One of the factors that affect the conduction characteristics by correcting (influencing) the gate electric field is the thickness of the Schottky barrier at the interface between the source electrode and the CNT.

  There is a Schottky barrier between metal and carbon. Therefore, in the CNT-FET, there is a Schottky barrier at the interface where the source / drain electrodes and the CNT contact. When current is injected into the CNT from the electrode side, it tunnels through the Schottky barrier or is thermally excited and jumps over.

  There are generally two mechanisms for the operation principle of a CNT-FET. One is a mechanism in which the thickness of the Schottky barrier is modulated by the gate electric field, and the probability that carriers are tunneled, that is, the current is modulated. The other is a mechanism in which the difference between the band edge of the channel portion and the Fermi level is modulated, that is, a mechanism in which the carrier density is modulated. As a case where such two mechanisms exist at the same time, there is a so-called back gate FET in which the substrate side is a full surface electrode.

  Therefore, there are two mechanisms that are affected by the change in the gate electric field, and it is considered that these two mechanisms cause the hysteresis.

  Of these two, the thickness of the first Schottky barrier changes abruptly because its tunnel probability changes exponentially with the thickness. This example is also shown in FIG.

  In order to reduce the hysteresis due to the thickness of the Schottky barrier, reducing the gate modulation of the barrier thickness is a fundamental solution. For this reason, it is important to separate the gate voltage from the region where the Schottky barrier exists. Such a method can be performed by locally forming a gate electrode such as a so-called top gate structure or bottom gate structure.

  However, doing so creates another problem. As described above, when the gate is formed away from the Schottky barrier, the thickness of the Schottky barrier is not modulated by the gate voltage, so that the barrier thickness is always thick. For this reason, the channel resistance becomes large, and the amount of current decreases as a whole.

  Incidentally, the structure that separates the position of the gate from the source is not new. The top gate structure is also exemplified in Non-Patent Document 4 and the like. The so-called bottom gate structure refers to a shape in which the top gate structure is embedded on the substrate side, and similarly, the gate position is separated from the source. The bottom gate structure may be considered to operate in the same manner as the top gate structure except that the gate position is geometrically different.

  It can be assumed that the thickness of the Schottky barrier is approximately inversely proportional to the power of the space charge density on the semiconductor side (CNT side) that cancels the electric field of the carrier on the metal side (the cross-sectional area is sufficiently large and the lateral variable Is separable if the can be separated). Doping is effective for increasing the space charge density.

  Patent Document 1 discloses a technique for doping the vicinity of a source / drain electrode. FIG. 11 of this document shows that the current value increases when the on-current value (Vg) is negative due to the doping process, but the threshold value also changes at the same time. Therefore, when the top gate or back gate structure is simply doped, the threshold value also changes depending on the doping amount. Therefore, Patent Document 1 discloses that a top gate structure is provided on an undoped region. However, even in this structure, the threshold value varies depending on the doping amount. Therefore, in order to obtain a desired threshold value while obtaining a good on-current, the gate 2 must be used in combination. In other words, since the threshold voltage (Vt) cannot be easily controlled by a conventional method such as channel doping, some other means is required to adjust the threshold voltage to a value suitable for the complementary CNT-FET. . In order to solve this problem, Patent Document 2 discloses a triple gate structure in which CNTs are controlled to be n-type or p-type by an electric field. However, the method described in Document 2 is inconvenient in practice because the number of electrodes increases and the structure becomes complicated.

  By the way, CNT doping is different from lattice substitution or impurity addition with Si or the like, and a substance for exchanging charges is attached to the CNT surface. In the case of an acceptor, electrons are extracted from the CNT side, and in the case of a donor, the CNT side This is done by giving electrons.

  On the other hand, Patent Document 3 discloses a technique for realizing a pn junction by utilizing a work function difference between a metal and CNT. However, with this method, it is difficult to set the Fermi level in the gate region within a desired range.

In summary, in the conventional CNT-FET structure, it is difficult to realize the hysteresis and the adjustment of the threshold voltage with respect to the gate voltage while maintaining the on-current.
Nano Letters, 2003, Volume 3, 193 Applied Physics Letters, 2006, 89, 162108 Physical Review B, 66, 073307, 2002 Japanese Journal of Applied Physics Part 2, Volume 41, L1049 JP 2006-240898 A JP2007-132721 JP 2005-322836 A

  It solves the problem of hysteresis in FETs using CNTs as a channel, and at the same time, achieves an absolute value of on-current, and further enables threshold voltage adjustment.

The field effect transistor according to the present invention is
In a field effect transistor using a carbon nanotube as a channel,
The drain electrode and the source electrode are connected in series with a plurality of carbon nanotubes,
The first carbon nanotube in contact with the gate through the gate insulating layer is doped n-type or p-type,
The second carbon nanotube in contact with the source and drain electrodes is doped in a complementary manner with the first carbon nanotube.

  The effect of the present invention is that the hysteresis can be suppressed, the threshold value is controlled, and the transistor is in an off state, that is, no current flows when no gate voltage is applied (the gate voltage is zero). Power consumption in integrated circuits fabricated by coating can be reduced and circuit design is facilitated.

  Further, by using CNTs doped in advance, it is not necessary to introduce a doping process separately, and the manufacturing process can be shortened, so that the manufacturing cost can be reduced.

  The present specification discloses a technique capable of overcoming the inherent hysteresis problem of a CNT-FET and allowing independent threshold adjustment. One embodiment of the present invention provides either a stable p-type CNT-FET or a stable n-type CNT-FET. Another embodiment of the present invention provides a complementary CNT device that combines a stable p-type CNT-FET and a stable n-type CNT-FET as described above.

  In the method of manufacturing a CNT-FET according to the present invention, a region where a gate electrode and a CNT serving as a channel are in contact with an insulating layer is formed apart from a source electrode, and the CNT is in contact with the gate electrode via the insulating layer And doping complementary to the CNT in contact with the source electrode.

  More specifically, one embodiment of the CNT-FET of the present invention comprises a system in which the source and drain are electrically coupled to each other via a plurality of CNTs.

  Specifically, the network CNT functions as a spider web or a network-like transmission path composed of a plurality of CNTs. Since the electrical conduction mechanism of network-like CNTs has a mechanism close to that of organic semiconductors, and may be compared with organic semiconductors, as a term that makes it easy to grasp the image, semiconductor materials composed of network-like CNTs, Here, for convenience of explanation, it will be called a CNT thin film. An FET using a CNT thin film is also referred to as a CNT-FET.

  The FET structure composed of a CNT thin film has a central channel region and source / drain electrodes on both sides of the central channel region (that is, on both ends). The source and drain electrodes are in contact with the first side of the CNT at both ends. The CNT-FET structure further includes a gate for applying a potential to the channel region of the CNT to change the CNT-FET from a conductive state to a non-conductive state (ie, to turn the FET on or off). CNT in a region where the source electrode and the CNT are in contact (referred to as a first CNT region), and a region of the CNT on the gate electrode side from the region where the source electrode and the CNT are in contact, excluding the region in contact with the gate electrode through the insulating layer The region, that is, the region not in contact with any electrode (second CNT region) is doped p-type or n-type. A region in contact with the gate electrode through the insulating layer (referred to as a third CNT region) is doped in a complementary manner with the first and second CNT regions. The gate may be a gate conductor (eg, doped polysilicon, tungsten silicide, aluminum, gold or any other suitable conductive material) and a gate dielectric (eg, silicon dioxide, silicon nitride, aluminum oxide or other Any suitable dielectric material).

  The gate is disposed between the source / drain electrodes on the channel region of the CNT. The gate and the source electrode should not overlap even with an insulating layer so that the electric field due to the gate does not affect the Schottky barrier in the CNT thin film near the end of the source electrode. Specifically, it is preferable that the distance is 0.1 μm or more, which is about the thickness of a Schottky barrier at a typical CNT-metal interface.

  The doping to CNT is preferably performed so that the Fermi level is changed by about 0.1 eV to 0.5 eV. This is because the band gap of CNT is at most about 1.2 eV (when the diameter is 0.7 nm), and p-type and n-type have intrinsic Fermi levels at half the band gap width of intrinsic CNT. It is.

  The gate structure disposed away from the source electrode can suppress fluctuation of the Schottky barrier at the source electrode-CNT interface due to the gate voltage. In addition, since the n-pn or pnp doping profile can be realized with the source electrode-gate adjacent portion-drain electrode, the current can be suppressed when the gate voltage is zero, and the so-called normally-off state is obtained. it can.

The threshold of the gate voltage is determined by a voltage that flattens the built-in potential Vbi of the pn junction. Ideally, Vbi can be increased to the band gap of CNT. For example, in the case of CNT having a diameter of about 0.8 nm, the band gap is about 1.1 eV. The rough gate threshold voltage Vth is Vth = (1+ (εCNTtins) / (εinstCNT)) × Vbi, where the thickness of the gate insulating layer and the CNT film is tins and tCNT, respectively, and the relative dielectric constant is εins and εCNT.
It is expressed as This can be derived from a simple model in which the gate voltage is divided by the gate insulating layer and the CNT.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  An embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a cross-sectional view of a p-channel CNT-FET according to the present invention.

  The substrate 8 can be made of, for example, poly (ethylene naphthalate) polyethylenphthalate (PEN), and the thickness thereof is, for example, 200 μm.

  The CNT-FET has a channel composed of CNT thin films 5 and 6, source electrode 1 and drain electrode 2 in contact with both ends thereof, and a CNT thin film region sandwiched between the source and drain electrodes via a gate insulating layer 7. It is comprised from the gate 3 which touched.

  The gate 3 is formed of silver (Ag) having a thickness of, for example, 0.5 μm on the PEN substrate, and the gate 3 is covered with a parylene (more precisely, polyparaxylylene) film having a thickness of, for example, 200 nm formed by thermal CVD. It can be a layer. The length along the channel of the gate is, for example, 100 μm.

A CNT thin film is formed on the gate insulating layer. The density of CNTs is preferably in the range of 1 to 10 / μm ² .

  The source / drain electrodes are, for example, silver, and the thickness thereof is, for example, 0.5 μm. The distance between the source and drain electrodes is, for example, 300 μm. The distance between the source electrode end (or drain electrode end) and the gate is, for example, 10 μm.

  The above is the basic FET structure.

The CNT thin film in contact with the source / drain electrodes may be p-type doped CNTs with F ₄ TCNQ (Tetrafluor-Tetracanoquinodimethane). For the CNT thin film in contact with the gate through the gate insulating layer, CNT doped with n-type with TTF (Tetrathiafulvalene) can be used. The boundary between the p-type and n-type CNTs is at a position intermediate between the gate and source electrodes along the channel. The same applies to the drain side. The CNT thin film on the side in contact with the drain electrode is selected to be lightly doped than the CNT on the source side. In the case of a CNT-FET in which the CNT in contact with the source electrode and the CNT in contact with the drain electrode are doped p-type, the electrons of the dopant (acceptor) in contact with the CNT in contact with the source electrode The affinity is greater than the electron affinity of the dopant (acceptor) in contact with the CNT in contact with the drain electrode. In the CNT-FET in which the CNT in contact with the source electrode and the CNT in contact with the drain electrode are doped n-type, the ionization of the dopant (donor) in contact with the CNT in contact with the source electrode The potential is made smaller than the ionization potential of the dopant (donor) in contact with the CNT in contact with the drain electrode.

The doping amount can be adjusted by the density at which the dopant adheres to the CNT surface. In this case, since the degree of adhesion varies depending on the dopant and the surface state of the CNT, it is necessary to find conditions in advance by trial and error for the CNT and the dopant to be used. As a guide, the surface density of the dopant is 10 ¹⁴ to 10 ¹⁶ / cm ² and the Fermi level is shifted by 0.6 to 0.8 eV.

  Complementary CNTs constituting the CNT thin film can be obtained by dividing a group of CNT aggregates and doping each in a solution. Then, the doped CNTs are locally attached by dropping or printing.

  Thus, preparing p-type and n-type CNTs separately can shorten the manufacturing process. When one CNT is used, the doping process cannot be performed before being deposited on the substrate. Therefore, for example, as shown in FIG. 7, it is necessary to perform a doping process separately for each of the p-type and n-type regions. The number of processes increases, such as forming a mask for protecting the doped region and performing complementary doping.

  When the CNTs constituting the CNT thin film are a mixture of semiconductor and metal, it is desirable that the lengths are uniform. Desirable CNT length (LCNT) is about one-tenth or less of channel length (source-drain distance) LC, and the length distribution is regarded as a normal distribution and σ is 0.5 × 0.1 × Within LC. The length distribution may not be so strict, but it is important that the maximum length does not exceed 0.1 × LC. This is because the length of the CNTs constituting the CNT thin film may affect variations and short circuits. In the case of a CNT in which a semiconductor and a metal are mixed, if the LCNT is about the same as the LC, the metal CNT may be short-circuited. In actual production, fluctuations in the CNT density are unavoidable. On the other hand, the length and density of CNTs that obtain a good switching current ratio are in a contradictory relationship. When CNTs are long, the optimum density is small, and when CNTs are short, the density is the opposite. Therefore, when LCNT is large, it means that the number of constituent CNTs may have a relatively large fluctuation.

  In order to prevent the characteristics from changing due to moisture or oxygen in the air, it is desirable to cover the upper part of the CNT thin film with a parylene film as a protective layer. The thickness of the protective layer is 0.2 μm, for example.

  In the above-described FET structure, the conductivity type of the channel portion CNT may be complementarily changed. That is, by combining elements in which the p-type and n-type are interchanged, a so-called complementary FET can be configured.

  In the above FET structure, the upper surface of the substrate may be protected by the insulating layer 10.

  In the above-described FET structure, a silicon substrate, a glass substrate, stainless steel protected by an insulating layer, or the like, which has been conventionally used, may be used.

  In the above-mentioned FET structure, the gate insulating layer is a high dielectric such as silicon oxide film, silicon nitride film, aluminum oxide film, titanium oxide, hafnia (hafnium oxide) or zirconia (zirconium oxide), which are conventionally used. A rate material or the like may be used. Alternatively, an organic material film such as an acrylic resin such as polyimide, photoresist, PMMA, or polycarbonate may be used.

  In the above-described FET structure, the gate material may be gold, platinum, aluminum, titanium, doped polysilicon, copper, tantalum, tungsten, niobium, molybdenum, or the like.

  In the above FET structure, the source / drain electrodes may be made of gold, platinum, palladium, aluminum, titanium, doped polysilicon, magnesium, calcium, iron, nickel, cobalt, or the like. It is desirable to cover the surface of an easily oxidizable material such as magnesium or calcium with a protective layer such as aluminum. When the CNT in contact with the source / drain is p-type, it is preferable to use gold, platinum, palladium or the like because the Schottky barrier is lowered. When the CNT in contact with the source / drain is n-type, it is desirable to use aluminum, calcium, magnesium or the like because the Schottky barrier is lowered. Moreover, a TTF-TCNQ complex etc. may be sufficient.

In the above FET structure, the p-type dopant (acceptor) of the channel CNT includes fullerene fluoride, Cl ₂ TCNQ, TCNQ, p-chloroanil (Terachloro-p-benzo-quinine), DDQ (2,3-Dichloro- 5,6-dicyano-p-benzo-quinine), C ₆₀ F ₃₆ (fluorofullerene), or the like may be used. In addition, there are no limitations on materials having electron withdrawing properties such as -F group, -Cl group -Br group, -I group (halogen compound), = O group (oxo compound), and ≡N group. In general, a material having an electron affinity in vacuum of 2.7 eV or more is preferable.

In the above FET structure, the n-type dopant (donor) of the channel CNT includes TDAE (Tetrakis (dimethylamino) ethylene), TMTSF (Tetramethyltetralena-fullvalene), TMPD (N, N, N ′, N′-Teramethyl-p -Phenylenediamine), decamethynickelosene (Bis (pentamethycyclo-pentadienyl) nickel), and the like may be used. In addition, the material having an electron donating group such as (CH ₃ ) ₃ C— group, (CH ₃ ) ₂ CH— group, CH ₃ CH ₂ — group or CH ₃ — group is not limited. In general, a material having an ionization potential in a vacuum of 5.8 eV or less is preferable.

  In the above-described FET structure, the positional relationship between the source and drain electrodes is not necessarily symmetric when viewed from the gate. In order to increase the breakdown voltage between the source and the drain, it is desirable to make the gate-drain larger (longer) than the gate-source. For example, the gate-drain interval is made twice the gate-source interval.

  In the above FET structure, the positional relationship between the substrate, CNT, and source or drain electrode may be as follows: on substrate-source or drain electrode-CNT. That is, the CNT may be positioned above the source or drain electrode when the substrate is on the bottom side. This structure is convenient when a structure other than the channel is first manufactured using a lithography technique and then only the channel is formed by printing.

  FIG. 2 shows another embodiment of a CNT-FET. The basic FET structure is the same as in FIG.

F ₄ TCNQ, which is a p-type dopant, is inserted into the interface between the CNT in the CNT region in the middle of the gate and the source electrode and the insulating layer along the channel and channel of the CNT in contact with the source electrode. Similarly, a dopant is inserted on the drain side. TTF, which is an n-type dopant, is inserted into the interface between the CNT and the insulating layer in the gate region.

In the above FET structure, the p-type dopant (acceptor) of the channel CNT includes fullerene fluoride, Cl ₂ TCNQ, TCNQ, p-chloroanil (Terachloro-p-benzo-quinine), DDQ (2,3-Dichloro- 5,6-dicyano-p-benzo-quinine), C ₆₀ F ₃₆ (fluorofullerene), or the like may be used. In addition, there are no limitations on materials having electron withdrawing properties such as -F group, -Cl group -Br group, -I group (halogen compound), = O group (oxo compound), and ≡N group. In general, a material having an electron affinity in vacuum of 2.7 eV or more is preferable.

In the above FET structure, the n-type dopant (donor) of the channel CNT includes TDAE (Tetrakis (dimethylamino) ethylene), TMTSF (Tetramethyltetralena-fullvalene), TMPD (N, N, N ′, N′-Teramethyl-p -Phenylenediamine), decamethynickelosene (Bis (pentamethycyclo-pentadienyl) nickel), and the like may be used. In addition, the material having an electron donating group such as (CH ₃ ) ₃ C— group, (CH ₃ ) ₂ CH— group, CH ₃ CH ₂ — group or CH ₃ — group is not limited. In general, a material having an ionization potential in a vacuum of 5.8 eV or less is preferable.

  FIG. 3 shows another embodiment of a CNT-FET. The basic FET structure is the same as in FIG. 1 except that the gate is at the top.

The CNT thin film in contact with the source / drain electrodes is made of CNT doped in p-type with F ₄ TCNQ (Tetrafluor-Tetracanoquinodimethane). For the CNT thin film in contact with the gate through the gate insulating layer, CNT doped with n-type with TTF (Tetrathiafulvalene) is used. The boundary between the p-type and n-type CNTs is at a position intermediate between the gate and source electrodes along the channel. The same applies to the drain side. The CNT thin film on the side in contact with the drain electrode is selected to be lightly doped than the CNT on the source side.

In the above FET structure, the p-type dopant (acceptor) of the channel CNT includes fullerene fluoride, Cl ₂ TCNQ, TCNQ, p-chloroanil (Terachloro-p-benzo-quinine), DDQ (2,3-Dichloro- 5,6-dicyano-p-benzo-quinine), C ₆₀ F ₃₆ (fluorofullerene), or the like may be used. In addition, there are no limitations on materials having electron withdrawing properties such as -F group, -Cl group -Br group, -I group (halogen compound), = O group (oxo compound), and ≡N group. In general, a material having an electron affinity in vacuum of 2.7 eV or more is preferable.

In the above FET structure, the n-type dopant (donor) of the channel CNT includes TDAE (Tetrakis (dimethylamino) ethylene), TMTSF (Tetramethyltetralena-fullvalene), TMPD (N, N, N ′, N′-Teramethyl-p -Phenylenediamine), decamethynickelosene (Bis (pentamethycyclo-pentadienyl) nickel), and the like may be used. In addition, the material having an electron donating group such as (CH ₃ ) ₃ C— group, (CH ₃ ) ₂ CH— group, CH ₃ CH ₂ — group or CH ₃ — group is not limited. In general, a material having an ionization potential in a vacuum of 5.8 eV or less is preferable.

  FIG. 4 shows another embodiment of a CNT-FET. The basic FET structure is the same as in FIG.

F ₄ TCNQ, which is a p-type dopant, is inserted into the interface between the CNT in the CNT region in the middle of the gate and the source electrode and the insulating layer along the channel and channel of the CNT in contact with the source electrode. Similarly, a dopant is inserted on the drain side. TTF, which is an n-type dopant, is inserted into the interface between the CNT and the insulating layer in the gate region.

  In this example, a silicon oxide film is formed on a silicon substrate. A CNT-FET is composed of a channel made of a CNT thin film, a source electrode and a drain electrode that are in contact with both ends thereof, and a gate that is in contact with a CNT thin film region sandwiched between the source and drain electrodes via an insulating layer. Has been.

In the above FET structure, p-type dopants (acceptors) of the channel CNT include F ₄ TCNQ, fluoride fullerene, Cl ₂ TCNQ, TCNQ, p-chloroanil (Terachloro-p-benzo-quinine), DDQ (2,3-Dichloro-5,6-dicyano-p-benzo-quinine), C ₆₀ F ₃₆ (fluorofullerene), or the like may be used. In addition, the materials having an electron withdrawing property such as -F group, -Cl group -Br group, -I group (halogen compound), = O group (oxo compound) or ≡N group are not limited. In general, a material having an electron affinity in vacuum of 2.7 eV or more is preferable.

In the above-described FET structure, the n-type dopant (donor) of the channel CNT includes TDAE (Tetrakis (dimethylamino) ethylene), TMTSF (Tetramethyltetralena-fulvalene), TMPD (N, N, N ′, N ′) in addition to TTF. -Teramethyl-p-phenylenediamine), decathynickelosene (Bis (pentamethycyclo-pentadienyl) nickel), etc. may be used. In addition, the material having an electron donating group such as (CH ₃ ) ₃ C— group, (CH ₃ ) ₂ CH— group, CH ₃ CH ₂ — group or CH ₃ — group is not limited. In general, a material having an ionization potential in a vacuum of 5.8 eV or less is preferable.

  The upper part of the CNT thin film is covered with a parylene film having a thickness of, for example, 200 nm as a protective layer.

(Description of manufacturing method)
Next, an example of the manufacturing method of the first embodiment of FIG. 1 will be described with reference to FIG.

(1) First, a gate electrode is formed on a PEN substrate.
For example, in the case of silver, it is formed by a dispenser and a syringe or ink jet printing using a silver paste ink. In order to remove the additive between the silver particles after the formation, heat treatment is performed at about 150 ° C. in the atmosphere.

  As another method, for example, after sputtering (or vapor deposition) film formation on the entire surface of the substrate, pattern formation is performed using general lithography, and wet etching is performed. In this case, aluminum or the like is used as a gate material. For etching aluminum, a general etchant can be used. For example, a mixture of phosphoric acid, nitric acid, acetic acid and water is commonly used. Photolithographic positive resist alkaline developer can also be used as an etchant. Since silver can generally use an etchant, this method can also be used.

  As another method, for example, a pattern in which a resist is removed from a place where a gate is to be formed is first formed by lithography, and aluminum is formed there. In this case, a highly anisotropic film forming method such as vapor deposition is preferable. Thereafter, unnecessary aluminum is removed together with the resist with a solvent for dissolving the resist. This is generally known as the lift-off method.

(2) A gate insulating film is formed.
For example, a parylene film is formed as the gate insulating film. For example, a film can be formed by using a vapor deposition method using diparaxylylene monomer as a raw material. The thickness is 0.2 μm, for example.

  As another method, for example, a silicon nitride film can be formed by sputtering. The target is silicon nitride and the plasma gas is argon gas. In order to improve the film quality, 20 sccm of nitrogen is also introduced at the same time. The pressure is 2 pascals. The film thickness is 0.2 μm.

(3) A CNT film is formed.
For example, a method in which a CNT solution is dropped and dried only on the channel portion using a dispenser and a syringe is used. In that case, CNT is dissolved in dichloroethane. The density is adjusted to a density of about 10 to the seventh power. Specifically, first, 1 milligram of CNT is dissolved in 1000 milliliters of dichloroethane. This is dispersed with ultrasonic waves for about 1 hour. Next, 3 milliliters is removed from the 1000 milliliter CNT solution and diluted with 27 milliliters of dichloroethane. Thus, a CNT solution with a weight ratio of about 10 to the power of minus 7 is obtained. This is dispersed for 1 hour with a commercially available ultrasonic homogenizer. In the case of using a dispenser and a syringe, about 40 microliters of the CNT solution is dropped and then naturally dried. Although the density of CNTs varies depending on the surface state of the substrate, the density is about 0.6 / μm ² in 1 to 5 dropping steps. The density of CNTs is adjusted by the number of dropping steps.

  As another method, it is also possible to print with an inkjet printer, for example. In order to form a channel with complementary-doped CNTs, an n-type or p-type CNT film is first formed, and then a complementary CNT film is formed. In such a process, it is easy to form by a method using a dispenser and a syringe or an ink jet printer.

  Such a method capable of locally dripping does not require a step of removing unnecessary portions as described below.

As another method, for example, a film is formed by spin coating. First, CNT is dissolved in dichloroethane. The density is adjusted to a density of about 10 to the sixth power. Specifically, first, 1 milligram of CNT is dissolved in 100 milliliters of dichloroethane. This is dispersed with ultrasonic waves for about 1 hour. Next, 3 ml is taken out from this 100 ml CNT solution and diluted with 27 ml dichloroethane. Thus, a CNT solution having a weight ratio of about 10 to the negative sixth power is obtained. This is dispersed for 1 hour with a commercially available ultrasonic homogenizer. Spin coating is performed by dropping about 40 microliters of the diluted and ultrasonically dispersed CNT solution onto the substrate and then rotating the substrate at about 800 rpm for about 10 seconds. Although the density of CNTs varies depending on the surface state of the substrate, the density is about 0.6 / μm ² in 4 to 5 spin coating steps. The density of CNTs is adjusted by the number of spin coating steps. In this state, since the CNTs are dispersed on the entire surface of the substrate, separation from the adjacent elements is not performed, so unnecessary CNTs are removed. Although omitted in FIG. 6, it is removed in the same process as the formation of the gate and sub-gate electrodes. The removal uses oxygen ashing. A silicon nitride film is formed on the mask for ashing by sputtering, a pattern is formed by photolithography, and the silicon nitride film other than the channel portion is removed by dry etching. Thereafter, oxygen ashing is performed.

  The lift-off method described above can also be used for removing unnecessary portions of CNTs. That is, a pattern in which the resist is removed from only the channel portion is formed by lithography, and then CNT is spin-coated. Thereafter, unnecessary portions of CNT together with the resist are removed with a resist solvent.

  As another CNT film forming method, for example, there is a method in which a substrate is dipped in a CNT solution and then lifted and dried. In the method of pulling up after the immersion, CNT adheres to the entire surface of the substrate in the same manner as the above method, and thus the same removal process is necessary.

(4) A source electrode and a drain electrode are formed.
For example, in the case of silver, a silver paste ink is used and formed by a dispenser and a syringe or ink jet printing. In order to remove the additive between the silver particles after the formation, heat treatment is performed at about 150 ° C. in the atmosphere.

  As another method, for example, after depositing gold on a photoresist patterned by photolithography, unnecessary portions are removed by lift-off.

  As another method, for example, a technique generally used in a normal method for manufacturing a semiconductor device can be used. As an example, there may be mentioned a method in which a metal is first formed on the entire surface of the third insulating layer, and then a resist pattern is formed by lithography and etching is performed using the resist pattern as a mask.

(5) A protective film is formed.
For example, a parylene film is formed as the protective layer. For example, a film can be formed by using a vapor deposition method using diparaxylylene monomer as a raw material. .

  As another method, for example, a silicon nitride film can be formed by sputtering.

  In addition to the above, the gate insulating film and the protective film should be formed using a vapor deposition method, a thermal vapor deposition method, a method of heating and activating and depositing an organic insulating layer, which are generally used as a manufacturing method. Can do.

  The order of the above (3) and (4) may be switched to form a CNT film on the source / drain electrodes.

  Next, a manufacturing method in which a doping step is separately provided will be described with reference to FIG.

  (1) As the substrate, for example, 200 μm-thick polyethylene naphthalate (polyethylenenaphthalate) (PEN) can be used.

(2) The gate electrode 3 is formed on the insulating film.
For example, aluminum is formed on an insulating film by sputtering, a film is formed over the insulating film, a pattern is formed using general lithography, and wet etching is performed. For etching aluminum, a general etchant can be used. For example, a mixture of phosphoric acid, nitric acid, acetic acid and water is commonly used. Photolithographic positive resist alkaline developer can also be used as an etchant.

  As another method, for example, a pattern from which a resist is removed at a place where a gate and a sub-gate are to be formed is formed using lithography, and aluminum is formed there. In this case, a highly anisotropic film forming method such as vapor deposition is preferable. Thereafter, unnecessary aluminum is removed together with the resist with a solvent for dissolving the resist. This is generally known as the lift-off method.

  As another method, for example, a silver paste ink can be used to form an electrode by using a dispenser and a syringe or ink jet printing. In this case, heat treatment is performed at about 150 ° C. in the atmosphere in order to remove the additive between the silver particles after the formation.

  When the substrate is not an insulator such as PEN, for example, when the substrate is stainless steel, an insulating layer 10 such as a parylene film is provided.

(3) The gate insulating film 7 is formed.
For example, a silicon nitride film is formed by sputtering. The target is silicon nitride and the plasma gas is argon gas. In order to improve the film quality, 20 sccm of nitrogen is also introduced at the same time. The pressure is 2 pascals. The film thickness is 0.4 μm. Further, at this stage, the data line 101 and the current supply line 111 are formed. This uses the same process as the above-mentioned sub-gate.

(4) Form a CNT film and form a protective layer For example, a film is formed by spin coating. First, CNT is dissolved in dichloroethane and adjusted to a concentration of about 10 minus 6 to the weight ratio. Specifically, for example, 1 milligram of CNT is first dissolved in 100 milliliters of dichloroethane. This is dispersed with ultrasonic waves for about 1 hour. Next, 3 ml is taken out from this 100 ml CNT solution and diluted with 27 ml dichloroethane. Thus, a CNT solution having a weight ratio of about 10 to the negative sixth power is obtained. This is dispersed for 1 hour with a commercially available ultrasonic homogenizer. Spin coating is performed by dropping about 40 microliters of the diluted and ultrasonically dispersed CNT solution onto the substrate and then rotating the substrate at about 800 rpm for about 10 seconds. Although the density of CNTs varies depending on the surface state of the substrate, the density is about 0.6 / μm ² in 4 to 5 spin coating steps. The density of CNTs is adjusted by the number of spin coating steps. In this state, since the CNTs are dispersed on the entire surface of the substrate, separation from the adjacent elements is not performed, so unnecessary CNTs are removed. Although omitted in FIG. 6, it is removed in the same process as the formation of the gate electrode. The removal uses oxygen ashing. A silicon nitride film is formed on the mask for ashing by sputtering, a pattern is formed by photolithography, and the silicon nitride film other than the channel portion is removed by dry etching. Thereafter, oxygen ashing is performed.

  The lift-off method described above can also be used for removing unnecessary portions of CNTs. That is, a pattern in which the resist is removed from only the channel portion is formed by lithography, and then CNT is spin-coated. Thereafter, unnecessary portions of CNT together with the resist are removed with a resist solvent.

  As another CNT film forming method, for example, a method in which a substrate is dipped in a CNT solution and then dried and dried can be used. The method of pulling up after dipping requires the same removal step because CNT adheres to the entire surface of the substrate as in the above method.

As another method, a method of dropping and drying the CNT solution only on the channel portion with a dispenser and a syringe is used. In that case, CNT is dissolved in dichloroethane. The density is adjusted to a density of about 10 to the seventh power. Specifically, for example, 1 milligram of CNT is first dissolved in 1000 milliliters of dichloroethane. This is dispersed with ultrasonic waves for about 1 hour. Next, 3 milliliters is removed from the 1000 milliliter CNT solution and diluted with 27 milliliters of dichloroethane. Thus, a CNT solution with a weight ratio of about 10 to the power of minus 7 is obtained. This is dispersed for 1 hour with a commercially available ultrasonic homogenizer. In the case of using a dispenser and a syringe, about 40 microliters of the CNT solution is dropped and then naturally dried. Although the density of CNTs varies depending on the surface state of the substrate, the density is about 0.6 / μm ² in 1 to 5 dropping steps. The density of CNTs is adjusted by the number of dropping steps.

  As another method, printing with an inkjet printer is also possible. Such a method capable of locally dripping does not require a step of removing unnecessary portions as described below.

  An example of the protective film is a silicon oxide film formed by sputtering.

  In addition to the above, the gate insulating film and the protective film are formed by a vapor deposition method, a thermal vapor deposition method, a method of heating and activating and depositing an organic insulating layer, which are generally used as manufacturing methods.

  As another method, a parylene film is formed. A vapor deposition method using diparaxylylene monomer as a raw material is used.

  As another method, an organic film such as a photoresist is applied by spin coating or the like, followed by curing in a nitrogen atmosphere. The temperature of the curing process depends on the material, but is higher than the vitrification point.

(5) The element is separated.
In this case, for example, the insulating layer 9 is partly peeled to expose the CNTs. Peeling is performed by wet etching using weak dry etching or buffered fluoro acid (BHF). In element isolation, the CNT channel is separated from adjacent elements. That is, it is burned out by oxygen ashing or the like. Alternatively, it is burned out by laser irradiation or evaporated.

(6) Doping is applied to the CNT in the source / drain electrode region.
In this case, for example, the insulating layer 9 is partly peeled to expose the CNTs. Peeling is performed by wet etching using weak dry etching or buffered fluoro acid (BHF). Doping is performed by immersing the substrate in a TCNQ solution dissolved in chloroform. After doping, the upper part is covered with a protective layer 11. This is also a silicon oxide film formed by sputtering.

(7) A protective layer is formed.
A process similar to the formation of the protective layer 7 is used.

(8) The resist for forming the source / drain electrodes is patterned.
Conventional lithography technology is used.

(9) Volume the source / drain electrode material.
For example, sputtering or electron beam evaporation is used.

(10) Form source / drain electrodes.
An unnecessary resist and metal are removed by a lift-off method.

(11) Doping the gate portion.
Similarly to the above (7), part of the protective layers 9 and 11 in the gate region is removed and doped. Doping is performed by immersing the substrate in a TTF solution dissolved in chloroform.

(12) Cover the gate portion with a protective layer.
After doping, the upper part is covered with a protective layer 13. The protective layer 13 forms a parylene film. A vapor deposition method using diparaxylylene monomer as a raw material is used.

  FIG. 9 shows an embodiment of a NOT gate logic circuit composed of complementary CNT-FETs. The CNT-FET configured as shown in FIG. 1 is composed of p-type (left side) and n-type (right side) channels, and has a common drain. In FIG. 9, although the gates 3 and 33 are depicted as being independent, they are electrically shorted in the vicinity of the FET. The source / drain electrodes 1, 2 and 31, 32 are formed of gold and aluminum, respectively. For this, one having a small Schottky barrier with p-type and n-type CNTs is selected.

  Below, the manufacturing method of embodiment of FIG. 9 is demonstrated.

(1) First, a gate electrode is formed on a PEN substrate.
For example, in the case of silver, a silver paste ink is used and formed by a dispenser and a syringe or ink jet printing. In order to remove the additive between the silver particles after the formation, heat treatment is performed at about 150 ° C. in the atmosphere.

  As another method, for example, after sputtering (or vapor deposition) film formation on the entire surface of the substrate, pattern formation is performed using general lithography, and wet etching is performed. In this case, aluminum or the like is used as a gate material. For etching aluminum, a general etchant can be used. For example, a mixture of phosphoric acid, nitric acid, acetic acid and water is commonly used. Photolithographic positive resist alkaline developer can also be used as an etchant. Since silver can generally use an etchant, this method can also be used.

  As another method, for example, a pattern in which a resist is removed from a place where a gate is to be formed is first formed by lithography, and aluminum is formed there. In this case, a highly anisotropic film forming method such as vapor deposition is preferable. Thereafter, unnecessary aluminum is removed together with the resist with a solvent for dissolving the resist. This is generally known as the lift-off method.

(2) A gate insulating film is formed.
For example, a parylene film is formed as the gate insulating film. A vapor deposition method using diparaxylylene monomer as a raw material is used. The thickness is 0.2 μm.

  As another technique, a silicon nitride film can be formed by sputtering. The target is silicon nitride and the plasma gas is argon gas. In order to improve the film quality, 20 sccm of nitrogen is also introduced at the same time. The pressure is 2 pascals. The film thickness is 0.2 μm.

(3) A CNT film is formed.
For example, a method of dropping and drying the CNT solution only on the channel portion with a dispenser and a syringe can be used. In that case, CNT is dissolved in dichloroethane. The density is adjusted to a density of about 10 to the seventh power. Specifically, first, 1 milligram of CNT is dissolved in 1000 milliliters of dichloroethane. This is dispersed with ultrasonic waves for about 1 hour. Next, 3 milliliters is removed from the 1000 milliliter CNT solution and diluted with 27 milliliters of dichloroethane. Thus, a CNT solution with a weight ratio of about 10 to the power of minus 7 is obtained. This is dispersed for 1 hour with a commercially available ultrasonic homogenizer. In the case of using a dispenser and a syringe, about 40 microliters of the CNT solution is dropped and then naturally dried. Although the density of CNTs varies depending on the surface state of the substrate, the density is about 0.6 / μm ² in 1 to 5 dropping steps. The density of CNTs is adjusted by the number of dropping steps.

As another method, for example, printing with an ink jet printer is also possible.
In order to form a channel with complementary-doped CNTs, an n-type or p-type CNT film is first formed, and then a complementary CNT film is formed. In such a process, it is easy to form by a method using a dispenser and a syringe or an ink jet printer. Such a method capable of locally dripping does not require a step of removing unnecessary portions as described below.

As another method, for example, a film is formed by spin coating. First, CNT is dissolved in dichloroethane. The density is adjusted to a density of about 10 to the sixth power. Specifically, first, 1 milligram of CNT is dissolved in 100 milliliters of dichloroethane. This is dispersed with ultrasonic waves for about 1 hour. Next, 3 ml is taken out from this 100 ml CNT solution and diluted with 27 ml dichloroethane. Thus, a CNT solution having a weight ratio of about 10 to the negative sixth power is obtained. This is dispersed for 1 hour with a commercially available ultrasonic homogenizer. Spin coating is performed by dropping about 40 microliters of the diluted and ultrasonically dispersed CNT solution onto the substrate and then rotating the substrate at about 800 rpm for about 10 seconds. Although the density of CNTs varies depending on the surface state of the substrate, the density is about 0.6 / μm ² in 4 to 5 spin coating steps. The density of CNTs is adjusted by the number of spin coating steps. In this state, since the CNTs are dispersed on the entire surface of the substrate, separation from the adjacent elements is not performed, so unnecessary CNTs are removed. Although omitted in FIG. 6, it is removed in the same process as the formation of the gate and sub-gate electrodes. The removal uses oxygen ashing. A silicon nitride film is formed on the mask for ashing by sputtering, a pattern is formed by photolithography, and the silicon nitride film other than the channel portion is removed by dry etching. Thereafter, oxygen ashing is performed.

  The lift-off method described above can also be used for removing unnecessary portions of CNTs. That is, a pattern in which the resist is removed from only the channel portion is formed by lithography, and then CNT is spin-coated. Thereafter, unnecessary portions of CNT together with the resist are removed with a resist solvent.

  As another CNT film forming method, for example, the substrate can be formed by dipping the substrate in a CNT solution and then drying it. In the method of pulling up after the immersion, CNT adheres to the entire surface of the substrate in the same manner as the above method, and thus the same removal process is necessary.

(4) A source electrode and a drain electrode are formed.
For example, a silver paste ink or a gold paste ink is used to form a dispenser and a syringe or ink jet printing. In order to remove the additive between the silver particles after the formation, heat treatment is performed at about 150 ° C. in the atmosphere.

  As another method, for example, gold, silver, or aluminum is deposited on a photoresist patterned by photolithography by vapor deposition, and then unnecessary portions are removed by lift-off.

  As another technique, for example, a technique generally used in a normal method for manufacturing a semiconductor device can be used. As an example, there may be mentioned a method in which a metal is first formed on the entire surface of the third insulating layer, and then a resist pattern is formed by lithography and etching is performed using the resist pattern as a mask.

  In the case of FIG. 9, after forming the source / drain on the FET side operating in n-type or p-type, the source / drain of CNT operating in a complementary manner is formed.

(5) A protective film is formed.
For example, a parylene film is formed as a protective layer. A vapor deposition method using diparaxylylene monomer as a raw material is used.

  As another method, a silicon nitride film can be formed by sputtering.

  In addition to the above, the gate insulating film and the protective film are formed by a vapor deposition method, a thermal vapor deposition method, a method of heating and activating and depositing an organic insulating layer, which are generally used as manufacturing methods.

  The order of the above (3) and (4) may be switched to form a CNT film on the source / drain electrodes.

  A display apparatus is mentioned as an example of utilization of this invention.

Sectional drawing of CNT-FET of this invention. Sectional drawing of another Example of CNT-FET of this invention. Sectional drawing of another Example of CNT-FET of this invention. Sectional drawing of another Example of CNT-FET of this invention. The manufacturing method of CNT-FET of FIG. Sectional drawing of CNT-FET of a conventional structure. Sectional drawing of CNT-FET of a conventional structure. A manufacturing method when a doping step is provided separately. An embodiment of a NOT gate logic circuit composed of complementary CNT-FETs.

Explanation of symbols

1 Source electrode 2 Drain electrode 3 Gate electrode 4 Channel layer (undoped CNT film)
5 Channel layer (p-type CNT film)
6 Channel layer (n-type CNT film)
7 Gate insulating layer 8 Substrate 9 Protective layer 10 Insulating layer 11 Current supply line 12 Insulating layer 31 for insulating the substrate surface Source electrode 32 Drain electrode 33 Gate electrode

Claims (10)

In a field effect transistor using a carbon nanotube as a channel,
The drain electrode and the source electrode are connected in series with a plurality of carbon nanotubes,
The first carbon nanotube in contact with the gate through the gate insulating layer is doped n-type or p-type,
A field effect transistor, wherein the second carbon nanotubes in contact with the source electrode and the drain electrode are doped in a complementary manner to the first carbon nanotubes.   The material having an electron affinity in a vacuum of 2.7 eV or more and a material having an ionization potential in a vacuum of 5.8 eV or less are in contact with the carbon nanotubes. Field effect transistor.   A first material having an electron affinity in a vacuum of 2.7 eV or more and a second material having an ionization potential in a vacuum of 5.8 eV or less are located at the interface between the gate insulating layer and the carbon nanotube. The field effect transistor according to claim 1, wherein the field effect transistor is in contact with the carbon nanotube.   4. The field effect transistor according to claim 1, wherein a distance between the gate and the drain electrode is larger than a distance between the gate and the source electrode. In the field effect transistor in which the second carbon nanotubes in contact with the source electrode and the second carbon nanotubes in contact with the drain electrode are doped p-type,
The electron affinity of the material in contact with the second carbon nanotube in contact with the source electrode is greater than the electron affinity of the material in contact with the second carbon nanotube in contact with the drain electrode. The field effect transistor according to any one of claims 1 to 3, wherein the field effect transistor is provided. In the field effect transistor in which the second carbon nanotube in contact with the source electrode and the second carbon nanotube in contact with the drain electrode are doped n-type,
The ionization potential of the second material in contact with the carbon nanotube is smaller than the ionization potential of the material in contact with the second carbon nanotube in contact with the drain electrode. The field effect transistor according to any one of claims 1 to 3, wherein the field effect transistor is provided.   5. The positional relationship among the gate, the gate insulating layer, the carbon nanotube, and the substrate is formed in the order of the substrate, the carbon nanotube, the gate insulating layer, and the gate. The field effect transistor according to claim 1.   5. The positional relationship among the gate, the gate insulating layer, the carbon nanotube, and the previous substrate is formed in the order of the substrate, the gate, the gate insulating layer, and the carbon nanotube. The field effect transistor according to claim 1.   The boundary between the carbon nanotubes doped in p-type and n-type is in the middle between the gate and the source electrode and in the middle between the gate and the drain electrode. The field effect transistor according to claim 1.   5. A logic circuit using the field-effect transistor according to claim 1 in a complementary manner.

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