KR20180071703A - Power supply apparatus - Google Patents

Abstract

Disclosed is a power supply device capable of reducing costs and a standby current. The power supply device includes: a first rectifying circuit for smoothing AC power; a transformer including a primary winding and a secondary winding; a second rectifying circuit for rectifying the power outputted through the secondary winding and outputting an output voltage and a secondary side ground voltage; and a controller for controlling the switching timing of the primary winding based on a first sensing current corresponding to the output voltage and a second sensing current corresponding to the secondary ground voltage. Since an output target voltage which is a difference voltage between a secondary side output voltage and the secondary side ground voltage can be simply obtained, a photo-coupler can be omitted from the power supply device.

Description

POWER SUPPLY APPARATUS

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply apparatus, and more particularly, to a power supply apparatus capable of reducing a cost and reducing standby current.

In general, the Switched-Mode Power Supply (SMPS) is a device that converts DC input voltage to square-wave voltage by using a semiconductor device such as a power transistor as a switch, and then obtains a DC output voltage after being controlled through a filter.

SMPS uses a photo-coupler to use the output voltage (VOUT) of the secondary side because the potential of the primary side ground voltage (GND1) and the secondary side ground voltage (GND2) of the power conversion transformer is different. To monitor the secondary side voltage.

There may be a difference in relative voltage between the ground voltage GND1 on the primary side and the ground voltage GND2 on the secondary side. It may vary from 0V to about 2KV (2,000V).

Therefore, in the conventional method, the voltage of the secondary side is monitored by the controller of the primary side using a photo-coupler capable of transmitting signals at different ground levels, thereby controlling the switching timing of the transformer.

However, this monitoring method is costly due to the use of a photo-coupler, and a separate circuit for monitoring is required on the secondary side.

In addition, it is difficult to reduce the current consumption in the stand-by mode without load on the secondary side since it must be monitored at all times.

Korean Registered Patent No. 1996-0016603 (Dec. 16, 1996) (SMPS overvoltage rise prevention circuit) Korean Registered Patent No. 10-0681641 (May 28, 2007) (Variable Constant Voltage Device in SMPS) Korean Patent No. 10-0180480 (Dec. 01, 1998) (Line filter circuit of switching power supply SMPS)

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and it is an object of the present invention to provide a photoelectric transducer which can reduce a cost by omitting a photo-coupler, monitor a no-load state or a short state of a secondary side, Power supply that can reduce power consumption.

In order to achieve the object of the present invention, the power supply apparatus according to an embodiment includes a primary rectifying circuit for smoothing an AC power supply; A transformer including a primary winding and a secondary winding; A secondary rectifying circuit for rectifying a power output through the secondary winding and outputting an output voltage and a secondary side ground voltage; And a controller for controlling the switching timing of the primary winding based on a first sensing current corresponding to the output voltage and a second sensing current corresponding to the secondary side ground voltage.

In one embodiment, the controller may include a second generation current conveyor that detects the first sensing current and the second sensing current.

In one embodiment, the second generation current conveyor comprises a first balanced output rail-to-rail second generation current conveyor (hereinafter referred to as a first BORRCC II); And a second balanced output rail-to-rail second generation current conveyor (hereinafter referred to as a second BORRCC II), wherein the first BORRCC II and the second BORRCC II current conveyor 2 BORRCC II each implement a rail-to-rail input / output through an upper differential input stage and a lower differential input stage commonly connected to the Y-port and the X-port, and the current applied by the bias voltage is connected to the Y- A core block for outputting a first driving voltage (P_DRV) and a second driving voltage (N_DRV) by mirroring based on a voltage of an X-port; And outputting a normal output current through a ZP port in response to the first driving voltage (P_DRV) and the second driving voltage (N_DRV), and outputting an inverted output current having a phase opposite to the normal output current to a ZN- Port and an X-port of the first BORRCC II define a YP-port and an XP-port, respectively, and the Y-port and the X-port of the second BORRCC II define a Y- Ports of the first BORRCC II and the ZN-ports of the second BORRCC II define a ZPF-port, and the ZN-port of the first BORRCC II defines the ZN- -Port and the ZP-port of the second BORRCCII can be connected to define a ZNF-port.

In one embodiment, the controller further includes an upper FBDR RCC II and a lower FBDR RCC II for measuring the DP signal and the DM signal, respectively, provided from the whole object via a USB cable to variably adjust the secondary output voltage according to the entire object .

In one embodiment, the common mode voltage VCM is applied to the YP-port and the YN- port of the upper FBDRRCC II, one end of the DP resistor RDP is connected to the XP-port of the upper FBDRRCC II, Resistor RXN is connected to the XN- port of the upper FBDRRCCII and the other end of the XN-resistor RXN is connected to the secondary ground voltage GND2, The ZP-port of the upper FBDRRCC II is connected to the ZPO1 terminal and the common mode voltage VCM is connected to the ZP-resistor RZP. The ZN-port of the upper FBDRRCC II is connected to the ZNO1 terminal and the ZN- The common mode voltage VCM can be connected.

In one embodiment, the common mode voltage VCM is applied to the YP-port and the YN- port of the lower FBDRRCC II, one end of the DM-resistor RDM is connected to the XP-port of the lower FBDRRCC II, One end of the XN resistor RXN is connected to the XN port of the lower FBDRRCC II and the other end of the XN resistor RXN is connected to the secondary ground voltage GND2, The ZP-port of the lower FBDRRCC II is connected to the ZPO 2 terminal and the common mode voltage VCM is connected to the ZP-resistor RZP. The ZN-port of the lower FBDRRCC II is connected to the ZNO 2 terminal, The common mode voltage VCM can be connected.

In one embodiment, the power supply includes an EMI filter (F0) composed of L and R, connected between the plug and the bridge diode, for preventing switching noise generated by switching of the transformer from being radiated to EMI, As shown in FIG.

In one embodiment, the power supply comprises a voltage clamping snubber (F1) coupled to both ends of the primary winding to prevent damage to the switch due to sparking voltage caused by leakage inductance present in the transformer .

In one embodiment, the power supply device is connected to the other end of the primary winding and the other end of the tertiary winding to prevent damage to the switch due to a back electromotive voltage generated when a switch provided on the primary side is turned on / off And an RCD snubber (F2) for preventing the RCD snubber (F2).

According to such a power supply device, since the output target voltage VO which is a difference voltage between the secondary side output voltage VOUT and the secondary side ground voltage GND2 can be simply obtained, it is possible to omit the photo- have. A photo-coupler provided separately from the power supply unit can be omitted, and a separate circuit for monitoring at the secondary side of the transformer can be omitted, thereby reducing the manufacturing cost of the power supply unit. In addition, DP signal and DM signal transmitted through a USB cable can be measured, and a quick-charger or a separate additional voltage can be detected to variably adjust the secondary side output voltage VOUT. In addition, by monitoring the no-load state or the short state of the secondary side from the primary side, it is possible to minimize the stand-by power when no load is applied by using the deep sleep & wake-up function in a no-load state. In addition, since the state of the short circuit can be confirmed, it is possible to prevent the breakdown of the transformer connected to the secondary side due to fire or overheating, thereby providing a safety function.

1 is a diagram showing a bias circuit block.
2 is a circuit diagram of a bias circuit block.
3 is a graph for explaining normal bias voltages generated in the bias circuit block.
4 is a graph for explaining the reverse bias voltages generated in the bias circuit block.
5 is a symbol representing a core block.
6 is a symbol representing the first output driver among the drivers of the second generation current conveyor.
7 is a circuit diagram of the first output driver.
8 is a symbol representing the second output driver among the drivers of the current conveyor.
9 is a circuit diagram of the second output driver among the drivers of the current conveyor.
10 is a symbol representing a driving block among the drivers of the current conveyor.
11 is a circuit diagram of the driving block.
12 is a symbol representing a balanced output rail-to-rail second generation current conveyor (hereinafter referred to as BORRCC II).
13 is a configuration diagram for explaining a common mode voltage supply.
14 is a diagram for explaining an implementation of a fully balanced differential rail-to-rail second generation current conveyor (hereinafter referred to as FBDRRCC II).
15 is a circuit diagram for explaining a balanced output rail-to-rail second generation current conveyor according to an embodiment of the present invention.
16 is a graph for explaining the rail-to-rail input.
17 is a graph for explaining drain-current versus drain-to-source voltage characteristics corresponding to current mirrors.
18 is a graph for explaining the input / output waveform of the second output current-to-rail current conveyor of FIG. 15;
19 is a graph for explaining current characteristics of the MP10 and MN10 provided in the first driver.
20 is an equivalent circuit diagram for explaining features of the second generation current conveyor.
21 is a configuration diagram of a voltage-current converter using BORRCCII according to the present invention.
22 is a graph for explaining the operation of the voltage-current converter shown in Fig.
23 is a configuration diagram of a voltage amplifier using BORRCC II according to the present invention.
24 is a graph for explaining the operation of the voltage amplifier shown in FIG.
25 is a configuration diagram of a current-voltage converter using BORRCCII according to the present invention.
26 is a graph for explaining the operation of the current-voltage converter shown in Fig.
27 is a configuration diagram of a current amplifier using BORRCC II according to the present invention.
FIG. 28 is a graph for explaining the operation of the current amplifier shown in FIG. 27; FIG.
FIG. 29 is a configuration diagram of FBDRRCC II using BORRCC II according to two inventions. FIG.
30 shows the symbols of FBDRRCCII.
31 is a configuration diagram of a fully differential voltage-current converter using FBDRRCC II according to the present invention.
FIG. 32 is a graph for explaining the operation of the fully differential voltage-current converter shown in FIG. 31; FIG.
33 is a configuration diagram of a fully differential voltage amplifier using FBDRRCC II according to the present invention.
34 is a graph for explaining the operation of the fully differential voltage amplifier shown in Fig.
FIG. 35 is a configuration diagram of a fully differential current-voltage converter using FBDRRCC II according to the present invention.
FIG. 36 is a graph for explaining the operation of the fully differential current-voltage converter shown in FIG.
37 is a configuration diagram of a fully differential current amplifier using FBDRRCC II according to the present invention.
FIG. 38 is a graph for explaining the operation of the fully differential current amplifier shown in FIG. 37; FIG.
39 is a circuit diagram illustrating a power supply apparatus according to an embodiment of the present invention.
40 is a view for explaining the primary side ground voltage and the secondary side ground voltage.
FIG. 41 is a block diagram showing the FBDRRCC II which is built in the controller shown in FIG. 39 and calculates the output target voltage VO based on the secondary side output voltage VOUT and the secondary side ground voltage GND2.
FIG. 42 is a circuit diagram for explaining a power supply apparatus according to another embodiment of the present invention. FIG.
FIG. 43 is a configuration diagram showing FBDR RCCs II, which are built in the controller shown in FIG. 42 and measure a DP signal and a DM signal so that a variable output voltage is output.
44 is a circuit diagram for explaining a power supply device according to another embodiment of the present invention.
45 is a flowchart for explaining the method of driving the power supply apparatus shown in Fig.
46 is a waveform diagram for explaining power consumption by the deep sleep and wake-up function of the SMPS shown in Fig.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in more detail with reference to the accompanying drawings. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Like reference numerals are used for like elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged to illustrate the present invention in order to clarify the present invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. The singular expressions include plural expressions unless the context clearly dictates otherwise.

In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Also, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

First, the names and symbols of the circuits mentioned in this specification will be described.

1 is a diagram showing a bias circuit block. 2 is a circuit diagram of a bias circuit block. 3 is a graph for explaining normal bias voltages generated in the bias circuit block. 4 is a graph for explaining the reverse bias voltages generated in the bias circuit block.

1 to 4, the bias circuit block BIAS includes a plurality of PMOSs and a plurality of NMOSs. The bias circuit block BIAS receives a reference current IREF from the outside, A first normal bias voltage VBP0, a second normal bias voltage VBP1 and a third normal bias voltage VBP2 and supplies a first reverse bias voltage VBN0 and a second reverse bias voltage VBN2 supplied as a bias current to the NMOS VBN1 and the third reverse bias voltage VBN2.

In this embodiment, VDD, which is a relatively high power supply voltage, is applied to the PMOSs, and VSS, which is a relatively low power supply voltage, is applied to the NMOSs. In the PMOS, a terminal connected to a relatively high voltage is referred to as a source, a terminal to which a control voltage is applied is referred to as a gate, and the remaining terminal is referred to as a drain. Also, a terminal connected to a relatively low voltage in the NMOS is referred to as a source, a terminal to which a control voltage is applied is referred to as a gate, and the remaining terminal is referred to as a drain.

The source of MN0 is connected to VSS, the gate and drain are connected in common and connected to the source of MN1. The source of MN1 is connected to the drain of MN0, and the gate and the drain are connected in common to a terminal to which reference current IREF is applied. The source of MN2 is connected to VSS, the gate is connected to the gate of MN0, and the drain is connected to the source of MN3. The source of MN3 is connected to the drain of MN2, the gate is connected to the gate of MN1, and the drain is connected to the drain of MP2. The source of MN4 is connected to VSS, the gate is connected to the gate of each of MN0 and MN2, and the drain is connected to the source of MN5. The source of MN5 is connected to the drain of MN4, the gate is connected to the gate of each of MN1 and MN3, and the drain is connected to the drain of MP3.

The source of MP0 is connected to VDD, the gate is connected to the drain of MP1, and the drain is connected to the source of MP1. The source of MP1 is connected to the drain of MP0, the gate is connected to the gate of MP3, and the drain is connected to the source of MP2. The source of MP2 is connected to the drain of MP1 and the gate of MP0, and the gate and the drain are commonly connected to the drain of MN3. The source of MP3 is connected to VDD, the gate is connected to the gate of MP1, and the drain is connected to the drain of MN5. The source of MP4 is connected to VDD, the gate is connected to the gate of MP0, and the drain is connected to the source of MP5. The source of MP5 is connected to the drain of MP4, the gate is connected to the gate of MP3, and the drain is connected to the drain of MN8. The source of MP6 is connected to VDD, the gate is connected to the gate of each of MP0 and MP4, and the drain is connected to the source of MP7. The source of MP7 is connected to the drain of MP6, the gate is connected to the gate of each of MP3 and MP5, and the drain is connected to the drain of MN9.

Here, a first normal bias voltage VBP0 is generated through the gates of MP0, MP4 and MP6, a second normal bias voltage VBP1 is generated through the gates of MP1, MP3, MP5 and MP7, A third normal bias voltage VBP2 is generated through the gate.

The source of MN6 is connected to VSS, the gate is connected to the drain of MN7, and the drain is connected to the source of MN7. The source of MN7 is connected to the drain of MN6, the gate is connected to the gate of MN9, and the drain is connected to the source of MN8 and the gate of MN6. The drain and gate of MN8 are connected in common to the drain of MP5, and the source is connected to the drain of MN7. The source of MN9 is connected to VSS, the gate is connected to the gate of MN7, and the drain is connected to the drain of MP7.

Here, a first reverse bias voltage VBN0 is generated through the gate of MN6, a second reverse bias voltage VBN1 is generated through the gates of MN7 and MN9, and a third reverse bias voltage VBN2 ) Is generated.

The normal bias voltage VBP applied to the bias voltage of the PMOS, that is, the first normal bias voltage VBP0, the second normal bias voltage VBP1, and the third normal bias voltage VBP2 are precisely set in the actual circuit design , And can be roughly generated by Equation 1 as follows.

[Equation 1]

VBP0 = VDD - (Vthp * 1)

VBP1 = VDD - (Vthp * 2)

VBP2 = VDD - (Vthp * 3)

Here, it is assumed that Vthp is about 0.5V to 0.8V as a threshold voltage of the PMOS.

Here, it is assumed that Vthp is about 0.5V to 0.8V as a threshold voltage of the PMOS.

The first normal bias voltage VBP0, the second normal bias voltage VBP1 and the third normal bias voltage VBP2 generated in the bias circuit block BIAS are as shown in FIG.

On the other hand, the reverse bias voltage VBN applied to the bias voltage of the NMOS, that is, the first reverse bias voltage VBN0, the second reverse bias voltage VBN1, and the third reverse bias voltage VBN2, But it can be roughly generated by the following Equation (2).

[Equation 2]

VBN0 = VSS (0V) + (Vthn * 1)

VBN1 = VSS (0V) + (Vthn * 2)

VBN2 = VSS (0V) + (Vthn * 3)

Here, it is assumed that Vthn is about 0.4V to 0.7V as a threshold voltage of the NMOS.

The first inverted bias voltage VBN0, the second inverted bias voltage VBN1 and the third inverted bias voltage VBN2 generated in the bias circuit block BIAS are as shown in FIG.

As shown in Fig. 3, the magnitude of the voltage in the order of the first normal bias voltage VBP0, the second normal bias voltage VBP1, and the third normal bias voltage VBP2 becomes smaller, Likewise, the magnitude of the voltage increases in the order of the first reverse bias voltage VBN0, the second reverse bias voltage VBN1, and the third reverse bias voltage VBN2.

In this embodiment, the reference current IREF is about several uA to several tens uA, and the channel width and the channel length for generating the gate area of all the PMOSs are the same, and the channel width And the channel length are the same. Generally, when the channel lengths of the PMOS and the NMOS are made the same, the channel width of the PMOS is selected to be about three times or more than the channel width of the NMOS. The channel length of MP3 is about 4 to 6 times longer than the remaining PMOS gate area. The channel length of MN9 is about 4 to 6 times longer than the remaining NMOS gate area.

5 is a symbol representing a core block.

As shown in FIG. 5, the core block CORE has a function of outputting a gate voltage of a rail-to-rail input stage and an AB class driver.

The core block (CORE) may be designed as an operational transconductance amplifier (OTA) or an operational amplifier (Op-Amp). Both amplification circuits are circuits that amplify and output the difference of the input, and have a large voltage gain (for example, several thousands to tens of thousands) and a high input resistance.

In the case of OTA, when the capacitive load is driven, the output voltage becomes close to an ideal voltage controlled current source, so a high output resistance is a desirable characteristic.

On the other hand, in order to drive a resistive load, the output resistance of the Op-Amp must be low to avoid a loading effect. This output resistance is designed to be very low and operate as a voltage controlled voltage source.

6 is a symbol representing the first output driver D0 among the drivers of the second generation current conveyor. 7 is a circuit diagram of the first output driver D0.

Referring to Figs. 6 and 7, the first output driver D0 has a normal output voltage buffer for voltage feedback.

The first output driver D0 is composed of a series-connected MP10 and MN10. MP10 has a source to which VDD is applied, a gate to which the first driving voltage (P_DRV) is applied, a drain of MN10, and a drain connected to the X-port. MN10 has a source to which VSS is applied, a gate to which the second driving voltage N_DRV is applied, and a drain connected to the drain of MP10 and a X-port.

8 is a symbol representing the second output driver D1 among the drivers of the current conveyor. 9 is a circuit diagram of the second output driver D1.

Referring to Figs. 8 and 9, the second output driver D1 has a normal output voltage buffer for voltage feedback and a ZP-port.

The second output driver D1 constitutes the MP10 and MN10 connected in series and the MP11 and MN11 connected in series.

MP10 has a source to which VDD is applied, a gate to which the first driving voltage P_DRV is applied, a source of MN10, and a drain connected to the X-port. MN10 has a source to which VSS is applied, a gate to which the second driving voltage N_DRV is applied, and a drain connected to the drain of MP10 and a X-port.

MP11 has a source to which VDD is applied, a gate commonly connected to the gate of MP10 to which a first driving voltage P_DRV is applied, a source of MN11, and a drain connected to the ZP-port. MN11 has a source to which VSS is applied, a gate commonly connected to the gate of MN10 and to which the second driving voltage N_DRV is applied, and a drain connected to the drain and ZP-port of MP11.

10 is a symbol representing the driving block D2 among the drivers of the current conveyor. 11 is a circuit diagram of the driving block D2.

Referring to Figs. 10 and 11, the driving block D2 has a normal output voltage buffer for voltage feedback, a ZP-port, and a ZN-port.

The driving block D2 is composed of MP10, MN10, MP11, MN11, MP12, MN12, MP13, MN13, MP14 and MN14.

MP10 has a source to which VDD is applied, a gate to which the first driving voltage P_DRV is applied, a source of MN10, and a drain connected to the X-port. MN10 has a source to which VSS is applied, a gate to which the second driving voltage N_DRV is applied, and a drain connected to the drain of MP10 and a X-port.

MP11 has a source to which VDD is applied, a gate commonly connected to the gate of MP10 to which a first driving voltage P_DRV is applied, a source of MN11, and a drain connected to the ZP-port. MN11 has a source to which VSS is applied, a gate commonly connected to the gate of MN10 and to which the second driving voltage N_DRV is applied, and a drain connected to the drain and ZP-port of MP11.

MP12 has a source to which VDD is applied, a gate commonly connected to the gate of MP10 to which a first driving voltage P_DRV is applied, and a drain connected to the source of MN13. MN12 has a source to which VSS is applied, a gate commonly connected to the gate of MN10 to which a second driving voltage N_DRV is applied, and a source connected to the drain of MP13.

MP13 has a source to which VDD is applied, a gate connected to a source of MN12 in common and a drain. MN13 has a source to which VSS is applied, a source connected in common to the drain of MP12, and a gate.

MP14 has a source to which VDD is applied, a gate connected to the gate of MP13, and a drain connected to the ZN-port. MN14 has a source to which VSS is applied, a gate connected to the gate of MN13, and a drain connected to the ZN-port.

12 is a symbol representing a balanced output rail-to-rail current conveyor (hereinafter referred to as BORRCC II).

As shown in FIG. 12, a balanced output rail-to-rail second generation current conveyor (BORRCCII) is implemented by connecting the core block CORE and the driving block D2 in series.

13 is a configuration diagram for explaining a common mode voltage supply.

As shown in FIG. 13, the common mode voltage generator (VCM Generator) includes a functional block of a combination of a core block (CORE) and a first output driver (D0).

The reference voltage Vref is generated at a ratio of the first resistor R1 and the second resistor R2 connected in series between VDD and GND and applied to the Y-port of the core block CORE. When the reference voltage Vref is applied to the Y-port of the core block CORE, an ideal common mode voltage (VCM) having a very low output impedance is generated through the X-port outputting the same voltage do.

FIG. 14 is a diagram for explaining an implementation of a fully balanced differential rail-to-rail current conveyor (hereinafter referred to as FBDRRCC II).

Referring to FIG. 14, two BORRCC IIs are arranged on the upper and lower sides to define a fully balanced differential rail-to-rail second generation current conveyor (hereinafter referred to as FBDRRCC II).

The Y-port of BORRCC II arranged on the upper side defines the YP port of FBDRRCC II, the X-port of BORRCC II arranged on the upper side defines the XP-port of FBDRRCC II, and the Y port of BORRCC II arranged on the lower side defines FBDRRCC II Port, and the X-port of BORRCC II located on the lower side defines the XN-port of FBDRRCC II.

The ZP-port of BORRCC II located on the upper side and the ZN-port of BORRCC II disposed on the lower side are connected to each other to define the ZP-port of FBDRRCC II. The ZN-port of BORRCC II located on the upper side and the ZP-port of BORRCC II disposed on the lower side are connected to each other to define the ZN-port of FBDRRCC II.

The ZP-port and ZN-port of the FBDRRCC II output only the differential components of the voltage or current of the input ports of the upper BORRCC II and the lower BORRCC II, respectively.

15 is a circuit diagram for explaining a balanced output rail-to-rail second generation current conveyor according to an embodiment of the present invention.

Referring to FIG. 15, a balanced output rail-to-rail current conveyor according to an embodiment of the present invention includes a core block and a driving block D2 do.

The core block CORE includes an upper differential input terminal 110, a lower differential input terminal 120, an upper current mirror stage 130, a lower current mirror stage 140, a switching stage 150, a first capacitor C1, 2 capacitor C2 and receives VBP0, VBP1 and VBP2 as the bias voltages of the PMOS devices from the bias circuit block (shown in Figs. 1 and 2), VBN0, VBN1 and VBN2 as bias voltages of the NMOS devices . The illustration of the bias circuit block in the balanced output rail-to-rail second generation current conveyor shown in Fig. 15 has been omitted.

The core block CORE implements a rail-to-rail input / output through an upper differential input stage 110 and a lower differential input stage 120 that are commonly connected to the Y-port and the X-port, And outputs the first driving voltage P_DRV and the second driving voltage N_DRV to the driving block D2 by mirroring the current applied by the bias voltage based on the voltage of the driving voltage V_DRV.

The upper differential input stage 110 is composed of MP2 and MP3 connected in parallel with MP0 and MP1 connected in series. MP0 has a source to which VDD is applied, a gate to which VBP0 is applied, and a drain connected to the source of MP1. MP1 has a source connected to the drain of MP0, a gate to which VBP1 is applied, a source of MP2 and a drain connected to the source of MP3. MP2 has a source coupled to the drain of MP1, a gate coupled to the Y-port, and a drain coupled to the lower current mirror stage 140. MP3 has a source coupled to the drain of MP1, a gate coupled to the X-port, and a drain coupled to the lower current mirror stage 140. MP2 and MP3 are responsible for input, and compare the voltage of the Y-port with the voltage of the X-port to flow the tail current (Ip) applied by the bias voltage to the gate to which the lower voltage is input do. Here, the range of the operable input signal voltage (common mode voltage) is about 2.5V to 0V when VDD is assumed to be about 3.3V.

The lower differential input stage 120 consists of MN0 and MN1 connected in series and MN2 and MN3 connected in parallel. MN0 has a drain connected to the source of MN1, a gate to which VBN0 is applied, and a source to which VSS is applied. MN1 has a source connected to the source of MN2 and a drain connected to the source of MN3, a gate to which VBN1 is applied, and a source connected to the drain of MN0. MN2 has a drain coupled to the upper current mirror stage 130, a gate coupled to the Y-port, and a source coupled to the drain of MN1. MN3 has a drain connected to the upper current mirror stage 130, a gate connected to the X-port, and a source connected to the drain of MN1. MN2 and MN3 take charge of the input, and compare the voltage of the Y-port with the voltage of the X-port to flow the current (In) applied by the bias voltage toward the input gate. Here, the range of the operable input signal voltage (common mode voltage) is about 0.7V to 3.3V when VDD is assumed to be about 3.3V.

Since the upper differential input stage 110 and the lower differential input stage 120 are disposed as an input stage of the current conveyor, a rail-to-rail input can be realized. That is, the current (Ip, In) can be supplied so that the range of the input voltage (Common Mode Voltage) covers the entire range of the power supply voltage (VDD) when the power source is 3.3V. The range of the input voltage is shown in FIG.

16 is a graph for explaining the rail-to-rail input.

As shown in FIG. 16, the rail-to-rail input covers a range of the input signal from 0 V to VDD, so that a wider range of inputs is obtained when the conventional circuit receives the upper input or the lower input It has the advantage of operating on voltage.

Referring back to FIG. 15, the upper current mirror stage 130 consists of MP4, MP5, MP6, and MP7 to define a current mirror. MP4 has a source to which VDD is applied, a drain of MP5, a gate connected to the gate of MP6, and a drain connected to the source of MP5. Further, the drain of MP4 is connected to the source of MN3 of the lower differential input terminal 120. [ MP5 has a source connected to the drain of MP4, a gate connected to the gate of MP7, and a drain connected to the gate of MP4. Further, the source of MP5 is connected to the source of MN3 of the lower differential input stage 120. [ MP6 has a source to which VDD is applied, a drain of MP5, a gate connected to the gate of MP4, and a drain connected to the source of MP7. Further, the drain of MP6 is connected to the source of MN2 of the lower differential input terminal 120. [ MP7 has a source connected to the drain of MP6, a gate connected to the gate of MP5, a driving block D2 and a drain connected to the switching stage 150. Here, MP5 and MP7 are biased with VBP1 voltage, and the bias voltage between MP4 and MP6 has a circuit characteristic in which a drain voltage of MP5 is applied.

If the gate area of MP4 is equal to the gate area of MP6, and the gate area of MP5 is equal to the gate area of MP7, the current flowing through MP6 and MP7 is the same as the current flowing through MP4 and MP5. At this time, the saturation voltage of MP5 is higher than the threshold voltage (Vth) of MP4, thereby supplying current to the drain of MP7. Therefore, the range of the operable voltage is wider than the current mirror of the general structure.

At this time, if the current is applied to the drains of MP4 and MP6 at different values due to the difference of the input voltages of the lower differential input terminal 120, the final output current I (MP7) flowing through the MP7 becomes the bias current It is determined by the current of ± @ IN. Here, @ denotes a ratio of a current (In) to a difference value of the input voltage obtained from the upper differential input terminal 110 and the lower differential input terminal 120, which are the input stages of the current conveyor.

The lower current mirror stage 140 consists of MN4, MN5, MN6 and MN7 to define a current mirror. MN4 has a drain connected to the source of MN5, a gate connected to the gate of MN6, and a source to which VSS is applied. Further, the drain of MN4 is connected to the source of the MP3 of the upper differential input stage 110. [ MN5 has a drain connected to the switching stage 150, a gate connected to the gate of MN7, and a source connected to the drain of MN4. Further, the source of MN5 is connected to the source of MP2 of the upper differential input stage 110. [ MN6 has a drain connected to the source of MN7, a gate connected to the gate of MN4, and a source to which VSS is applied. MN7 has a drain connected to the switching node 150, a gate connected to the gate of MN5, and a source connected to the drain of MN6. Further, the drain of MN7 is connected to the source of MP2 of the upper differential input stage 110. [ Here, MN5 and MN7 are biased with a VBN1 voltage, and bias voltages of MN4 and MN6 have a circuit characteristic in which a source voltage of MN5 is applied.

If the gate area of MN4 is equal to the gate area of MN6 and the gate area of MN5 is equal to the gate area of MN7, the current flowing through MN6 and MN7 is the same as the current flowing through MN4 and MN5. At this time, the saturation voltage of MN5 becomes higher than the threshold voltage (Vth) of MN4, thereby supplying current to the source of MN7. Therefore, the range of the operable voltage is wider than the current mirror of the general structure.

At this time, if the current is applied to the sources of MN4 and MN6 at different values due to the difference of the input voltages of the upper differential input terminal 110, the final output current I (MN7) flowing through MN7 becomes equal to the bias current It is determined by the current of ± @ IP. Here, @ denotes the ratio of the current Ip to the difference value of the input voltage obtained from the upper differential input terminal 110 and the lower differential input terminal 120, which are the input stages of the current conveyor.

In this embodiment, the upper current mirror stage 130 and the lower current mirror stage 140 employ a High-compliance current mirror.

17 is a graph for explaining drain-current versus drain-to-source voltage characteristics corresponding to current mirrors.

Referring to FIG. 17, the high-compliance current mirror has a wide Vds (drain-source voltage) in comparison with conventional triple cascode, regulated cathode, Wilson cathode method, . Thus, a wide voltage swing with a current source is possible.

In addition, the variation of Id (drain current) with respect to Vds is smaller than that of a simple scheme which is a conventional structure of the high-compliance current mirror.

15, one end of the first capacitor C1 is connected to a node between MP6 and MP7 of the upper current mirror stage 130, and one end of the second capacitor C2 is connected to a node between the MP6 and the MP7 of the lower current mirror stage 130 And is connected to a node between MN6 and MN7. The other end of the first capacitor C1 and the other end of the second capacitor C2 are connected in common to the X-port.

The first capacitor C1 and the second capacitor C2 are frequency stabilized capacitors inserted to provide a phase margin in case the core block CORE is operated with OTA AMP.

The switching stage 150 includes a CMOS transmission gate composed of MP8 and MN8 and a CMOS transmission gate composed of MP9 and MN9 and is disposed between the upper current mirror stage 130 and the lower current mirror stage 140 . Due to the voltage difference between the source and the drain of MP8, MN8, MP9 and MN9 biased with VBN2 and VBP2, the switching stage 150 has a driver type with a Class AB amplification structure.

Due to the current mirror structure of the upper current mirror stage 130 and the lower current mirror stage 140, the switching stage 150 has a rail-to-rail output (rail) in which the width of the output voltage is able to cover all of the supply voltage -to-rail output) structure.

18 is a graph for explaining the input / output waveform of the second output current-to-rail current conveyor of FIG. 15; In particular, a schematic waveform for the voltage input signal applied to the Y-port or the voltage output signal outputted through the ZP-port, the first driving voltage P_DRV and the second driving voltage N_DRV is shown.

As shown in FIG. 18, in the section A, the NMOSs MN10, MN11 and MN12 shown in FIG. 15 are driven weakly but kept in a cut-off state by the second driving voltage N_DRV. However, the first driving voltage P_DRV controls the voltage of the ZP-port by driving the PMOSs MP10, MP11 and MP12 shown in FIG.

In the section B, the PMOSs MP10, MP11 and MP12 shown in FIG. 15 are driven weakly but kept in a cut-off state by the first driving voltage P_DRV. However, the second driving voltage N_DRV controls the voltage of the ZP-port by driving the NMOSs MN10, MN11 and MN12 shown in FIG.

The signal driving of the section A or the signal driving of the section B is a typical driving voltage waveform of the class AB driver.

Referring again to FIG. 15, the driving block D2 includes a first driver 210, a second driver 220, a third driver 230, a fourth driver 240, and a fifth driver 250 Port through the ZP-port in response to the first driving voltage P_DRV and the second driving voltage N_DRV, and outputs the inverted output current through the ZN-port.

The first driver 210 is composed of the MP10 and the MN10 connected in series. MP10 has a source to which VDD is applied, a gate connected to the upper current mirror stage 130, and a drain connected to the drain and X-port of MN10. MN10 has a source to which VSS is applied, a gate connected to the lower current mirror stage 140, and a drain connected to the drain of the MP10 and an X-port. The first driver 210 serves to connect the output to the X-port of the input stage according to the structure of the second generation current conveyor.

19 is a graph for explaining current characteristics of the MP10 and MN10 provided in the first driver.

As shown in FIG. 19, the output current I _{MP of the MP} 10 is controlled by the first driving voltage P_DRV, which is the output of the upper current mirror stage 130. In the section where the output current (I _MP ) is larger than +4J, the MP10 operates in the linear mode. In the section smaller than +4J, the MP10 has the nonlinear characteristic. (cut-off), and the current can not be driven any more. Here, J is the quiescent current of the driven MOSFET, which means the standby mode current (i.e., the value of the current flowing before the operation in the standby state). AB driver (Class AB driver) is designed by defining a section with respect to the bias voltage until the gate voltage of the driver MOS exceeds the threshold voltage and reaches the linear operation mode in a period of about 4J.

On the other hand, the output current I _{MN of the MN} 10 is controlled by the second driving voltage N_DRV, which is the output of the lower current mirror stage 140. In the section where the output current I _MN is smaller than -4 J, the _{MN 10} operates in a linear mode. In the section larger than -4 J, the MN 10 has a nonlinear characteristic. In the section longer than + 4 J, cut-off) and the current can not be driven any more.

Therefore, since the current values of MP10 and MN10 are present in the zero current period (ie, the non-signal interval) in which there is no signal, they have the smallest current value in the operating mode. Therefore, this output buffer stage is referred to as AB class AB stage). A driver having such a function is referred to as an AB class driver. In addition, by using the current conveyor with AB class driver, it is possible to reduce the consumption current of the silent screen, adjust the size of the output driver appropriately to suit the application, and realize the low power operation characteristic and drive the large current .

Referring again to FIG. 15, the second driver 220 includes the MP11 and the MN11 connected in series in the same manner as the first driver 210. MP11 has a source to which VDD is applied, a gate connected to the gate of the MP10 of the first driver 210, and a drain connected to the drain of the MN11 and a ZP-port. MN11 has a source to which VSS is applied, a lower current mirror stage 140 and a gate connected to the gate of MN10, and a drain connected to the drain and ZP-port of MP11. Port of the differential input stage of the upper differential input stage 110 and the differential input stage of the lower differential input stage 120. The second driver 220 is connected to the ZP port for output driving do.

The third driver 230 is composed of MP12 and MN12. The gate of MP12 is connected to the gate of MP11, and the gate of MN12 is connected to the gate of MN11. VDD is applied to the source of MP12, and VSS is applied to the source of MN12.

The fourth driver 240 is composed of MP13 and MN13. The drain of the MP13 is connected to the drain of the MN12 of the third driver 230 and the drain of the MN13 is connected to the drain of the MP12 of the third driver 203. [ VDD is applied to the source of MP13, and VSS is applied to the source of MN13.

The fifth driver 250 is composed of MP14 and MN14. The gate of the MP14 is connected to the gate of the MP13, the drain of the MP13, and the drain of the MN12 of the third driver 230. The gate of the MN14 is connected to the gate of the MN13, do. VDD is applied to the MP14 source, and VSS is applied to the source of the MN14. The drain of the MP14 and the drain of the MN14 are commonly connected to the ZN-port.

The third driver 230 and the fourth driver 240 have a reverse current mirror structure for driving the ZN-port of the fifth driver 250.

The same current as the PMOS that was used to drive the ZP-port flows in MP12, and this current is mirrored to MN13 to drive MN14.

In addition, the same current as the NMOS that was used to drive the ZP-port flows in the MN 12, and this current is mirrored in the MP 13 to drive the MP 14.

Through this inversion current mirror, the ZN-port of the fifth driver 250 has an output current or output voltage that is completely in phase with the ZP-port.

All the PMOSs of the first driver 210, the second driver 220, the third driver 230, the fourth driver 240 and the fifth driver 250 have the same gate area And the NMOS is also designed to have the same gate area. In particular, for correct operation of the current mirror, each of the PMOSs and NMOSs can be set to use the same value for both the width and the length of the channel generating the gate area.

A block completed with the configuration from the upper differential input terminal 110 to the fifth driver 250 is defined as a 'balanced output rail-to-rail current converter' (BORRCCII).

The BORRCC II described above satisfies the features of the second generation current conveyor (CCII).

20 is an equivalent circuit diagram for explaining features of the second generation current conveyor.

20, a second-generation current conveyor CCII is constructed by mirroring the low impedance input of the X-port, the high impedance input of the Y-port, and the current i0 flowing to the X-port 100% Or Z + port) and an inverting current output through the ZN-port (or Z-port).

That is, the second-generation current conveyor follows the voltage from the Y-port to the X-port according to the impedance characteristic, and if positive, the Z-port follows the current in the same direction as the current flow in the X-port. On the other hand, in the case of a negative electrode, the Z-port follows the current in the direction opposite to the current flow direction of the X-port.

In addition, the second-generation current conveyor follows the voltage from the Y-port to the X-port according to the impedance characteristics as shown in Table 1 below.

[Table 1]

Therefore, the current I _{Y of the Y} -port, the voltage V _{X of the X} -port, and the current I _Z of the Z-port can be expressed by the following Equation 3.

[Equation 3]

Hereinafter, various application circuits using BORRCC II according to an embodiment of the present invention will be described.

FIG. 21 is a configuration diagram of a voltage-current converter using BORRCC II according to the present invention, and FIG. 22 is a graph for explaining the operation of the voltage-current converter shown in FIG.

As shown in FIGS. 21 and 22, in order to implement a voltage-to-current converter for converting a voltage into a current, a common mode voltage (VCM) and an X-resistor (RX) are connected in series to the X-port of BORRCC II .

When the input voltage (VIN) is supplied to the Y-port, the same voltage as the input voltage (VIN) is output to the X-port by the second generation current (CCII) formula. That is, V (VIN) = V (X).

The voltage difference between the common mode voltage (VCM) and the X-port causes the current (ix) to be generated by the X-resistor (RX). This current (ix) is mirrored by the current of iZPO in the ZP-port and the current of iZNO is mirrored in the ZN-port. Therefore, the input voltage VIN is converted into a current output such as ZPO and ZNO.

That is, the voltage is converted into the current in accordance with the following expression (4).

[Equation 4]

I (ZPO) = VIN * (1 / RX)

I (ZNO) = -VIN * (1 / RX)

The value at which the input voltage VIN is converted into the current has a relation proportional to the reciprocal (1 / RX) of the X-resistor RX. The relationship between the voltage input and the current output is shown in FIG.

FIG. 23 is a configuration diagram of a voltage amplifier using BORRCC II according to the present invention, and FIG. 24 is a graph for explaining the operation of the voltage amplifier shown in FIG.

23 and 24, in order to implement a voltage amplifier for amplifying the voltage, the Y-port of BORRCC II is connected to the terminal to which the input voltage VIN is applied, and the X-port of BORRCC II and the common mode voltage (RX) is arranged between the terminals to which the common mode voltage (VCM) is applied and the ZP-resistor (RZP) is arranged between the terminals to which the common mode voltage (VCM) is applied and the ZP port of the BORRCCII, The ZN-resistor RZN is disposed between the port and the terminal to which the common mode voltage VCM is applied.

The input voltage VIN is supplied to the Y-port which is a voltage input port and the voltage of the voltage-current converter to which the same voltage as the input voltage VIN is supplied is converted into a current, When the ZP-resistor (RZP) and ZN-resistor (RZN), which can set the voltage gain to the ZP-port and ZN- port, are connected between the terminals to which the common mode voltage (VCM) is applied, .

When the ZP-resistor (RZP) is connected between the ZPO terminal and the terminal to which the common mode voltage (VCM) is applied and the ZN-resistor (RZN) is connected between the ZNO terminal and the common mode voltage (VCM) The voltage has a relationship expressed by the following equation (5).

[Equation 5]

V (ZPO) = VIN * (RZP / RX)

V (ZNO) = -VIN * (RZN / RX)

따라서 ZPO 단자를 통한 출력 전압(V(ZPO))과 ZNO 단자를 통한 출력 전압(V(ZNO))는 입력전압(VIN)에 대해서 X-저항(RX)과 ZP-저항(RZP), X-저항(RX)과 ZN-저항(RZN)의 각각의 비율에 따라 전압 이득(또는 증폭율)이 설정됨을 알 수 있다. 이러한 특징을 도식화하면 도 24와 같다.

Therefore, the output voltage V (ZPO) through the ZPO terminal and the output voltage V (ZNO) through the ZNO terminal are the X-resistor RX and the ZP-resistor RZP for the input voltage VIN, It can be seen that the voltage gain (or the amplification factor) is set according to the ratio of each of the resistance RX and the resistance ZN-resistor RZN. This feature is illustrated in FIG.

FIG. 25 is a configuration diagram of a current-voltage converter using BORRCC II according to the present invention, and FIG. 26 is a graph for explaining the operation of the current-voltage converter shown in FIG.

25 and 26, the Y-port of BORRCC II is connected to the terminal to which the common mode voltage (VCM) is applied, and the BORRCC II X- Port is connected to the terminal to which the input current IIN is applied and the ZP-resistor RZP is arranged between the ZP port of the BORRCC II and the terminal to which the common mode voltage VCM is applied and the ZN- The ZN-resistor RZN is disposed between the terminals to which the voltage VCM is applied.

When the input current (IIN) is supplied to the X-port of the BORRCC II while the common mode voltage (VCM) is connected to the Y-port of the BORRCC II, the current equal to the input current IIN is supplied to the second generation current conveyor To the ZP-port and the ZN-port. That is, I (ZPO) = I (X) and I (ZNO) = -I (X).

At this time, when the ZP-resistor RZP is connected between the ZPO terminal and the terminal to which the common mode voltage VCM is applied, V (ZPO) has a product of I (ZPO) and RZP. Conversely, when the ZN-resistor RZN is connected between the ZNO terminal and the terminal to which the common mode voltage VCM is applied, V (ZNO) has a product of I (ZNO) and RZN. At this time, I (ZNO) and I (ZPO) have current values of opposite phases having different values but different signs.

Therefore, the input current IIN is converted into an output of a voltage such as an output voltage V (ZPO) through the ZPO terminal and an output voltage V (ZNO) through the ZNO terminal. That is, the voltage is converted into the current in accordance with the following equation (6).

[Equation 6]

V (ZPO) = IIN * RZP

V (ZNO) = - IIN * RZN

Such a characteristic is illustrated in FIG. 26.

FIG. 27 is a configuration diagram of a current amplifier using BORRCC II according to the present invention, and FIG. 28 is a graph for explaining the operation of the current amplifier shown in FIG.

27 and 28, in order to implement a current amplifier for amplifying current, a terminal to which an input current IIN is applied is connected to a Y-port of BORRCC II, and a Y-port and a common mode voltage VCM When the Y-resistor RY is connected between the terminals to which the common mode voltage VCM is applied and the X-resistor RX is connected in series between the X-port of BORRCC II and the common mode voltage VCM, The voltage (V (Y)) of the transistor Q1 is expressed by the following equation: IIN * RY.

This degree of voltage is generated in the X-port, and this voltage V (X) is formed by the X-resistor RX such that a current relationship such as iX = V (X) / RX is formed. This current (iX) is output as iZPO and iZNO with normal and reverse phase, respectively.

At this time, the current (i (X)) of the X-port is defined by a relational expression such as IIN * RY / RX.

Therefore, the current outputs I (ZPO) and I (ZNO) are defined by the following relational expressions.

[Equation 7]

I (ZPO) = IIN * (RY / RX)

I (ZNO) = - IIN * (RY / RX)

This characteristic is illustrated in FIG. 28.

FIG. 29 is a configuration diagram of FBDRRCC II using BORRCC II according to two inventions, and FIG. 30 is a symbol of FBDRRCC II. FIG.

Referring to FIGS. 29 and 30, two BORRCC IIs are arranged to define FBDRRCC II. That is, the ZP-port of the upper BORRCC II and the ZN-port of the lower BORRCC II are connected to each other to define the ZPF-port of the FBDRRCC II. In addition, the ZN-port of the upper BORRCC II and the ZP-port of the lower BORRCC II are interconnected to define the ZNF-port of the FBDRRCC II.

The ZPF-port and ZNF-port of the FBDRRCC II have a function of outputting only the differential component of the voltage or current of the input port of the upper BORRCC II and the lower BORRCC II.

When the terminal to which the common mode voltage (VCM) is applied is connected to the YP-port and the YN- port, and the current input is connected to the XP-port and the XN-port,

[Equation 8]

Izppo = Ixp

Izpno = -Ixp

Iznpo = Ixn

Iznno = -Ixn

Izpo = Izppo + Iznno

Izno = Izpno + Iznpo

Izpo = Ixp - Izn

Izno = - (Izp - Izn)

The final output current through the ZPF-port is XP-XN and the final output current through the ZNF-port is - (XP-XN).

Therefore, it becomes a current conveyor structure that outputs only the difference component of the input current.

FIG. 31 is a configuration diagram of a fully differential voltage-to-current converter using FBDRRCC II according to the present invention, and FIG. 32 is a diagram illustrating the operation of the fully differential voltage-current converter shown in FIG. .

As shown in FIGS. 31 and 32, a fully differential voltage-current converter is implemented by connecting an X-resistor (RX) between the XP-port and the XN-port of FBDRRCC II.

When the input voltage VINP is supplied to the YP-port and the input voltage VINN is supplied to the YN-port, the difference voltage between the input voltage VINP and the input voltage VINN is calculated by the second generation current Port, and the difference voltage between the input voltage (VINN) and the input voltage (VINP) is output to the XN-port by the second generation current (CCII) formula. That is, a relation such as V (VINP-VINN) = V (XP) and V (VINN-VINP) = V (XN) can be defined.

The difference between the voltage of the XP-port and the voltage of the XN-port generates the current (XP) or the current (XN) by the X-resistor (RX). This current (XP) mirrors the current as much as iZPO to the ZPF-port, and the current as much as iZNO to the ZNF-port. Therefore, the difference voltage between the input voltage VINP and the input voltage VINN is converted into a current output such as ZPO and ZNO.

FIG. 33 is a configuration diagram of a fully differential voltage amplifier using FBDRRCC II according to the present invention, and FIG. 34 is a graph for explaining the operation of the fully differential voltage amplifier shown in FIG.

As shown in FIGS. 33 and 34, an X-resistor RX is connected between the XP-port and the XN-port of the FBDRRCC II, and a ZP-port is connected between the ZPF-port and the terminal to which the common mode voltage VCM is applied. Connect the resistor (RZP) and connect the ZN-resistor (RZN) between the ZNF-port and the terminal to which the common mode voltage (VCM) is applied to implement a fully differential voltage amplifier.

FIG. 35 is a configuration diagram of a fully differential current-to-voltage converter using FBDRRCC II according to the present invention, and FIG. 36 is a diagram illustrating the operation of the fully differential current-voltage converter shown in FIG. .

35 and 36, the common mode voltage VCM is applied to each of the YP-port and the YN-port of the FBDRRCC II, and the ZP-port is connected between the terminal to which the common mode voltage VCM is applied and the ZPF- A fully differential current-to-voltage converter is implemented by connecting the resistor RZP and connecting the ZN-resistor RZN between the terminal to which the common mode voltage VCM is applied and the ZNF-port.

FIG. 37 is a configuration diagram of a fully differential current amplifier using FBDRRCC II according to the present invention, and FIG. 38 is a graph for explaining the operation of the fully differential current amplifier shown in FIG.

As shown in FIGS. 37 and 38, a YP-resistor RYP is provided between the terminal for applying the input current IINP to the YP- port of the FBDRRCC II and the terminal for applying the common mode voltage VCM to the XN- Connect the YN-resistor (RYN) between the terminal for applying the input current (IINN) to the YN- port of FBDRRCC II and the terminal for applying the common mode voltage (VCM) to the XN- port, Resistor RXP is connected between the terminal to which the common mode voltage VCM is applied and the terminal to which the common mode voltage VCM is applied to the XN-port of the FBDRRCC II, Implement a fully differential current amplifier.

As described above, according to the present invention, a block of a balanced output rail-to-rail second generation current conveyor (BORRCCII) is constructed, and a full balanced differential rail-to- (FBDRRCCII).

The above-mentioned FBDRRCCII circuit has the following characteristics.

The FBDR RCC II circuit according to this embodiment operates in a single supply.

In addition, the FBDR RCC II circuit according to the present embodiment has a voltage input or a current input.

In addition, the FBDR RCC II circuit according to the present embodiment has a voltage output or a current output.

In addition, the FBDR RCC II circuit according to the present embodiment has a fully differential input and output with respect to voltage or current.

In the FBDR RCC II circuit according to the present embodiment, the common mode voltage (VCM) for the input of differential voltage or differential current is generally 1 / 2VDD (where VDD is the supply voltage) , And can be variously set from 0V to VDD depending on the application.

In addition, the FBDR RCC II circuit according to the present embodiment has a rail-to-rail input / output function for a voltage input and a voltage output.

In addition, the FBDR RCC II circuit according to the present embodiment has a function of amplifying a differential voltage or amplifying a differential current.

In addition, the FBDR RCC II circuit according to this embodiment has a function of converting a differential voltage into a current or a differential current into a voltage.

In the case of outputting a voltage or a current, the FBDR RCC II circuit according to this embodiment has a balanced output having a reverse phase output with a structure in which ZP-port and ZP-port are symmetrical with respect to 1/2 VDD, (balanced output) function.

In addition, the FBDR RCC II circuit according to the present embodiment has an advantage of obtaining a differential voltage and a current output of a phase-reversed phase exactly on the basis of the common mode voltage (VCM) without using a common mode feed back (CMFB) .

39 is a circuit diagram illustrating a power supply apparatus according to an embodiment of the present invention.

Referring to FIG. 39, a power supply apparatus according to an embodiment of the present invention includes a primary rectifier circuit, a transformer T0, a secondary rectifier circuit, a switching unit, and a controller.

The primary rectifying circuit includes a resistor R0, a bridge diode D0 and a capacitor C1. The primary rectifier circuit smoothes the AC power supplied through the plug AC and supplies the AC power to the transformer T0. One end of the bridge diode D0 and one end of the capacitor C1 are connected to the primary side ground voltage GND1.

The transformer T0 includes a primary winding T1P, a secondary winding T2N, and a tertiary winding T1N. One end of the tertiary winding T1N is connected to the anode of the first diode D1 provided in the switching unit and the other end of the tertiary winding T1N is connected to the primary ground voltage GND1.

The secondary rectification circuit is composed of a combination of a second diode D2 and a capacitor C3 and rectifies the power output through the secondary winding T2N of the transformer T0 so as to rectify the output voltage VOUT, And outputs the ground voltage GND2.

The switching unit is responsive to the control of the controller by the combination of the starting resistor R1, the starting switch M0, the first diode D1, the capacitor C2, the resistor R2 and the switch M1, Thereby controlling the supply timing of the smoothing power source applied to the power source T1P. The start switch M0 and the switch M1 may be made of a MOSFET. The source of the start switch M0 is connected to the primary side ground voltage GND1 via the capacitor C2. The source of the switch M1 is connected to the primary side ground voltage GND1 via the resistor R2.

The controller switches the primary winding T1P based on a first sensing current ixp0 corresponding to the output voltage VOUT and a second sensing current ixn0 corresponding to the secondary ground voltage GND2, Timing. The controller may be implemented as an IC type. A resistor R3 is disposed between a terminal corresponding to the output voltage VOUT and a terminal corresponding to the secondary side ground voltage GND2. An XP-resistor (RXP) is disposed between one end of a resistor (R3) connected to a terminal corresponding to the output voltage (VOUT) and the controller for detecting the first sensing current (ixp0) (RZN) is arranged between the other end of the resistor (R3) connected to the terminal corresponding to the secondary side ground voltage (GND2) and the controller for detection of the voltage (ixn0). The controller may be a PWM controller for controlling the operation of the switching unit in a PWM manner. The controller may include a second-generation current conveyor that detects the first sensing current (ixp0) and the second sensing current (ixn0).

The AC AC power source is full-wave rectified through the bridge diode D0. The power source that is full-wave rectified through the bridge diode D0 is charged / discharged to the capacitor C1 and smoothed to have a DC component voltage characteristic.

An initial voltage is generated by the starting resistor R1 and the starting switch M0 and a constant voltage is supplied to the controller.

The controller starts up with the supplied voltage and turns on the switch M1. Thus, current flows from one end (A) to the other end (B) of the primary coil (T1P) of the transformer (T0), and energy is stored in the primary coil (T1P). At this time, since the tertiary coil T1N and the secondary coil T2N are generated by the tertiary coil T1N and the secondary coil T2N, the reverse voltage is cut off by the diodes D1 and D2, and the current does not flow.

The controller starts and turns off the switch Ml. At this time, a forward voltage is generated in the tertiary coil T1N and the secondary coil T2N, and a current flows through the diodes D1 and D2.

The current flowing through the first diode (D1) generates a voltage for normally starting the controller, and turns off the switch (M0) to terminate the start-up.

The current flowing through the second diode D2 generates the voltage of the secondary side. The voltage generated on the secondary side is smoothed by the capacitor C3 to have the output of the direct current component.

An XP-resistor (RXP) and an XN-resistor (RXN) are arranged in the secondary winding (T2N) to sense the voltage on the secondary side and the sensed voltage is fed back to the controller disposed on the primary side. That is, the XP-resistor RXP is arranged to detect the secondary output voltage VOUT output from one end of the secondary winding T2N, and the secondary-side ground voltage Vout output from the other end of the secondary winding T2N (XN-resistor RXN) to detect the ground potential GND2.

In the present invention, it is assumed that the potential difference between the primary side ground voltage GND1 and the secondary side ground voltage GND2 is usually within a range of about 0-1V from 0V. The reason for this is that the dielectric breakdown voltage of the photo-coupler, which is typically used to monitor the secondary voltage at the primary, is about ± 1 KV, so the potential difference between the primary ground voltage (GND1) and the secondary ground voltage (GND2) It can be estimated from 0V to ± 1KV. The range of such voltages is a basis that can be considered to be a level that is sufficiently commercially viable for circuit and expression calculations used in this specification.

40 is a view for explaining the primary side ground voltage and the secondary side ground voltage.

40, the secondary side ground voltage GND2 may be larger than the primary side ground voltage GND1 and may be smaller than the secondary side output voltage VOUT.

The potential difference between the primary side ground voltage GND1 and the secondary side ground voltage GND2 is the difference voltage VD and the potential difference between the secondary side ground voltage GND2 and the secondary side output voltage VOUT is the output target voltage VO .

That is, the voltage of the secondary side output voltage VOUT and the voltage of the secondary side ground voltage GND2 on the basis of the primary side ground voltage GND1 are as follows.

V (VOUT) = VD + VO

V (GND2) = VD

FIG. 41 is a block diagram showing the FBDRRCC II which is built in the controller shown in FIG. 39 and calculates the output target voltage VO based on the secondary side output voltage VOUT and the secondary side ground voltage GND2.

39 and 41, a common mode voltage (VCM) is applied to the YP-port and the YN- port. One end of the XP-resistor (RXP) is connected to the XP-port and the other end of the XP-resistor (RXP) is connected to the secondary output voltage (VOUT). One end of the XN resistor RXN is connected to the XN- port and the other end of the XN resistor RXN is connected to the secondary ground voltage GND2.

The ZP-port is connected to the ZPO terminal and the common-mode voltage (VCM) is connected via the ZP-resistor (RZP). The ZN-port is connected to the ZNO terminal and the common mode voltage (VCM) is connected via the ZN-resistor (RZN).

The formula of current is calculated as follows.

The voltages of YP-port and YN-port of FBDRRCC II are V (VCM) = VCM.

는 다음의 수식 9로 나타낼 수 있다.At this time, the current flowing in the XP-resistor (RXP)

Can be expressed by the following equation (9).

[Equation 9]

= (V(VOUT) -V(VCM)) / RXP

= (V (VOUT) - V (VCM)) / RXP

= ((VD + VO -VCM)) / RXP

= ((VD + VO-VCM)) / RXP

은 다음의 수식 10으로 나타낼 수 있다.Also, the current flowing in the XN-resistor (RXN)

Can be expressed by the following equation (10).

[Equation 10]

= (V(GND2) -V(VCM)) / RXN

= (V (GND2) - V (VCM)) / RXN

= (VD -VCM) / RXN

= (VD-VCM) / RXN

Assuming that the value of the XN resistor (RXN) connected to the secondary output voltage (VOUT) and the value of the XP resistor (RXP) connected to the secondary ground voltage (GND2) are the same and RX is assumed to be RXN = RXP = RX do.

By substituting these in Eqs. 9 and 10, the current flowing in the ZPO terminal can be summarized as Eq. (11) according to the formula of FBDRRCCII.

[Equation 11]

=

=

= (VD+VO-VCM)/RX - (VD-VCM)/RX

= (VD + VO-VCM) / RX- (VD-VCM) / RX

= VO/RX

= VO / RX

The current flowing through the ZNO terminal can be summarized as shown in Equation 12 according to the formula of FBDRRCCII.

[Equation 12]

= -(

)

= - (

)

= - ((VD+VO-VCM)/RX - (VD-VCM)/RX)

= - ((VD + VO-VCM) / RX- (VD-VCM) / RX)

= - VO/RX

= - VO / RX

At this time, the voltage of the ZPO terminal and the voltage of ZNO are expressed by the following equation (13).

[Equation 13]

* RZP = (VO * RZP)/RXV (ZPO) =

* RZP = (VO * RZP) / RX

* RZN = -(VO * RZN)/RXV (ZNO) =

* RZN = - (VO * RZN) / RX

At this time, assuming that RZP = RZN = RX, the following Expression 14 can be obtained.

[Equation 14]

V (ZPO) = VO

V (ZNO) = -VO

Therefore, by applying FBDRRCCII in the application of SMPS having an unknown potential difference between the primary side ground voltage GND1 and the secondary side ground voltage GND2, the difference between the secondary side output voltage VOUT and the secondary side ground voltage GND2 It is possible to simply obtain the output target voltage VO. Accordingly, the power supply can detect the secondary side power supply of the transformer and omit the photo-coupler to receive it. A photo-coupler provided separately from the power supply unit can be omitted, and a separate circuit for monitoring at the secondary side of the transformer can be omitted, thereby reducing the manufacturing cost of the power supply unit.

FIG. 42 is a circuit diagram for explaining a power supply apparatus according to another embodiment of the present invention. FIG.

42, a power supply apparatus according to another embodiment of the present invention includes a primary rectifier circuit, a transformer T0, a secondary rectifier circuit, a switching unit, a controller, an EMI filter F0, a voltage clamping snubber F1) and an RCD snubber (F2). 39, the same constituent elements are given the same reference numerals, and a detailed description thereof will be omitted.

The EMI filter F0 is composed of L and R and is connected between the plug AC and the bridge diode D0 to prevent the switching noise generated by the switching of the transformer T0 from being radiated to the EMI.

The voltage clamping snubber F1 is connected to both ends of the primary winding T1P of the transformer T0 so that the damage of the switch due to the sparking voltage caused by the leakage inductance existing in the transformer T0 . The voltage clamping snubber F1 includes a capacitor and a resistor connected in parallel to the output terminal of the bridge diode D0 and one end of the primary winding T1P and a resistor connected in series to the capacitor and resistor in parallel, And a diode connected to the other end of the primary winding T1P.

In the voltage clamping snubber F1, since the voltage of the capacitor is always charged to a high level, it has no effect on the rising portion of the drain voltage of the switch M1 and is effective only when the drain voltage becomes higher than the voltage value of the capacitor.

The RCD snubber (RCD snubber) F2 comprises a diode and a resistor connected in parallel to the other end of the primary winding T1P, and a capacitor connected in series with the diode and the resistor and connected to the other end of the tertiary winding Thereby preventing the switch M1 from being damaged by a counter electromotive voltage or the like generated when the switch M1 is turned on / off. That is, the current flows to the diode and the capacitor at the moment of the turn-off of the switch M1, thereby lowering the voltage rising rate between the drain and the source of the switch M1. The moment the switch M1 is turned on, the charge of the capacitor is rapidly discharged through the resistor.

Generally, when the primary-side switches M0 and M1 change state from on to off, the primary-side switches M0 and M1 are supplied with a voltage based on the power source, a back electromotive voltage generated in the inductor itself of the transformer, The overshoot voltage caused by the secondary winding T2N and the induction voltage derived from the secondary winding T2N are applied to the primary side switches M0 and M1, which may cause an excessive burden on the primary side switches M0 and M1.

However, since the voltage clamping snubber F1 and the RCD snubber F2 are disposed on the primary side, the primary side switches M0 and M1 due to the back electromotive voltage generated when the primary side switches M0 and M1 are turned off, Can be prevented from being damaged.

FIG. 43 is a configuration diagram showing FBDR RCCs II, which are built in the controller shown in FIG. 42 and measure a DP signal and a DM signal so as to output a variable output voltage.

Referring to FIGS. 42 and 43, in order to variably adjust the secondary output voltage VOUT according to the entirety of the object to be charged by the output voltage VOUT of the power supply, the DP signal And the lower FBDR RCC II for measuring the DM signal (D-) provided through the USB cable in the whole of the object. Typically, a USB cable carries a DP signal (D +) and a DM signal (D-) through a pair of differential data lines and delivers power (Vbias) and ground (GND).

The common mode voltage (VCM) is applied to the YP-port and YN- port of the upper FBDRRCC II. One end of the DP-resistor (RDP) is connected to the XP-port of the upper FBDRRCC II, and the DP signal is connected to the other end of the DP-resistor (RDP). One end of the XN resistor (RXN) is connected to the XN- port of the upper FBDRRCC II and the other end of the XN resistor (RXN) is connected to the secondary ground voltage (GND2). The ZP-port of the upper FBDRRCC II is connected to the ZPO1 terminal and the common mode voltage (VCM) is connected via the ZP-resistor (RZP). The ZN-port of the upper FBDRRCC II is connected to the ZNO1 terminal and the common mode voltage (VCM) is connected via the ZN-resistor (RZN).

The common mode voltage (VCM) is applied to the YP-port and YN- port of the lower FBDRRCC II. One end of the DM-resistor (RDM) is connected to the XP-port of the lower FBDRRCC II, and the DM signal is connected to the other end of the DM-resistor (RDM). One terminal of the XN resistor (RXN) is connected to the XN-port of the lower FBDRRCC II, and the other terminal of the XN resistor (RXN) is connected to the secondary ground voltage (GND2). The ZP-port of the lower FBDRRCC II is connected to the ZPO2 terminal and the common mode voltage (VCM) is connected via the ZP-resistor (RZP). The ZN-port of the lower FBDRRCC II is connected to the ZNO2 terminal and the common mode voltage (VCM) is connected via the ZN-resistor (RZN).

DP signal and DM signal transmitted through a USB cable can be measured in the same way and a secondary quick-charger or a separate additional voltage can be detected to adjust the secondary output voltage VOUT variably.

That is, when the level of the DP signal and the level of the DM signal are provided to a power supply, for example, a charger, in the mobile phone, the charger outputs the secondary output voltage VOUT based on the level described above. In particular, the controller is designed to vary the secondary output voltage VOUT based on the level of the DP signal and the level of the DM signal.

For example, if the DP signal is 0.6V, the DM signal is 0.0V, or both the DP signal and the DM signal are 0V, the controller is designed to provide an output voltage (VOUT) of 5V (5W to 10W charge mode). For example, an output voltage (VOUT) of 5V may correspond to most chargers.

On the other hand, if the DP signal is 3.3V and the DM signal is 0.6V, the controller is designed to provide an output voltage (VOUT) of 9V (i.e., a 10W to 15W charge mode). For example, the output voltage (VOUT) of 9V can be applied to Samsung Electronics' Galaxy series smartphone.

On the other hand, if the DP signal is 30.6V and the DM signal is 0.6V, the controller is designed to provide an output voltage (VOUT) of 12V (i.e., a 15W to 30W charge mode). For example, an output voltage (VOUT) of 12V can be used in power tools, notebook computers, and the like.

On the other hand, if the DP signal is 3.3V and the DM signal is 3.3V, the controller is designed to provide an output voltage (VOUT) of 20.0V (i.e., a 30W to 60W charge mode). For example, an output voltage (VOUT) of 20.0 V can be applied to small appliances.

44 is a circuit diagram for explaining a power supply device according to another embodiment of the present invention.

44, a power supply apparatus according to another embodiment of the present invention includes a primary rectifier circuit, a transformer T0, a secondary rectifier circuit, a switching unit, a controller, an upper current amount monitoring unit, and a lower current amount monitoring unit . 39, the same constituent elements are given the same reference numerals, and a detailed description thereof will be omitted.

The upper current amount monitoring unit includes a resistor RS0 connected to the cathode of the second diode D2 between the output voltage VOUT and a resistor RSU having one end connected to the cathode of the second diode D2 and the other end connected to the controller , And monitors the amount of the upper side current by comparing the current with the secondary side ground voltage (GND2). Accordingly, the non-load state or the short state of the secondary side can be monitored on the primary side of the transformer by monitoring the upper side current amount.

The lower current amount monitoring unit includes a resistor RS1 connected between the other end of the secondary winding T2N and the secondary ground voltage GND2 and a resistor RSD having one end connected to the other end of the secondary winding T2N and the other end connected to the controller, And monitors the lower current amount by comparing the current with the secondary side ground voltage GND2. Accordingly, it is possible to monitor the no-load state or the short state of the secondary side from the primary side of the transformer through the monitoring of the lower side current amount.

According to the conventional technique, if a short is generated on the secondary side, the problem caused by the short circuit can not be monitored on the primary side of the transformer.

However, according to the present embodiment, it is possible to monitor whether or not there is a short circuit on the terminal side from which the output voltage VOUT is output by using a resistor RS0 connected between the output voltage VOUT and the cathode of the second diode D2 . It is also possible to monitor whether or not there is a short circuit on the terminal side from which the secondary side ground voltage GND2 is output by using the resistor RS1 connected between the other end of the secondary winding T2N and the secondary side ground voltage GND2.

Either one may be used for monitoring whether or not both the resistor RS0 connected between the output voltage VOUT and the resistor RS1 connected between the secondary side ground voltage GND2 are short-circuited.

According to conventional techniques, monitoring of the no-load state of the secondary side of the transformer is impossible or incomplete.

However, according to the present embodiment, a resistance (RSU) connected between the second diode (D2) connected to one end of the secondary winding and the controller or a resistor (RSD) connected to the other end of the secondary winding You can monitor the no-load condition of the secondary by calculating the difference in voltage.

While there is no load, the switching of the primary side is stopped to minimize standby power. On the other hand, when the load is connected, the amount of current flowing by the resistor RS0 connected to the output voltage VOUT or the resistor RS1 connected to the secondary-side ground voltage GND2 increases, causing a voltage difference across the resistor. When the generated voltage difference is recognized, the primary transformer is switched to supply power to supply the load.

As described above, by monitoring the no-load state or the short state of the secondary side from the primary side, the deep sleep & wake-up function can be used to minimize standby power when no load is applied in a no-load state .

In addition, since the state of the short circuit can be confirmed, it is possible to prevent the breakdown of the transformer connected to the secondary side due to fire or overheating, thereby providing a safety function.

45 is a flowchart for explaining the method of driving the power supply apparatus shown in Fig.

44 and 45, as the plug (AC Plug) is inserted into a socket or the like, the primary side of the power supply apparatus is started (step S110).

The primary side is switched by the switches M0 and M12 to generate the secondary side voltage in the secondary winding of the transformer (step S120).

The secondary side is monitored as the secondary side voltage is generated (step S103). The secondary side can be monitored by the upper current amount monitoring unit and the lower current amount monitoring unit, and the monitored signal is provided to the controller.

It is checked whether the overload state is present (step S140). The overload state can be performed by the controller based on the monitored signal.

If the overload state is checked in step S140, the primary side switching by the switches M0 and M12 is stopped (step S150).

After the primary side switching is stopped, it is deep-slipped and waked up (step S160) and then fed back to step S120.

On the other hand, if the overload state is not checked in step S140, it is checked whether it is a no-load state (step S170). The non-load state can be performed by the controller based on the monitored signal.

If the no-load state is checked in step S170, the flow returns to step S150.

If the no-load state is not checked in step S170, it is checked whether or not the target voltage is reached (step S180).

If it is checked in step S180 that the target voltage has been reached, the primary side switching is stopped (step S190), and then fed back to step S130.

If it is checked in step S180 that the target voltage has not been reached, then it is fed back to step S120.

46 is a waveform diagram for explaining power consumption by the deep sleep and wake-up function of the SMPS shown in Fig.

Referring to FIG. 46, all the functions of the power supply unit are suspended while operating in the sleep mode during the TS interval, and only the timer is operated with a minimum internal clock to minimize the current consumption.

If the load on the secondary side is checked after starting from the TO interval, the sleep mode is entered again to minimize standby power.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. You will understand.

CORE: Core block 110: Upper differential input stage
120: lower differential input stage 130: upper current mirror stage
140: lower current mirror stage 150: switching stage
D2: Driving block 210: First driver
220: second driver 230: third driver
240: fourth driver 250: fifth driver
C1: first capacitor C2: second capacitor
RX: X-resistor RY: Y-resistor
RZP: ZP-resistor RZN: ZN-resistor
RXP: XP-resistor RXN: XN-resistor
RZP: ZP-resistor RZN: ZN-resistor

Claims (9)

A primary rectifying circuit for smoothing AC power;
A transformer including a primary winding and a secondary winding;
A secondary rectifying circuit for rectifying a power output through the secondary winding and outputting an output voltage and a secondary side ground voltage; And
And a controller for controlling the switching timing of the primary winding based on a first sensing current corresponding to the output voltage and a second sensing current corresponding to the secondary ground voltage. The power supply according to claim 1, wherein the controller includes a second-generation current conveyor for detecting the first sensing current and the second sensing current. 3. The method of claim 2, wherein the second-
A first balanced output rail-to-rail second generation current conveyor (hereinafter referred to as a first BORRCC II); And
Rail second generation current conveyor (hereinafter referred to as FBDRRCC II) including a first balanced output rail-to-rail second generation current conveyor (hereinafter referred to as a second BORRCC II), and a second balanced output rail- For each BORRCCII,
To-rail input / output through an upper differential input stage and a lower differential input stage commonly connected to the Y-port and the X-port, and the current applied by the bias voltage is controlled by the voltage of the Y- And outputs a first driving voltage (P_DRV) and a second driving voltage (N_DRV); And
Port in response to the first driving voltage (P_DRV) and the second driving voltage (N_DRV), and outputs an inverted output current having a phase opposite to the normal output current to the ZN-port And a driving block which outputs the driving block through the driving block,
The Y-port and the X-port of the first BORRCC II define a YP-port and the XP-port, respectively, and the Y-port and the X-port of the second BORRCC II define a YN-port and an XN- Port of the first BORRCC II and the ZN-port of the second BORRCC II are connected to define a ZPF-port, and the ZP-port of the first BORRCC II and the ZP- Ports are connected to each other to define a ZNF-port. The apparatus as claimed in claim 3,
Further comprising an upper side FBDRRCC II and a lower side FBDRRCC II for measuring the DP signal and the DM signal provided by the whole of the object via a USB cable in order to variably adjust the secondary side output voltage according to the entire object. 5. The method of claim 4,
The common mode voltage VCM is applied to the YP-port and the YN- port of the upper FBDR RCC II,
One end of the DP-resistor (RDP) is connected to the XP-port of the upper FBDRRCC II, a DP signal is connected to the other end of the DP-resistor (RDP)
One end of the XN resistor RXN is connected to the XN port of the upper FBDRRCC II and the other end of the XN resistor RXN is connected to the secondary ground voltage GND2,
The ZP-port of the upper FBDRRCC II is connected to the ZPO1 terminal and the common mode voltage (VCM) is connected via the ZP-resistor (RZP)
And the ZN-port of the upper FBDRRCC II is connected to the ZNO1 terminal and the common mode voltage VCM is connected via the ZN-resistor RZN. 5. The method of claim 4,
The common mode voltage VCM is applied to the YP-port and the YN- port of the lower FBDRRCC II,
One end of the DM-resistor (RDM) is connected to the XP-port of the lower FBDRRCC II, the DM signal is connected to the other end of the DM-resistor (RDM)
One terminal of the XN resistor (RXN) is connected to the XN- port of the lower FBDRRCC II, the other terminal of the XN resistor (RXN) is connected to the secondary terminal ground voltage (GND2)
The ZP-port of the lower FBDRRCC II is connected to the ZPO2 terminal and the common mode voltage VCM is connected via the ZP-resistor RZP,
And the ZN-port of the lower FBDRRCC II is connected to the ZNO2 terminal and the common mode voltage VCM is connected via the ZN-resistor RZN. 2. The transformer according to claim 1, further comprising an EMI filter, which is composed of L and R, and is connected between the plug and the bridge diode so as to prevent switching noise generated by switching of the transformer from being radiated to the EMI Power supply. The power supply according to claim 1, further comprising a voltage clamping snubber connected to both ends of the primary winding to prevent damage to the switch due to sparking voltage caused by leakage inductance present in the transformer Supply device. The RCD snubber circuit according to claim 1, further comprising an RCD snubber which is connected to the other end of the primary winding and the other end of the tertiary winding to prevent damage to the switch due to a back electromotive voltage generated when the switch is turned on / Further comprising a power supply for supplying power to the power supply.

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