KR20180071051A - Driver Intergrated Circuit and Differentiated Display Device Having The Same - Google Patents

Abstract

The present invention relates to a driver integrated circuit and a free-form display device having the same. The free-form display device comprises: a display panel including an active region in which a plurality of sub-pixels are arranged in a matrix form and a plurality of data lines and a plurality of gate lines for supplying a data voltage and a scan signal to the sub-pixels are arranged, a bezel region which is arranged along a circumference of the active region, and a pad region which is formed at one side of the bezel region and in which a plurality of pads connected to the data lines of the active region, respectively, are formed; and a driver integrated circuit supplying the data voltage to the data lines and having a pad portion coupled to each pad of the pad region. At least a portion of each pad of the pad region is formed with a conductive layer at a predetermined interval from a pad on the opposite side of a surface being in contact with the pad portion, and thus a ratio of supplying the data voltage provided to each data line becomes uniform, thereby preventing a luminance difference.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a driver integrated circuit,

The present embodiments relate to a driver integrated circuit and a mold release display device including the same.

2. Description of the Related Art [0002] As an information-oriented society develops, there have been various demands for a display device for displaying images. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) And various display devices such as an organic light emitting display (OLED) device are used.

The display device further includes a display panel on which the subpixels defined by the data lines and the gate lines are arranged and the data lines and the gate lines intersect, a data driver for supplying data voltages to the data lines, A gate driver for driving the gate driver, and a controller for controlling the driving timing of the data driver and the gate driver.

Among these display devices, the mold release display device includes an active area (A / A) in which a plurality of sub-pixels are arranged and a pad area PA (PA) in which a plurality of pads are formed along the outside of the active area A / A Pad Area), and a bezel area (BA) composed of areas where signal lines are arranged.

In the mold release display device, the active area is not a quadrangle but a circle, an ellipse, or a triangle. In this case, the length of each data line arranged in the active area varies depending on the area of the active area. For example, in the central region of the active region, the length of the data line becomes long, and in both side regions of the active region, the length of the data line becomes short.

When the length of the data line is changed according to the portion of the active region, the load applied to the data line varies depending on the length of the data line. That is, relatively short loads on the short data lines, while relatively long loads on the relatively long data lines. In a data line with a low load, a desired data voltage is quickly reached while the scan signal is turned on. However, the time required to reach the desired data voltage is long in the data line in which the load is high, while the scan signal is turned on. Accordingly, a difference in luminance occurs due to the difference in load between the data lines.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a driver integrated circuit and a mold release display device including the same that can prevent a difference in brightness caused by a difference in load between data lines.

One embodiment provides a mold release display. An active region in which a plurality of subpixels are arranged in a matrix and in which a plurality of data lines and a plurality of gate lines are arranged to provide a data voltage and a scan signal to the plurality of subpixels, And a pad region formed on one side of the bezel region and having a plurality of pads connected to the data lines of the active region. And a driver integrated circuit that provides the data voltage to the plurality of data lines and has a pad portion coupled to each pad of the pad region. At least a part of each pad of the pad region is provided with a conductive layer at a predetermined interval from the pad on the side opposite to the side in contact with the pad portion.

In another embodiment, a driver integrated circuit is provided. Film. A plurality of signal lines arranged alternately so as to form a double layer for bonding with the film are formed, and the intervals between the signal lines forming the same layer are different from each other according to the positions of the signal lines. Chip.

In another embodiment, a mold release display device is provided. There is provided a display panel including a plurality of subpixels arranged in a matrix and a plurality of data lines for providing a data voltage and a scan signal to the plurality of subpixels and an active region having a plurality of gate lines arranged therein. A plurality of signal lines arranged alternately so as to form a double layer for coupling the film and the film, and a plurality of signal lines forming the same layer, And a driver integrated circuit chip which is arranged differently according to the position of the signal line.

According to the embodiments described above, since the ratio of the data voltage supplied to each data line is uniform, the luminance difference can be prevented.

According to the present embodiment, it is possible to prevent the difficulty of providing a separate region in which a capacitor can be realized by forming a capacitor in a bezel region. Further, by implementing the capacitor in the bezel region, it is possible to prevent occurrence of metallic foreign matter and occurrence of short circuit with other circuit wiring.

1 is a schematic system configuration diagram of an OLED display according to an embodiment of the present invention.
2 is an equivalent circuit diagram of subpixels of the organic light emitting diode display of this embodiment.
FIGS. 3 and 4 are views showing a structure of a curved display device according to the present embodiment.
5 is a plan view of the pad region viewed from the second surface according to an embodiment of the present invention.
6 and 7 are cross-sectional views of two different pads in a pad region according to an embodiment of the present invention.
8 is a front view of a source driver integrated circuit according to another embodiment of the present invention.
Figs. 9A to 9C are enlarged views of regions a, b, and c in Fig. 8.
Figs. 10A to 10C are front sectional views of the regions a, b, and c in Fig.
11 is a side sectional view of one of the areas a, b, and c in Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. However, it is to be understood that the present invention is not limited to the disclosed embodiments, but may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification. The dimensions and relative sizes of the layers and regions in the figures may be exaggerated for clarity of illustration.

It will be understood that when an element or layer is referred to as being another element or "on" or "on ", it includes both intervening layers or other elements in the middle, do. On the other hand, when a device is referred to as "directly on" or "directly above ", it does not intervene another device or layer in the middle.

The terms spatially relative, "below," "lower," "above," "upper," and the like, And may be used to easily describe the correlation with other elements or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components.

Fig. 1 is a schematic system configuration diagram of a display device according to the present embodiment, and Fig. 2 is an equivalent circuit diagram for a subpixel of the display device of this embodiment.

1 and 2, a display device 100 according to the present embodiment includes a plurality of data lines DL # 1, DL # 2 ... DL # 4M, (GL # 1, GL # 2 ... GL # N, N are natural numbers of 1 or more) are arranged in a second direction (e.g., a row direction) A display panel 110 in which subpixels SP are arranged in a matrix type, a data driver 120 for driving a plurality of data lines DL # 1, DL # 2 ... DL # 4M, A gate driver 130 for driving lines GL # 1, GL # 2 ... GL #N and a controller T-CON 140 for controlling the data driver 120 and gate driver 130, .

The data driver 120 drives a plurality of data lines by supplying data voltages to the plurality of data lines DL # 1, DL # 2 ... DL # 4M.

The gate driver 130 sequentially supplies the scan signals to the plurality of gate lines GL # 1, GL # 2 ... GL # N to sequentially supply the plurality of gate lines GL # 1, GL # 2 ... GL # GL #N) are sequentially driven.

The controller 140 supplies various control signals to the data driver 120 and the gate driver 130 to control the data driver 120 and the gate driver 130.

The controller 140 starts scanning in accordance with the timing implemented in each frame, switches the input image data input from the outside according to the data signal format used by the data driver 120, and outputs the converted image data (DATA) And controls the data driving at a proper time according to the scan.

The gate driver 130 applies a scan signal of an On voltage or an Off voltage to the gate lines GL # 1, GL # 2 ... GL #N under the control of the controller 140, And sequentially drives the plurality of gate lines GL # 1, GL # 2 ... GL #N.

The gate driver 130 may be located only on one side of the display panel 110, or may be located on both sides, as the case may be, depending on the driving method. In addition, the gate driver 130 may include one or more gate driver integrated circuits.

When the specific gate line is opened, the data driver 120 converts the image data (DATA) received from the controller 140 into a data voltage of an analog type to generate a plurality of data lines DL # 1, DL # 2 ... DL # 4M) to drive a plurality of data lines (DL # 1, DL # 2 ... DL # 4M).

The data driver 120 may drive a plurality of data lines DL # 1, DL # 2 ... DL # 4M including at least one source driver integrated circuit.

Each source driver integrated circuit may be connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) And may be integrated and disposed on the display panel 110 as occasion demands.

On the other hand, the controller 140 outputs various kinds of signals including the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the input data enable signal (DE), and the clock signal (CLK) Timing signals from the outside (e.g., the host system).

The controller 140 outputs the converted image data by switching the input image data inputted from the outside in accordance with the data signal format used by the data driver 120 and outputs the converted image data to the data driver 120 and the gate driver 130, A timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input DE signal and a clock signal and generates various control signals to control the data driver 120 and the gate driver 130, .

Each of the subpixels SP disposed in the display panel 110 of the organic light emitting diode display device 100 shown as an example of the display device in this embodiment includes an organic light emitting diode (OLED) , At least one capacitor, or the like.

Referring to FIG. 2, each sub-pixel SP is connected to one data line DL and receives only one scan signal SCAN through one gate line GL.

Each of the sub-pixels includes an organic light emitting diode (OLED), and includes a driving transistor (DT), a first transistor (T1), a second transistor (T2), a storage capacitor (Cst) . Since each sub-pixel includes three transistors DT, T1, and T2 and one storage capacitor Cst, each sub-pixel has a 3T (Capacitor) structure.

The driving transistor DT in each sub-pixel receives the driving voltage EVDD supplied from the driving voltage line DVL (driving voltage line), and the voltage of the gate node N2 applied through the second transistor T2 (Data voltage) to drive the organic light emitting diode OLED. EVSS shown in the figure is a low voltage.

The driving transistor DT has a first node N1, a second node N2 and a third node N3. The first transistor N1 is connected to the first transistor T1, The node N2 is connected to the second transistor T2 and the third node N3 is supplied with the driving voltage EVDD.

The storage capacitor Cst may be connected between the first node N1 and the second node N2 of the driving transistor DT to maintain the data voltage for one frame.

FIGS. 3 and 4 are views showing a structure of a curved display device according to the present embodiment.

Referring to FIG. 3, the curved display device 420 according to the present embodiment may have a circular or elliptical structure. The display panel 110 shown in FIG. 1 has a rectangular shape, but may be formed of a curved display panel 310 having a predetermined curvature when used in a display device such as a clock.

The curved display panel 310 according to the present embodiment may have a predetermined curvature along the periphery. For example, the curved display panel 310 according to the present embodiment includes a circular display panel 310 in which the edges of the curved display panel are formed to have the same length from the center of the active area A / A, And may include an oval display panel having different echo lengths.

As shown in FIG. 1, a plurality of sub-pixels are arranged in an active area (A / A) of the curved display panel 310, and a plurality of pads are arranged along the outside of the active area A / And a bezel area (BA) composed of a pad area (PA) and a region where signal lines are arranged.

As shown in FIG. 3, when the active area A / A is circular, the signal lines arranged in the bezel area PA may be formed in a curved shape so as to surround the active area A / A. The signal lines include a driving voltage line DVL for supplying a driving voltage EVDD to each sub pixel, a base low voltage line SVL for supplying a base voltage EVSS to each organic light emitting diode, a gate driver GIP, A reference voltage line RVL for providing a reference voltage VREF and a data line DL for providing a data voltage and the like may be further included in the bezel area BA, .

A plurality of gate lines (not shown) are formed in the active area A / A in the first direction, for example, in the row direction. Each gate line is arranged in the second direction of the active area A / For example, at regular intervals along the column direction. Each of the gate lines is connected to the gate driver 130 and provides a scan signal provided from the gate driver 130 to each sub-pixel SP.

A plurality of data lines DL are formed in the active area A / A along a second direction, for example, a column direction. Each data line DL is divided into an active area A / A, For example, in the row direction. Each data line DL extends from the bezel area BA and is supplied with a data voltage to each sub-pixel SP.

Accordingly, in the active area A / A, a plurality of gate lines and data lines DL are arranged in a matrix such that the gate lines and the data lines DL cross each other, and the sub pixels SP Is formed. FIG. 3 shows only a part of the data lines DL for convenience of explanation.

In the display panel 310 of the present embodiment, the active area A / A is formed in a circular shape, and the length of each data line DL varies depending on the area of the active area A / A. Accordingly, the load applied to the data line DL varies depending on the length of the data line DL, so that the time required to reach the desired data voltage in each data line DL becomes different. Such a time difference causes a difference in luminance depending on the data line DL.

In order to prevent this, in the present embodiment, capacitors are formed in the respective data lines DL and the capacitances of the capacitors are made different from each other, so that each data voltage supplied to each data line DL is set at a voltage level set at the same time So that it can be reached. Thus, it is possible to compensate for the difference in luminance due to the difference in the load applied to each data line DL. The configuration of the capacitors formed in each data line DL will be described later.

A plurality of pads 350 formed of a metal are formed in the pad region PA. The plurality of pads 350 are formed in a strip shape toward the active region A / A, and the active region A / A in the circumferential direction. A source driver integrated circuit 200 for providing a data voltage, a driving voltage, a base voltage, and the like to the data line DL may be connected to the pad region PA.

The source driver integrated circuit 200 may be implemented by a chip on film (COF) method, as shown in FIG. One end of each source driver integrated circuit 200 is bonded to a source printed circuit board and the other end is bonded to a pad area PA.

The source driver integrated circuit 200 implemented by the COF method includes a source driver integrated circuit chip 250 mounted on the film 220 and electrically connected to the driver integrated circuit chip 250 at both ends of the film 220 The first pad portion 230 and the second pad portion 210 are formed of metal strips. The first pad portion 230 and the second pad portion 210 are formed of metal strips having predetermined pitches and widths, and the pitch and width of the metal strips formed on the first pad portions 230, Is formed to be smaller than the pitch and the width of the metal strip formed on the metal strip (210).

The pads 350 of the pad region PA to which the source driver integrated circuit 200 is coupled are formed to have a size and width matched with the pads 350 formed on the first pad portion 230 of the driver IC .

5 is a plan view of the pad area PA according to the embodiment of the present invention, viewed from the second surface.

Conductive layers 360a and 360b are formed on at least a part of each of the pads 350 in the pad area PA at predetermined intervals from the pads 350a and 350b. The source driver circuit 200 is bonded to the first surface of each pad 350 and each pad 350a of the pad 350a is bonded to the first surface of each pad 350. [ Conductive layers 360a and 360b are formed on the second surface of the first and second electrodes 350a and 350b at predetermined intervals. At this time, the conductive layers 360a and 360b may not be formed on some of the pads 350.

On the other hand, the conductive layers 360a and 360b disposed on the second surface of the pads 350a and 350b at predetermined intervals form a capacitor together with the pads 350a and 350b. The conductive layers 360a and 360b are formed to have different sizes depending on the lengths of the data lines DL connected to the pads 350a and 350b of the pad area PA, have. That is, the capacitances of the capacitors are designed to vary according to the load of each data line DL.

For example, when the length of the data line DL is long, the load of the data line DL becomes large, and the size of the conductive layer 360a is relatively small. That is, when the load of the data line DL is increased, the capacity of the capacitor is reduced. Conversely, if the length of the data line DL is shortened, the load of the data line DL becomes small. At this time, the size of the conductive layer 360b is relatively large. That is, when the load of the data line DL is reduced, the capacitance of the capacitor is increased.

If the conductive layers 360a and 360b are formed so that the capacitances of the capacitors are changed according to the loads of the data lines DL, the capacitances of the data lines DL having a small load and the data lines DL having a large load The time for reaching the data voltage becomes the same, so that a difference in luminance according to the data line DL can be prevented.

On the other hand, in the case of the data lines DL arranged at the center of the active area A / A, the length of the data lines DL is large and the load of the data lines DL is large. Therefore, in the case of the data line DL arranged in the central region of the active area A / A, it is not necessary to add another load using a capacitor. That is, unlike the other pads 350a and 350b, the conductive layers 360a and 360b may not be formed on the pad 350 connected to the data line DL disposed at the center of the active area A / A.

5, the pads 350 connected to the data lines DL disposed in the central region of the active region A / A are not formed with the conductive layers 360a and 360b, The sizes of the conductive layers 360a and 360b are increased from the central region of the region A / A to the both side portions.

In this embodiment, since the data lines DL arranged in the central region have a long length and a large load, the conductive layers 360a and 360b are not formed on the pads 350 connected to the corresponding data lines DL. On the other hand, since the length of the data line DL becomes shorter and the load becomes smaller from the central region to both ends, the sizes of the conductive layers 360a and 360b are gradually increased. Accordingly, the time required for the data voltages applied to all the data lines DL to rise to a certain level is equalized.

Each conductive layer 360a and 360b is connected to a ground layer or a power source to form a capacitor together with the pads 350. [ Each of the conductive layers 360a and 360b may be formed in a layer in which a gate driver is formed or another layer. Accordingly, a separate space is not required for forming the conductive layers 360a and 360b, There is no fear that the volume or the area of the display device will become large due to the formation of the reflective films 360a and 360b.

6 and 7 are cross-sectional views of two different pads in a pad region according to an embodiment of the present invention.

6 and 7 are sectional views of the pad area PA of the display panel in which the first pad part 230 of the source driver integrated circuit 200 is coupled. And FIG. 7 is a cross-sectional view of a pad having a capacitor with a large capacitance.

6, a first insulating layer 355 is formed on the first surface of each pad 350a for insulating each pad 350a, and the first surface of each pad 350a is connected to a source A part of the first insulating layer 355 is removed so as to be coupled with the first pad portion 230 of the driver integrated circuit 200. [ A bonding ball 356 for bonding with the first pad portion 230 of the source driver integrated circuit 200 is applied to a region where the first insulating layer 355 is removed. The bonding balls 356 are melted by heat when each of the first pad portions 230 of the source driver integrated circuit 200 is coupled to the first surface of each pad 350a, So that one pad portion 230 is coupled to the first surface of each pad 350a.

A second insulating layer 365 is formed on the second surface of each pad 350a and the conductive layer 360a. The conductive layer 360a shown in FIG. 6 is formed to be relatively small in size . Accordingly, a capacitor having a small capacitance is formed in the pad 350a of FIG. The capacitor having such a small capacitance may be formed in the data line DL having a large load among the data lines DL shown in Fig.

On the other hand, the conductive layer 360b formed on the pad 350b of FIG. 7 is formed to be relatively large, so that a capacitor having a large capacitance is formed on the pad 350b of FIG. The capacitor having such a large capacitance may be formed in the data line DL having a small load among the data lines DL shown in FIG.

When capacitors are formed in the respective data lines DL and the capacitances of the capacitors are adjusted according to the sizes of the conductive layers 360a and 360b in accordance with the loads of the data lines DL, The same effect can be obtained. Accordingly, when a data voltage is supplied to each data line DL by a scan signal, a data voltage is supplied at the same rate for the same time period, so that a luminance difference can be prevented from occurring according to each data line DL have.

FIG. 8 is a front view of a source driver integrated circuit according to another embodiment of the present invention, and FIGS. 9A to 9C are enlarged views of regions a, b, and c of FIG.

The source driver integrated circuit 700 according to this embodiment forms a capacitor by adjusting the interval between the signal lines connecting the source driver integrated circuit chip 750 and the film 720.

The source driver integrated circuit chip 750 is formed with a plurality of signal lines formed by metal strips at a pair of opposing corners, and the signal lines at one corner are connected to the first pad (not shown) through metal strips formed on the film 720, And the signal lines at the other edge are connected to the second pad portion 710 through the metal strips formed on the film 720. [

These signal lines are vertically arranged in a double direction with respect to a direction extending from the source driver integrated circuit chip 750. For example, the odd-numbered signal lines are arranged above the even-numbered signal lines or the even-numbered signal lines are arranged above the odd-numbered signal lines, so that the signal lines are alternately arranged up and down to form a double layer. For convenience of explanation, the signal lines disposed at the upper portion are referred to as first signal lines 760, and the signal lines disposed at the lower portion are referred to as second signal lines 770.

The first signal lines 760 and the second signal lines 770 are spaced apart from each other so that at least a part of the second signal lines 770 disposed below may be exposed to the outside, And are arranged so as to be spaced apart from each other between the second signal lines 770.

The first signal lines 760 and the second signal lines 770 are formed at the ends thereof with pads for bonding bonding with the film 720. The pads connected to the first signal lines 760 are connected to the first chip pads 760. [ And a pad connected to the second signal lines 770 is referred to as a second chip pad unit 775. [

The first signal lines 760 are longer than the second signal lines 770 by a predetermined length so that the first chip pads 765 of the first signal lines 760 are connected to the second signal lines 770 Chip pads 775 are spaced apart from the source driver chip. At this time, since the first signal lines 760 are formed above the second signal lines 770, the first chip pad portion 765 is also formed above the second chip pad portion 775.

11, a first film pad 725a and a second film pad 720b are bonded to the first chip pad portion 765 and the second chip pad portion 775, respectively, A portion 725b is formed. Since the first chip pad portion 765 is formed on the upper portion of the second chip pad portion 775, the region of the film 720 where the first film pad portion 725a is formed is formed in the second film pad portion 725b Is formed at a predetermined step height from the area of the film 720 where the film 720 is formed.

Since the first signal lines 760 and the second signal lines 770 of the source driver integrated circuit chip 750 are vertically spaced apart from each other, the first signal line 760 and the second signal line 770, which are adjacent to each other, It is possible to form a capacitor between them. At this time, the capacity of the capacitor is determined by the interval between the first signal lines 760 and the interval between the second signal lines 770.

For example, as shown in FIG. 10A, when the interval between the first signal lines 760 and the interval between the second signal lines 770 is more than a predetermined value, that is, when the interval between the first signal lines 760 is the first When the width of the signal line 760 is greater than the width of the second signal line 770 and the distance between the second signal lines 770 is larger than the width of the second signal line 770, the first signal lines 760 and the second signal lines 770 overlap each other I will not. 9A, the gap between the first signal lines 760 and the second signal lines 770 is formed in the front view, and the first signal lines 760 and the second signal lines 770 are spaced from each other, (770) are exposed so that they can be viewed from the outside. If the first signal lines 760 and the second signal lines 770 are not overlapped with each other, the gap between the neighboring first signal lines 760 and the second signal lines 770 becomes large, And the capacitances of the capacitors formed between the second signal lines 770 are relatively small.

10B, when the interval between the first signal lines 760 and the interval between the second signal lines 770 is substantially the same as the width of the first signal line 760 or the second signal line 770, The first signal lines 760 and the second signal lines 770 do not almost overlap each other in the vertical direction. 9B, there is no gap between the first signal lines 760 and the second signal lines 770 when viewed from the front, and they appear to be almost not overlapped. If the first signal lines 760 and the second signal lines 770 are disposed adjacent to each other, the gap between the neighboring first signal line 760 and the second signal line 770 becomes narrower than the state shown in FIG. 10A The capacitance of the capacitor becomes relatively large.

10C, when the interval between the first signal lines 760 and the interval between the second signal lines 770 is smaller than the width of the first signal line 760 or the second signal line 770 by a certain amount or more The first signal lines 760 and the second signal lines 770 are overlapped in a vertical direction by a predetermined width or more. Accordingly, as seen in FIG. 9C, when viewed from the front, a portion of the second signal lines 770 is covered by the first signal lines 760. When the area where the first signal lines 760 and the second signal lines 770 are overlapped with each other increases, the interval between the neighboring first signal line 760 and the second signal line 770 becomes narrow. Therefore, the first signal line 760 And the capacitances of the capacitors formed between the second signal lines 770 are relatively large.

Accordingly, in this embodiment, the capacity of the capacitor can be adjusted by adjusting the interval between the first signal lines 760 and the interval between the second signal lines 770, and the first signal line 760 and the second signal line 770 A capacitor having a suitable capacitance can be formed in the source driver integrated circuit 700 according to the length of the data line DL to which the data line DL is connected.

That is, the first signal lines 760 and the second signal lines 770 connected to the relatively short data lines DL are arranged adjacent to each other so that the capacitances of the capacitors are increased, and the first signal lines 760 and the second signal lines 770 are connected to the relatively long data lines DL The first signal lines 760 and the second signal lines 770 may be spaced apart from each other such that the capacitances of the capacitors are reduced.

Accordingly, in the case of the data lines DL arranged at the center of the active area A / A, since the length of the data lines DL is long and the load of the data lines DL is large, The first signal lines 760 and the second signal lines 770 are arranged relatively wide so that a capacitor having a small capacitance is formed.

On the other hand, in the case of the data lines DL arranged at both side ends of the active area A / A, since the data lines DL are short and the load of the data lines DL is relatively small, It is preferable that the interval between the first signal lines 760 and the interval between the second signal lines 770 are relatively narrow so that a capacitor having a large capacitance is formed.

According to this embodiment, the capacitances of the capacitors are adjusted by adjusting the intervals between the first signal lines 760 and the second signal lines 770 according to the load of the data lines DL, Lt; RTI ID = 0.0 > DL) < / RTI >

In the above-described embodiment, the capacitors are classified into three capacitors. However, it is needless to say that the capacity of the capacitors can be adaptively changed according to the load of the data lines DL. That is, the capacitance of the capacitor can be adjusted to change linearly.

As described above, in the embodiment of the present invention, the capacities of the capacitors are adjusted by adjusting the sizes of the conductive layers 360a and 360b corresponding to the respective pads of the pad region PA to which the source driver integrated circuit 700 is coupled, So that a capacitor having a capacitance in inverse proportion to the load of each data line DL is formed for each data line DL.

In another embodiment of the present invention, by adjusting the distance between the double metal strips connecting the source driver integrated circuit chip 750 and the film 720 on the source driver integrated circuit 700, the first signal lines 760 and the second The size of the capacitor formed between the signal lines 770 is adjusted in inverse proportion to the load of the data line DL.

Thus, the ratio of the data voltages supplied to the data lines DL is uniform, so that the luminance difference can be prevented. In addition, since the capacitor is formed in the bezel region, it is possible to prevent the difficulty of providing a separate region for implementing the capacitor. Moreover, by implementing the capacitor in the bezel region, it is possible to prevent the occurrence of metal foreign matter and the occurrence of short circuit between other circuit wiring.

The features, structures, effects and the like described in the foregoing embodiments are included in at least one embodiment of the present invention and are not necessarily limited to one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the present invention. It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiments may be modified and implemented. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

200: source driver driving circuit
220, 720: film
230: first pad portion
250, 750: Source driver integrated circuit chip
310: Display panel
350: Pad
360: conductive layer
760: first signal line
765: first chip pad portion
770: Second signal line
775: second chip pad portion

Claims (6)

An active region in which a plurality of subpixels are arranged in a matrix and in which a plurality of data lines and a plurality of gate lines are arranged to provide a data voltage and a scan signal to the plurality of subpixels, And a pad region formed on one side of the bezel region and having a plurality of pads connected to respective data lines of the active region; And
And a driver integrated circuit providing the data voltage to the plurality of data lines and having a pad portion coupled to each pad of the pad region,
Wherein at least a part of each of the pads of the pad region has a conductive layer formed on a side opposite to a side contacting the pad portion at a predetermined distance from the pad. The method according to claim 1,
The conductive layer is formed on the pad connected to the data line having a relatively large load, or the pad is connected to the data line having a relatively small load, and the conductive layer is relatively large And a display unit. film; And
A plurality of signal lines arranged alternately so as to form a double layer for bonding with the film are formed, and the intervals between the signal lines forming the same layer are different from each other according to the positions of the signal lines. Chip integrated circuit. The method of claim 3,
The first signal line and the second signal line are connected to a data line for supplying a data voltage to the display panel, and the first signal line and the second signal line are connected to a data line for supplying a data voltage to the display panel, And the interval between the first signal lines and the interval between the second signal lines increases as the load of the data line increases. A display panel including a plurality of subpixels arranged in a matrix and having an active region in which a plurality of data lines and a plurality of gate lines are arranged to provide a data voltage and a scan signal to the plurality of subpixels; And
A plurality of signal lines arranged alternately so as to form a double layer for coupling the film and the film, and a plurality of signal lines forming the same layer, And a driver integrated circuit having driver IC chips different from each other in accordance with positions of the signal lines. 6. The method of claim 5,
The signal lines arranged in the upper layer and the lower layer, respectively, of the double layer are referred to as a first signal line and a second signal line. As the load of the data line connected to the first signal line and the second line line increases, And the interval between the second signal lines is widened.

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