KR20180058610A - Etchant compositions and methods of manufacturing integrated circuit device using the same - Google Patents

Abstract

An etching composition comprises an inorganic acid, a siloxane compound, an ammonium compound, and a solvent, wherein the siloxane compound is represented by general formula (I). To manufacture an integrated circuit device, a structure having a surface on which an oxide film and a nitride film are exposed on a substrate is formed, and the etching composition of general formula (I) is applied to be in contact to the structure to selectively remove the nitride film among the oxide film and the nitride film.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an etchant composition and an integrated circuit device using the same,

TECHNICAL FIELD The present invention relates to an etching composition and a method for manufacturing an integrated circuit device using the same. More particularly, the present invention relates to an etching composition for etching a nitride film and a method for manufacturing an integrated circuit device using the same.

BACKGROUND ART [0002] In recent years, there has been a demand for a large capacity and high integration of integrated circuit devices including memory devices in accordance with the multifunctionality of information communication devices. With the reduction of the memory cell size for high integration, the operation circuits and the wiring structure included in the memory element for the operation and the electrical connection of the memory element are becoming complicated. In the manufacturing process of a highly down-scaled integrated circuit device, oxide films and nitride films, which are typical insulating films, can be used alone or alternately stacked, and complex and finely-structured structures, for example, three-dimensional structures A selective etching process of a nitride film having various shapes of patterns may be required to construct an electronic device. In particular, there is a need for an etching composition capable of securing a sufficient etch selectivity of a nitride film relative to an oxide film without causing problems such as unnecessary generation of particles during the etching process of the nitride film or undesirable growth of by-products on the oxide film surface.

The technical problem to be solved by the technical idea of the present invention is to secure a sufficient etch selectivity of the nitride film relative to the oxide film without causing problems such as generation of unnecessary particles or undesirable growth of by-products on the surface of the oxide film during the etching process of the nitride film To provide an etch composition.

Another technical problem to be solved by the technical idea of the present invention is that unnecessary particles are generated during the etching of nitride films having various shapes to realize an electronic device having complicated and miniaturized structure or undesirable growth of byproducts on the surface of the oxide film, A method of manufacturing an integrated circuit device capable of securing a sufficient etch selectivity ratio of a nitride film to an oxide film without causing the same problems and securing the stability and reliability of a nitride film etching process and improving the productivity of an integrated circuit device manufacturing process .

An etching composition according to an embodiment of the present invention includes inorganic acid, siloxane compound, ammonium compound, and solvent, and the siloxane compound is represented by the following formula (I).

The compound of formula (I)

In the general formula (I)

m is an integer of 0 to 5,

^{R 1, R 2, R 3} , R 4, R 5, R 6, R 7, and R ⁸ are each independently a hydrogen atom, an alkyl group of C1-C20, C2-C20 alkenyl group, an alkynyl group of C2-C20 , A hydroxyalkyl group of C1-C20, an aminoalkyl group of C1-C20, a C1-C20 alkoxy group, a C1-C20 aminoalkoxy group, a phosphate group, a sulfate group, a nitrile group, a carboxyl group, Lt; / RTI >

In general formula (II)

In the general formula (II)

n is an integer of 0 to 5,

R ⁹ , R ¹⁰ and R ¹¹ are each independently a hydrogen atom, a C 1 -C 20 alkyl group, a C 2 -C 20 alkenyl group, a C 2 -C 20 alkynyl group, a C 1 -C 20 hydroxyalkyl group, a C 1 -C 20 aminoalkyl group , A C1-C20 alkoxy group, a C1-C20 aminoalkoxy group, a phosphate group, a sulfate group, a nitrile group, or a carboxyl group.

In the method of manufacturing an integrated circuit device according to an aspect of the present invention, a structure having a surface on which an oxide film and a nitride film are exposed is formed on a substrate. The etching composition according to the technical idea of the present invention is brought into contact with the structure to selectively remove the nitride film among the oxide film and the nitride film.

In the method of manufacturing an integrated circuit device according to another aspect of the present invention, a plurality of oxide films and a plurality of nitride films are alternately stacked a plurality of times on a substrate. A cut region having inner sidewalls through which the plurality of oxide films and the plurality of nitride films are exposed is formed by removing a part of each of the plurality of oxide films and the plurality of nitride films. The etching composition according to the technical idea of the present invention is brought into contact with the structure to selectively remove the plurality of nitride films among the plurality of oxide films and the plurality of nitride films through the cut region.

Even when the nitride film and the oxide film are alternately laminated or mixed when the nitride film is etched using the etching composition according to the technical idea of the present invention, the etch selectivity ratio between the nitride film and the oxide film is relatively high, about 200: 1 to about 600: Only the nitride film can be selectively etched with the etching selectivity. Therefore, in order to construct an electronic device having a complicated and miniaturized structure, there is a problem that unnecessary particles are not generated during the etching of the nitride film having various patterns, or undesired abnormal growth is not caused on the surface of the oxide film, It is possible to secure the stability and reliability of the nitride film etching process by ensuring a sufficient etching selection ratio and to improve the productivity of the integrated circuit device manufacturing process by preventing damage to the oxide film exposed to the etching composition or degradation of the electrical characteristics of the oxide film together with the nitride film And the reliability of the integrated circuit device can be improved.

1 is a flowchart illustrating a method of manufacturing an integrated circuit device according to embodiments of the present invention.
FIG. 2 is a flowchart illustrating a method of manufacturing an integrated circuit device according to another embodiment of the present invention. Referring to FIG.
3 is a flowchart illustrating a method of manufacturing an integrated circuit device according to still another embodiment of the present invention.
4A is a plan view of the major components of an exemplary integrated circuit device that can be implemented by the method of manufacturing an integrated circuit device according to embodiments of the present invention; Fig. 4B is a cross- FIG. 4C is a schematic vertical cross-sectional view taken along the line C-C 'in FIG. 4A. FIG.
5 is a cross-sectional view illustrating an exemplary structure of a gate dielectric film in an exemplary integrated circuit device that can be implemented by a method of manufacturing an integrated circuit device according to embodiments of the present invention.
6A to 6F are cross-sectional views illustrating a method of fabricating an integrated circuit device according to embodiments of the present invention.
7A and 7B are graphs showing the influence of the Si concentration in the etching composition on the etching selectivity of the nitride film to the oxide film in etching the nitride film using the etching composition according to the technical idea of the present invention These are the pictures that show the result.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings, and a duplicate description thereof will be omitted.

The term "C1-C20 alkyl group" as used herein refers to a straight chain or branched noncyclic saturated aliphatic hydrocarbon group having 1 to 20 carbon atoms. The term "C2-C20 alkenyl group" refers to a straight or branched non-cyclic unsaturated aliphatic hydrocarbon group having 2 to 20 carbon atoms and having at least one double bond between adjacent carbon atoms. The term "C2-C20 alkynyl group" refers to a straight chain or branched non-cyclic unsaturated aliphatic hydrocarbon group having 2 to 20 carbon atoms and having at least one triple bond between adjacent carbon atoms. The term "C1-C20 alkoxy group" refers to a straight or branched noncyclic saturated or unsaturated aliphatic hydrocarbon group having at least one ether group and from 1 to 20 carbon atoms.

The etching composition according to embodiments of the present invention includes inorganic acid, a siloxane compound, an ammonium compound, and a solvent.

The inorganic acid may be sulfuric acid, nitric acid, phosphoric acid, silicic acid, hydrofluoric acid, boric acid, hydrochloric acid, perchloric acid, or a combination thereof.

The siloxane compound may be represented by the following general formula (I).

The compound of formula (I)

In the general formula (I)

m is an integer of 0 to 5,

^{R 1, R 2, R 3} , R 4, R 5, R 6, R 7, and R ⁸ are each independently a hydrogen atom, an alkyl group of C1-C20, C2-C20 alkenyl group, an alkynyl group of C2-C20 , A hydroxyalkyl group of C1-C20, an aminoalkyl group of C1-C20, a C1-C20 alkoxy group, a C1-C20 aminoalkoxy group, a phosphate group, a sulfate group, a nitrile group, a carboxyl group, Lt; / RTI >

In general formula (II)

In the general formula (II)

n is an integer of 0 to 5,

R ⁹ , R ¹⁰ and R ¹¹ are each independently a hydrogen atom, a C 1 -C 20 alkyl group, a C 2 -C 20 alkenyl group, a C 2 -C 20 alkynyl group, a C 1 -C 20 hydroxyalkyl group, a C 1 -C 20 aminoalkyl group , A C1-C20 alkoxy group, a C1-C20 aminoalkoxy group, a phosphate group, a sulfate group, a nitrile group, or a carboxyl group.

In some embodiments, at least one of R ¹ , R ² , R ³ , R ⁴ , R ⁵ , R ⁶ , R ⁷ , and R ⁸ is represented by general formula (II) Lt; / RTI > For example, the siloxane compound of the general formula (I) may be represented by any one of the general formulas (III), (IV) and (V), but the technical idea of the present invention is not limited thereto no.

In the formula (III)

In general formula (IV)

In general formula (V)

In the general formulas (III), (IV) and (V), A is a substituent represented by the general formula (II).

In some embodiments, as the siloxane compound, compounds represented by the following formulas (1) to (5) can be used, but these are merely examples, and the technical idea of the present invention is not limited thereto.

(1)

(dimethoxy-propan-2-yl-trimethylsilyloxysilane; CAS No. 141192-68-9)

(2)

(dimethoxysilyl trimethyl silicate; CAS No. 139485-19-1)

(3)

(3 - [[3-aminopropyl (dimethyl) silyl] oxy-dimethylsilyl] propan-1-amine CAS No. 2469-55-8)

(4)

(1,5-Trisiloxanediol, 1,1,3,3,5,5-hexamethyl-, diacetate; CAS No. 5314-59-0)

(5)

(Triacetoxyl-trimethyl-disiloxane)

The compound of formula (5) is prepared by reacting dichloro - [chloro (dimethyl) silyl] oxy-methylsilane (CAS No. 4617-28-1) with acetic acid Can be obtained by reacting at room temperature according to reaction formula (1).

Reaction formula (1)

In the etching composition according to embodiments of the present invention, the ammonium compound may be at least one selected from the group consisting of ammonium hydroxide, ammonium chloride, ammonium acetate, ammonium phosphate, Ammonium persulfate, ammonium peroxydisulfate, ammonium sulfate, ammonium hydrofluoric acid salt, ammonia, or combinations thereof.

In the etching composition according to embodiments of the present invention, the solvent may be DIW (deionized water).

In the etching composition according to embodiments of the present invention, the inorganic acid may serve as an etchant for etching the nitride film. In some embodiments, phosphoric acid may be used as the inorganic acid. Phosphoric acid may serve to accelerate the etching of the nitride film by providing hydrogen ions in the etching composition. In some other embodiments, a combination of phosphoric acid and sulfuric acid may be used as the inorganic acid. Sulfuric acid may serve to promote nitridation etching by raising the boiling point of the etching composition containing phosphoric acid. The inorganic acid may be included in an amount of about 70 to 99 wt% based on the total amount of the etching composition. For example, the inorganic acid may be included in an amount of about 75% to 85% by weight based on the total amount of the etching composition. When the inorganic acid is contained in an excessively small amount in the etching composition, etching of the nitride film may not be easily performed, and there is a risk of generation of particles. When the inorganic acid is contained in an excessively large amount, It may be difficult to secure etching selectivity.

In the etching composition according to the technical idea of the present invention, the siloxane compound may improve the etch selectivity of the nitride film to the oxide film. The siloxane compound may be included in an amount of about 0.01 to 15% by weight based on the total amount of the etching composition. In one example, the siloxane compound may be included in an amount of about 0.5-15 wt% based on the total amount of the etching composition. In another example, the siloxane compound may be included in an amount of about 1 to 15% by weight based on the total amount of the etching composition. In another example, the siloxane compound may be included in an amount of about 3 to 7 wt% based on the total amount of the etching composition. If the content of the siloxane compound in the etching composition is too low, it may be difficult to ensure a high etch selectivity of the nitride film to the oxide film. If the content of the siloxane compound is too large, The pyrolysis effect can be reduced.

In the etching composition according to the technical idea of the present invention, the ammonium compound may play a role of keeping the etching rate of the nitride film constant when the nitride film is etched using the etching composition. The inclusion of the ammonium compound in the etching composition can prevent the etching rate from being lowered or the etch selectivity from being changed even when the etching composition is used for a long time. The ammonium-based compound may be included in an amount of about 0.01 to 20% by weight based on the total amount of the etching composition. If the content of the ammonium compound is too small, the effect of keeping the etching selectivity of the nitride film constant when the etching composition is used for a long period of time can be reduced. If the content of the ammonium compound is too large, the etching rate of the nitride film and the oxide film is changed, The selection ratio can be changed.

In some embodiments, the ammonium-based compound may comprise a compound having an ammonium ion. For example, the ammonium-based compound may include ammonia. In this case, the etching composition may include phosphoric acid and hydrochloric acid as inorganic acids.

In the etching composition according to embodiments of the present invention, when the inorganic acid includes phosphoric acid, phosphoric acid reacts with silicon nitride to etch the nitride when the silicon nitride film is etched using the etching composition . Silicon nitride can react with phosphoric acid to form silicic acid. Silicic acid may be adsorbed on the surface of the oxide film exposed to the etching composition together with the silicon nitride film when the silicon nitride film is etched to cause an abnormal growth phenomenon in which the thickness of the oxide film is increased. In particular, the concentration of silicic acid in the etching composition can be increased if the nitriding process is repeatedly carried out in the etching composition. As the concentration of silicic acid in the etching composition increases, the possibility of an abnormal growth phenomenon in which the thickness of the oxide film increases may increase. The etching composition according to embodiments of the present invention includes an ammonium-based compound. The etching composition may contain ammonium ions obtained from ammonium-based compounds. In the etching composition, ammonium ions are combined with silicic acid to form a water-soluble compound, thereby preventing abnormal growth phenomenon in which the thickness of the oxide film is increased. As described above, the etching composition according to the technical idea of the present invention is an ammonium compound which provides ammonium ions capable of converting silicate, which may cause abnormal growth when nitrides are etched using phosphoric acid, It is possible to prevent the abnormal growth phenomenon in which the thickness of the oxide film is increased due to the reaction byproduct while increasing the etch selectivity of the nitride film to the oxide film.

In some embodiments, the content of the siloxane compound in the etching composition may be equal to or greater than the content of the ammonium compound. In some other embodiments, the content of the siloxane compound in the etching composition may be less than the content of the ammonium compound.

The etching composition according to embodiments of the present invention may further include an amine compound. The amine compound may be selected from the group consisting of methylamine, ethylamine, propylamine, isopropylamine, 2-aminopentane, dimethylamine, methylethanolamine, trimethylamine, triphenylamine or combinations thereof. Similar to the ammonium compound, the amine compound can suppress the abnormal growth phenomenon on the surface of the oxide film exposed to the etching composition together with the nitride film when the nitride film is etched.

In some embodiments, the amine based compound may be included in an amount of about 0.1 to 10 wt% based on the total amount of the etching composition. When the content of the amine compound is too low, it is difficult to control the abnormal growth phenomenon on the surface of the oxide film exposed to the etching composition together with the nitride film in the nitride film etching. If the content is too large, The ratio may be lowered.

In the case where the etching composition further comprises an amine compound, the content of the siloxane compound in the etching composition may be smaller than the sum of the content of the ammonium compound and the content of the amine compound. However, But is not limited thereto.

The etching composition according to embodiments of the present invention may further include a fluorine-based compound. The fluorine-based compound may be composed of hydrogen fluoride, ammonium fluoride, ammonium hydrogen fluoride, or a combination thereof. The fluorine-based compound may serve to increase the etching rate of the nitride film.

In some embodiments, the fluorine-based compound may be included in an amount of about 0.01 to 1 wt% based on the total amount of the etching composition. If the content of the fluorine-based compound is too small, the etching rate of the nitride film becomes small to easily remove the nitride film. If the content of the fluorine compound is too large, the etching rate of the nitride film is greatly improved. Etching problems may occur.

The etching composition according to embodiments of the present invention may further include at least one of a surfactant, a sequestering agent, and a metal corrosion inhibitor.

The surfactant may serve to remove the etch residue during the etching of the nitride film using the etching composition. The surfactant may be an anionic surfactant, a cationic surfactant, a nonionic surfactant, or a combination thereof. For example, cetyltrimethylammonium chloride (CTAC), dodecyltrimethylammonium chloride (DTAC), monoethanolamine lauryl sulfate (MLS), and dodecylbenzenesulfonic acid (DBSA) may be used as the surfactant. However, the technical idea of the present invention is limited to the above- It is not.

The metal ion sequestering agent and the metal corrosion inhibitor may protect the metal film exposed to the etching composition together with the nitride film while etching the nitride film using the etching composition. In some embodiments, ethylenediamine tetraacetic acid (EDTA) may be used as the metal ion sequestrant, and triazoles, imidazoles, thiol compounds, and the like may be used as the metal corrosion inhibitor. However, It is not limited to a bar.

1 is a flowchart illustrating a method of manufacturing an integrated circuit device according to embodiments of the present invention.

Referring to FIG. 1, a substrate is prepared in step P12.

In some embodiments, the substrate may have a configuration as described below with respect to substrate 102 with reference to FIG. 4A.

In Step P14 of Fig. 1, a structure having a surface on which an oxide film and a nitride film are exposed is formed on a substrate.

The oxide film may be a silicon oxide film. In some embodiments, the oxide layer is formed of a material selected from the group consisting of spin on dielectric (SOD) oxide, high density plasma (HDP) oxide, thermal oxide, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), polysilazane , Fluorinated silicate glass (FSG), low pressure tetraethylorthosilicate (LP-TEOS), plasma enhanced tetraethylorthosilicate (PE-TEOS), high temperature oxide (HTO), medium temperature oxide (MTO), undoped silicate glass on glass, atomic layer deposition (ALD) oxide, plasma enhanced oxide, O ₃ -TEOS, or a combination thereof.

The nitride layer may be formed of Si ₃ N ₄ , SiON, SiCN, SiOCN, or a combination thereof.

In Step P16 of Fig. 1, an etching composition comprising an inorganic acid, a siloxane compound represented by the general formula (I), an ammonium compound, and a solvent is brought into contact with the structure formed in the step P14, The nitride film is selectively removed.

The etching composition may be composed of an etching composition having various compositions and contents according to embodiments of the present invention as described above.

The etching composition may simultaneously contact the oxide film and the nitride film to selectively remove the nitride film. In some embodiments, in order to contact the etching composition with the structure, the substrate on which the structure is formed may be dipped into the etching composition. In some other embodiments, the etching composition may be applied by spray or spin coating method on the substrate on which the structure is formed, in order to contact the etching composition with the structure.

During the selective removal of the nitride film in the process P16, the etching composition can maintain a temperature of about 50 to 300 deg. For example, the etching composition may contact the structure at a temperature of about 100 to 200 ° C to selectively remove the nitride film. However, the technical idea of the present invention is not limited to the above-described temperature range, but may be changed as necessary in consideration of other process conditions accompanying the nitride film etching process.

According to the method of manufacturing an integrated circuit device according to the technical idea of the present invention, when a nitride film and an oxide film are alternately stacked or mixed on a substrate, the nitride film and the oxide film are formed using the etching composition according to the technical idea of the present invention. It is possible to selectively etch only the nitride film with a relatively high etch selectivity ratio of the etch selectivity to the oxide film of about 200: 1 to about 600: 1. Further, it is possible to secure the stability and reliability of the nitride film etching process by preventing unnecessary generation of particles or undesirable growth of by-products on the surface of the oxide film exposed to the etching composition during the etching of the nitride film using the etching composition And it is possible to improve the productivity of the integrated circuit device manufacturing process and improve the reliability of the integrated circuit device by preventing damage to the oxide film exposed to the etching composition or deterioration of the electrical characteristics of the oxide film together with the nitride film.

FIG. 2 is a flowchart illustrating a method of manufacturing an integrated circuit device according to another embodiment of the present invention. Referring to FIG.

In Step P22 of FIG. 2, a structure is formed in which a plurality of oxide films and a plurality of nitride films are alternately stacked one by one on a substrate.

In some embodiments, the substrate may have a configuration as described below with respect to substrate 102 with reference to FIG. 4A.

In some embodiments, the structure may include at least 24 pairs of oxide and nitride film pairs. For example, the structure may be formed to include various pairs of oxide films and nitride films as needed, such as 24 pairs, 32 pairs, 48 pairs, 64 pairs, and the like. In some embodiments, the plurality of oxide films are formed of a silicon oxide film, and the plurality of nitride films may be formed of a silicon nitride film, but the technical idea of the present invention is not limited thereto.

In the structure, the plurality of oxide films and the plurality of nitride films may each be stacked so as to extend in parallel to the extending direction of the main surface of the substrate. More detailed structures of the plurality of oxide films and the plurality of nitride films will be described with reference to the oxide film and the nitride film in step P14, respectively, with reference to Fig.

In Step P24, a part of each of the plurality of oxide films and the plurality of nitride films is removed to form a cut region having inner sidewalls through which the plurality of oxide films and the plurality of nitride films are exposed.

The cut region may be formed to extend in a line shape along a plane perpendicular to the main surface of the substrate. The cut region may be formed so as to pass through at least 24 pairs of the oxide film and the nitride film pair constituting the structure.

In Step P26, an etching composition comprising an inorganic acid, a siloxane compound represented by the general formula (I), an ammonium compound, and a solvent is brought into contact with a structure in which the cut region is formed, and the plurality of oxide films and / The plurality of nitride films among the plurality of nitride films are selectively removed.

The etching composition may be composed of an etching composition having various compositions and contents according to embodiments of the present invention as described above.

The etching composition may simultaneously contact the plurality of oxide films and the plurality of nitride films through the cut region to selectively remove the plurality of nitride films. In some embodiments, in order to contact the etch composition with the structure, the substrate on which the structure is formed is dipped into the etch composition, or the etch composition is applied by spray or spin coating on the substrate on which the structure is formed .

In step P26, the etching composition can maintain a temperature of about 50 to 300 DEG C during the selective removal of the plurality of nitride films.

3 is a flowchart illustrating a method of manufacturing an integrated circuit device according to still another embodiment of the present invention.

3, a structure in which a plurality of oxide films and a plurality of nitride films are alternately stacked one by one is formed on the substrate in the same manner as in the process 22 of Fig.

In Step P33, a gate dielectric film that penetrates the plurality of oxide films and the plurality of nitride films in the structure formed in Step P32 and a channel region surrounded by the gate dielectric film are formed.

The gate dielectric layer may include an oxide layer. For example, the gate dielectric layer may include a silicon oxide layer, a hafnium oxide layer, an aluminum oxide layer, a zirconium oxide layer, a tantalum oxide layer, or a combination thereof.

In Step P34, a portion of each of the plurality of oxide films and the plurality of nitride films is removed in the same manner as in the process P24 of FIG. 2 to form a cut region having inner sidewalls through which the plurality of oxide films and the plurality of nitride films are exposed.

In Step P36, an etching composition comprising a mineral acid, a siloxane compound represented by the general formula (I), an ammonium compound, and a solvent is contacted with the structure in which the cut region is formed in a similar manner to Step P26 in Fig. 2 And selectively removing the plurality of nitride films among the plurality of oxide films and the plurality of nitride films through the cut region. However, in step P36, the plurality of nitride films are selectively removed to expose the gate dielectric film between the plurality of oxide films. The portion of the gate dielectric layer exposed between the plurality of oxide layers may be an oxide layer. For example, a portion of the gate dielectric layer exposed between each of the plurality of oxide films may include a silicon oxide film, a hafnium oxide film, an aluminum oxide film, a zirconium oxide film, a tantalum oxide film, or a combination thereof.

As the VNAND element is highly scaled, the height of the vertical channels increases while the spacing of the vertical channels becomes narrower. According to this trend, a process of selectively removing only a plurality of nitride films from a structure including a plurality of oxide films and a plurality of nitride film pairs having a finer size and a further increased number of stages through a gradually narrower and deeper cut region . According to the method for fabricating an integrated circuit device according to embodiments of the present invention described with reference to FIGS. 2 and 3, in a process for manufacturing a memory device having a three-dimensional vertical structure such as a VNAND device, It is possible to selectively etch only a plurality of nitride films through a narrow and deep cut region from a structure in which a nitride film and a plurality of oxide films are alternately stacked a plurality of times one layer at a time and the etching selectivity ratio of a plurality of nitride films to a plurality of oxide films is about 200: A relatively high etch selectivity of about 600: 1 can be provided. In addition, during the etching of a plurality of nitride films by using the etching composition, occurrence of unnecessary particles or undesirable growth of by-products on the surface of a plurality of oxide films is prevented, thereby ensuring stability and reliability of a plurality of nitride film etching processes And it is possible to prevent damage to a plurality of oxide films exposed to the etching composition together with a plurality of nitride films or deterioration of electrical characteristics of the oxide film. In addition, the amount of by-products remaining in the etching composition after etching the plurality of nitride films using the etching composition can be minimized. Therefore, the nitride film etching process can be performed on a larger number of substrates by using a predetermined amount of the etching composition prepared one time, so that the manufacturing cost of the integrated circuit device can be reduced and the productivity can be improved.

4A to 4C are diagrams for explaining an exemplary integrated circuit device that can be implemented by a method of manufacturing an integrated circuit device according to embodiments of the present invention, 4B is a schematic perspective view of the main components of the area indicated by "B" in FIG. 4A, and FIG. 4C is a schematic vertical section along line C-C ' to be.

4A to 4C, an integrated circuit device 100 includes a memory cell array region MC formed on a substrate 102. The memory cell array region MC includes a plurality of memory cell array regions MC.

The substrate 102 may have a main surface 102M extending in the X and Y directions. The substrate 102 may comprise Si, Ge, or SiGe. In some other embodiments, the substrate 102 may comprise a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GeOI) substrate.

The memory cell array region MC of the integrated circuit device 100 includes a plurality of memory cell arrays MCA.

In the memory cell array area MC, a plurality of word lines WL1, WL2, ..., WLn-1, WLn extend parallel to the main surface 102M extension direction of the substrate 102 on the substrate 102 (Z direction) perpendicular to the main surface 102M of the substrate 102, and overlap each other. A plurality of word lines WL1, WL2, ..., WLn-1 and WLn are arranged in a first direction (X direction in FIGS. 4A to 4C) parallel to the extending direction of the main surface 102M of the substrate 102 And are arranged repeatedly spaced apart from each other at regular intervals by the word line cut area WLC. The plurality of word line cut areas WLC define the widths of the plurality of word lines WL1, WL2, ..., WLn-1, WLn along the first direction, (The Y direction in Figs. 4A to 4C) perpendicular to the first direction along a plane (YZ plane) perpendicular to the first direction.

A plurality of common source regions 172 may extend along the extending direction of the word line cut region WLC (Y direction in FIGS. 4A to 4C). In some embodiments, the plurality of common source regions 172 may be heavily doped impurity regions of the n-type impurity. A plurality of common source regions 172 may be used as source regions for supplying current to vertical memory cells. A plurality of common source lines CSL may extend along the extending direction of the word line cut region WLC (Y direction in Figs. 4A to 4C) above the common source region 172. [ The plurality of common source lines CSL are connected to one side of the pair of ground selection lines GSL, the word lines WL1, WL2, ..., WLn-1, WLn, The word line cut region WLC may be formed to fill a portion of the word line cut region WLC.

At least one ground selection line GSL, a plurality of word lines WL1, WL2, ..., WLn-1, WLn, and at least one string selection line GSL are provided between two neighboring word line cut areas WLC. (SSL) may be stacked in this order. At least one string selection line GSL and a plurality of word lines WL1 to WLn and at least one string selection line SSL may be doped with a metal, , Or a combination thereof. For example, at least one ground select line GSL, a plurality of word lines WL1, WL2, ..., WLn-1, WLn, and at least one string select line SSL may be tungsten, nickel, Metal such as cobalt, tantalum and the like, metal silicide such as tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide and the like, polysilicon doped with impurities, or a combination thereof.

At least one ground selection line GSL, a plurality of word lines WL1, WL2, ..., WLn-1, WLn, and at least one ground selection line GSL between the substrate 102 and the at least one ground selection line GSL. An oxide film 176 is interposed between each of the string selection lines SSL. The oxide film 176 may be formed of a silicon oxide film.

In the memory cell array MCA, a plurality of channel regions 180 (see FIG. 4C) are formed by at least one ground selection line GSL, a plurality of word lines WL1, WL2, ..., WLn- And may extend in a direction (Z direction) perpendicular to the main surface 102M of the substrate 102 through at least one string selection line SSL and a plurality of oxide films 176. [ The plurality of channel regions 180 may be spaced apart from each other by a predetermined distance along the X and Y directions. The arrangement of the plurality of channel regions 180 illustrated in FIG. 4C is merely an example, and the arrangement of the plurality of channel regions 180 may be variously modified and changed. The plurality of channel regions 180 may be connected to corresponding bit lines BL of the plurality of bit lines BL, respectively. The plurality of channel regions 180 may be repeatedly formed at a constant pitch. The plurality of channel regions 180 may comprise doped polysilicon, undoped polysilicon, metal, conductive metal nitride, silicide, carbon nanotubes, graphene, or combinations thereof. The plurality of channel regions 180 may each have a cylindrical shape. In some embodiments, the inner space of each of the plurality of channel regions 180 may be filled with a buried insulating film 182. In some other embodiments, the plurality of channel regions 180 may have a pillar structure, as illustrated in Figures 4C and 4C, in which case the buried insulating film 182 may be omitted.

A gate dielectric layer is formed between each of the plurality of channel regions 180, the ground selection line GSL, the plurality of word lines WL1, WL2, ..., WLn-1, WLn and the string selection line SSL, (184) may be interposed.

5 is an enlarged cross-sectional view of a partial area 5A of FIG. 4C.

5, the gate dielectric layer 184 includes a tunnel insulating layer 184A, a charge storage layer 184B, and a blocking insulating layer 184C that are sequentially stacked from the channel region 180 toward the word line WL can do. The tunnel insulating film 184A may include a silicon oxide film, a hafnium oxide film, an aluminum oxide film, a zirconium oxide film, a tantalum oxide film, or a combination thereof. The charge storage film 184B is a region where electrons tunneled through the tunnel insulating film 184A from the plurality of channel regions 180 can be stored. The silicon nitride film, the boron nitride film, the silicon boron nitride film, the polysilicon film doped with the impurity, Or a combination thereof. The blocking insulating film 184C may include a silicon oxide film, a hafnium oxide film, an aluminum oxide film, a zirconium oxide film, a tantalum oxide film, or a combination thereof. In some embodiments, the blocking insulating film 184C may be made of a high dielectric constant film having a higher dielectric constant than the silicon oxide film.

4C and FIG. 5 illustrate the case where the gate dielectric layer 184 has a shape extending along the outer sidewall of the channel region 180, but the technical idea of the present invention is not limited thereto. For example, at least some of the blocking insulating film 184C, the charge storage film 184B, and the tunnel insulating film 184A constituting the gate dielectric film 184 are formed on the surface of the word line WL facing the channel region 180 The top surface, and the sidewalls of the word line WL to cover the surfaces facing the oxide layer 176 and the surfaces facing the oxide layer 176.

Referring again to FIGS. 4A to 4C, an insulating spacer 192 covering the sidewalls of the common source line CSL may be formed in the word line cut area WLC. The insulating spacer 192 is connected between the ground select line GSL and the plurality of word lines WL1 to WLn and between the string select line SSL and the common source line CSL. Thereby electrically isolating the semiconductor device. The common source line (CSL) may be a metal such as tungsten, copper, or aluminum; Conductive metal nitrides such as titanium nitride, tantalum nitride, and the like; Transition metals such as titanium, tantalum and the like; Or a combination thereof. The insulating spacers 192 may be made of silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric material. The word line cut region buried insulating film 194 may be formed on the common source line CSL in the word line cut region WLC.

A plurality of bit line contact pads 186 may be formed on the plurality of channel regions 180. The plurality of bit line contact pads 186 may be comprised of impurity doped polysilicon, metal, conductive metal nitride, or combinations thereof. A plurality of bit lines BL may be formed on the plurality of bit line contact pads 186. In some embodiments, as illustrated in Figure 4C, a plurality of bit lines (BL) may directly contact the top surface of a plurality of bit line contact pads 186. 4C, a plurality of bit lines BL may be connected to a plurality of bit line contact pads 186 via contact plugs (not shown). The plurality of bit lines BL may extend in a direction parallel to the main surface 102M of the substrate 102 (X direction). The plurality of bit lines BL may be made of polysilicon doped with an impurity, a metal, a conductive metal nitride, or a combination thereof.

An insulating film is formed between the laminated structure including the ground selection line GSL, the plurality of word lines WL1, WL2, ..., WLn-1 and WLn and the string selection line SSL, (185) may be formed. The bit line BL may be covered with an upper insulating layer 196.

6A to 6F are cross-sectional views illustrating a method of fabricating an integrated circuit device according to embodiments of the present invention. In this example, a manufacturing method of the integrated circuit device 100 illustrated in FIGS. 4A to 4C will be described as an example. 6A to 6F schematically show major structures in regions corresponding to the cross section taken along the line C-C 'of FIG. 4A according to the manufacturing process of the integrated circuit device 100. FIG. 6A to 6F, the same reference numerals as in Figs. 4A to 4C denote the same members, and a detailed description thereof will be omitted here.

6A, an element isolation film (not shown) for defining an active region AC is formed on a substrate 102, a plurality of oxide films 176 and a plurality of nitride films 178 (not shown) are formed on the substrate 102, ) Are alternately stacked a plurality of times to form a structure. In FIG. 6A, nine pairs of oxide films 176 and 178 adjacent to each other in the structure are illustrated. However, the oxide films 176 and the nitride films 178 adjacent to each other in FIG. 178) pairs can be formed in various numbers according to need, such as 24 pairs, 32 pairs, 48 pairs, 64 pairs. The plurality of oxide films 176 may be formed of a silicon oxide film. The plurality of nitride films 178 may be made of silicon nitride, silicon carbide, or polysilicon. A plurality of nitride films 178 are formed on at least one ground select line GSL, a plurality of word lines WL1, WL2, ..., WLn-1, WLn and at least one string select line SSL May be a preliminary film or a sacrificial layer.

6B, a plurality of channel holes 180H extending through a plurality of oxide films 176 and a nitride film 178 and extending in a direction (Z direction) perpendicular to the extending direction of the main surface 102M of the substrate 102 A gate dielectric film 184, a channel region 180, and a buried insulating film 182 are formed in a plurality of channel holes 180H, respectively. The buried insulating film 182 may be surrounded by the channel region 180 and the channel region 180 may be surrounded by the gate dielectric film 184 in the plurality of channel holes 180H.

Thereafter, an insulating film 185 covering the upper surface of each of the channel region 180, the buried insulating film 182 and the gate insulating film 184 is formed and the channel region 180 and the buried insulating film 182 A plurality of bit line contact pads 186 are formed in the plurality of contact holes 185H.

6C, after a plurality of word line cut areas WLC are formed to expose the substrate 102 through a plurality of oxide films 176 and a plurality of nitride films 178, a plurality of word line cut areas (WLC) to form a plurality of common source regions 172. A plurality of oxide films 176 and a plurality of nitride films 178 can be exposed from the inner sidewalls of the plurality of word line cut regions WLC.

Referring to FIG. 6D, a plurality of nitride films 178 are removed through a plurality of word line cut regions WLC to provide a plurality of gate spaces GS arranged one-by-one between a plurality of oxide films 176, respectively. A portion of the gate dielectric layer 184 may be exposed through the plurality of gate spaces GS.

In order to remove the plurality of nitride films 178, etching compositions having various compositions and contents may be used according to the embodiments of the present invention. In some embodiments, to selectively remove the plurality of nitride films 178, the etch composition according to embodiments of the present invention may be applied to a plurality of oxide films 176 through a plurality of wordline cut regions (WLC) And the plurality of nitride films 178 at the same time. In some embodiments, a substrate 102 on which a plurality of oxide films 176 and a plurality of nitride films 178 are formed, may be dipped into the etch composition to contact the etch composition with the structure. During the selective removal of the plurality of nitride films 178, the etch composition may maintain a temperature of about 50 to 300 DEG C, for example, a temperature of about 100 to 200 DEG C.

Only a plurality of nitride films 178 are selectively etched through a plurality of relatively narrow and deep word line cut regions WLC from a structure in which a plurality of oxide films 176 and a plurality of nitride films 178 are alternately stacked on a substrate 102 At this time, the etch selectivity ratio between the plurality of nitride films 178 and the plurality of oxide films 176 can be about 200: 1 to about 600: 1, which can provide a relatively high etch selectivity. It is possible to prevent unnecessary generation of particles or undesirable growth of by-products on the surface of the plurality of oxide films 176 while the plurality of nitride films 178 are etched using the etching composition. Therefore, the plurality of oxide films 176 are not damaged during the removal of the plurality of nitride films 178 using the etching composition. In addition, a part of the gate dielectric layer 184 may be exposed through the plurality of gate spaces GS formed by removing the plurality of nitride films 178. In this case, even when an oxide film, for example, a silicon oxide film or a metal oxide film, constituting the gate dielectric film 184 is exposed through the plurality of gate spaces GS to contact the etching composition, It is possible to cleanly remove the plurality of nitride films 178 without damaging or consuming the exposed portions of the nitride films 178. [

6E, a plurality of ground selection lines GSL, a plurality of word lines WL1, WL2, ..., WLn-1, WLn, and a plurality of string selection lines GS1, SSL) is formed.

6F, an insulating spacer 192, a plurality of common source lines CSL, and a word line cut region buried insulating film 194 are formed in a plurality of word line cut areas WLC, respectively.

A plurality of bit lines BL connected to some channel regions 180 selected from a plurality of channel regions 180 and an upper insulating film 196 covering a plurality of bit lines BL are formed, The integrated circuit device 100 illustrated in Figs. 4A to 4C can be formed.

6A to 6F, according to the method of fabricating an integrated circuit device according to embodiments of the present invention, a three-dimensional vertical memory device such as a VNAND device is highly scaled to form a vertical channel A plurality of oxide films 176 and a plurality of oxide films 176 having a finer size and an increased number of stages through a relatively narrow and deep word line cut region WLC, The plurality of nitride films 178 can be selectively etched only through the narrow and deep word line cut regions WLC even when a plurality of nitride films 178 are selectively removed from a structure including a pair of nitride films 178, And the plurality of oxide films 176 can provide a relatively high etch selectivity ratio of about 200: 1 to about 600: 1. In addition, during the etching of the plurality of nitride films 178 by using the etching composition, unnecessary generation of particles or undesirable growth of by-products on the surface of the plurality of oxide films is prevented, Stability and reliability can be ensured and damage to the oxide films 176 and the gate dielectric film 184 exposed to the etching composition or deterioration of electrical characteristics can be prevented.

≪ Evaluation Example 1 &

The etch selectivity between the nitride film and the oxide film was evaluated using the etching composition having various compositions according to the embodiments of the present invention.

In Table 1, COMPARATIVE EXAMPLE is a case where a nitride film and an oxide film are etched using an etching composition composed only of phosphoric acid (85 wt% aqueous solution), and Examples 1 to 5 (EXAMPLES 1-5) The nitride film and the oxide film are etched by using etching compositions having various compositions according to the embodiments by technological mapping. More specifically, Example 1 uses, in addition to phosphoric acid, an etching composition further comprising 1% by weight of a siloxane compound of formula (1) based on the total amount of the etching composition, and 0.5% by weight of ammonium phosphate And the nitride film and the oxide film are etched. Example 2 is a case where a nitride film and an oxide film are etched using an etching composition further comprising phosphoric acid and further containing 1 wt% of a siloxane compound of the formula (2) and 0.5 wt% of ammonium phosphate based on the total amount of the etching composition. Example 3 is a case where a nitride film and an oxide film are etched using an etching composition further comprising phosphoric acid and further containing 3% by weight of a siloxane compound of the formula (3) and 0.5% by weight of ammonium phosphate based on the total amount of the etching composition. Example 4 is a process for preparing a nitride film and a nitride film using an etching composition further comprising phosphoric acid and further containing 1.5% by weight based on the total amount of the etching composition, the siloxane compound of formula (4), 0.5% by weight ammonium phosphate, and 2% by weight trimethylamine. And the oxide film is etched. Example 5 is an etching process that includes, in addition to phosphoric acid, 2 wt% siloxane compound of formula (5) based on the total amount of etching composition, 0.5 wt% ammonium phosphate, 2 wt% isopropylamine, and 30 ppm DBSA And the nitride film and the oxide film are etched using the composition.

From the results shown in Table 1, it can be seen that the etching composition according to the technical idea of the present invention has a significantly higher etching selectivity ratio of the nitride film to the oxide film than the etching composition containing only the aqueous phosphoric acid solution.

≪ Evaluation Example 2 &

The effect of the Si concentration in the etching composition on the etching selectivity of the nitride film to the oxide film was evaluated in the etching of the nitride film using the etching composition according to the technical idea of the present invention.

To this end, etching compositions having various Si concentrations were prepared by dissolving different amounts of Si ₃ N ₄ film in a plurality of etching compositions for testing made up of the etching composition according to Example 1 of Table 1. Further, a test structure in which a plurality of TEOS films and a plurality of Si ₃ N ₄ films are alternately stacked a plurality of times is formed on a silicon substrate, a cut region penetrating the test structure is formed, A plurality of Si ₃ N ₄ films were selectively removed from the test structures through the cut regions by dipping the test structures having the cut regions in the etch compositions having the concentration of the Si ₃ N ₄ .

FIG. 7A is a photograph showing a result of etching a test structure using an etching composition having a Si concentration of 300 ppm, and FIG. 7B is a photograph showing a result of etching a test structure using an etching composition having a Si concentration of 350 ppm.

7A and 7B, when the Si concentrations in the etching composition were 300 ppm and 350 ppm, the plurality of Si ₃ N ₄ films were cleanly removed from the test structure without causing damage or abnormal growth of the plurality of TEOS films, respectively Respectively.

As can be seen from the results of the evaluation example 2, even if the nitriding film is dissolved in the etching composition and the Si concentration in the etching composition becomes higher than before the nitriding film etching, the byproducts are undesirably grown excessively on the surface of the oxide film, It is possible to etch the nitride film with a high etch selectivity.

Therefore, when the nitride film is etched using the etching composition according to the technical idea of the present invention in the integrated circuit device manufacturing process, a predetermined amount of the etching composition prepared once is used, for example, to contain 50 wafers The nitride film etch process can be performed on a relatively large number of wafers of a plurality of batches, for example, three batches or more, rather than processing only one batch of wafers. As a result, the manufacturing cost of the integrated circuit device can be reduced, and the productivity can be improved.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, This is possible.

A gate dielectric layer, and a gate dielectric layer. GS: Gate space, WLC: Word line cut area.

Claims (20)

The inorganic acid,
Siloxane compounds,
Ammonium compound,
A solvent,
Wherein the siloxane compound is represented by the following formula (I).
The compound of formula (I)

In the general formula (I)
m is an integer of 0 to 5,
^{R 1, R 2, R 3} , R 4, R 5, R 6, R 7, and R ⁸ are each independently a hydrogen atom, an alkyl group of C1-C20, C2-C20 alkenyl group, an alkynyl group of C2-C20 , A hydroxyalkyl group of C1-C20, an aminoalkyl group of C1-C20, a C1-C20 alkoxy group, a C1-C20 aminoalkoxy group, a phosphate group, a sulfate group, a nitrile group, a carboxyl group, Lt; / RTI >
In general formula (II)

In the general formula (II)
n is an integer of 0 to 5,
R ⁹ , R ¹⁰ and R ¹¹ are each independently a hydrogen atom, a C 1 -C 20 alkyl group, a C 2 -C 20 alkenyl group, a C 2 -C 20 alkynyl group, a C 1 -C 20 hydroxyalkyl group, a C 1 -C 20 aminoalkyl group , A C1-C20 alkoxy group, a C1-C20 aminoalkoxy group, a phosphate group, a sulfate group, a nitrile group, or a carboxyl group. The method according to claim 1,
In the general formula (I), at least one of R ¹ , R ² , R ³ , R ⁴ , R ⁵ , R ⁶ , R ⁷ and R ⁸ is a substituent represented by the general formula (II) Lt; / RTI > The method according to claim 1,
Wherein the inorganic acid comprises sulfuric acid, nitric acid, phosphoric acid, silicic acid, hydrofluoric acid, boric acid, hydrochloric acid, perchloric acid, or a combination thereof. The method according to claim 1,
The ammonium-based compound may be at least one selected from the group consisting of ammonium hydroxide, ammonium chloride, ammonium acetate, ammonium phosphate, ammonium peroxydisulfate, ammonium sulfate, An ammonium hydrofluoric acid salt, ammonia, or a combination thereof. The method according to claim 1,
Wherein the ammonium-based compound comprises ammonia,
Wherein the inorganic acid comprises phosphoric acid and hydrochloric acid. The method according to claim 1,
Further comprising an amine-based compound,
Wherein the amine compound is selected from the group consisting of methylamine, ethylamine, propylamine, isopropylamine, 2-aminopentane, dimethylamine, methylethanolamine, trimethylamine, triphenylamine or combinations thereof. The method according to claim 1,
Further comprising a fluorine-based compound,
Wherein the fluorine-based compound is composed of hydrogen fluoride, ammonium fluoride, ammonium hydrogen fluoride, or a combination thereof. The method according to claim 1,
A surfactant, a surfactant, a sequestering agent, and a metal corrosion inhibitor. Forming a structure having a surface on which an oxide film and a nitride film are exposed on a substrate,
And selectively removing the nitride film among the oxide film and the nitride film by bringing the etching composition according to claim 1 into contact with the structure. 10. The method of claim 9,
Wherein the nitride film is made of Si ₃ N ₄ , SiON, SiCN, SiOCN, or a combination thereof. 10. The method of claim 9,
In the general formula (I), at least one of R ¹ , R ² , R ³ , R ⁴ , R ⁵ , R ⁶ , R ⁷ and R ⁸ is a substituent represented by the general formula (II) Of the integrated circuit device. 10. The method of claim 9,
Wherein the etch composition comprises phosphoric acid, hydrochloric acid, and ammonia. 10. The method of claim 9,
Wherein the etching composition further comprises at least one of an amine-based compound and a fluorine-based compound. Forming a structure in which a plurality of oxide films and a plurality of nitride films are alternately stacked a plurality of times on a substrate,
Forming a cut region having inner sidewalls through which the plurality of oxide films and the plurality of nitride films are exposed by removing a part of each of the plurality of oxide films and the plurality of nitride films;
And selectively removing the plurality of nitride films among the plurality of oxide films and the plurality of nitride films through the cut region by bringing the etching composition according to claim 1 into contact with the structure. Way. 15. The method of claim 14,
In the structure, the plurality of oxide films and the plurality of nitride films are each stacked so as to extend in parallel to the extending direction of the main surface of the substrate,
Wherein the cut region is formed to extend along a plane perpendicular to the main surface of the substrate in the step of forming the cut region. 15. The method of claim 14,
Further comprising the step of forming a channel region surrounded by the gate dielectric layer and the gate dielectric layer through the plurality of oxide layers and the plurality of nitride layers before the step of forming the cut region after the step of forming the structure,
And removing the plurality of nitride films so that the gate dielectric film is exposed between each of the plurality of oxide films in the step of selectively removing the plurality of nitride films. 15. The method of claim 14,
In the general formula (I), at least one of R ¹ , R ² , R ³ , R ⁴ , R ⁵ , R ⁶ , R ⁷ and R ⁸ is a substituent represented by the general formula (II) Of the integrated circuit device. 15. The method of claim 14,
Wherein the etching composition comprises an aqueous solution of phosphoric acid, the siloxane compound according to the general formula (I), and the ammonium compound. 19. The method of claim 18,
Wherein the etching composition further comprises a surfactant. 15. The method of claim 14,
Wherein the etch composition comprises phosphoric acid, hydrochloric acid, and ammonia.

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