KR101730453B1 - Etchant compositions for nitride layers and methods of manufacturing semiconductor devices using the same - Google Patents

Abstract

The present invention is to provide an etchant composition for nitride layers having an improved etchant selective ratio, and a method for manufacturing a semiconductor device using the same. The etchant composition for nitride layers comprises phosphoric acid, a silicon-fluorine compound containing a silicon-fluorine bond, an adsorption preventing agent and water.

Description

TECHNICAL FIELD [0001] The present invention relates to a nitride film etching composition, and a method of manufacturing a semiconductor device using the nitride film etching composition. BACKGROUND ART < RTI ID = 0.0 >

The present invention relates to a nitride-based etching composition and a method of manufacturing a semiconductor device using the same. More particularly, the present invention relates to a nitride film etching composition including an acid component and an additive, and a method of manufacturing a semiconductor device using the same.

For example, in manufacturing a semiconductor device, various insulating films such as a silicon oxide film and a silicon nitride film can be laminated. A selective etching process of the silicon nitride film may be required depending on the necessity of forming various patterns included in the semiconductor device.

The silicon nitride film may be removed by, for example, a wet etching process using an etching solution containing phosphoric acid or an etching composition.

Patent Document 1 discloses a nitride film etchant for semiconductor devices including phosphoric acid and hydrofluoric acid. However, when hydrofluoric acid is included in the etching solution, the silicon oxide film is also removed, so that it is difficult to secure a sufficient etch selectivity ratio of the nitride film to the oxide film.

Patent Document 2 discloses a composition for etching a silicon nitride film containing oxime silane in phosphoric acid. However, since the composition has a low solubility in a solvent such as deionized water, it can produce adsorbed residues on a semiconductor substrate or a silicon oxide film .

1. Published Patent Application No. 10-2005-0003163 (Oct. 10, 2005) 2. Open Patent Publication No. 10-2011-0037741 (Apr. 13, 2011)

An object of the present invention is to provide a nitride-based etching composition having an improved etch selectivity.

An object of the present invention is to provide a method of manufacturing a semiconductor device using a nitride film etching composition having an improved etching selectivity.

However, the problems to be solved by the present invention are not limited to the above-mentioned problems, but may be variously expanded without departing from the spirit and scope of the present invention.

In order to accomplish one aspect of the present invention, a nitride-based etching composition according to embodiments of the present invention includes a silicon-fluorine compound containing phosphoric acid, a silicon-fluorine bond (Si-F bond) .

According to exemplary embodiments, the nitridation film etch composition comprises 80 wt% to 90 wt% of the phosphoric acid, 0.02 wt% to 0.1 wt% of the silicon-fluorine compound, 0.001 wt% to 0.05 wt% And extra water.

According to exemplary embodiments, the adsorption inhibitor comprises a compound of the following formula (1).

≪ Formula 1 >

(Wherein R 1 represents Li, Na or an alkyl group having 1 to 3 carbon atoms, R 2, R 3 and R 4 each independently represent F, Cl or an alkyl group having 1 to 10 carbon atoms, and R 5, R 6, Independently represents F, Br or an alkyl group having 1 to 10 carbon atoms.

According to exemplary embodiments, the nitride film etching composition may further include a fluorine-based surfactant.

According to exemplary embodiments, the fluorinated surfactant may comprise ammonium fluoroalkylsulfonate.

According to exemplary embodiments, the silicon-fluorine compound is selected from the group consisting of ammonium hexafluorosilicate (AHFS), ammonium fluorosilicate (AFS), sodium fluorosilicate (SFS), silicon tetra And may include silicon tetrafluoride (STF) and / or hexafluorosilicic acid (HFSA).

According to exemplary embodiments, the silicon-fluorine compound may comprise AHFS.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising the steps of: stacking interlayer insulating films and sacrificial layers alternately and repeatedly on a substrate; A plurality of channels passing through the interlayer insulating films and the sacrificial layers may be formed. The interlayer insulating films and portions of the sacrificial films between adjacent ones of the channels may be etched to form openings. The sacrificial films exposed by the openings can be removed using a nitride-based etchant composition comprising phosphoric acid, a silicon-fluorine compound comprising a silicon-fluorine bond (Si-F bond), an adsorption inhibitor and an excess of water. A gate line may be formed in each of the spaces where the sacrificial layers are removed.

According to exemplary embodiments, the nitride etch composition comprises about 80 wt% to about 90 wt% of the phosphoric acid, about 0.02 wt% to about 0.1 wt% of the silicon-fluorine compound, about 0.001 To about 0.05% by weight of the adsorption inhibitor and the excess water.

According to exemplary embodiments, the interlayer insulating film includes silicon oxide, and the sacrificial layer may include silicon nitride.

According to exemplary embodiments, the silicon-fluorine compound may comprise ammonium hexafluorosilicate (AHFS).

As described above, according to embodiments of the present invention, the nitride film etching composition may include phosphoric acid, a silicon-fluorine compound, and an anti-adsorption agent. The silicon-fluorine compound promotes the etching rate for the nitride film, and the silicon oxide film is prevented from being damaged through the interaction of the anti-adsorption agent, and the re-adsorption of the etching by-products to the etching target structure can be prevented.

Therefore, a high-resolution etching process can be realized without damaging the structure to be etched, for example, while ensuring the etch selectivity ratio of the nitride film to the high oxide film of about 200 or more by using the etching composition.

1 to 15 are a plan view and a cross-sectional view for explaining a manufacturing method of a semiconductor device according to exemplary embodiments.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the drawings of the present invention, the dimensions of the structures are enlarged to illustrate the present invention in order to clarify the present invention.

In the present invention, the terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In the present invention, it is to be understood that each layer (film), region, electrode, pattern or structure may be formed on, over, or under the object, substrate, layer, Means that each layer (film), region, electrode, pattern or structure is directly formed or positioned below a substrate, each layer (film), region, or pattern, , Other regions, other electrodes, other patterns, or other structures may additionally be formed on the object or substrate.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, But should not be construed as limited to the embodiments set forth in the claims.

That is, the present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the following description. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Nitride film etching composition

The nitride etch composition according to exemplary embodiments may comprise phosphoric acid, a silicon-fluorine (Si-F) compound, an adsorption inhibitor, and excess water.

The nitride film etching composition may be supplied on a structure containing an oxide film and a nitride film at the same time so as to etch only the nitride film with a high selectivity ratio without substantially damaging the oxide film. In addition, the adsorption inhibitor can prevent re-adsorption of silicon by-products generated in the etching process.

For example, the nitride film etching composition can be used to selectively etch a silicon nitride film in a manufacturing process of a semiconductor device

Phosphoric acid can be represented, for example, by the formula H ₃ PO ₄ and can act as a major etch component for nitride etch. According to exemplary embodiments, the nitride etch composition may comprise from about 80 wt% to about 90 wt% phosphoric acid, expressed as percent by weight relative to the total weight of the composition.

If the content of phosphoric acid is less than about 80% by weight, the overall etching rate may be lowered. When the content of phosphoric acid exceeds about 90 wt%, the etching rate of the conductive film such as an oxide film or a metal film as well as the nitride film increases together, so that the etching selectivity to the nitride film can be reduced.

The silicon-fluorine compound may include a compound having a Si-F bond in one molecule. As the fluorine atom is bonded to the silicon atom, the solubility in the composition or the phosphoric acid solution can be improved. Further, as fluorine is contained, the etching rate can be improved. In exemplary embodiments, the silicon atom may be bonded to the fluorine atom to block or buffer the etching rate of the oxide layer from being increased by the fluorine component.

Therefore, as the silicon-fluorine compound is included in the nitride-based etching composition, the etching rate of the oxide film can be suppressed and the etching rate of the nitride film can be improved. Accordingly, when performing the wet etching process using the nitride film etching composition, the etching selectivity ratio of the nitride film to the oxide film can be remarkably improved.

According to exemplary embodiments, the nitride etch composition may comprise about 0.02 wt.% To about 0.1 wt.% Of the silicon-fluorine compound relative to the total weight of the composition.

If the content of the silicon-fluorine compound is less than about 0.02% by weight, the overall etching rate may be lowered. If the content of the silicon-fluorine compound exceeds about 0.1 wt%, the etch selectivity to the nitride film may be reduced due to the increase of the fluorine component.

 According to exemplary embodiments, the silicon-fluorine compound is selected from the group consisting of ammonium hexafluorosilicate (AHFS), ammonium fluorosilicate (AFS), sodium fluorosilicate (SFS), silicon tetra And may include silicon tetrafluoride (STF) or hexafluorosilicic acid (HFSA), which may be used alone or in combination of two or more.

In some embodiments, AHFS may be used as the silicon-fluorine compound. AHFS is an ammonium-based compound with six fluorine atoms bonded and can exhibit high etching rates for nitride films compared to other silicon-fluoride compounds.

The anti-adsorption agent may be added to the nitride film etching composition in a small amount to prevent re-adsorption or reverse adsorption of the silicon by-products generated in the etching process into the structure to be etched.

The anti-adsorption agent may be provided, for example, as an antistatic agent. For example, the surface of the structure to be etched or the charge contained in the silicon by-product can be removed or neutralized by the adsorption inhibitor. Thus, it is possible to prevent the silicon by-product from being reabsorbed on the surface of the etch target structure.

According to exemplary embodiments, the adsorption inhibitor may include a compound represented by the following formula (1).

≪ Formula 1 >

(Wherein R 1 represents Li, Na or an alkyl group having 1 to 3 carbon atoms, R 2, R 3 and R 4 each independently represent F, Cl or an alkyl group having 1 to 10 carbon atoms, and R 5, R 6, Independently represents F, Br or an alkyl group having 1 to 10 carbon atoms.

Preferably, in the above formula (1), R1 represents Li, and R2, R3, R4, R5, R6 and R7 each represent F.

According to exemplary embodiments, the nitride etch composition may comprise from about 0.001% to about 0.05% by weight of the adsorption inhibitor based on the total weight of the composition.

If the content of the adsorption inhibitor is less than about 0.001% by weight, the effect of preventing the re-adsorption of the silicon by-products may not be sufficiently realized. If the content of the adsorption inhibitor is more than about 0.05% by weight, the etching action of the other components of the nitride film etching composition may be inhibited, and the etching rate or etching selectivity may be lowered. Preferably, the content of the adsorption inhibitor may be 0.001 wt% to 0.02 wt%, and more preferably 0.001 wt% to 0.01 wt%.

The excess water contained in the nitride film etching composition includes, for example, distilled water or deionized water (DIW), and may be included as a remaining amount of the composition.

In some exemplary embodiments, the nitride etch composition may further comprise a fluorochemical surfactant. The fluorine-based surfactant may improve the etching uniformity and the etching resolution by lowering the surface tension of the structure to be etched.

Examples of the fluorine-based surfactant include ammonium fluoroalkylsulfonate.

In some embodiments, the fluorosurfactant may be added in an amount of about 0.001% to about 0.01% by weight based on the total weight of the composition when added. If the content of the fluorine-based surfactant exceeds about 0.01% by weight, the etch selectivity may be lowered by the fluorine component.

In some embodiments, the nitride etch composition may be substantially composed of the phosphoric acid, silicon-fluorine compound, adsorption inhibitor and excess water described above. In one embodiment, the nitride-based etching composition may be substantially composed of the above-mentioned phosphoric acid, a silicon-fluorine compound, an adsorption inhibitor, a fluorine-based surfactant, and an excess of water.

According to exemplary embodiments, the nitride etch composition may not include additional fluorine containing etch components such as hydrofluoric acid, ammonium fluoride, and the like. Therefore, the etching for the oxide film is suppressed, and a high etching selectivity for the nitride film can be realized.

As described above, the nitride-based etching composition according to the exemplary embodiments can ensure a high etch selectivity for the nitride film by the silicon-fluorine compound. Also, by the interaction of the adsorption inhibitor, the silicon by-product generated from the etching process can be prevented from being re-adsorbed.

Method for manufacturing semiconductor device

1 to 15 are a plan view and a cross-sectional view for explaining a manufacturing method of a semiconductor device according to exemplary embodiments. 2 and 9 are plan views for explaining a method of manufacturing the semiconductor device. FIGS. 1, 3 to 8, and 10 to 15 are cross-sectional views taken along the line I-I 'shown in FIGS. 2 and 9 along the first direction.

For example, Figures 1 to 15 illustrate a method of fabricating a vertical memory device having a channel perpendicular to the top surface of the substrate.

In FIGS. 1 to 15, a direction substantially perpendicular to the upper surface of the substrate is defined as a first direction, and two directions parallel to the upper surface of the substrate and intersecting with each other are defined as a second direction and a third direction, respectively. For example, the second direction and the third direction may be substantially perpendicular to each other. The direction indicated by the arrow in the figure and the direction opposite thereto are described in the same direction.

Referring to FIG. 1, a plurality of interlayer insulating films 102 (for example, 102a to 102g) and sacrificial films 104 (for example, 104a to 104f) are alternately and repeatedly laminated on a substrate 100, The structure 105 can be formed.

As the substrate 100, a semiconductor substrate such as a single crystal silicon substrate or a single crystal germanium substrate can be used. In some embodiments, the substrate 100 may be provided as a p-type well of the semiconductor device.

According to exemplary embodiments, the interlayer insulating films 102 may be formed using an oxide-based material such as silicon oxide, silicon carbonitride, or silicon oxyfluoride. The sacrificial films 104 may have a high etch selectivity to the interlayer insulating film 102 and may be formed using a material that can be easily removed by a wet etching process. For example, the sacrificial films 104 may be formed using a nitride based material such as silicon nitride (SiN) or silicon boron nitride (SiBN).

The interlayer insulating layer 102 and the sacrificial layer 104 may be formed through a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a spin coating process, or the like. . In the case of the lowermost interlayer insulating film 102a directly formed on the upper surface of the substrate 100, the upper surface of the substrate 100 may be formed by thermal oxidation.

The sacrificial films 104 may be removed through a subsequent process to provide a space in which a ground selection line (GSL), a word line, and a String Selection Line (SSL) are formed . Accordingly, the number of the interlayer insulating films 102 and the sacrificial films 104 stacked may be varied depending on the number of the GSLs, word lines, and SSL formed later.

For example, the GSL and SSL may be formed in one layer, respectively, and the word lines may be formed in four layers. In this case, the sacrificial films 104 are all stacked in six layers, and the interlayer insulating films 102 can be all stacked in seven layers.

However, the number of the interlayer insulating films 102 and the sacrificial films 104 stacked is not particularly limited. For example, the GSL and / or SSL may each be formed of two layers. The word line may be formed of four, eight, or sixteen layers. The word lines may be formed in 16 or more layers, for example, 2 x n layers (n is an integer of 8 or more).

Referring to FIGS. 2 and 3, channel holes 110 may be formed through the mold structure 105 to expose the upper surface of the substrate 100.

According to exemplary embodiments, a hard mask (not shown) is formed on the uppermost interlayer insulating film 102g, and the interlayer insulating films 102 and the sacrificial layer 102 are formed through a dry etching process using the hard mask as an etch mask. The channel holes 110 may be formed by etching the films 104 sequentially.

The hard mask may be formed using, for example, a silicon-based or carbon-based spin-on hard mask (SOH) material or a photoresist material. After formation of the channel hole 110, the hard mask may be removed through an ashing process and / or a strip process.

As shown in FIG. 2, a plurality of channel holes 110 may be formed along the third direction to form a channel hole column. In addition, a plurality of the channel hole rows may be formed along the second direction.

The channel holes may be formed in a zig-zag manner along the second direction and / or the third direction. Accordingly, the density of the channel holes 110 formed per unit area of the substrate 100 can be increased.

The predetermined number of the channel hole rows may form one channel hole group. For example, the four channel hole sequences shown in FIG. 2 may define one channel hole group. Although only one channel hole group is shown in FIG. 2, a plurality of the channel hole groups may be formed along the second direction.

Referring to FIG. 4, the dielectric layer 115 may be formed along the sidewalls and bottoms of the channel holes 110 and the upper surface of the uppermost interlayer insulating layer 102g.

For example, although not specifically shown, the dielectric film 115 may be formed by sequentially laminating a blocking film, a charge storage film, and a tunnel insulating film.

The blocking film may be formed using an oxide such as silicon oxide, and the charge storage film may be formed using a nitride such as silicon nitride or a metal oxide, and the tunnel insulating film may be formed using an oxide such as silicon oxide . For example, the dielectric layer 115 may be formed to have an ONO (Oxide-Nitride-Oxide) structure in which an oxide-nitride-oxide-oxide layer is sequentially stacked. The blocking film, the charge storage film, and the tunnel insulating films may be formed through a CVD process, a PECVD process, an atomic layer deposition (ALD process), or the like.

Referring to FIG. 5, the dielectric layer 115 may be partially removed to form the dielectric layer structure 120.

For example, the top and bottom portions of the dielectric layer 115 may be partially removed through an etch-back process. The upper surface of the interlayer insulating film 102g on the uppermost layer of the dielectric film 115 and portions formed on the upper surface of the substrate 100 may be substantially removed to form the dielectric film structure 120. [

The dielectric layer structure 120 may be formed in the channel hole 110. For example, the dielectric layer structure 120 may be formed on the sidewalls of the channel hole 110 and may have a substantially straw or cylinder shell shape. As the dielectric film structure 120 is formed, the upper surface of the substrate 100 may be exposed again.

6, a channel film 125 is formed along the upper surfaces of the uppermost interlayer insulating film 102g and the dielectric film structure 120 and the upper surface of the substrate 100, and a channel film 125 is formed on the channel film 125. [ The first buried layer 127 filling the remaining portion of the hole 110 can be formed.

According to exemplary embodiments, the channel film 125 may be selectively formed to include polysilicon doped with impurities or amorphous silicon. The first buried film 127 may be formed to include an insulating material such as silicon oxide or silicon nitride. The channel film 125 and the first buried film 127 may be formed through a CVD process, a PECVD process, an ALD process, or the like.

According to one embodiment, the channel film 125 may be formed to completely fill the inside of the channel hole 110. In this case, the formation of the first embedded film 127 may be omitted.

7, the first buried layer 127 and the channel layer 125 are planarized until the interlayer dielectric layer 102g of the uppermost layer is exposed, and are sequentially stacked from the side walls of the dielectric layer structure 120, The channel 130 and the first buried pattern 135 may be formed. The planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

The channel 130 has a substantially cup shape and can be in contact with the upper surface of the substrate 100 exposed by the channel hole 110. The first embedding pattern 135 may have a substantially pillar or hollow cylindrical shape. The formation of the first buried pattern 135 is omitted and the channel 130 is substantially a pillar and the second buried pattern 135 is formed in the channel 130. In one embodiment, Or it may have a hollow cylinder shape.

Meanwhile, as the channel 130 is formed for each channel hole 110, a channel column corresponding to the arrangement of the channel hole columns may be formed. In addition, for example, four channel columns can form one channel group.

In one embodiment, a semiconductor pattern (not shown) may be further formed to fill the bottom of the channel hole 110 prior to forming the dielectric layer structure 120 and the channel 130. For example, the semiconductor pattern may be formed by performing a selective epitaxial growth (SEG) process using a top surface of the substrate 100 as a seed. The semiconductor pattern may include polysilicon or single crystal silicon.

Referring to FIG. 8, a pad 140 filling the channel hole 110 may be formed.

8, the upper portions of the dielectric film structure 120, the channel 130, and the first buried pattern 135 are removed through an etch-back process to form a recess 137. [ Thereafter, a pad film filling the recess 137 is formed on the first buried pattern 135, the channel 130, the dielectric film structure 120 and the uppermost interlayer insulating film 102g, and the uppermost interlayer insulating film 102g The upper portion of the pad film may be planarized by, for example, a CMP process to form the pad 140. According to exemplary embodiments, the pad film may be formed of polysilicon or an n-type impurity May be formed to include the doped polysilicon. Alternatively, the pad film may be formed by forming a preliminary pad film using amorphous silicon and then crystallizing the preliminary pad film.

Referring to FIGS. 9 and 10, the mold structure 105 may be partially etched to form the opening 150.

For example, a hard mask (not shown) may be formed that covers the pads 140 and partially exposes the uppermost interlayer insulating film 102g between some of the channel columns adjacent in the second direction. The opening 150 may be formed by etching the interlayer insulating films 102 and the sacrificial films 104 through a dry etching process using the hard mask as an etching mask. The hard mask may be formed using, for example, a photoresist or an SOH material. The hard mask may also be removed through an ashing and / or strip process after formation of the openings 150.

The opening 150 may expose the upper surface of the substrate 100 through the mold structure 105 along the first direction. Also, the opening 150 may extend along the third direction, and a plurality of openings 150 may be formed along the second direction.

The opening 150 may be provided in a gate line cut region. The channel group may be defined by the openings 150 neighboring along the second direction. In one embodiment, a predetermined number, e.g., four, of the channel columns may be grouped by neighboring openings 150. [

On the other hand, as the openings 150 are formed, the interlayer insulating films 102 and the sacrificial films 104 are formed on the interlayer insulating patterns 106 (for example, 106a to 106g) and the sacrificial patterns 108 For example, 108a to 108f. The interlayer insulating pattern 106 and the sacrificial pattern 108 may have a line shape or a plate shape extending and extending around the channel group.

Referring to FIG. 11, the opening 150 may remove the sacrificial patterns 108 on which the side walls are exposed. When the sacrificial patterns 108 are removed, a gap 160 is formed between the interlayer dielectric patterns 106 of each layer, and the outer wall of the dielectric film structure 120 is partially exposed by the gap 160 .

As described above, the sacrificial pattern 108 and the interlayer dielectric pattern 106 may comprise a nitride-based material and an oxide-based material, respectively. According to exemplary embodiments, the sacrificial pattern 108 and the interlayer dielectric pattern 106 may comprise silicon nitride (Si ₃ N ₄ ) and silicon oxide (SiO ₂ ), respectively.

Thus, the sacrificial pattern 108 may be removed through a wet etch process using a nitride etch composition according to the exemplary embodiments described above.

The nitride film etch composition may include phosphoric acid, a silicon-fluorine (Si-F) compound, an adsorption inhibitor, and an excess of water. In some exemplary embodiments, the nitride etch composition comprises about 80 wt.% To about 90 wt.% Phosphoric acid, about 0.02 wt.% To about 0.1 wt.% Of the silicon-fluorine compound relative to the total weight of the nitride etch composition, From 0.001 wt% to about 0.05 wt% of the adsorption inhibitor and the excess water.

In some embodiments, the nitride etch composition may further comprise a fluorochemical surfactant.

The sacrificial pattern 108 can be etched away with the nitride etch composition with an etch selectivity ratio of at least about 200 to the interlayer dielectric pattern 106. According to exemplary embodiments, the sacrificial pattern 108 may be removed by the nitride etch composition with an etch selectivity of about 200 or greater.

Even when the interlayer insulating pattern 106 and the sacrificial pattern 108 are alternately repeatedly stacked or laminated in three dimensions as shown in FIG. 10, the etchant has a predetermined etch selectivity to the nitride, The pattern 108 may be damaged. In this case, when the gate line is formed in the gap 160 by a subsequent process, the gate lines formed in the adjacent layers are not completely separated, which may lower the operational reliability of the semiconductor device.

Further, even if a small amount of the interlayer insulating pattern 106 is etched by the wet etching process, for example, etching by-products containing silicon oxide may be adsorbed on the substrate 100 or other structures. In addition, various silicon by-products generated from the wet etching process can be reabsorbed.

However, in the case of the nitride film etching composition, a high etch selectivity for the sacrificial pattern 108 including silicon nitride can be ensured by the silicon-fluorine compound. Also, by the interaction of the adsorption inhibitor, the silicon by-product generated from the etching process can be prevented from being re-adsorbed. For example, the sidewall of the opening 150 may be surface treated with the adsorption inhibitor to suppress the re-adsorption of the silicon by-product.

Thus, for example, the sacrificial patterns 108 can be removed with a high etch selectivity ratio of about 200 or more.

In some embodiments, AHFS may be used as the silicon-fluorine compound. As the adsorption inhibitor, a compound represented by the following formula (1) may be used.

≪ Formula 1 >

(Wherein R 1 represents Li, Na or an alkyl group having 1 to 3 carbon atoms, R 2, R 3 and R 4 each independently represent F, Cl or an alkyl group having 1 to 10 carbon atoms, and R 5, R 6, Independently represents F, Br or an alkyl group having 1 to 10 carbon atoms.

Referring to FIG. 12, a gate electrode film 165 filling the gaps 160 can be formed.

In accordance with exemplary embodiments, a plurality of gate electrodes are formed along the outer walls of the exposed dielectric layer structure 120, the surfaces of the interlayer dielectric patterns 106, the upper surface of the exposed substrate 100, A film can be formed. The gate electrode film completely fills the gaps 160 and may be formed to partially fill the second openings 150.

The gate electrode film 165 may be formed using a metal or a metal nitride. For example, the gate electrode film 165 may be formed using a metal or a metal nitride having a low work function and electrical resistance such as tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, and platinum. According to one embodiment, the gate electrode film 165 may be formed of a multilayer film in which a barrier film including a metal nitride and a metal film including a metal are stacked. The gate electrode film 165 may be formed using a CVD process, a PECVD process, an ALD process, a physical vapor deposition (PVD) process, or a sputtering process.

In one embodiment, along the surfaces of the inner walls of the gaps 160 and the interlayer dielectric patterns 106 before forming the gate electrode film 165, (Not shown) can be further formed.

Referring to FIG. 13, the gate electrode film 165 may be partially removed to form gate lines 170 (for example, 170a to 170f) in the gaps 160 of each layer.

For example, the upper portion of the gate electrode film 165 can be planarized by, for example, a CMP process until the uppermost interlayer insulating film pattern 106g is exposed. The gate lines 170 may then be formed by etching the portions of the gate electrode film 165 formed within the openings 150 and on the upper surface of the substrate 100. [ The gate electrode film 165 may be partially etched through a wet etching process that includes, for example, hydrogen peroxide (H ₂ O ₂ ).

The gate lines 170 may comprise a GSL, a word line, and a SSL formed sequentially apart from the upper surface of the substrate 100 along the first direction. For example, the lowest gate line 170a may be provided with the GSL. The four-layer gate lines 170b, 170c, 170d, and 170e above the GSL may be provided as the word lines. The uppermost gate line 170f above the word line may be provided by the SSL. However, the number of the GSL, the word line, and the SSL is not particularly limited, and may be changed according to the circuit design and the degree of integration of the vertical memory device.

The gate line 170 of each layer may surround the dielectric film structure 120 and the channel 130 and may be formed to extend in the third direction. In addition, the gate line 170 of each layer may extend around the channel group including a predetermined number of the channel columns, for example, four channel columns. Thus, the gate line structure can be defined by the gate lines 170 that surround the channel group and extend in the third direction, and are stacked in the first direction.

Referring to FIG. 14, the impurity region 101 may be formed on the substrate 100 exposed by the opening 150, and the second buried pattern 175 may be formed to fill the opening 150.

For example, an ion implantation mask (not shown) covering the upper surface of the pad 140 is formed and an n-type impurity such as phosphorus (P) or arsenic (As) is implanted using the ion implantation mask The impurity region 101 can be formed.

The impurity region 101 may extend in the third direction, for example, and may be provided as a common source line (CSL) of the vertical memory device. In one embodiment, a metal suicide pattern (not shown) such as a nickel suicide pattern or a cobalt suicide pattern may be further formed on the impurity region 101. Thus, the resistance between the impurity region 101 and, for example, the CSL contact (not shown) can be reduced.

Thereafter, a second buried film is formed on the substrate 100, the uppermost interlayer insulating film pattern 106g and the pad 140 to fill the opening 150, and the upper portion of the second buried film is covered with the uppermost interlayer insulating film pattern 106g. The second buried pattern 175 may be formed by planarization through an etch-back process and / or a CMP process until the exposed portions are exposed. The second buried layer may be formed using an insulating material such as silicon oxide.

Referring to FIG. 15, the upper insulating layer 180 may be formed on the uppermost interlayer insulating pattern 106g, the second buried pattern 175, and the pad 140. An upper insulating film 180, an insulating material such as silicon oxide, and the like through a CVD process, a spin coating process, or the like.

Thereafter, the bit line contact 185 that contacts the pad 140 through the upper insulating layer 180 can be formed. A bit line 190 electrically connected to the bit line contact 185 may then be formed on the upper insulating layer 180. The bit line contact 185 and the bit line 190 may be formed through a PVD process, an ALD process, a sputtering process, or the like using a metal, a metal nitride, a doped polysilicon, or the like.

The bit line contacts 185 may be formed to correspond to the pads 140 to form bit line contact arrays. In addition, the bit line 190 may extend in the second direction, for example, and may be electrically connected to the plurality of pads 140 and extended. In addition, a plurality of bit lines 190 may be arranged in the third direction.

Hereinafter, etching characteristics of the nitride-based etching composition according to exemplary embodiments will be described with reference to concrete examples.

Experimental Example

The comparative etching compositions with phosphoric acid and water (DIW) or silicon-fluorine compounds in phosphoric acid and water were prepared according to Table 1 below. Further, the etching compositions of Examples 1 to 8, in which the adsorbing preventive and / or the fluorine-containing surfactant were added to the phosphoric acid, water and the silicon-fluorine compound were prepared. R1 is Li, R2, R3, R4, R5, R6 and R7 each represent F. The compound of the following formula 1 is used as the adsorption inhibitor.

≪ Formula 1 >

[Table 1]

The etch rate (Å / min) of the silicon nitride film (Si ₃ N ₄ ) and the thermal oxide film (SiO ₂ ) was measured at 160 ^° C using each composition and the etch selectivity ratio of the nitride film to the oxide film was calculated. In addition, it was observed whether or not the re-adsorption of etching by-products occurred after the etching process.

The experimental results are shown in Table 2 below.

[Table 2]

Referring to Table 2, in the case of the compositions of Comparative Examples 2 to 8 in which a phosphorus-silicon-phosphorus compound was added, the etch selectivity was improved as compared with the composition of Comparative Example 1, but the re-adsorption of etch by-products from the nitride film and / A phenomenon was observed. In Comparative Examples 2 to 6, when the AHFS was used as the silicon-fluorine compound, the etch rate and etch selectivity for the highest nitride film were obtained.

In addition, in the case of the compositions of Examples 1, 3 and 5-8 containing an adsorption inhibitor, it can be confirmed that no adsorption was observed.

It can be seen from the above Experimental Example that the etch rate for the nitride film is improved by the addition of the silicon compound and the adsorption inhibitor in the etch composition, and the oxide film is protected, thereby improving the etch selectivity. Further, it can be confirmed that the etching by-products are reduced and the re-adsorption of the etching object is blocked.

In addition, it can be confirmed that the etching rate for the nitride film is further improved by adding the fluorine series surfactant into the etching composition.

By using the nitride-based etchant composition according to the embodiments of the present invention, it is possible to selectively remove only the nitride film substantially without adsorbing etching by-products and damaging the oxide film. Accordingly, in the vertical memory device fabrication process using the nitride film etchant composition having a high degree of integration and a fine critical dimension, the sacrificial film containing silicon nitride can be effectively removed. In addition, the etchant composition can be utilized in various semiconductor device manufacturing processes requiring nitride film etching.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be understood that the present invention can be changed.

100: substrate 101: impurity region
102: interlayer insulating film 104: sacrificial film
106: interlayer insulation pattern 108: sacrificial pattern
105: mold structure 110: channel hole
115: Dielectric film 120: Dielectric film structure
125: channel film 127: first buried film
130: channel 135: first embedded film pattern
137: recess 140: pad
150: opening 160: gap
165: gate electrode film 170: gate line
175: second embedded film pattern 180: upper insulating film
185: bit line contact 190: bit line

Claims (12)

Phosphoric acid;
Silicon-fluorine compounds comprising silicon-fluorine bonds (Si-F bonds);
An adsorption inhibitor; And
Water,
Wherein the adsorption inhibitor comprises a compound represented by the following formula (1).
≪ Formula 1 >

(Wherein R 1 represents Li, Na or an alkyl group having 1 to 3 carbon atoms, R 2, R 3 and R 4 each independently represent F, Cl or an alkyl group having 1 to 10 carbon atoms, and R 5, R 6, Independently represents F, Br or an alkyl group having 1 to 10 carbon atoms. The cleaning composition of claim 1, further comprising 80 wt% to 90 wt% of the phosphoric acid, 0.02 wt% to 0.1 wt% of the silicon-fluorine compound, 0.001 wt% to 0.05 wt% of the anti- Wherein the nitride film etch composition comprises: delete The nitride-based etching composition according to claim 1, further comprising a fluorine-based surfactant. The nitride-based etching composition according to claim 4, wherein the fluorine-based surfactant comprises ammonium fluoroalkylsulfonate. The method of claim 1, wherein the silicon-fluorine compound is selected from the group consisting of ammonium hexafluorosilicate (AHFS), ammonium fluorosilicate (AFS), sodium fluorosilicate (SFS), silicon tetrafluoride at least one selected from the group consisting of silicon tetrafluoride (STF) and hexafluorosilicic acid (HFSA). The nitride-based etching composition according to claim 6, wherein the silicon-fluorine compound comprises AHFS. Alternately and repeatedly depositing interlayer insulating films and sacrificial films on a substrate;
Forming a plurality of channels through the interlayer dielectric films and the sacrificial films;
Etching the portions of the interlayer insulating films and the sacrificial films between adjacent ones of the channels to form openings;
Removing the sacrificial layers exposed by the opening using a nitride-based etching composition comprising phosphoric acid, a silicon-fluorine compound comprising a silicon-fluorine bond (Si-F bond), an adsorption inhibitor and an excess of water; And
Forming a gate line in each of the spaces in which the sacrificial films are removed,
Wherein the adsorption inhibitor comprises a compound represented by the following formula (1).
≪ Formula 1 >

(Wherein R 1 represents Li, Na or an alkyl group having 1 to 3 carbon atoms, R 2, R 3 and R 4 each independently represent F, Cl or an alkyl group having 1 to 10 carbon atoms, and R 5, R 6, Independently represents F, Br or an alkyl group having 1 to 10 carbon atoms. 9. The method of claim 8, wherein the nitride etch composition comprises 80 to 90% by weight of the phosphoric acid, 0.02 to 0.1% by weight of the silicon-fluorine compound, 0.001 to 0.05% The adsorption inhibitor, and the excess water. 9. The method according to claim 8, wherein the interlayer insulating film comprises silicon oxide, and the sacrificial layer comprises silicon nitride. delete 9. The method of claim 8, wherein the silicon-fluorine compound comprises ammonium hexafluorosilicate (AHFS).

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