KR20180057085A - Autostereoscopic image display and driving method thereof - Google Patents

Abstract

The present invention relates to an autostereoscopic image display device and a driving method thereof. The autostereoscopic image display device includes resistors connected to the electrodes of a switchable cell and a timing controller for generating a driving signal of the switchable cell. The timing controller changes the level of a driving signal voltage during a vertical blank period in which the pixel data of an input image is not received. It is possible to prevent the deterioration of the image quality of a display panel due to a change in the driving signal of the switchable cell.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a three-

The present invention relates to an eyeglass stereoscopic image display apparatus and a driving method thereof.

Due to the development of stereoscopic image display technology, stereoscopic image reproduction technology has been applied to a display device such as a television or a monitor, so that 3D stereoscopic images can be viewed at home. The stereoscopic image display device can be divided into a spectacle method and a non-spectacle method. The spectacle method realizes a stereoscopic image by using polarizing glasses or liquid crystal shutter glasses to display the right and left parallax images in a direct view type display device or a projector by changing the polarization directions of the parallax images in a time division manner. The non-eyeglass system generally displays optical components such as a parallax barrier (hereinafter referred to as a "barrier") and a lenticular lens (hereinafter referred to as a "lens") for separating the optical axis of left and right parallax images It is installed in front of or behind the screen to realize a stereoscopic image.

Recently, a switchable cell in which a barrier and a lens are implemented by adjusting a voltage applied to a liquid crystal layer is being developed. The switchable cell separates the left eye image data of the 3D image data and the optical axis of the right eye image data using an electrically controllable liquid crystal layer. Because of this switchable cell, the viewer sees the pixels on which the left eye image is displayed through the left eye and the pixels on which the right eye image is displayed through the right eye, so that a three-dimensional effect can be felt with binocular parallax without special glasses. The switchable cell may be implemented as a switchable barrier or a switchable lens. The applicant of the present application has proposed a switchable barrier and a switchable lens through US Application No. 13/077565, US Application No. 13/325272, Application No. 10-2010-0030531, and Application No. 10-2010-0130547, etc.

Power can be shared between display panels and switchable cells. In this case, glitch may occur in the drive signal of the switchable cell if the current capacity of the power supply circuit is not sufficiently large when the change width in the drive signal of the switchable cell is large. This may affect the output of the power supply circuit, Resulting in an output change of the panel drive circuit. The change in the output of the display panel drive circuit can cause noise in the image displayed on the display panel.

The present invention provides a non-eyeglass stereoscopic image display device and a driving method thereof, which can prevent degradation of image quality of a display panel due to a change in driving signal of a switchable cell.

The non-eyeglass stereoscopic image display apparatus of the present invention includes a display panel in which data lines, gate lines intersecting with the data lines, and pixels are arranged in a matrix form; A display panel driver for writing data of a stereoscopic image of the display panel; A switchable cell disposed on the display panel or incorporated in the display panel for separating the optical axis of the left eye image and the right eye image from the stereoscopic image; Resistors connected to the electrodes of the switchable cell; And a timing controller for generating a driving signal of the switchable signal. The timing controller changes the level of the driving signal voltage during a vertical blank period in which pixel data of the input image is not received.

The non-eyeglass stereoscopic image display device includes a power supply circuit for generating a first voltage and a second voltage; And a level shifter for converting a high level voltage of the driving signal into the first voltage and converting a low level voltage of the driving signal into the second voltage. The driving signal output through the level shifter is applied to the electrodes of the switchable cell through the resistor.

The resistors include a first resistor connected to the centrally located electrodes of the switchable cell and second resistors connected to the electrodes disposed in the left and right regions of the switchable cell. The resistance values of the first and second resistors are equal to each other.

The resistors have different resistance values depending on the positions of the switchable cells.

The resistors include a first resistor connected to the centrally located electrodes of the switchable cell and second resistors connected to the electrodes disposed in the left and right regions of the switchable cell. The resistance value of the first resistor is smaller than the resistance value of the second resistors.

Wherein the display panel driving unit converts the data received from the timing controller into a data voltage and outputs the data voltage to the data lines; And a gate driving circuit for sequentially outputting gate pulses synchronized with the data voltage in response to a gate timing control signal received from the timing controller. The level shifter converts a high level voltage of each of the driving signal and the gate timing control signal into the first voltage and converts a low level voltage of each of the driving signal and the gate timing control signal into the second voltage. And the drive signal and the gate pulse each swing between the first voltage and the second voltage.

The method of driving a spectacles stereoscopic image display apparatus according to the present invention includes the steps of generating a driving signal of a switchable signal in the timing controller and changing a level of the driving signal voltage during a vertical blank period in which pixel data of an input image is not received .

The present invention relates to a display apparatus and a display apparatus, which are capable of changing a voltage level of a drive signal of a switchable cell during a vertical blank period in which pixel data is not received in an input image, It is possible to prevent degradation. In addition, the present invention can prevent a voltage variation of a driving signal by connecting a relatively large resistance to the electrodes of the switchable cell, thereby limiting a current generated when the driving signal applied to the switchable cell is changed.

1 is a block diagram showing a spectacle-free three-dimensional image display apparatus according to an embodiment of the present invention.
2 is a view schematically showing a path of light passing through a switchable lens in a 3D mode.
3A and 3B are views showing a cross-sectional structure of a switchable lens and a driving method thereof.
4 is a diagram schematically showing the path of light passing through the switchable barrier in the 3D mode.
5A and 5B are views showing a cross-sectional structure of a switchable lens and a driving method thereof.
6 is a view showing the timing of changing the driving signal voltage of the switchable cell.
7 is a detailed view showing the display timing of the Video Electronics Standards Association (VESA) standard.
8 is a plan view showing a wiring connected to the switchable cell.
9 is a waveform diagram showing a waveform distortion of a driving signal applied to the switchable cell in the circuit shown in FIG.
10 is a plan view showing the resistance added to the wiring connected to the switchable cell.
11 is a waveform diagram showing a waveform of a driving signal applied to the switchable cell in the circuit shown in FIG.
12 is a view showing a connection relationship between the timing controller, the power supply circuit, the level shifter, and the resistance shown in FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. To fully disclose the scope of the invention, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited to those shown in the drawings. Like reference numerals refer to like elements throughout the specification. In the following description of the present invention, detailed description of known related arts will be omitted when it is determined that the gist of the present invention may be unnecessarily blurred.

Where the term "comprises", "comprising", "having", "having", or the like is used herein, other parts may be added as long as "only" is not used. The singular forms of the components may be construed in plural unless otherwise expressly stated.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two components is described as 'on', 'on top', 'under', or 'next to' Quot; directly " or " direct " may be interposed between those components that are not used.

The first, second, etc. may be used to distinguish the components, but these components are not limited to the function or structure of the component or the names of components attached to the components.

The following embodiments can be combined or combined with each other partly or entirely, and technically various interlocking and driving are possible. Each embodiment may be feasible independently of one another and may be feasible in conjunction.

The non-eyeglass stereoscopic image display apparatus of the present invention can be implemented as a flat panel display substrate such as a liquid crystal display (LCD) or an electroluminescence display.

1, the non-eyeglass stereoscopic image display apparatus includes a display panel 100, a display panel driver, a switchable cell 200, a timing controller 101, a power supply circuit 300, a level shifter 310, And the like.

The active area of the display panel 100 includes data lines 105, gate lines (or scan lines) 106 that intersect the data lines 105, pixels arranged in a matrix form do. The active area is a screen including a pixel array for reproducing an input image. The pixel array displays a 2D image in a 2D mode and displays a left eye image and a right eye image separately in a 3D mode. Each of the pixels has red (R), green (G), and blue (B) Pixels. Each of the pixels may further include white (W, W) subpixels in addition to RGB subpixels. Each of the subpixels may include one or more thin film transistors (TFTs).

The display panel driver writes the data of the 2D / 3D image on the data lines 105 of the display panel 100 to the pixels. The display panel driving unit includes a data driving circuit 102 for supplying a pixel data voltage of an input image to the data lines 105 and a gate driving circuit 102 for supplying a gate pulse (or a scan pulse) (103). The display panel driver may spatially distribute the left eye and right eye image data input as data of the multi-view image data format in the 3D mode to the pixels of the display panel 100 and write them.

The data driving circuit 102 converts the pixel data (digital data) of the input image received from the timing controller 101 into an analog gamma compensation voltage to generate data voltages and supplies the data voltages to the data lines (105).

The gate drive circuit 103 receives the gate timing control signal GDC (VGH, VGL) through the level shifter 310 and generates an output under the control of the timing controller 101. The gate driving circuit 103 supplies a gate pulse (or a scan pulse) to the gate lines 106, which is synchronized with a data voltage supplied to the data lines 105. The gate driving circuit 103 sequentially shifts gate pulses by using a shift register to sequentially supply gate pulses to the gate lines 106. [ The TFTs of the pixel array are turned on in response to the gate-on voltage of the gate pulse to supply the data voltage to the pixel electrode.

The gate pulse output from the gate drive circuit 103 swings between the gate on voltage and the gate off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the TFT, and the gate-off voltage is set to a voltage lower than the threshold voltage of the TFT. In the case of an n-type TFT, the gate-on voltage may be a gate high voltage (VGH) and the gate-off voltage may be a gate low voltage (VGL). In the case of a p-type TFT, the gate-on voltage may be a gate-low voltage (VGL) and the gate-off voltage may be a gate-high voltage (VGH).

The switchable cell 200 may be implemented as a switchable lens (LENS) or a switchable barrier (BAR) as shown in FIGS. 2 to 5B. The switchable cell 200 is joined to the front or back of the display panel 100 or embedded in the display panel 100 to separate the left eye image data of the 3D image data and the optical axis of the right eye image data. A switchable barrier (BAR) or a switchable lens (LENS) is driven by a drive signal (3DC (VGH, VGL)) including a birefringent medium such as liquid crystal, an electrode and the like and applied through a resistor 210, Separates the optical axis of the light of the right eye image. The liquid crystal layer of the switchable cell 200 forms a lens for deflecting light, such as a barrier or a lens curved surface, by driving liquid crystal molecules according to a voltage level of a driving voltage applied through an electrode.

The driving signal 3DC of the switchable cell 200 is synchronized with a vertical blank period VB in which pixel data of the input image is not received in the 3D mode under the control of the timing controller 101 It changes. The power supply circuit 300 may be shared by the display panel 100 and the switchable cell 200. In this case, the driving signal voltage of the switchable cell 200 may swing between VGH and VGL.

The timing controller 101 supplies digital video data (RGB) of a 2D / 3D input image input from the host system 110 to the data driving circuit 102. The timing controller 101 generates a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE synchronized with the digital video data RGB of the 2D / 3D input video, , A clock (CLK), and the like. The timing controller 101 controls the operation timings of the display panel driving units 102 and 103 and the switchable cells 200 using the timing signals received from the host system 110 and controls the driving units 102, And generates timing control signals (DDC, GDC, 3DC) for synchronizing the operation timings of the plurality of memory cells.

The gate timing control signal GDC includes a start pulse VST, a shift clock GCLK, an output enable signal GOE, and the like. The output enable signal (GOE) may be omitted. The start pulse (VST) controls the start timing of the gate driving circuit (103). The shift clock signal GCLK controls the timing at which the gate pulse is shifted in the gate driving circuit 103.

The timing controller 101 increases the frame rate by the frequency of the frame rate × N (N is a positive integer of 2 or more) Hz of the input image and sets the operation frequency of the display panel driver 102, 103 and the switchable cell 200 to N The frame rate can be controlled at a multiple of the frame rate. The frame rate of the input image is 60 Hz in the National Television Standards Committee (NTSC) method and 50 Hz in the PAL (Phase-Alternating Line) method.

The power supply circuit 300 generates a DC power required for driving the display panel 100 and the switchable cell 200 using a DC-DC converter. The DC-DC converter includes a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply circuit 300) outputs a gamma reference voltage, VGH, VGL, etc., to be supplied to the data driving circuit 102. The power supply circuit 300 may be implemented as a power integrated circuit (IC).

The voltage levels of the gate timing control signal GDC and the switchable cell driving signal 3DC output from the timing controller 101 are very small digital signal level voltages. The level shifter 310 converts the high level voltage of the gate timing control signal GDC and the switchable cell driving signal 3DC received from the timing controller 101 to a higher VGH and supplies the signals GDC and 3DC ) To a lower VGL to increase the voltage of the signals.

A 3D data formatter 120 may be installed between the host system 110 and the timing controller 101. The 3D data formatter 120 rearranges the left eye image data and the right eye image data of the 3D image inputted from the host system 110 in the 3D mode into the multi view image data format and transmits them to the timing controller 101. When the 2D image data is input in the 3D mode, the 3D data formatter 120 executes a predetermined 2D-3D image transformation algorithm to generate left eye image data and right eye image data from 2D image data, Can be rearranged and transmitted to the timing controller 101.

The host system 110 may include main control circuitry such as a television system, a set top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, a mobile system, . The host system 110 converts the digital video data of the 2D / 3D input image into a format suitable for the resolution of the display panel (PNL) 100 using a scaler, and transmits a timing signal to the timing controller 101 together with the data. Lt; / RTI >

The host system 110 supplies the 2D image in the 2D mode to the timing controller 101 while supplying the 3D image or the 2D image data in the 3D mode to the 3D data formatter 120. [ The host system 110 can transmit a mode signal to the timing controller 101 in response to user data input through the user interface 112 to switch the operation mode of the spectacle-free three-dimensional image display device in the 2D mode and the 3D mode have. The user interface 112 may include a keypad, a keyboard, a mouse, an on screen display (OSD), a remote controller, a graphical user interface (GUI), a touch UI UI, 3D UI, and the like. The user can select the 2D mode and the 3D mode through the user interface, and select the 2D-3D image conversion in the 3D mode.

2 is a view schematically showing a path of light passing through a switchable lens in a 3D mode. 3A and 3B are views showing a cross-sectional structure of a switchable lens and a driving method thereof. In Fig. 2, " PIX " represents a pixel array of the display panel 100. Fig.

Referring to FIGS. 2 to 3B, the switchable lens LENS forms a lenticular lens in the 3D mode. The light of the left eye pixel L in which the data of the left eye image is written is refracted from the lens surface toward the left eye of the user. The light of the right eye pixel R in which the data of the right eye image is written is refracted toward the right eye of the user on the lens surface.

3A and 3B, the switchable lens LENS includes a first substrate 31 on which a first electrode 32 is formed, a second substrate 36 on which a second electrode 35 is formed, A lens structure 33 disposed between the first substrate 31 and the second substrate 35, and a liquid crystal 34. The substrates 31 and 36 of the switchable lens LENS and the electrodes 32 and 35 are formed of a transparent material. Switchable lenses (LENS) do not require a polarizer.

For example, VGH or VGL without a potential difference to the first and second electrodes 32 and 35 of the switchable lens LENS in the 3D mode. At this time, due to the refractive index difference between the medium of the lens structure 33 and the liquid crystal molecules, a lens surface is formed therebetween.

Different voltages V32 and V35 are applied to the electrodes 32 and 35 in order to increase the potential difference between the first and second electrodes 32 and 35 of the switchable lens LENS in the 2D mode. For example, when VGH is applied to the first electrode 32, VGL may be applied to the second electrode 35. On the other hand, when VGL is applied to the first electrode 32, VGH may be applied to the second electrode 35. The voltage V35 of the second electrode 35 may be a DC voltage having a potential difference from the voltage of the first electrode 32. [ Due to the potential difference between the first and second electrodes 32 and 35, the liquid crystal molecules are vertically arranged along the vertical electric field direction. When the liquid crystal molecules are arranged vertically, there is no difference in refractive index between the liquid crystal molecules and the medium of the lens structure 33, and as a result, the lens surface disappears in the switchable lens LENS. At this time, the light of all the pixels passes through the switchable lens (LENS) without being refracted by the switchable lens (LENS).

4 is a diagram schematically showing a path of light passing through a switchable barrier (BAR) in a 3D mode. 5A and 5B are views showing a cross-sectional structure of a switchable lens and a driving method thereof.

4 to 5B, the switchable barrier (BAR) forms a light blocking portion in the 3D mode to partially block the light from the pixels (L, R). In the 3D mode, the user sees only the left eye pixels L in which the left eye image is displayed in the left eye, and only the left eye pixels L in which the right eye image is displayed in the right eye.

As shown in FIGS. 5A and 5B, the switchable barrier (BAR) includes a first substrate 51 on which first electrodes 52a and 52b are formed, a second substrate 55 on which a second electrode 54 is formed, And a liquid crystal 53 disposed between the first substrate 51 and the second substrate 55. The first electrodes 52a and 52b are divided into a plurality of first electrodes 52a and a plurality of first electrodes 52b so that an electric field can be independently applied to the subpixels. The substrates 51 and 55 of the switchable barrier (BAR) and the electrodes 52a, 52b and 54 are formed of a transparent material. The polarizer is bonded to at least the first substrate 51 among the substrates 51 and 55 of the switchable barrier (BAR). The polarizer of the switchable barrier (BAR) blocks light other than linearly polarized light such as a light transmission axis.

For example, VGH or VGL with no potential difference is applied to the first and second electrodes 52a, 52b and 54 of the switchable barrier (BAR) in the 2D mode. At this time, the optical axis of the linearly polarized light passed through the liquid crystal 53 is maintained as it is and passes through the polarizing plate.

A voltage having a large potential difference may be applied to the first and second electrodes 51a, 51b, and 54 of the switchable barrier (BAR) in the 3D mode. The optical axis of the linearly polarized light having passed through the liquid crystal layer in the light shielding portion where VGH (or VGL) is applied to one of the first electrodes 51a and 51b and VGL (or VGH) is applied to the second electrode 54 And can not pass through the polarizer. . On the other hand, the portion where the first electrodes 51a and 51b and the second electrode 54 do not have a potential difference can pass the liquid crystal 53 through the polarizing plate as it is.

As described above, the switchable cell 200 is driven by the driving signals (3DC (VGH, VGL)) swinging between VGH and VGL having a relatively large potential difference to control the path of light in the 2D mode and the 3D mode . Since the switchable cell 200 and the display panel 100 share the power supply circuit 300, the drive signal applied to the display panel 100 when the drive signal voltage of the switchable cell 200 is changed, that is, The voltage (VGH, VGL) may change and cause image quality problems. The voltage level of the switchable cell driving signal 3DC is changed within the vertical blank period VB as shown in Fig. 6, so that the active period during which data is updated in the display panel (VGH, VGL) of the display panel 100 during a predetermined period (e.g., AT).

7 is a detailed view showing the display timing of the VESA standard.

Referring to FIG. 7, the host system 110 transmits timing signals (Vsync, Hsync, DE) synchronized with the input image or standby mode setting data to the timing controller 101. The vertical synchronization signal Vsync defines one frame period. The horizontal synchronization signal (Hsync) defines one horizontal period. The data enable signal DE defines an effective data period in which pixel data exists in the input image.

The data enable signal DE is synchronized with the valid data to be displayed on the pixel array of the display panel 100. One pulse period of the data enable signal DE is one horizontal period, and a high logic period of the data enable signal DE indicates one line data input timing. One horizontal period is a time required to write data to pixels of one line in the display panel 100. [

The data enable signal DE and the pixel data of the input image are input during the vertical active period AT and are not input to the vertical blank period VB. The vertical active period AT is time for displaying one frame of data in all the pixels of the pixel array in which the image is displayed on the display panel 100. One frame period is a time required for displaying one frame of data on the display panel 100, which is the sum of one vertical active period (AT) and one vertical blank period (VB).

As can be seen from the data enable signal DE, no input data is received on the display device during the vertical blank period. The vertical blank period VB includes a vertical sync time VS, a vertical front porch FP, and a vertical back porch BP. The vertical sync time (VS) is the time from the falling edge of the Vsync to the rising edge, and indicates the start (or end) timing of one screen. The vertical front porch FP is a time from the polling edge of the last DE indicating the last line data timing of one frame data to the start of the vertical blank period VB. The vertical back porch BP is the time from the end of the vertical blank period VB to the rising edge of the first DE indicating the first line data timing of one frame of data.

8 is a plan view showing a wiring connected to the switchable cell 200. FIG. 9 is a waveform diagram showing a waveform distortion of a driving signal applied to the switchable cell 200 in the circuit shown in FIG.

10 is a plan view showing the resistance 210 added to the wiring between the switchable cells 200. FIG. 11 is a waveform diagram showing a waveform of a driving signal (3DC (VGH, VGL)) applied to the switchable cell in the circuit as shown in Fig.

Referring to FIGS. 10 and 11, the switchable cell 200 functions as a large capacitance load to the power supply circuit 300. In order to drive the switchable cell 200, a driving signal of a relatively large voltage (approximately 30 V) is required. VGH (27V) and VGL (-5V) among the driving signal voltages applied to the display panel 100 can be used as the voltages of the driving signals 3DC (VGH, VGL) of the switchable cells. An instantaneous high current output is generated to charge a large capacity of the switchable cell 200. [ As a result, when the driving signal (3DC (VGH, VGL)) applied to the switchable cell 200 changes, the driving signal voltage is distorted as shown in FIG. 9B due to the abrupt change of the current, The VGH output from the power supply circuit 300 varies as shown in FIG. 9C. The distortion of VGH causes VGH fluctuation of the gate pulse applied through the gate line 106, resulting in poor pixel voltage charging, and appears as a deterioration in image quality. 9A shows an ideal waveform of the drive signal 3DC (VGH, VGL), that is, a target waveform.

As shown in FIG. 8, when a separate resistor is not added, the resistance value obtained by adding the resistance of the wiring connected to the electrode of the switchable cell 200 and the contact resistance is less than 1 k ?. In this case, when the voltage level of the drive signal 3DC (VGH, VGL) is inverted, the waveform distortion of the drive signal and the output VGH of the power supply circuit 300 change as shown in Fig.

In order to prevent such a problem, in the present invention, resistors R1, R2 and R3 are added to the wiring connected to the switchable cell 200 as shown in FIG. 10 to limit the current applied to the electrodes of the switchable cell 200 do.

10 and 11, the wiring connected to the electrodes of the switchable cell 200 includes resistors R1, R2, and R3. The resistors R1, R2 and R3 prevent the distortion of the driving signal waveform applied to the electrodes of the switchable cell 200 by limiting the current when the driving signals 3DC (VGH, VGL) are changed. The resistors R1, R2, and R3 may be set to the same resistance value, or may be set to different resistance values depending on the position of the switchable cell 200. [

Regardless of the position of the switchable cell 200, the resistors R1, R2, and R3 can be set to the same resistance value, for example, equal to or greater than 3 k? As a result of the simulation, the resistance of 3 k [Omega] or more requires no distortion of the drive signal and the output (VGH) of the power supply circuit is stabilized.

Another embodiment of the resistors R1, R2, and R3 is set to have a different resistance value depending on the position of the switchable cell 200. [ For example, the resistors R1, R2, and R3 connected to the electrodes of the switchable cell 200 may include a first resistor R2 connected to the electrodes disposed at the center of the switchable cell 200, And second resistors R1 and R3 connected to the electrodes disposed in the left and right regions (① and ③) of the switchable cell 200, respectively. The left and right areas (1, 3) are the left and right edge areas of the screen separated by the center part (2) therebetween.

When the resistance value of the first resistor R1 is set smaller than the second resistances R1 and R3, the voltage of the driving signal 3DC (VGH, VGL) is first charged to the central cell of the switchable cell 200 . This method first secures the performance of the center of the screen in the stereoscopic image display device. The main viewing area is the center of the screen, so that the quality of the center is secured, and the driving stability is ensured even if the quality of the left and right areas of the screen is somewhat deteriorated. The present invention is not limited to setting the resistance value of the first resistor R1 smaller than that of the second resistors R1 and R3. The resistance values can be set in various ways according to the screen size, screen shape, or driving method of the switchable cell of the spectacle-free three-dimensional image display device.

11 is a simulation result in which the first resistor R2 is set to 3 k? And each of the second resistors R1 and R3 is set to 6 k ?. 11A shows a target drive waveform of the drive signal 3DC (VGH, VGL). 11 (B) is a waveform of the driving signal (3DC (VGH, VGL)) measured at the center portion (2) of the switchable cell 200. 11C is a waveform of the driving signals 3DC (VGH, VGL) measured in the left and right regions (1, 3) of the switchable cell 200. FIG. 11D shows VGH when the drive signal 3DC (VGH, VGL) changes.

12 is a view showing a connection relationship between the timing controller, the power supply circuit, the level shifter, and the resistance shown in FIG.

Referring to FIG. 12, the voltage of the digital driving signal 3DC from the timing controller 101 is increased by the level shifter 310 to a voltage swinging between VGH and VGL. The power supply circuit 300 supplies VGH and VGL to the level shifter 310. The driving signals 3DC (VGH, VGL) output from the level shifter 310 are applied to the electrodes of the switchable cell 200 through the resistors R1, R2, and R3.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

100: display panel 101: timing controller
102: Data driving circuit 103: Gate driving circuit
110: host system 120: 3D data formatter
200: Switchable cell 210, R1, R2, R3: Resistance
300: power supply circuit 310: level shifter
LENS: Switchable lens BAR: Switchable barrier

Claims (9)

A display panel in which data lines, gate lines crossing the data lines, and pixels are arranged in a matrix form;
A display panel driver for writing data of a stereoscopic image of the display panel;
A switchable cell disposed on the display panel or incorporated in the display panel for separating the optical axis of the left eye image and the right eye image from the stereoscopic image;
Resistors connected to the electrodes of the switchable cell; And
And a timing controller for generating a drive signal of the switchable signal,
Wherein the timing controller changes a level of the driving signal voltage during a vertical blank period in which pixel data of an input image is not received. The method according to claim 1,
A power supply circuit for generating a first voltage and a second voltage; And
Further comprising a level shifter for converting a high level voltage of the driving signal into the first voltage and converting a low level voltage of the driving signal into the second voltage,
And the driving signal output through the level shifter is applied to the electrodes of the switchable cell through the resistor. The method according to claim 1,
The resistors,
A first resistor connected to the electrodes disposed at the center of the switchable cell and a second resistor connected to the electrodes disposed in the left and right regions of the switchable cell,
Wherein the resistance values of the first and second resistors are equal to each other. The method according to claim 1,
Wherein the resistors have different resistance values depending on positions of the switchable cells. 5. The method of claim 4,
The resistors,
A first resistor connected to the electrodes disposed at the center of the switchable cell and a second resistor connected to the electrodes disposed in the left and right regions of the switchable cell,
Wherein a resistance value of the first resistor is smaller than a resistance value of the second resistors. 3. The method of claim 2,
The display panel drive unit includes:
A data driving circuit for converting data received from the timing controller into data voltages and outputting the data voltages to the data lines; And
And a gate driving circuit for sequentially outputting gate pulses synchronized with the data voltage in response to a gate timing control signal received from the timing controller,
Wherein the level shifter converts a high level voltage of each of the driving signal and the gate timing control signal into the first voltage and converts a low level voltage of each of the driving signal and the gate timing control signal into the second voltage,
Wherein the driving signal and the gate pulse each swing between the first voltage and the second voltage. A liquid crystal display device comprising: a display panel in which data lines, gate lines and pixels intersecting with the data lines are arranged in a matrix form, a display panel driver for writing data of a stereoscopic image of the display panel, Eye stereoscopic image display apparatus having a switchable cell built in a panel and separating an optical axis of a left eye image and a right eye image from the stereoscopic image,
Generating a drive signal of the switchable signal in the timing controller; And
And changing a level of the driving signal voltage during a vertical blank period in which pixel data of an input image is not received. 8. The method of claim 7,
Further comprising setting resistance values of the resistors connected to the electrodes of the switchable cell to different values according to positions of the switchable cells. 8. The method of claim 7,
Supplying a gate timing control signal to a gate driving circuit to sequentially supply gate pulses to gate lines of the display panel;
Converting a high level voltage of each of the driving signal and the gate timing control signal into the first voltage and converting a low level voltage of each of the driving signal and the gate timing control signal into the second voltage; And
Wherein each of the driving signal and the gate pulse swings between the first voltage and the second voltage.

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